Software defined computing element resource allocation mode

Abstract

A program code [400] executing on a processing system [100], the program code including one or more instructions, each instruction identifying a workload including a plurality of waves [344], and each instruction identifying a resource allocation [348] for the plurality of waves of a work group. In response to receiving an instruction identifying a workload and a resource allocation for a plurality of waves of a work group, a processor [114] allocates a first set of processing resources to a computing unit [224] of the processor based on the resource allocation for the plurality of waves. The computing unit then performs an operation for the work group using the allocated set of processing resources.

Description

Background Technology

[0001] To execute instructions for an application, a processing system includes a processor with compute units configured to execute operation waves for the application. Each compute unit also includes processing resources, such as vector registers and temporary storage for storing data used in the execution of the wave, to execute these waves. To concurrently fire multiple waves on a compute unit, the processor's fixed-function hardware allocates a portion of the available processing resources to each wave to be fired on that compute unit. However, when allocating available processing resources to waves, such fixed-function hardware considers only limited conditions, causing it to allocate more resources to waves than necessary. This over-allocation reduces the number of waves that can be concurrently fired on a compute unit, thus reducing the efficiency and processing speed of the processing system. Attached Figure Description

[0002] This disclosure can be better understood by referring to the accompanying drawings, and many of its features and advantages will be apparent to those skilled in the art. The same reference numerals are used in different drawings to denote similar or identical items.

[0003] Figure 1 It is a block diagram of a software-defined computing unit resource allocation processing system based on some implementation schemes.

[0004] Figure 2 This is a block diagram of an example processor core configured for software-defined computing unit resource allocation according to some implementation schemes.

[0005] Figure 3 This is a flowchart of an example process for software-defined allocation of computing unit resources according to some implementation schemes.

[0006] Figure 4 It is a block diagram of sample program code for resource allocation of software-defined computing units according to some implementation schemes.

[0007] Figure 5 This is a block diagram of an example method for allocating resources for software-defined computing units, based on some implementation schemes. Detailed Implementation

[0008] An application (e.g., a shader program, a ray tracing program) executing on a processing system generates program code that instructs multiple work items (e.g., functions, operations) to be performed for the application. In an embodiment, the processing system is configured to group such work items into one or more workgroups, each workgroup comprising a corresponding number of waves to be executed (e.g., subgroups of work items). To execute these waves of a workgroup, the processing system includes an accelerated processing unit (APU) having one or more compute units, each compute unit including a slot (e.g., a portion of the compute unit) configured to execute a corresponding wave of the workgroup (e.g., executing one or more operations of the wave of the workgroup). Each compute unit also includes, or is otherwise connected to, compute unit resources (e.g., vector registers, local data sharing, scratch memory), which are configured to store data used in the execution of operations for the wave. To facilitate concurrent execution of multiple waves on compute units, the fixed-function hardware of the processing system allocates a portion of the compute unit resources to each wave (e.g., a slot allocated to the compute unit assigned to the wave). However, due to the nature of the fixed-function hardware, only limited conditions are considered when allocating compute unit resources to waves. Therefore, computing unit resources are not allocated efficiently or effectively to waves. For example, under certain conditions, fixed-function hardware allocates more computing unit resources to waves than are necessary for or conducive to the execution of waves, thus limiting the number of computing unit resources that can be assigned to other waves and the number of waves that can be executed concurrently by computing units.

[0009] Therefore, the systems and techniques described herein relate to software-defined computing unit (CMU) resource allocation. To facilitate such CMU resource allocation, applications (e.g., shader programs, ray tracing programs) generate program code indicating multiple work items (e.g., functions, operations) grouped into one or more workgroups, each workgroup having one or more waves (e.g., subgroups of work items). Additionally, the applications generate program code indicating resource allocation and synchronization data for waves. Such resource allocation includes data indicating one or more corresponding CMU resources to be allocated to each wave of the workgroup. For example, resource allocation includes data indicating one or more corresponding CMU resources to be allocated to each wave (e.g., the number of registers, the amount of memory), one or more CMU resources to be shared (e.g., allocated to two or more waves) (e.g., the number of registers, the amount of memory), or both. Furthermore, such synchronization data indicates, for example, one or more workgroup barriers (e.g., thread barriers) for waves of a workgroup, two or more waves of a workgroup to be executed concurrently, two or more waves of two or more workgroups to be executed concurrently, or any combination thereof. Before each thread of the wave has executed a predetermined operation, function, or both indicated by a workgroup barrier (e.g., a thread barrier), the barrier causes one or more threads of the wave to pause.

[0010] In response to receiving program code (e.g., as a command, instruction, or both) that includes workgroups, resource allocation, and synchronization data, the processor allocates computing unit resources to waves within a workgroup (e.g., a wave slot of a computing unit executing a wave) based on the received program code. For example, the processor allocates computing unit resources to a wave such that one or more conditions indicated in the resource allocation, synchronization data, or both are satisfied. In this way, the allocation of computing unit resources to waves is defined by program code rather than by the fixed-function hardware of the processing system. Because the computing unit resource allocation is defined by program code, additional conditions are considered when allocating computing unit resources, thereby increasing the amount of available resources to be allocated to waves and increasing the number of concurrent waves emitted on computing units. Furthermore, because the computing unit resource allocation is defined by program code, the processor can dynamically allocate available resources each time a workgroup is assigned (e.g., the processor can allocate resources each time a workgroup is assigned). Therefore, the processing speed and efficiency of the processing system are improved. Moreover, to allocate such resources, the processor is configured to modify one or more hardware registers of the processor based on the received program code (e.g., based on the resource allocation and synchronization data indicated in the program code). As an example, the processor updates a hardware register (e.g., a base address register) that stores the base address of one or more computing unit resources to allocate computing unit resources to a wave. In this way, the processor allocates computing unit resources to a wave using the physical address of the computing unit resources (e.g., based on the base address), thereby limiting the need to call, for example, a rename table and improving the processing speed and efficiency of the processing system.

[0011] Figure 1 This is a block diagram of a processing system 100 implementing software-defined computing unit resource allocation according to some embodiments. The processing system 100 includes or has access to memory 106 or other storage components implemented using non-transitory computer-readable media (e.g., dynamic random access memory (DRAM)). However, in embodiments, memory 106 is implemented using other types of memory (including, for example, static random access memory (SRAM), non-volatile RAM, etc.). According to embodiments, memory 106 includes external memory implemented outside the processing units implemented in the processing system 100. The processing system 100 also includes a bus 112 to support communication between entities implemented in the processing system 100, such as memory 106. Some embodiments of the processing system 100 include other buses, bridges, switches, routers, etc., which are not shown for clarity. Figure 1 As shown in the image.

[0012] In various implementations, the techniques described herein are employed at an Accelerated Processing Unit (APU) 114. APU 114 includes, for example, various parallel processors, vector processors, coprocessors, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), nonscalar processors, highly parallel processors, artificial intelligence (AI) processors, inference engines, machine learning processors, other multi-threaded processing units, scalar processors, serial processors, or any combination thereof. APU 114 renders images for presentation on display 120 according to one or more applications 110 (e.g., shader programs). For example, APU 114 renders objects (e.g., primitives) according to one or more shader programs to produce pixel values ​​provided to display 120, which uses the pixel values ​​to display an image representing the rendered objects. To render objects, APU 114 implements multiple processor cores 116-1 to 116-N that execute instructions from, for example, one or more applications 110 concurrently or in parallel. For example, the APU114 uses multiple processor cores 116 to execute instructions from shader programs, ray tracing programs, graphics pipelines, or both to render one or more objects. Although in Figure 1 In the illustrated implementation, three processor cores (116-1, 116-2, 116-N) representing N cores are presented, but the number of processor cores 116 implemented in the APU 114 is a design choice. Therefore, in other implementations, the APU 114 may include any number of processor cores 116. Some implementations of the APU 114 are used for general-purpose computing. The APU 114 executes instructions, such as program code 108 (e.g., shader code, ray tracing code), for one or more applications 110 (e.g., shader programs, ray tracing programs) stored in memory 106, and the APU 114 stores information (such as the results of the executed instructions) in memory 106.

[0013] In one implementation, instructions indicated in program code 108 (e.g., shader code, ray tracing code) from one or more applications 110 (e.g., shader program, ray tracing program) define one or more work items (e.g., functions), each work item identifying, for example, one or more operations to be performed, the size of one or more workgroups (e.g., groups of work items), or both. Additionally, in another implementation, the processing system 100 groups such work items into one or more workgroups based on, for example, predetermined values, the type of operation identified in the work item, the architecture of the APU 114, the availability of computing unit resources, or any combination thereof. To execute a workgroup (e.g., a group of work items), one or more processor cores 116 of the APU 114 operate as one or more computing units, each computing unit configured to emit one or more wavefronts (e.g., waves) to execute the workgroup. For this purpose, each computing unit includes one or more Single Instruction Multiple Data (SIMD) units, each SIMD unit including multiple channels configured, for example, to perform the same operation on different sets of data indicated in one or more instructions received from the application 110. As an example, each SIMD unit includes multiple arithmetic logic units (ALUs), each ALU performing the same operation on multiple data sets. In embodiments, one or more SIMD units of the computing unit include vector SIMD units (e.g., SIMD units including one or more vector ALUs), scalar SIMD units (e.g., SIMD units including one or more scalar ALUs), or both. According to embodiments, each computing unit is configured to concurrently emit one or more waves. For example, one or more channels of each SIMD unit of the computing unit are configured to concurrently perform operations against one or more waves. Each portion (e.g., a channel) of the SIMD unit configured to perform operations against waves is also referred to herein, for example, a slot. In this way, the computing unit has several slots (e.g., several portions of the SIMD unit) each configured to concurrently perform one or more waves (e.g., perform operations against one or more waves).

[0014] Furthermore, to support SIMD units, each processor core 116 includes or is otherwise coupled to one or more corresponding sets of computing unit resources 122. For example, each computing unit of processor core 116 includes or is otherwise coupled to a corresponding set of computing unit resources 122. For example, these computing unit resources 122 are configured to store auxiliary or helpful values, register files, operands, instructions, variables, result data (e.g., data generated by the execution of one or more operations), flags, or any combination thereof necessary for executing one or more operations indicated in one or more instructions from application 110 (e.g., in a workgroup based on instructions from application 110). Additionally, such computing unit resources 122 include, for example, one or more registers (e.g., vector registers, scalar registers), local data sharing, temporary storage, or any combination thereof. According to embodiments, one or more computing unit resources 122 are included in corresponding computing units, one or more computing unit resources 122 are shared between two or more computing units, or both of the above. Although Figure 1 The example implementation shown presents a processing system 100 with three sets (122-1, 122-2, 122-N) of computing unit resources for three respective processor cores 116, but in other implementations, the processing system 100 may have any number of sets of computing unit resources 122 for one or more respective processor cores 116.

[0015] In one implementation, the processing system 100 is configured to allocate one or more portions of one or more computing unit resources 122 (e.g., registers, local data shares, temporary storage) to one or more waves of a workgroup (e.g., portions of the SIMD units of one or more computing units that perform operations against waves). To this end, in one implementation, the APU 114 includes a command processor (not shown for clarity) that includes hardware-based circuitry, software-based circuitry, or both, configured to issue appropriate workgroups (e.g., as commands, instructions, or both) to one or more computing units of one or more processor cores 116. In response to issuing a workgroup to one or more compute units, the fixed-function hardware of APU 114 (e.g., software-based circuitry, hardware-based circuitry, or both configured to implement a graphics pipeline level, tessellation level, rasterization level, or any combination thereof) allocates one or more portions of one or more compute unit resources 122 to waves of the workgroup to be emitted on the compute unit (e.g., channels allocated to SIMD units to perform wave-based operations) based on the type of operation identified in the workload, the availability of compute unit resources 122, the priority associated with the workload, or any combination thereof. For example, the fixed-function hardware of APU 114 (e.g., via a Serial Peripheral Interface (SPI)) programs a base address register with a base address to allocate one or more physical registers (e.g., vector registers, scalar registers) of the set of compute unit resources 122 to one or more waves to be emitted on the compute unit. In response to receiving an instruction to emit a wave, the compute unit of processor core 116 determines the physical registers (e.g., vector registers, scalar registers) of the set of compute unit resources 122 to be allocated to the wave to be emitted based on the base address in the base address register. However, using the fixed-function hardware of the APU 114 to allocate compute unit resources 122 to waves limits the flexibility of allocating compute unit resources 122 to different waves, SIMD units, or both. For example, operations for some applications (e.g., shader programs) require fewer compute unit resources 122 than are allocated by the fixed-function hardware of the APU 114. As another example, the number of compute unit resources 122 necessary to perform operations for some applications changes as operations (e.g., workgroups) are being executed. Therefore, the fixed-function hardware of the APU 114 allocates more compute unit resources 122 to waves, SIMD units, or both than are necessary or helpful for performing these operations. In this way, the processing system 100 limits the number of compute unit resources 122 available for allocation, which reduces the number of concurrent waves emitted by the compute units and decreases the processing efficiency of the processing system 100.

[0016] To help increase the number of concurrent waves on the computing unit and improve the processing efficiency of the processing system 100, the processing system 100 is configured to allocate one or more portions of one or more computing unit resources 122 (e.g., register sets, local data shares, scratch memory) to one or more waves based on program code 108 (e.g., shader code, ray tracing code) from one or more applications 110 (e.g., shader programs, ray tracing programs). For example, in one embodiment, program code 108 includes data identifying a workgroup comprising multiple waves and data identifying resource allocations for one or more waves of the workgroup. Such resource allocations for waves include, for example, data identifying one or more registers allocated to the corresponding wave, an amount of local data share allocated to the corresponding wave (e.g., in kilobytes), one or more barriers of the corresponding wave, one or more other waves to be synchronized with the corresponding wave (e.g., one or more waves to run concurrently with the corresponding wave), or any combination thereof. Such barriers include one or more thread barriers (e.g., thread synchronization points) for a corresponding wave, which, for example, cause one or more threads of the wave to pause before each thread of the wave has executed a predetermined operation, function, or both indicated by the barrier. Based on data (e.g., as a command, instruction, or both) indicating workgroups, resource allocations, synchronization data, or any combination thereof received from program code 108, APU 114 allocates at least a portion of the set of computing unit resources 122 to one or more waves indicated in program code 108 based on the resource allocation indicated in program code 108. For example, in response to data indicating workgroups, resource allocations, and synchronization data received from program code 108, APU 114 edits one or more hardware registers of APU 114 based on one or more resource allocations indicated in program code 108. In some embodiments, data identifying workgroups, resource allocations, or synchronization data in program code 108 is provided to APU 114 via commands or instructions (e.g., instructions identifying workgroups and resource allocations). For example, in some implementations, APU 114 receives instructions to identify workgroups, allocate resources, and synchronize data, and based on those instructions, allocates at least a portion of the set of computing unit resources 122 to one or more waves of the workgroup.

[0017] Assigning computing unit resources 122 to waves in this manner allows for greater flexibility in resource allocation. For example, only the amount of computing unit resources 122 necessary for performing one or more operations on a wave can be allocated to it. Furthermore, when a workgroup is assigned to or received by an APU 114, the APU 114 can dynamically allocate computing unit resources 122. That is, the APU 114 is configured to dynamically allocate corresponding computing unit resources 122 to each workgroup received by the APU 114, such that, for example, a first workgroup received by the APU 114 is allocated a first set of computing unit resources 122 with a first number of computing unit resources, and a second workgroup received by the APU 114 is allocated a second set of computing unit resources 122 with a second number of computing unit resources 122 different from the first number. Moreover, assigning computing unit resources 122 in this manner allows the APU 114 to allocate computing unit resources 122 while a workgroup, a wave, or both are being processed (e.g., operations are being performed on the workgroup or the wave). For example, when executing a workgroup, APU 114 receives one or more instructions identifying a second set of computing unit resources 122 to be allocated to the workgroup. Therefore, APU 114 can change the allocation of computing unit resources 122 as the number of computing unit resources 122 required for executing the workgroup, waves, or both changes. In this way, as the amount of excess processing resources assigned to waves decreases, the processing efficiency of processing system 100 increases, allowing additional concurrent waves to be emitted on computing units. Additionally, specifying which waves to be emitted concurrently allows processing system 100 to further improve the allocation efficiency of computing unit resources 122 by grouping such waves together based on the availability of computing unit resources 122 (e.g., grouping waves together to maximize the number of concurrent waves emitted by computing units). Furthermore, in an embodiment, program code 108 includes data indicating that two or more waves will be allocated the same processing resources (e.g., vector registers, scalar registers, LDS) to the set of computing unit resources 122. In other words, program code 108 includes data indicating that one or more computing unit resources 122 will be shared across two or more waves. Therefore, sharing computing unit resources 122 between two or more waves increases the amount of computing unit resources 122 available to the entire workgroup, thereby increasing the number of concurrent waves emitted by the computing units and improving the processing efficiency of the processing system 100.

[0018] The processing system 100 also includes a central processing unit (CPU) 102 connected to and thus communicating with the APU 114 and memory 106 via the bus 112. The CPU 102 implements multiple processor cores 104-1 to 104-N that execute instructions concurrently or in parallel. In embodiments, one or more processor cores 104 each operate as one or more computing units (e.g., SIMD units) performing the same operation on different sets of data. Although in Figure 1 The example implementation shown presents three processor cores (104-1, 104-2, 104-M) representing M cores, but the number of processor cores 104 implemented in CPU 102 is a design choice. Therefore, in other implementations, CPU 102 may include any number of processor cores 104. In some implementations, CPU 102 and APU 114 have an equal number of processor cores 104 and 116, while in other implementations, CPU 102 and APU 114 have different numbers of processor cores 104 and 116. Processor cores 104 execute instructions (such as program code 108 stored in memory 106), and CPU 102 stores information (such as the results of executed instructions) in memory 106. CPU 102 is also capable of initiating graphics processing by issuing a draw call to APU 114. In implementations, CPU 102 implements multiple processor cores that execute instructions concurrently or in parallel (for clarity). Figure 1 (Not shown in the image).

[0019] The input / output (I / O) engine 118 includes hardware and software for handling input or output operations associated with the display 120, as well as other components of the processing system 100, such as a keyboard, mouse, printer, external disk, etc. The I / O engine 118 is coupled to a bus 112, enabling the I / O engine 118 to communicate with the memory 106, APU 114, or CPU 102.

[0020] Now for reference Figure 2 This presents an example processor core 200 configured for software-defined computing unit resource allocation. In an implementation, processor core 200 (similar or identical to processor core 116) includes two computing units 224 configured to execute one or more workgroups (e.g., groups of work projects) indicated in program code 108 from application 110 (e.g., shader program, ray tracing program). Although Figure 2The example implementation presents a processor core 200 with two computing units (224-1, 224-2), but in other implementations, the processor core 200 may have any number of computing units 224. To execute the workgroup indicated in program code 108, each computing unit 224 is configured to emit one or more waves (e.g., wavefronts) to perform one or more functions, operations, or both indicated in the workgroup (e.g., indicated in program code 108). For this purpose, each computing unit 224 includes one or more SIMD units 226 (e.g., vector SIMD units, vector-SIMD units), each SIMD unit being configured to perform one or more operations for one or more functions identified in the workgroup within one or more waves. That is, at least a portion of each SIMD unit 226 is configured to emit waves using one or more channels of the SIMD unit 226 to perform one or more operations for one or more functions identified in the workgroup. Although Figure 2 Example implementations present a computing unit 224-1 having three SIMD units (226-1, 226-2, 226-N) representing N SIMD units and a computing unit 224-2 having three SIMD units (226-3, 226-4, 226-M) representing M SIMD units, but in other implementations, each computing unit 224 may include any number of SIMD units 226.

[0021] To assist SIMD unit 226 in performing one or more operations of a workgroup, each computing unit 224 includes or is otherwise connected to instruction cache 230. For example, in one embodiment, each computing unit 224-1, 224-2 includes a corresponding instruction cache 230, while in other embodiments, one or more instruction caches 230 are connected to each computing unit 224-1, 224-2 (e.g., shared by computing units 224). Instruction cache 230 includes, for example, memory (e.g., SRAM) configured to store one or more instructions necessary, auxiliary, or helpful for performing one or more operations of the workgroup (e.g., one or more operations for a wave of the workgroup). In one embodiment, instruction cache 230 is shared by each wave emitted by one or more computing units (e.g., a channel of the SIMD unit performing an operation for that wave). For example, instruction cache 230 is shared by waves emitted on computing units 224-1, 224-2. Similarly, each computing unit 224 also includes or is otherwise connected to data cache 232. For example, in one embodiment, each computing unit 224-1, 224-2 includes a corresponding data cache 232, while in other embodiments, one or more data caches 232 are connected to each computing unit 224-1, 224-2 (e.g., shared by computing units 224). The data cache 232 includes, for example, memory (e.g., SRAM) configured to store auxiliary or helpful data (e.g., cache lines) necessary for performing one or more operations of a workgroup (e.g., one or more operations for a wave of the workgroup). In one embodiment, the instruction cache 230 is shared by each wave emitted by one or more computing units (e.g., a channel of a SIMD unit performing an operation for that wave).

[0022] Additionally, to assist SIMD unit 226 in performing one or more operations for a workgroup, processor core 200 includes or is otherwise connected to a set of computing unit resources similar to or the same as the set of computing unit resources 122. This set of computing unit resources is configured, for example, to store, assisting or aiding values, register files, operands, instructions, variables, resulting data (e.g., data generated by the execution of one or more operations), flags, or any combination thereof, necessary for the execution of one or more operations indicated in the workgroup received by processor core 200. Such processing resources include, for example, register 228, local data share 234, or both. For example, each computing unit 224 includes or is otherwise connected to a set of registers 228, which is configured to store, assisting or aiding values, operands, resulting data (e.g., data obtained from the execution of one or more operations, register files, or any combination thereof), necessary for the execution of one or more operations for the workgroup. In one embodiment, the set of registers 228 includes one or more vector registers 240 configured to store auxiliary or helpful data (e.g., operands, values) necessary for performing one or more operations by, for example, vector SIMD unit 226. Such vector registers 240 are shared, for example, by one or more channels of SIMD unit 226 performing operations for one or more waves of a workgroup. According to one embodiment, one or more vector registers 240 are allocated to one or more channels of SIMD unit 226 performing operations for the same wave, one or more vector registers are allocated to one or more channels of SIMD unit 226 performing operations for two or more waves (e.g., one or more vector registers are allocated such that the vector registers are shared by channels of SIMD unit 226 performing operations for two or more waves), or both. In one embodiment, the set of registers 228 additionally or alternatively includes one or more scalar registers 242 configured to store auxiliary or helpful data (e.g., operands, values) necessary for performing one or more operations by, for example, scalar SIMD unit 226. Although Figure 2 The example implementation presented provides a first computation unit 224-1 having a set of registers 228-1 (e.g., including vector registers 240-1 and scalar registers 242-1) and a second computation unit having a set of registers 228-2 (e.g., including vector registers 240-2 and scalar registers 242-2), but in other implementations, each computation unit 224 may have any number of sets of registers 228, each set including any number of vector registers 240, scalar registers 242, or both.

[0023] Furthermore, each computing unit 224 includes or is otherwise connected to a local data share 234. The local data share 234 includes memory (e.g., SRAM) shared across one or more computing units across each SIMD unit 226. That is, the local data share 234 is shared across each wave performed on one or more computing units 224. For example, in Figure 2 In the example implementation presented, each SIMD unit 226 across computing units 224-1 and 224-2 shares a local data share 234, such that waves transmitted across computing units 224-1 and 224-2 share the local data share 234. In this implementation, the local data share 234 is configured to store results (e.g., data generated by the execution of one or more operations of one or more SIMD units 226), operands, register files, or any combination thereof, which are necessary, auxiliary, or helpful for the execution of one or more operations of one or more SIMD units 226. As an example, the local data share 234 is used as a temporary storage to store results that are necessary, auxiliary, or helpful for the execution of one or more operations by one or more SIMD units 226. Furthermore, because the local data share 234 is shared across each SIMD unit 226 and one or more computing units (e.g., across wave sharing performed on one or more computing units 224), the local data share 234 allows data to be shared across the SIMD units 226 of one or more computing units 224 (e.g., across wave sharing performed on computing units 224). For example, results determined from the execution of operations on a first wave by, for example, one or more channels of SIMD units 226 are stored in the local data share 234. Such results can then be used for one or more operations on one or more other waves performed on, for example, one or more other channels of the same or different SIMD units 226. According to an embodiment, the processing system 100 is configured to allocate at least a portion of the local data share 234 to one or more waves of a workgroup to be executed on one or more computing units 224. For example, processing system 100 defines one or more corresponding portions of local data share 234 (e.g., in kilobytes) that are visible to one or more waves of a workgroup to be executed on one or more computing units 224 (e.g., visible to one or more channels of one or more SIMD units 226 configured to execute one or more waves of a workgroup).

[0024] Now for reference Figure 3This document presents an example operation 300 for software-defined allocation of computing unit resources. In one embodiment, example operation 300 includes: processing system 100 executing an application 310 similar to or identical to application 110. Application 310 includes, for example, a shader program, ray tracing program, machine learning program, or any combination thereof running on processing system 100. In another embodiment, application 310 includes generating program code similar to or identical to program code 108, which includes one or more instructions to be executed by APU 114. For example, the program code includes one or more work items (e.g., functions) to be executed by APU 114. According to the embodiment, application 310 is configured to group one or more work items of the program code into one or more workgroups 344 based on, for example, the available computing unit resources of APU 114, the functions, operations, or both indicated in the work items, the priority of the work items, or any combination thereof. For example, application 310 is configured to group work items together based on the available computing unit resources of APU 114, such that one or more resulting workgroups 344 include a predetermined number of waves, a number of waves based on the maximum number of currently available slots on one or more computing units, a number of waves based on the maximum number of slots associated with one or more computing units, or any combination thereof. Furthermore, application 310 is configured to define synchronization data for workgroups 344 in program code. Such synchronization data includes, for example, one or more corresponding thread barriers (e.g., thread synchronization points) for workgroups, workgroup groups, or one or more waves of both. Such workgroup groups include, for example, data indicating one or more waves of one or more workgroups 344 to be executed concurrently. For example, a workgroup group includes data indicating that a first wave of a first workgroup 344 will be executed concurrently with a second wave of a first workgroup 344, a second workgroup 344, or both.

[0025] In the implementation, application 310 is also configured to determine one or more corresponding parameters 346 in the program code for workgroup 344. Such parameters 346 include one or more values, instructions, operands, register files, results (e.g., data generated by the execution of one or more operations), or any combination thereof, that are necessary, auxiliary, or helpful for the execution of workgroup 344 (e.g., work items of workgroup 344). Additionally, application 310 is configured to define one or more corresponding resource allocations 348 in the program code for one or more workgroups 344. For example, such resource allocations 348 include data that allocates one or more portions of one or more allocatable resources (e.g., vector register 240, scalar register 242, local data share 234) to one or more waves of workgroup 344. As an example, such resource allocations 348 include data indicating the corresponding number of vector registers 240 to be allocated to waves of workgroup 344 and the corresponding amount of data in local data share 234. In this implementation, resource allocation 348 includes data indicating that one or more allocated sources will be shared between two or more waves of workgroup 344 (e.g., shared between two or more slots of a computing unit). For example, resource allocation 348 includes data indicating that two vector registers 240 will be allocated to a first wave of workgroup 344, and the same two vector registers 240 will also be allocated to a second wave of workgroup 344 (e.g., shared with that second wave).

[0026] According to the implementation scheme, one or more workgroups 344, parameters 346, resource allocations 348, or any combination thereof in the program code of application 310 are stored in a local work queue 350. For example, data instructing one or more workgroups 344, parameters 346, resource allocations 348, or any combination thereof are stored in the local work queue 350 as one or more commands, instructions, or both. The local work queue 350 includes one or more hardware queues, software queues, or both, for example, communicatively coupled to one or more computing units of APU 114. In the implementation scheme, the local work queue 350 is configured to store workgroups 344, parameters 346, resource allocations 348, or any combination thereof as one or more work packets 352. These work packets 352 include, for example, data identifying workgroup 344 (e.g., commands, instructions), one or more parameters 346 associated with workgroup 344 (e.g., necessary, auxiliary, or helpful for the execution of the workgroup), one or more resource allocations 348 associated with workgroup 344 (e.g., defining resources to be allocated to the workgroup), or any combination thereof. For example, work group 352 includes work group 344, which includes instructions identifying one or more waves to be emitted, parameters 346 necessary for executing the waves (e.g., values, instructions, operands, register files, results), and resource allocation 348 defining the number of vector registers 240 to be assigned to each wave and the number of vector registers 240 to be shared between two or more waves. According to an implementation, compute unit 224 of APU 114 is configured to request one or more work groups 352 from local work queue 350. For example, compute unit 224 is configured to request (e.g., acquire) work group 352 from local work queue 350 in response to compute unit 224 having one or more idle slots (e.g., slots not currently performing operations for waves), compute unit 224 not currently being assigned to work group 344, compute unit 224 completing a wave, compute unit 224 completing work group 344 (e.g., completing a previous work group), or any combination thereof.

[0027] To this end, computing unit 224 includes a resource allocation module 354, which includes hardware-based circuitry, software-based circuitry, or both, configured to receive (e.g., acquire) work packets 352 from local work queue 350. In response to receiving work packets 352, resource allocation module 354 is configured to assign one or more waves of work group 344 indicated in work packets 352 to one or more corresponding slots of computing unit 224. For example, resource allocation module 354 is configured to assign waves of work group 344 to corresponding slots based on allocable resources to be shared between waves, synchronization data of waves (e.g., data indicating two or more waves to be emitted concurrently), data shared between two or more waves (e.g., results, operands), or any combination thereof. As another example, resource allocation module 354 is configured to assign waves of workgroup 344 to corresponding slots based on one or more associated instructions of workgroup 344, which indicate allocable resources to be shared between waves, synchronization data of waves (e.g., data indicating two or more waves to be emitted concurrently), data to be shared between two or more waves (e.g., results, operands), or any combination thereof. Additionally, resource allocation module 354 is also configured to allocate portions of one or more allocable resources associated with computing unit 224 (e.g., vector register 240, scalar register 242, local data share 234) to each slot of computing unit 224 (e.g., a portion of SIMD unit 226). For example, based on the corresponding resource allocation 348 for each wave of workgroup 344 indicated in workgroup 352, resource allocation module 354 is configured to allocate portions of allocable resources. To allocate such allocatable resources, resource allocation module 354 is configured to determine one or more addresses 356, values ​​360, or both for updating hardware registers 362 of APU 114. Such hardware registers 362 include, for example, hardware-based circuitry configured to define base addresses for one or more allocatable resources (e.g., vector register 240, scalar register 242, local data share 234) such that the allocatable resources are allocated to one or more waves of workgroup 344 (e.g., slots of one or more compute units 224). According to an embodiment, resource allocation module 354 determines one or more addresses 356, values ​​360, or both necessary for updating hardware register 362, such that allocatable resources of compute units 224 are allocated to one or more waves of workgroup 344 (e.g., slots of one or more compute units 224) based on the corresponding resource allocation 348 indicated in workgroup 352 for each wave of workgroup 344.As an example, the resource allocation module 354 determines one or more base addresses and values ​​necessary for allocating a portion of the vector register 240 of the computing unit 224 and a portion of the local data share 234 to one or more waves of the working group 344 (e.g., one or more slots of one or more computing units 224) based on the corresponding resource allocation 348 for each wave of the working group 344 indicated in the working group 352.

[0028] After updating hardware register 362 to allocate allocatable resources to one or more slots of computing unit 224, computing unit 224 is configured to: emit one or more waves of workgroup 344 indicated in workgroup 352, causing one or more SIMDs to perform operation 358 on the waves. In an embodiment, computing unit 224 (e.g., SIMD unit 226) is configured to: execute waves based on synchronization data indicated in workgroup 352. For example, computing unit 224 is configured to: concurrently emit two or more waves based on synchronization data indicated in workgroup 352. As another example, computing unit 224 is configured to: pause, resume, or both of the execution of one or more waves based on one or more barriers (e.g., thread barriers) indicated in the synchronization data of the workgroup. According to an embodiment, resource allocation module 354 is also configured to: allocate allocatable resources to one or more slots of the workgroup when the computing unit executes the workgroup. As an example, when a workgroup is being executed by a computing unit using a first set of allocable resources, the resource allocation module 354 is configured to allocate a second set of allocable resources, different from the first set of allocable resources, based on one or more received instructions identifying the workgroup (e.g., one or more instructions in work groups 352 associated with the workgroup).

[0029] Now for reference Figure 4Example program code 400 for resource allocation of a software-defined computing unit is presented. In an embodiment, program code 400 is generated by an application similar to or the same as applications 110, 310, which includes, for example, shader programs, ray tracing programs, machine learning programs, or any combination thereof. Program code 400 includes, for example, data indicating workgroup 344, parameters 346, resource allocation 348, and synchronization data 468. Workgroup 344 (e.g., one or more work items grouped together based on available allocable resources of APU 114, functions, operations, or both types indicated in the work items, priority of the work items, or any combination thereof) and parameters 346 include one or more corresponding values, instructions, operands, register files, results (e.g., data generated by the execution of one or more operations), or any combination thereof, necessary for, assisting in, or helpful to the execution of workgroup 344 (e.g., work items of workgroup 344).

[0030] For each workgroup in workgroup 344, program code 400 includes a corresponding resource allocation 348. Such resource allocation 348 includes, for example, vector register allocation 462, scalar register allocation 464, and local data sharing allocation 466. Vector register allocation 462 includes, for example, data indicating: a corresponding number of vector registers 240 to be allocated to each wave of workgroup 344, a corresponding number of vector registers 240 to be shared between two or more waves of workgroup 344, or both. As an example, vector register allocation 462 includes data indicating: a first number of vector registers 240 to be allocated to the first wave of workgroup 344, a second number of vector registers 240 to be allocated to the second wave of workgroup 344, and a number of vector registers 240 to be shared between the first and second waves. Similarly, scalar register allocation 464 includes, for example, data indicating: a corresponding number of scalar registers 242 to be allocated to each wave of workgroup 344, a corresponding number of scalar registers 242 to be shared between two or more waves of workgroup 344, or both. In the implementation, resource allocation 348 includes local data share allocation 466. Local data share allocation 466 includes data indicating, for example, the amount of local data share 234 to be allocated to each wave of workgroup 344 (e.g., to make it visible to each wave of that workgroup), the amount of local data share 234 to be shared between two or more waves of workgroup 344, or both. As an example, local data share allocation 466 includes data indicating the amount of local data share 234 to be allocated to the first wave of workgroup 344 (e.g., to make it visible to the first wave of that workgroup), the amount of local data share 234 to be allocated to the second wave of workgroup 344, and the amount of local data share 234 to be shared between the first and second waves.

[0031] According to the implementation scheme, program code 400 also includes synchronization data 468, which includes, for example, workgroup barriers 470, workgroup groups 472, or both. Workgroup barriers 470 include data defining one or more corresponding thread barriers (e.g., thread synchronization points) for one or more waves of workgroup 344. Such thread barriers include, for example, data identifying one or more operations, functions, or both of the wave. Based on the identified operation, function, or both, one or more threads of the wave (e.g., channels of SIMD unit 226) pause after completing the identified operation or function and resume operation when each thread of the wave has performed the identified operation or function. In this way, the threads of the wave are synchronized based on thread barriers. Workgroup groups 472 include, for example, data indicating: two or more workgroups 344 to be executed concurrently, two or more waves of workgroups 344 to be executed concurrently, two or more waves or two or more workgroups 344 to be executed concurrently, or any combination thereof. Based on such workgroup 472, one or more computing units 224 are configured to transmit waves such that workgroup 344, waves, or both identified in workgroup 472 are executed concurrently.

[0032] Now for reference Figure 5An example method 500 for performing software-defined processing resource allocation is presented. At step 505 of method 500, an APU similar to or the same as APU 114 receives program code similar to or the same as program code 108 (e.g., shader code, ray tracing code) from one or more applications similar to or the same as application 110 (e.g., shader program, ray tracing program). Such program code includes, for example, data identifying one or more workgroups similar to or the same as workgroup 344 (e.g., a group of work items) to be executed by the APU, and one or more resource allocations similar to or the same as resource allocation 348 for executing workgroup 344. For example, the program code includes data identifying a workgroup having a first number of waves, and a resource allocation indicating the number of vector registers (e.g., vector register 240) to be allocated to each wave of the workgroup, the number of vector registers to be shared between two or more waves of the workgroup, or both. In an embodiment, the APU receives the program code, the data identifying one or more workgroups, the resource allocation, or both as one or more commands, instructions, or both (e.g., instructions identifying one or more workgroups, resource allocations, or both). At step 510, the APU stores workgroups and resources (e.g., instructions identifying workgroups and resources) in a local work queue similar to or the same as local work queue 350. In an embodiment, the local work queue is configured to store workgroups and associated resource allocations (e.g., resource allocations for waves of a workgroup) as work groups similar to or the same as work group 352. At step 515, the APU requests (e.g., retrieves) one or more work groups identifying workgroups and one or more resource allocations from the local work queue. For example, in response to one or more computing units of the APU completing the execution of one or more workloads (e.g., completing a previous workgroup), completing one or more waves of one or more workloads, having one or more available (e.g., empty) wave slots, or any combination thereof, the APU requests (e.g., retrieves) one or more work groups from the local work queue.

[0033] At step 520, the APU allocates resources to slots (e.g., channels of one or more SIMD units) of one or more computing units similar to or identical to computing unit 224 based on received work packets (e.g., one or more instructions of the work packet). For example, the APU allocates resources to slots of one or more computing units based on resource allocations identified in the work packet (e.g., identified in one or more instructions). As another example, the APU allocates resources to one or more slots of the computing unit while the computing unit is processing one or more workgroups (e.g., performing operations for one or more workgroups) based on resource allocations identified in a second instruction of the work packet. To allocate such resources, the APU is configured to edit one or more hardware registers of the APU similar to or identical to hardware register 362. For example, the APU determines one or more addresses (e.g., address 356, base address), values ​​(e.g., value 360), or both, necessary for allocating resources to slots of one or more computing units based on the resource allocations identified in the work packet. After determining one or more addresses, values, or both, the APU updates one or more addresses in the hardware registers based on the determined addresses to allocate resources to slots of the computing unit. At step 525, in response to updating the hardware registers, the APU executes the workgroup identified in the workgroup by emitting one or more waves of the workgroup on one or more computing units.

[0034] As disclosed herein, in some embodiments, a method includes: in response to receiving from an application an instruction identifying a workgroup comprising multiple waves and identifying resource allocations for the multiple waves, allocating a set of processing resources to a computing unit based on the resource allocations for the multiple waves; and executing the workgroup using the set of processing resources allocated to the computing unit. In one aspect, the method includes: storing in a local work queue the instruction identifying the workgroup and the resource allocations for the multiple waves. In another aspect, the method includes: in response to the computing unit executing a previous workgroup, requesting from the local work queue data including: the instruction identifying the workgroup and the resource allocations for the multiple waves. In yet another aspect, the method includes: while the workgroup is being executed, allocating a second set of processing resources to the workgroup based on a second instruction identifying the workgroup. Still in another aspect, allocating the set of processing resources to the computing unit includes: allocating the same processing resources to two or more slots of the computing unit based on the resource allocations for the multiple waves.

[0035] In one aspect, the method includes: executing the plurality of waves of the workgroup based on synchronization data received from an application. In another aspect, the synchronization data identifies thread barriers for waves among the plurality of waves. Still in another aspect, the synchronization data identifies two or more waves among the plurality of waves to be executed concurrently. In yet another aspect, the resource allocation for the plurality of waves identifies a corresponding number of vector registers for each wave among the plurality of waves. In yet another aspect, the method includes: modifying hardware registers based on the resource allocation for the plurality of waves.

[0036] In some embodiments, a processing system includes: a memory; and a processor coupled to the memory and configured to: receive from an application instructions identifying a workgroup comprising multiple waves and identifying resource allocations for the multiple waves, wherein the processor includes: a plurality of computing units, wherein at least one of the plurality of computing units includes: a resource allocation module configured to: allocate a set of processing resources to the at least one computing unit based on the resource allocations for the multiple waves; and a plurality of wave slots configured to: execute the workgroup using the set of processing resources allocated to the computing unit. In one aspect, the processing system includes: a local work queue configured to: store the instructions identifying the workgroup and the resource allocations for the multiple waves. In another aspect, the at least one computing unit is configured to: in response to the at least one computing unit executing a previous workgroup, request from the local work queue data including: the instructions identifying the workgroup and the resource allocations for the multiple waves. Still in another aspect, the resource allocation module is configured to: when executing the workgroup, allocate a second set of processing resources to one or more wave slots based on a second instruction identifying the workgroup.

[0037] In one aspect, the resource allocation module is configured to allocate the same processing resources to two or more slots among the plurality of waves based on the resource allocation for the plurality of waves. In another aspect, the processor is configured to receive data from the application identifying corresponding thread barriers for one or more of the plurality of waves. In yet another aspect, the processor also includes hardware registers, and the resource allocation module is configured to allocate the set of processing resources by modifying the hardware registers based on the resource allocation for the plurality of waves. In yet another aspect, the resource allocation for the plurality of waves identifies a corresponding amount of local data sharing for each of the plurality of waves.

[0038] In some embodiments, a processor includes: one or more processing cores configured to: allocate a set of processing resources to a computing unit based on the resource allocation for the multiple waves, in response to receiving synchronization data for multiple waves from an application and an instruction identifying resource allocations for the multiple waves; and execute the multiple waves using the set of processing resources allocated to the computing unit and based on the synchronization data. In one aspect, the synchronization data identifies thread barriers for waves among the multiple waves. In another aspect, the synchronization data identifies two or more waves among the multiple waves to be executed concurrently. In yet another aspect, the one or more processor cores are configured to: allocate a second set of processing resources to the computing unit based on a second instruction while executing the multiple waves.

[0039] In some implementations, the above-described devices and techniques are implemented in systems including one or more integrated circuit (IC) devices (also known as integrated circuit packages or microchips), such as those referenced above. Figures 1 to 5 The described processing system configures software-defined resource allocation. Electronic design automation (EDA) and computer-aided design (CAD) software tools can be used in the design and manufacture of these IC devices. These design tools are typically represented as one or more software programs. One or more software programs include code executable by a computer system to manipulate the computer system to operate on code representing circuitry of one or more IC devices to perform at least a portion of a process for designing or adapting a manufacturing system to manufacture the circuitry. The code may include instructions, data, or a combination of instructions and data. Software instructions representing design or manufacturing tools are typically stored in a computer-readable storage medium accessible to the computing system. Similarly, code representing one or more stages of the design or manufacture of an IC device may be stored in or accessed from the same computer-readable storage medium or different computer-readable storage media.

[0040] Computer-readable storage media may include any non-transitory storage medium or a combination of non-transitory storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., optical discs (CDs), digital versatile optical discs (DVDs), Blu-ray discs), magnetic media (e.g., floppy disks, magnetic tapes, or magnetic hard disks), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or microelectromechanical systems (MEMS) based storage media. Computer-readable storage media may be embedded in a computing system (e.g., system RAM or ROM), fixedly attached to a computing system (e.g., a magnetic hard disk drive), removably attached to a computing system (e.g., an optical disc or a flash memory based on a universal serial bus (USB)), or coupled to a computer system via a wired or wireless network (e.g., a network accessible storage device (NAS)).

[0041] In some implementations, certain aspects of the techniques described above may be implemented by one or more processors of a processing system executing the software. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied on a non-transitory computer-readable storage medium. The software may include instructions and certain data that, when executed by one or more processors, manipulate one or more processors to perform one or more aspects of the techniques described above. The non-transitory computer-readable storage medium may include, for example, disk or optical disk storage devices, solid-state storage devices such as flash memory, cache memory, random access memory (RAM), or one or more other non-volatile memory devices. The executable instructions stored on the non-transitory computer-readable storage medium may be source code, assembly language code, object code, or another instruction format that is interpreted or otherwise executed by one or more processors.

[0042] It should be noted that not all activities or elements described above in the general description are essential. A particular activity or part of the apparatus may not be essential, and one or more additional activities may be performed, or elements may be included in addition to those described. Furthermore, the order in which the activities are listed is not necessarily the order in which they are performed. Additionally, these concepts have been described with reference to specific embodiments. However, those skilled in the art will understand that various modifications and changes can be made without departing from the scope of this disclosure as set forth in the following claims. Therefore, the specification and drawings are to be considered illustrative rather than restrictive, and all such modifications are intended to be included within the scope of this disclosure.

[0043] The benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, the benefits, advantages, solutions to problems, and any features that may lead to or make any benefit, advantage, or solution appear or become more significant should not be construed as key, essential, or fundamental features of any or all claims. Furthermore, the specific embodiments disclosed above are merely illustrative, as the disclosed subject matter can be modified and practiced in different but equivalent ways that will be apparent to those skilled in the art who benefit from the teachings herein. No limitation is intended on the details of the constructions or designs shown herein, except as described in the following claims. Therefore, it will be apparent that the specific embodiments disclosed above can be changed or modified, and all such changes are considered to be within the scope of the disclosed subject matter. Therefore, the protection sought herein is set forth in the following claims.

Claims

1. A method, the method comprising: In response to receiving an instruction from the application identifying workgroups comprising multiple waves and identifying resource allocations for said multiple waves, a set of processing resources is allocated to the computing unit based on the resource allocations for said multiple waves; and The workgroup is executed using the set of processing resources allocated to the computing unit.

2. The method according to claim 1, further comprising: The instructions identifying the workgroup and the resource allocation for the multiple waves are stored in the local work queue.

3. The method according to claim 2, further comprising: In response to the computing unit executing a previous workgroup, data including the following items is requested from the local work queue: an identifier of the workgroup and instructions for the resource allocation for the plurality of waves.

4. The method according to any one of claims 1 to 3, further comprising: While the workgroup is being executed, a second set of processing resources is allocated to the workgroup based on a second instruction that identifies the workgroup.

5. The method according to any one of claims 1 to 4, wherein allocating the set of processing resources to the computing unit comprises: Based on the resource allocation for the plurality of waves, the same processing resources are allocated to two or more slots of the computing unit.

6. The method according to any one of claims 1 to 5, further comprising: The multiple waves of the working group are executed based on the synchronization data received from the application.

7. The method of claim 6, wherein the synchronization data identifier is a thread barrier for one of the plurality of waves.

8. The method of claim 6, wherein the synchronization data identifies two or more of the plurality of waves to be executed concurrently.

9. The method according to any one of claims 1 to 8, wherein the resource allocation identifier for the plurality of waves corresponds to a corresponding number of vector registers for each of the plurality of waves.

10. The method according to any one of claims 1 to 9, further comprising: The hardware registers are modified based on the resource allocation for the multiple waves.

11. A processing system, the processing system comprising: Memory; and A processor, coupled to the memory and configured to: receive from an application instruction identifying workgroups comprising multiple waves and identifying resource allocations for the multiple waves, wherein the processor includes: Multiple computing units, wherein at least one of the multiple computing units includes: A resource allocation module, configured to: allocate a set of processing resources to the at least one computing unit based on the resource allocation for the plurality of waves; and Multiple slots are configured to execute the workgroup using the set of processing resources allocated to the computing unit.

12. The processing system according to claim 11, further comprising: A local work queue, configured to store the instructions identifying the workgroup and the resource allocation for the plurality of waves.

13. The processing system of claim 12, wherein the at least one computing unit is configured to: In response to at least one computing unit executing a previous workgroup, data including the following items is requested from the local work queue: an identifier of the workgroup and instructions for the resource allocation for the plurality of waves.

14. The processing system according to any one of claims 11 to 13, wherein the resource allocation module is configured to: When the workgroup is executed, a second set of processing resources is allocated to one or more slots based on a second instruction that identifies the workgroup.

15. The processing system according to any one of claims 11 to 14, wherein the resource allocation module is configured to: Based on the resource allocation for the plurality of waves, the same processing resources are allocated to two or more of the plurality of wave slots.

16. The processing system according to any one of claims 11 to 15, wherein the processor is configured to: The application receives data identifying the corresponding thread barrier for one or more of the plurality of waves.

17. The processing system of any one of claims 11 to 16, wherein the processor further comprises a hardware register, and wherein the resource allocation module is configured to allocate the set of processing resources by modifying the hardware register based on the resource allocation for the plurality of waves.

18. The processing system according to any one of claims 11 to 17, wherein the resource allocation identifier for the plurality of waves is a corresponding amount of local data sharing for each of the plurality of waves.

19. A processor, the processor comprising: One or more processing cores, wherein the one or more processing cores are configured to: In response to receiving synchronization data for multiple waves and instructions identifying resource allocations for the multiple waves from the application, a set of processing resources is allocated to the computing unit based on the resource allocations for the multiple waves. as well as The multiple waves are executed using the set of processing resources allocated to the computing unit and based on the synchronization data.

20. The processor of claim 19, wherein the synchronization data identifier is a thread barrier for a wave among the plurality of waves.

21. The processor of claim 19 or claim 20, wherein the synchronization data identifies two or more of the plurality of waves to be executed concurrently.

22. The processor according to any one of claims 19 to 21, wherein the one or more processor cores are configured to: When executing the plurality of waves, a second set of processing resources is allocated to the computing unit based on a second instruction.

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