Cross-connection NPN band-gap reference circuit with high power supply ripple suppression capability

Abstract

The invention discloses a cross-connection NPN band-gap reference circuit with high power supply ripple suppression capability, which comprises a thermotropic current generation circuit, a reference voltage generation circuit and a curvature compensation circuit, and is characterized in that the thermotropic current generation circuit forms a voltage feedback network through a cross-connected NPN transistor pair to replace an operational amplifier clamping function; the current mirror structure is used for copying bias current to the NPN transistor pair to fix the voltage of each node, the reference voltage generation circuit is used for generating first-order reference voltage with a low temperature coefficient by combining the positive temperature current and the voltage characteristic of the NPN transistor, and the curvature compensation circuit is used for compensating the high-order temperature drift of the first-order reference voltage. According to the invention, an operational amplifier is replaced by the NPN transistor pair in cross connection, voltage negative feedback is formed through base-emitter interconnection, an operational amplifier module is omitted, the structure is simple, and the static power consumption is reduced; a node voltage self-stabilization mechanism formed by the cooperation of the current mirror and the fixed resistor eliminates the offset voltage influence of the operational amplifier.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to a cross-connected NPN bandgap reference circuit with high power supply ripple suppression capability. Background Technology

[0002] With the development of integrated circuit technology, bandgap reference circuits, as the core module of analog / mixed-signal chips, directly affect the system accuracy due to their temperature stability and power supply noise suppression capabilities. Traditional bandgap references typically require operational amplifiers to clamp the voltage and improve power supply ripple suppression capabilities. Moreover, the temperature coefficient of the output voltage in the first-order case is relatively high, making them unsuitable for circuit systems with high requirements for temperature drift and high power supply ripple suppression capabilities. Summary of the Invention

[0003] The purpose of this invention is to provide a cross-connected NPN bandgap reference circuit with high power supply ripple suppression capability to solve the above-mentioned problems.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] A cross-connected NPN bandgap reference circuit with high power supply ripple suppression capability includes a positive temperature current generation circuit, a reference voltage generation circuit, and a curvature compensation circuit. The positive temperature current generation circuit forms a voltage feedback network through cross-connected NPN transistor pairs to replace the operational amplifier clamping function, and uses a current mirror structure to replicate the bias current to fix the voltage of each node of the NPN transistor pairs. The reference voltage generation circuit is used to generate a first-order reference voltage with a low temperature coefficient by combining the positive temperature current and the voltage characteristics of the NPN transistors. The curvature compensation circuit is used to compensate for the high-order temperature drift of the first-order reference voltage.

[0006] Preferably, the positive temperature current generating circuit includes NPN transistors Q1, Q2, Q3, Q4, Q7, and Q8, resistors R3, R4, R5, and R6, MOSFETs M2 and M3; the drains of MOSFETs M2 and M3 are connected to a regulated voltage V. REG The source of MOS transistor M2 is connected to the collectors of NPN transistors Q1 and Q3, and the source of MOS transistor M3 is connected to the collectors of NPN transistors Q3 and Q4. The emitters of NPN transistors Q1 and Q2 are connected together and, together with the emitters of NPN transistors Q3 and Q4, are connected to resistors R3 and R4. The collector of NPN transistor Q7 is connected to a regulated voltage V. REGThe emitter of the NPN transistor Q7 is connected to the base of the NPN transistor Q8, and the emitter of the NPN transistor Q8 is grounded through resistors R5 and R6.

[0007] Preferably, the NPN transistors Q1, Q2, Q3, and Q4 are configured to form a proportional current mirror, wherein the area ratio of NPN transistors Q1 and Q2 is 1:4, and the area ratio of NPN transistors Q3 and Q4 is 4:1. The positive temperature current generating circuit generates a voltage proportional to absolute temperature by utilizing the negative temperature coefficient of the emitter junction voltage of the NPN transistors and the difference in emitter current of NPN transistors of different sizes.

[0008] Preferably, it further includes a bias current generating circuit for generating a stable bias current to provide a basic bias for subsequent circuits; the bias current generating circuit includes MOSFET M1 and MOSFET M2. B1 MOSFET B2 Resistors R1 and R2; the drain of the MOS transistor M1 is connected to a regulated voltage V. REG The source of the MOS transistor M1 is connected to the source of the MOS transistor M. B1 The drain of the MOS transistor M B1 The source resistor R1 is connected to the MOSFET. B2 The drain of the MOS transistor B2 The source of the resistor is grounded; the other end of the resistor R1 is connected to the gate of the MOSFET M1, and one end of the resistor R2 is connected to the gate of the MOSFET M2. B1 The source of the resistor is connected to ground at the other end of the resistor R2.

[0009] Preferably, the reference voltage generating circuit includes MOSFET M4, MOSFET M5, NPN transistor Q9, resistor R7, and resistor R8; the drains of MOSFETs M4 and M5 are connected to a regulated voltage potential V. REG The source of the MOS transistor M4 is connected to the collector of the resistor R8, the source of the MOS transistor M5 is connected to the collector of the NPN transistor Q9, and the emitter of the NPN transistor Q9 is connected to ground via a series connection of resistor R7 and resistor R8.

[0010] Preferably, the curvature compensation circuit includes MOSFETs M6, M7, M8, M9, and M1. 10 MOSFET M 11 and MOSFET M 12 The drain of the MOS transistor M6 is connected to a regulated voltage V. REG The source of MOSFET M6 is connected to the drain of MOSFET M7, and the source of MOSFET M7 is grounded. The drains of MOSFETs M8 and M9 are connected to the drain of MOSFET M7.10 MOSFET M 11 The source of the MOSFET M 10 MOSFET M 11 The drain is connected to the regulated voltage V. REG The MOS transistor M 12 Drain output compensation current I CU The MOS transistor M 12 The source of is connected to the drain of MOSFET M9, and the MOSFET M9... 12 The gate of the transistor is connected to the gate of the MOSFET M6.

[0011] Preferably, the MOSFETs M6, M7, M8, M9, and M... 10 MOSFET M 11 and MOSFET M 12 By combining multiple current mirrors, a sensitive current proportional to absolute temperature is generated, and a parabolic compensation current I is generated based on this sensitive current. CU Its temperature change curve is complementary to the temperature change curve of the first-order reference voltage of the reference voltage generation circuit, forming at least three extreme points to compensate for the nonlinear temperature drift of the first-order reference voltage.

[0012] Preferably, it further includes a temperature coefficient adjustment circuit for calibrating the temperature coefficient error of the first-order reference voltage; the temperature coefficient adjustment circuit includes a MOSFET M r1 MOSFET M r2 MOSFET M r3 MOSFET M r4 MOSFET M sw0 MOSFET M sw1 MOSFET M sw2 and MOSFET M sw3 The MOS transistor M r1 MOSFET M r2 MOSFET M r3 MOSFET M r4 The drain is connected to the regulated voltage V. REG The MOS transistor M r1 MOSFET M r2 MOSFET M r3 MOSFET M r4 The source of each is connected to the MOSFET M. sw0 MOSFET M sw1 MOSFET M sw2 MOSFET M sw3 The drain of the MOS transistor M sw0 MOSFET M sw1 MOSFET M sw2 MOSFET Msw3 The source of the MOS transistor is grounded. sw0 MOSFET M sw1 MOSFET M sw2 MOSFET M sw3 The MOS transistor M is controlled by switching signals S0, S1, S2, and S3 respectively. r1 MOSFET M r2 MOSFET M r3 MOSFET M r4 The gate of the MOSFET is shorted and connected to the MOSFET M. sw0 MOSFET M sw1 MOSFET M sw2 and MOSFET M sw3 The gates together constitute the adjustment current I. TC .

[0013] Preferably, the temperature coefficient adjustment circuit controls the adjustment current mirror array through switching signals S0, S1, S2, and S3 to adjust the adjustment current I. TC The magnitude of the value is determined and injected into the reference voltage generation circuit to calibrate the temperature coefficient error of the first-order reference voltage caused by process deviations or temperature drift.

[0014] Preferably, it further includes a startup circuit and a pre-regulatory circuit, which are used to guide the circuit into the working state and provide a regulated voltage V for subsequent circuits, respectively. REG The startup circuit includes capacitor C1 and MOSFET M. 22 and MOSFET M 23 The pre-regulator circuit includes a MOSFET M 13 MOSFET M 14 MOSFET M 15 MOSFET M 16 MOSFET M 17 MOSFET M 18 MOSFET M 19 MOSFET M 20 and MOSFET M 21 ;

[0015] One end of capacitor C1 is connected to a node within the startup circuit, and the MOS transistor M 22 The drain of the transistor is connected to capacitor C1 and the pre-regulator circuit, and the MOSFET M 22 The source of the MOSFET is connected to the M 23 The drain of the MOSFET M 23 The source is grounded;

[0016] The MOS transistor M 20 and MOSFET M 21 This forms a current mirror structure, wherein the MOS transistor M 20The drain and gate are connected to the positive terminal V of the power supply. DD The MOS transistor M 21 The drain output of the MOSFET is connected to the bias current generation circuit. 21 The gate and MOSFET M 20 The gate is connected to the MOSFET M 20 The current in the branch flows to the MOSFET M 21 Side road,

[0017] The MOS transistor M 13 The drain of the MOSFET is connected to the M 21 The common node led out from the drain of the MOS transistor M 13 The source is connected to the MOSFET M 17 The branch circuit formed by the MOS transistor M 14 The gate is connected to the bias potential terminal V. B The MOS transistor M 14 The drain of the MOSFET is connected to the M 13 The source-side related node, the MOS transistor M 14 The source pole is connected to the subsequent sub-branch;

[0018] The MOS transistor M 15 The drain of the MOSFET is connected to the common node in front of it. 15 The source of the MOSFET is connected to the M 16 The drain of the MOS transistor M 16 The source is grounded, forming a current discharge or current regulation branch;

[0019] The MOS transistor M 17 The drain of the MOS transistor is connected to the relevant node. 17 The source of the MOS transistor is grounded. 17 The gate of the MOSFET M 18 The drain of the MOS transistor M 18 The drain of the MOSFET is connected to the preceding node. 18 The source of the MOS transistor is grounded. 18 The gate and MOSFET M 19 The gate connection forms a control relationship, and the MOS transistor M 19 The drain of the MOSFET is connected to the node of the startup circuit and the pre-regulator circuit. 19 The source of the MOS transistor is grounded. 19 The gate of the circuit is connected to the corresponding control node to jointly regulate the current and voltage of the pre-regulated circuit.

[0020] By adopting the above technical solution, the present invention has the following advantages compared with the prior art:

[0021] 1. This invention provides a cross-connected NPN bandgap reference circuit with high power supply ripple suppression capability. It uses cross-connected NPN transistor pairs to replace operational amplifiers and forms voltage negative feedback through base-emitter interconnection, eliminating the need for operational amplifier modules, simplifying the structure and reducing static power consumption. At the same time, the node voltage self-stabilization mechanism formed by the current mirror and fixed resistor eliminates the influence of operational amplifier offset voltage.

[0022] 2. This invention provides a cross-connected NPN bandgap reference circuit with high power supply ripple suppression capability. The curvature compensation circuit generates a parabolic compensation current, whose temperature curve rises slowly in the first half and steeply in the second half, complementing the temperature curve of the first-order reference voltage to form a three-extreme-point temperature curve, further reducing the temperature coefficient of the bandgap reference circuit and giving it better performance indicators.

[0023] 3. This invention provides a cross-connected NPN bandgap reference circuit with high power supply ripple suppression capability. The input terminal of the pre-regulator circuit is connected to the power supply voltage and noise is isolated from the power supply voltage. Its output terminal generates a regulated signal to power the bias circuit and the positive temperature coefficient current generation circuit. The temperature coefficient adjustment circuit corrects the temperature coefficient error of the first-order reference voltage caused by calibration process deviation or temperature drift in the reference voltage generation circuit. The pre-regulator circuit and the adjustment circuit work together to simultaneously improve the power supply rejection ratio and process tolerance. Attached Figure Description

[0024] Figure 1 This is a circuit structure diagram of the present invention;

[0025] Figure 2 This is a schematic diagram of the curvature compensation circuit of the present invention.

[0026] Figure 3 This is a small-signal analog circuit diagram of the power supply rejection ratio of this invention;

[0027] Figure 4 This is a diagram illustrating the bandgap reference voltage effect of the circuit of this invention.

[0028] Figure 5 This is a diagram showing the power supply rejection ratio of the circuit of the present invention. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0030] Example

[0031] Please refer to Figures 1 to 5As shown, this invention discloses a cross-connected NPN bandgap reference circuit with high power supply ripple suppression capability, including a startup circuit, a pre-regulation circuit, a bias current generation circuit, a positive temperature current generation circuit, a reference voltage generation circuit, a curvature compensation circuit, and a temperature coefficient adjustment circuit. The startup circuit and the pre-regulation circuit are used to guide the circuit into the working state and provide a regulated voltage potential V for subsequent circuits, respectively. REG The bias current generation circuit generates a stable bias current to provide a basic bias for subsequent circuits. The positive temperature current generation circuit forms a voltage feedback network through cross-connected NPN transistor pairs to replace the operational amplifier clamping function. The bias current is replicated to the NPN transistor pairs by a current mirror structure to fix the voltage at each node. The reference voltage generation circuit combines the positive temperature current and the voltage characteristics of the NPN transistors to generate a first-order reference voltage with a low temperature coefficient. The curvature compensation circuit is used to compensate for the high-order temperature drift of the first-order reference voltage. The temperature coefficient adjustment circuit is used to calibrate the temperature coefficient error of the first-order reference voltage.

[0032] The startup circuit includes capacitor C1 and MOSFET M. 22 and MOSFET M 23 The pre-regulator circuit includes a MOSFET M 13 MOSFET M 14 MOSFET M 15 MOSFET M 16 MOSFET M 17 MOSFET M 18 MOSFET M 19 MOSFET M 20 and MOSFET M 21 ;

[0033] One end of capacitor C1 is connected to a node within the startup circuit, and MOSFET M... 22 The drain is connected to capacitor C1 and the pre-regulator circuit, and the MOSFET M 22 The source of the MOSFET is connected to the M 23 The drain of the MOSFET M 23 The source is grounded;

[0034] MOSFET M 20 and MOSFET M 21 This forms a current mirror structure, with MOSFET M 20 The drain and gate are connected to the positive terminal V of the power supply. DD MOS transistor M 21 The drain output is connected to the bias current generation circuit, and the MOSFET M 21 The gate and MOSFET M 20 The gate is connected to the MOSFET M 20 The current in the branch flows to the MOSFET M 21 Side road,

[0035] MOSFET M 13 The drain of the MOSFET is connected to the M 21 The common node led out from the drain of the MOSFET M 13 The source is connected to the MOSFET M 17 The branch circuit formed by the MOSFET M 14 The gate is connected to the bias potential terminal V. B MOS transistor M 14 The drain of the MOSFET is connected to the M 13 The source-side related nodes, MOSFET M 14 The source pole is connected to the subsequent sub-branch;

[0036] MOSFET M 15 The drain of the MOSFET is connected to the common node in front of it. 15 The source of the MOSFET is connected to the M 16 The drain of the MOSFET M 16 The source is grounded, forming a current discharge or current regulation branch;

[0037] MOSFET M 17 The drain of the MOSFET is connected to the relevant node. 17 The source of the MOSFET is grounded. 17 The gate of the MOSFET M 18 The drain of the MOSFET M 18 The drain of the MOSFET is connected to the previous node. 18 The source of the MOSFET is grounded. 18 The gate and MOSFET M 19 The gate connection forms a control relationship, MOSFET M 19 The drain is connected to the node of the startup circuit and the pre-regulator circuit, and the MOSFET M 19 The source of the MOSFET is grounded. 19 The gate of the circuit is connected to the corresponding control node to jointly regulate the current and voltage of the pre-regulator circuit.

[0038] At the moment the chip powers on, capacitor C1 is initially uncharged, causing MOSFET M to... 22 The gate voltage rises rapidly to turn on the MOSFET, thereby enabling the MOSFET M to conduct. 23 The circuit is turned on, providing startup current to subsequent circuits and helping the circuit recover from its initial unstable degeneracy point state. As the circuit operates normally and establishes a stable potential, capacitor C1 completes charging, and MOSFET M... 22 When the gate potential is pulled low and cut off, the startup circuit automatically stops working, avoiding interference with the normal operating circuit. This startup circuit has a simple structure, starts up quickly and reliably, and can help the circuit enter the normal operating state in a very short time. The automatic shutdown mechanism effectively avoids additional power consumption and potential interference, improving the overall stability and reliability of the circuit.

[0039] The pre-regulator circuit, consisting of a current mirror structure, a voltage divider structure, and a feedback control structure composed of multiple MOSFETs, performs preliminary voltage regulation on the input power supply voltage. It uses the current mirror to replicate a stable current, and through the on-resistance of the MOSFETs and feedback adjustment, it attenuates ripple and noise in the power supply voltage, outputting a relatively stable regulated voltage V. REG It supplies power to subsequent circuits. For example, when the power supply voltage fluctuates and causes the regulated potential V to rise... REG During the rise, MOSFET M 13 The feedback branch composed of MOSFETs will adjust the current to maintain the regulated voltage V. REG The voltage drops back to a stable value. This pre-regulator circuit significantly improves the circuit's ability to suppress power supply ripple, providing a stable supply voltage for the subsequent bandgap reference core circuit, greatly reducing the impact of power supply fluctuations on the reference circuit performance, thereby improving the power supply ripple rejection ratio of the entire bandgap reference circuit.

[0040] Furthermore, since the bandgap reference needs to provide an "absolutely pure" reference voltage for modules such as ADCs and DACs, and power lines often carry the following noises: low-frequency ripple and high-frequency switching noise, the higher the PSRR, the less the power supply noise affects the output voltage, and the higher the system accuracy. The input of the pre-regulator circuit is connected to the power supply voltage and provides noise isolation for the power supply voltage. Its output generates a regulated signal to power the bias circuit and the positive temperature coefficient current generation circuit.

[0041] The bias current generation circuit includes MOSFET M1 and MOSFET M2. B1 MOSFET B2 Resistors R1 and R2; the drain of MOSFET M1 is connected to the regulated voltage V. REG The source of MOSFET M1 is connected to MOSFET M. B1 The drain of the MOSFET M B1 The source resistor R1 is connected to the MOSFET. B2 The drain of the MOSFET B2 The source of the transistor is grounded; the other end of resistor R1 is connected to the gate of MOSFET M1, and one end of resistor R2 is connected to the gate of MOSFET M2. B1 The source of resistor R2 is grounded.

[0042] The bias current generation circuit utilizes the conduction characteristics of the MOSFET and resistor voltage division, combined with a negative feedback mechanism, to generate a stable bias current. When the bias current changes due to external factors, the self-biasing loop automatically adjusts the conduction level of the MOSFET to maintain the stability of the bias current, providing a stable operating bias for positive temperature coefficient current generation circuits, output voltage generation circuits, etc. This process reduces dependence on complex external bias circuits, improves circuit integration, and can adaptively adjust the bias current according to the internal operating state of the circuit, enhancing the stability of the circuit under different operating conditions.

[0043] The positive temperature current generating circuit includes NPN transistors Q1, Q2, Q3, Q4, Q7, and Q8, resistors R3, R4, R5, and R6, and MOSFETs M2 and M3; the sources of MOSFETs M2 and M3 are connected to a regulated voltage V. REG The drain of MOSFET M2 is connected to the collectors of NPN transistors Q1 and Q3, and the drain of MOSFET M3 is connected to the collectors of NPN transistors Q3 and Q4. The emitters of NPN transistors Q1 and Q2 are connected together and, together with the emitters of NPN transistors Q3 and Q4, are connected to resistors R3 and R4. The collector of NPN transistor Q7 is connected to a regulated voltage V. REG The emitter of NPN transistor Q7 is connected to the base of NPN transistor Q8, and the emitter of NPN transistor Q8 is grounded through resistors R5 and R6.

[0044] The negative temperature coefficient (V) of the base-emitter voltage of an NPN transistor BE ) and V under emitter current of NPN transistors of different sizes BE Difference (ΔV) BE The characteristic of being proportional to absolute temperature. By using cross-connected pairs of NPN transistors, a self-clamping function for the node voltage is achieved, replacing the traditional op-amp structure to stabilize the circuit operating point.

[0045] NPN transistors Q1 and Q2, respectively, form current mirror structures with specific area ratios: NPN transistors Q1, Q2, Q3, and Q4. These structures work together to form a proportional current mirror, where the area ratio of NPN transistors Q1 to Q2 is 1:4, and the area ratio of NPN transistors Q3 to Q4 is 4:1. The positive temperature current generation circuit utilizes the negative temperature coefficient of the emitter junction voltage of the NPN transistors and the differences in emitter currents of NPN transistors of different sizes to generate a voltage proportional to absolute temperature.

[0046] After NPN transistors Q1 and Q2 are cross-connected, the collector of NPN transistor Q1 is connected to the base of NPN transistor Q2, and the collector of NPN transistor Q2 is connected to the base of NPN transistor Q1. This feedback between the two stabilizes the node voltage. Combined with the bias current provided by the bias circuit, a positive temperature coefficient (PTAT) current is generated across resistors R3 and R4. This cross-connected NPN transistor pair simplifies circuit design, reduces reliance on operational amplifiers, and decreases circuit power consumption and area. Furthermore, this structure is highly responsive to temperature changes and can accurately generate a PTAT current, providing an accurate current component for subsequent temperature compensation.

[0047] For example, I Bias With resistor R3 fixed, the emitter voltage of NPN transistor Q4 is fixed. Then, according to the formula... V T For thermal voltage, I S Given that IQ4 is the saturation current of NPN transistor Q4, we know that IQ4 is fixed, and V BEQ4 Since the base voltage of NPN transistor Q4 is also fixed, the base and emitter voltages of NPN transistors Q1, Q2, and Q3 are also fixed.

[0048] The reference voltage generation circuit includes MOSFETs M4 and M5, NPN transistor Q9, resistors R7 and R8; the drains of MOSFETs M4 and M5 are connected to a regulated voltage V. REG The source of MOSFET M4 is connected to the collector of resistor R8, and the source of MOSFET M5 is connected to the collector of NPN transistor Q9. The emitter of NPN transistor Q9 is connected to ground via resistors R7 and R8 in series. The regulated voltage V... REG The connection node between the drain of MOSFET M5 and the collector of NPN transistor Q9 is used to combine the positive temperature current and the voltage characteristics of BJT (bipolar NPN transistor) to generate a low temperature coefficient reference voltage.

[0049] This circuit combines the positive temperature coefficient (PTC) current output from the PTC current generation circuit with the characteristics of an NPN transistor. The PTC current generates a voltage drop across resistors R7 and R8, which is related to the voltage drop across NPN transistor Q9. BE By superimposing these parameters, a preliminary reference voltage prototype with certain temperature characteristics is generated. Through reasonable configuration of resistor values ​​and transistor parameters, the positive and negative temperature coefficients compensate for each other, reducing the drift of the reference voltage with temperature. This achieves temperature compensation to a certain extent, generating a relatively stable reference voltage prototype, providing a foundation for subsequent curvature compensation. Furthermore, the circuit structure is simple and easy to integrate with other modules.

[0050] The curvature compensation circuit includes MOSFETs M6, M7, M8, M9, and M1. 10 MOSFET M 11 and MOSFET M 12 The drain of MOSFET M6 is connected to the regulated voltage V. REG The source of MOSFET M6 is connected to the drain of MOSFET M7, the source of MOSFET M7 is grounded, and the drains of MOSFETs M8 and M9 are connected to the drain of MOSFET M7. 10 MOSFET M 11 The source of the MOSFET M 10 MOSFET M 11 The drain is connected to the regulated voltage V. REG ; MOS transistor M 12 Drain output compensation current I CU MOS transistor M 12 The source is connected to the drain of MOSFET M9, and MOSFET M 12 The gate of the transistor is connected to the gate of the MOSFET M6.

[0051] MOSFET M6, MOSFET M7, MOSFET M8, MOSFET M9, MOSFET M 10 MOSFET M 11 and MOSFET M 12 By combining multiple current mirrors, a sensitive current proportional to absolute temperature is generated, and a parabolic compensation current I is generated based on this sensitive current. CU Its temperature change curve is complementary to the temperature change curve of the first-order reference voltage of the reference voltage generation circuit, forming at least three extreme points to compensate for the nonlinear temperature drift of the first-order reference voltage.

[0052] By utilizing the nonlinearity (i.e., "curvature") of the current-voltage characteristics of a MOSFET at different temperatures, a multi-stage current mirror structure is used to precisely replicate and adjust the current, generating a compensating current I that is opposite to the higher-order temperature term. CU When the temperature changes, the current in the current mirror changes according to a specific ratio, and the compensation current I... CU This is used to counteract high-order temperature drift in the reference voltage prototype of the output voltage generation circuit, further improving the temperature stability of the reference voltage. By flexibly adjusting the current mirror scaling factor, the magnitude and variation of the compensation current can be precisely controlled, effectively adapting to the high-order compensation requirements under different process conditions and temperature ranges, and significantly improving the temperature stability of the reference voltage.

[0053] Temperature coefficient adjustment circuit includes MOSFET M r1 MOSFET M r2 MOSFET M r3 MOSFET M r4 MOSFET Msw0 MOSFET M sw1 MOSFET M sw2 and MOSFET M sw3 ; MOS transistor M r1 MOSFET M r2 MOSFET M r3 MOSFET M r4 The drain is connected to the regulated voltage V. REG MOS transistor M r1 MOSFET M r2 MOSFET M r3 MOSFET M r4 The source of each is connected to the MOSFET M. sw0 MOSFET M sw1 MOSFET M sw2 MOSFET M sw3 The drain of the MOSFET M sw0 MOSFET M sw1 MOSFET M sw2 MOSFET M sw3 The source of the MOSFET is grounded. sw0 MOSFET M sw1 MOSFET M sw2 MOSFET M sw3 The MOSFETs are controlled by switching signals S0, S1, S2, and S3 respectively. r1 MOSFET M r2 MOSFET M r3 MOSFET M r4 The gate of the MOSFET is shorted and connected to the MOSFET M. sw0 MOSFET M sw1 MOSFET M sw2 and MOSFET M sw3 The gates together constitute the adjustment current I. TC .

[0054] The temperature coefficient adjustment circuit controls the MOSFET M through switching signals S0, S1, S2, and S3. sw0 MOSFET M sw1 MOSFET M sw2 and MOSFET M sw3 The switching on and off of the MOSFET changes the MOSFET's state. r1 MOSFET M r2 MOSFET M r3 MOSFET M r4 The effective current path, thereby precisely adjusting the adjustment current I. TC The magnitude of the current. Adjustment current I TCInjected into the output voltage generation circuit or other relevant nodes, it calibrates the temperature coefficient error of the first-order reference voltage caused by process deviations or temperature drift.

[0055] In this embodiment, the temperature change curve of the first-order reference voltage (Vref1) is ensured to decrease slowly in the first half and decrease rapidly in the second half during curvature compensation. The temperature curve of the parabolic compensation current increases slowly in the first half and rises sharply in the second half, complementing the temperature curve of the first-order reference voltage to form a three-extreme-point temperature curve. This further reduces the temperature coefficient of the bandgap reference circuit, giving it better performance indicators.

[0056] Depend on Figure 4 and Figure 5 It can be concluded that the bandgap reference circuit of this embodiment has a reference voltage output of 1.126V in the temperature range of -40℃ to 125℃. After the curvature compensation circuit is compensated, three extreme points are formed at -40℃, 25℃ and 125℃. The average TC (temperature coefficient) is 7.70ppm / ℃ and the PSRR (power supply rejection ratio) reaches -122dB at 1kHz.

[0057] The above are merely preferred embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A cross-connected NPN bandgap reference circuit with high power supply ripple suppression capability, characterized in that: The system includes a positive temperature current generation circuit, a reference voltage generation circuit, and a curvature compensation circuit. The positive temperature current generation circuit forms a voltage feedback network through cross-connected NPN transistor pairs to replace the operational amplifier clamping function, and uses a current mirror structure to replicate the bias current to the NPN transistor pairs to fix the voltage at each node. The reference voltage generation circuit is used to generate a first-order reference voltage with a low temperature coefficient by combining the positive temperature current and the voltage characteristics of the NPN transistors. The curvature compensation circuit is used to compensate for the high-order temperature drift of the first-order reference voltage.

2. The cross-connected NPN bandgap reference circuit with high power supply ripple suppression capability as described in claim 1, characterized in that: The positive temperature current generating circuit includes NPN transistors Q1, Q2, Q3, Q4, Q7, and Q8, resistors R3, R4, R5, and R6, and MOSFETs M2 and M3; the sources of MOSFETs M2 and M3 are connected to a regulated voltage V. REG The drain of MOS transistor M2 is connected to the collectors of NPN transistors Q1 and Q3, and the drain of MOS transistor M3 is connected to the collectors of NPN transistors Q3 and Q4. The emitters of NPN transistors Q1 and Q2 are connected together and, together with the emitters of NPN transistors Q3 and Q4, are connected to resistors R3 and R4. The collector of NPN transistor Q7 is connected to a regulated voltage V. REG The emitter of the NPN transistor Q7 is connected to the base of the NPN transistor Q8, and the emitter of the NPN transistor Q8 is grounded through resistors R5 and R6.

3. The cross-connected NPN bandgap reference circuit with high power supply ripple suppression capability as described in claim 2, characterized in that: The NPN transistors Q1, Q2, Q3, and Q4 are used together to form a proportional current mirror. The area ratio of NPN transistors Q1 and Q2 is 1:4, and the area ratio of NPN transistors Q3 and Q4 is 4:

1. The positive temperature current generating circuit generates a voltage proportional to absolute temperature by utilizing the negative temperature coefficient of the emitter junction voltage of the NPN transistors and the difference in emitter current of NPN transistors of different sizes.

4. The cross-connected NPN bandgap reference circuit with high power supply ripple suppression capability as described in claim 1, characterized in that: It also includes a bias current generation circuit for generating a stable bias current to provide a basic bias for subsequent circuits; the bias current generation circuit includes MOSFET M1 and MOSFET M2. B1 MOSFET B2, resistors R1 and R2; the drain of MOSFET M1 is connected to a regulated voltage V. REG The source of the MOS transistor M1 is connected to the MOS transistor M. B1 The drain of the MOS transistor M B1 The source of MOSFET B1 is connected to the drain of MOSFET B2 via resistor R1, and the source of MOSFET B2 is grounded. The other end of resistor R1 is connected to the gate of MOSFET M1, and one end of resistor R2 is connected to the gate of MOSFET M2. B1 The source of the resistor is connected to ground at the other end of the resistor R2.

5. The cross-connected NPN bandgap reference circuit with high power supply ripple suppression capability as described in claim 1, characterized in that: The reference voltage generation circuit includes MOSFET M4, MOSFET M5, NPN transistor Q9, resistor R7, and resistor R8; the drains of MOSFETs M4 and M5 are connected to a regulated voltage V. REG The source of the MOS transistor M4 is connected to the collector of the resistor R8, the source of the MOS transistor M5 is connected to the collector of the NPN transistor Q9, and the emitter of the NPN transistor Q9 is connected to ground via a series connection of resistor R7 and resistor R8.

6. The cross-connected NPN bandgap reference circuit with high power supply ripple suppression capability as described in claim 5, characterized in that: The curvature compensation circuit includes MOSFETs M6, M7, M8, M9, and M1. 10 MOSFET M 11 and MOSFET M 12 The drain of the MOS transistor M6 is connected to a regulated voltage V. REG The source of MOSFET M6 is connected to the drain of MOSFET M7, and the source of MOSFET M7 is grounded. The drains of MOSFETs M8 and M9 are connected to the drain of MOSFET M7. 10 MOSFET M 11 The source of the MOSFET M 10 MOSFET M 11 The drain is connected to the regulated voltage V. REG The MOS transistor M 12 Drain output compensation current I CU The MOS transistor M 12 The source of is connected to the drain of MOSFET M9, and the MOSFET M9... 12 The gate of the transistor is connected to the gate of the MOSFET M6.

7. The cross-connected NPN bandgap reference circuit with high power supply ripple suppression capability as described in claim 6, characterized in that: The MOSFETs M6, M7, M8, M9, and M... 10 MOSFET M 11 and MOSFET M 12 By combining multiple current mirrors, a sensitive current proportional to absolute temperature is generated, and a parabolic compensation current I is generated based on this sensitive current. CU Its temperature change curve is complementary to the temperature change curve of the first-order reference voltage of the reference voltage generation circuit, forming at least three extreme points to compensate for the nonlinear temperature drift of the first-order reference voltage.

8. The cross-connected NPN bandgap reference circuit with high power supply ripple suppression capability as described in claim 1, characterized in that: It also includes a temperature coefficient adjustment circuit for calibrating the temperature coefficient error of the first-order reference voltage; the temperature coefficient adjustment circuit includes a MOSFET M r1 MOSFET M r2 MOSFET M r3 MOSFET M r4 MOSFET M sw0 MOSFET M sw1 MOSFET M sw2 and MOSFET M sw3 The MOS transistor M r1 MOSFET M r2 MOSFET M r3 MOSFET M r4 The drain is connected to the regulated voltage V. REG The MOS transistor M r1 MOSFET M r2 MOSFET M r3 MOSFET M r4 The source of each is connected to the MOSFET M. sw0 MOSFET M sw1 MOSFET M sw2 MOSFET M sw3 The drain of the MOS transistor M sw0 MOSFET M sw1 MOSFET M sw2 MOSFET M sw3 The source of the MOS transistor is grounded. sw0 MOSFET M sw1 MOSFET M sw2 MOSFET M sw3 The MOS transistor M is controlled by switching signals S0, S1, S2, and S3 respectively. r1 MOSFET M r2 MOSFET M r3 MOSFET M r4 The gate of the MOSFET is shorted and connected to the MOSFET M. sw0 MOSFET M sw1 MOSFET M sw2 and MOSFET M sw3 The gates together constitute the adjustment current I. TC .

9. The cross-connected NPN bandgap reference circuit with high power supply ripple suppression capability as described in claim 8, characterized in that: The temperature coefficient adjustment circuit controls the adjustment current mirror array through switching signals S0, S1, S2, and S3 to adjust the adjustment current I. TC The magnitude of the value is determined and injected into the reference voltage generation circuit to calibrate the temperature coefficient error of the first-order reference voltage caused by process deviations or temperature drift.

10. A cross-connected NPN bandgap reference circuit with high power supply ripple suppression capability as described in claim 4, characterized in that: It also includes a startup circuit and a pre-regulatory circuit, which are used to guide the circuit into the working state and provide a regulated voltage V for subsequent circuits, respectively. REG The startup circuit includes capacitor C1 and MOSFET M. 22 and MOSFET M 23 The pre-regulator circuit includes a MOSFET M 13 MOSFET M 14 MOSFET M 15 MOSFET M 16 MOSFET M 17 MOSFET M 18 MOSFET M 19 MOSFET M 20 and MOSFET M 21 ; One end of capacitor C1 is connected to a node within the startup circuit, and the MOS transistor M 22 The drain of the transistor is connected to capacitor C1 and the pre-regulator circuit, and the MOSFET M 22 The source of the MOSFET is connected to the M 23 The drain of the MOSFET M 23 The source is grounded; The MOS transistor M 20 and MOSFET M 21 This forms a current mirror structure, wherein the MOS transistor M 20 The drain and gate are connected to the positive terminal V of the power supply. DD The MOS transistor M 21 The drain output of the MOSFET is connected to the bias current generation circuit. 21 The gate and MOSFET M 20 The gate is connected to the MOSFET M 20 The current in the branch flows to the MOSFET M 21 Side road, The MOS transistor M 13 The drain of the MOSFET is connected to the M 21 The common node led out from the drain of the MOS transistor M 13 The source is connected to the MOSFET M 17 The branch circuit formed by the MOS transistor M 14 The gate is connected to the bias potential terminal V. B The MOS transistor M 14 The drain of the MOSFET is connected to the M 13 The source-side related node, the MOS transistor M 14 The source pole is connected to the subsequent sub-branch; The MOS transistor M 15 The drain of the MOSFET is connected to the common node in front of it. 15 The source of the MOSFET is connected to the M 16 The drain of the MOS transistor M 16 The source is grounded, forming a current discharge or current regulation branch; The MOS transistor M 17 The drain of the MOS transistor is connected to the relevant node. 17 The source of the MOS transistor is grounded. 17 The gate of the MOSFET M 18 The drain of the MOS transistor M 18 The drain of the MOSFET is connected to the preceding node. 18 The source of the MOS transistor is grounded. 18 The gate and MOSFET M 19 The gate connection forms a control relationship, and the MOS transistor M 19 The drain of the MOSFET is connected to the node of the startup circuit and the pre-regulator circuit. 19 The source of the MOS transistor is grounded. 19 The gate of the circuit is connected to the corresponding control node to jointly regulate the current and voltage of the pre-regulated circuit.

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