Data access method and device, electronic equipment and storage medium

Abstract

The application discloses a data access method and device, electronic equipment and a storage medium. The data access method comprises the following steps: obtaining a target access feature of a target memory region in a target program running process; determining a cache attribute corresponding to the target memory region according to the target access feature; performing data access according to a cache process when the cache attribute corresponding to the target memory region is a cacheable attribute; and performing data access in a main memory by skipping the cache when the cache attribute corresponding to the target memory region is an uncacheable attribute. The technical scheme provided by the application can dynamically determine the cache attribute of the memory region, and improve the cache resource utilization efficiency and the data access efficiency.

Description

Technical Field

[0001] This application relates to the field of computer application technology, and in particular to a data access method, apparatus, electronic device and storage medium. Background Technology

[0002] In computer architecture, cache is a key component connecting the central processing unit (CPU) and main memory. It can compensate for the speed difference between the CPU and main memory by temporarily storing frequently accessed data.

[0003] In traditional memory management, the cache attributes (cacheable or non-cacheable) of memory regions are typically statically configured. For example, architectures such as Advanced RISC Machines (ARM) and x86 use memory attribute registers (such as ARM's Memory Protection Unit (MPU) and x86's page attributes) to mark the cache attributes of memory regions during system initialization, or they are preset according to fixed rules (such as address range division).

[0004] This static configuration approach may reduce cache resource utilization and data access efficiency. For example, for a large block of data, if the cache attribute of its memory region is pre-marked as cacheable, it needs to be loaded into the cache. However, this data has no need for reuse in the short term, and the cache entries it occupies may be replaced later, making it impossible to hit the cache when accessed again, reducing the cache hit rate, increasing data access latency, reducing data access efficiency, and increasing cache loading overhead. At the same time, such data crowds out cache space that can be used for frequently accessed data, affecting the utilization efficiency of cache resources. Summary of the Invention

[0005] The purpose of this application is to provide a data access method, apparatus, electronic device, and storage medium to dynamically determine the cache attributes of memory regions, thereby improving cache resource utilization efficiency and data access efficiency.

[0006] To solve the above-mentioned technical problems, this application provides the following technical solution:

[0007] Firstly, a data access method is provided, including:

[0008] Obtain the target access characteristics of the target memory region during the execution of the target program;

[0009] determining, according to the target access feature, a cache attribute corresponding to the target memory region;

[0010] in a case where the cache attribute corresponding to the target memory region is the cacheable attribute, performing data access according to a cache process;

[0011] in a case where the cache attribute corresponding to the target memory region is the non-cacheable attribute, skipping cache and performing data access in main memory.

[0012] Optionally, the determining, according to the target access feature, of the cache attribute corresponding to the target memory region comprises:

[0013] determining, according to the target access feature, whether the target memory region satisfies a target condition;

[0014] if the target condition is satisfied, determining that the cache attribute corresponding to the target memory region is the non-cacheable attribute;

[0015] if the target condition is not satisfied, determining that the cache attribute corresponding to the target memory region is the cacheable attribute;

[0016] wherein the target condition comprises:

[0017] the target memory region is a continuous memory region;

[0018] an address length of the target memory region is greater than or equal to a first threshold value;

[0019] an access time interval corresponding to the target memory region is greater than or equal to a second threshold value.

[0020] Optionally, whether the target memory region is a continuous memory region is determined by the following steps:

[0021] in a case where, in the target memory region, a start address of a second access operation is equal to a start address of a first access operation plus an access data block size of the first access operation, the target memory region is determined to be a continuous memory region;

[0022] in a case where, in the target memory region, a start address of a second access operation is not equal to a start address of a first access operation plus an access data block size of the first access operation, the target memory region is determined to be not a continuous memory region.

[0023] Optionally, the first threshold value and / or the second threshold value are dynamically configured based on a current application scenario.

[0024] Optionally, after the determining of the cache attribute corresponding to the target memory region, the method further comprises:

[0025] updating, in a cache attribute metadata table, a cache attribute corresponding to the target memory region.

[0026] Optionally, in a case where the data access comprises data reading, the data access according to the cache procedure comprises:

[0027] reading data of the target memory region from the cache;

[0028] in a case of cache hit, returning the data read from the cache to the target program;

[0029] in a case of cache miss, reading data of the target memory region from the main memory, and returning the data read from the main memory to the target program after loading the data into the cache.

[0030] Optionally, in a case where the data access comprises data writing, the data access according to the cache procedure comprises:

[0031] writing data into a position corresponding to the target memory region in the cache;

[0032] updating data in the main memory according to a cache consistency protocol.

[0033] In a second aspect, a data access apparatus is provided, comprising:

[0034] an obtaining module configured to obtain a target access feature of a target memory region in a running process of a target program;

[0035] a determining module configured to determine a cache attribute corresponding to the target memory region according to the target access feature;

[0036] a first access module configured to perform data access according to a cache procedure in a case where the cache attribute corresponding to the target memory region is a cacheable attribute;

[0037] a second access module configured to skip cache and perform data access in the main memory in a case where the cache attribute corresponding to the target memory region is an uncacheable attribute.

[0038] In a third aspect, an electronic device is provided, comprising:

[0039] a memory configured to store a computer program;

[0040] a processor configured to implement steps of the data access method according to the first aspect when executing the computer program.

[0041] In a fourth aspect, a computer readable storage medium is provided, and the computer readable storage medium has stored thereon a computer program, which, when executed by a processor, implements the steps of the data access method according to the first aspect.

[0042] In a fifth aspect, a computer program product is provided, and the computer program product comprises computer instructions stored in a computer readable storage medium and adapted to be read and executed by a processor to cause a computer device having the processor to perform the steps of the data access method according to the first aspect.

[0043] According to the technical solution provided in the embodiments of the present application, after the target access feature of the target memory region in the running process of the target program is acquired, the cache attribute corresponding to the target memory region is determined according to the target access feature. If the cache attribute corresponding to the target memory region is a cacheable attribute, data access is performed according to the cache process. If the cache attribute corresponding to the target memory region is a non-cacheable attribute, the cache is skipped and data access is performed in the main memory. The cache attribute corresponding to the target memory region is not pre-configured statically, but is determined dynamically based on the target access feature of the target memory region. Therefore, data access can be performed according to the cache attribute corresponding to the target memory region which is determined dynamically, which helps to improve the cache resource utilization efficiency and the data access efficiency. For example, for a large block of data, if the cache attribute of the memory region where the data is located is determined to be a non-cacheable attribute, the cache can be skipped and data access can be directly performed in the main memory, which reduces the data access delay, improves the data access efficiency, reduces the cache loading overhead, and at the same time, can avoid occupying the cache space that can be used for high-frequency access data, thereby improving the utilization efficiency of the cache resource.

[0044] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the drawings needed to be used in the embodiments or the related art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0046] Figure 1 An implementation flowchart of a data access method in the embodiments of the present application;

[0047] Figure 2 A structural schematic diagram of a data access system in the embodiments of the present application;

[0048] Figure 3 FIG. 1 is a schematic diagram of a data access process according to an embodiment of the present application;

[0049] Figure 4 FIG. 2 is a schematic diagram of a data access device according to an embodiment of the present application;

[0050] Figure 5 FIG. 3 is a schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0051] The technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present application.

[0052] The terms "first", "second", and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than that illustrated or described herein, and the objects distinguished by "first", "second" are usually a category and do not limit the number of objects, for example, the first object can be one or more.

[0053] Referring to Figure 1 FIG. 1 is a schematic diagram of a data access method according to an embodiment of the present application, which can include the following steps:

[0054] S110: Obtain a target access feature of a target memory region in a running process of a target program.

[0055] In the embodiments of the present application, the target program can be any program deployed in a computer system, and the target memory region is a range of memory addresses accessed by the target program in a running process, which can be a subset of the address space of the target program. When the target program runs, data in the target memory region can be accessed. Data access can include data reading and / or data writing.

[0056] The running process of the target program can be monitored to obtain the target access feature of the target memory region in the running process of the target program. The target access feature can include an access address feature, an access block size feature, and an access time feature.

[0057] S120: Determine a cache attribute corresponding to the target memory region according to the target access feature.

[0058] After the target access feature of the target memory region in the running process of the target program is acquired, the target access feature can be further analyzed, and according to the analysis result, the cache attribute corresponding to the target memory region is determined.

[0059] Optionally, the access address feature, the access block size feature and the access time feature can be analyzed respectively to obtain an analysis result corresponding to the access address feature, an analysis result corresponding to the access block size feature and an analysis result corresponding to the access time feature, and the cache attribute corresponding to the target memory region is determined by comprehensively analyzing the analysis result corresponding to the access address feature, the analysis result corresponding to the access block size feature and the analysis result corresponding to the access time feature.

[0060] The cache attribute corresponding to the memory region includes a cacheable attribute and a non-cacheable attribute. If it is determined that the cache attribute corresponding to the target memory region is the cacheable attribute, it can be considered that the data of the target memory region has reusability. If the cache attribute corresponding to the target memory region is the non-cacheable attribute, it can be considered that the data of the target memory region has non-reusability or has no reusability, or that the data of the target memory region is one-time access data.

[0061] If the target access feature changes, the cache attribute of the target memory region determined according to the target access feature can also change. The cache attribute of the target memory region determined dynamically matches the current access scenario.

[0062] S130: In the case that the cache attribute corresponding to the target memory region is the cacheable attribute, data access is performed according to a cache process.

[0063] S140: In the case that the cache attribute corresponding to the target memory region is the non-cacheable attribute, cache is skipped and data access is performed in the main memory.

[0064] In the embodiment of the present application, after the cache attribute corresponding to the target memory region is determined according to the target access feature, data access can be further performed according to the cache attribute corresponding to the target memory region.

[0065] Optionally, if the cache attribute corresponding to the target memory region is the cacheable attribute, it can be considered that the data of the target memory region has reusability, and the probability of being accessed again in the short term is relatively high, and data access can be performed according to the cache process. The cache process can be understood as a traditional cache process.

[0066] Optionally, if the cache attribute corresponding to the target memory region is the non-cacheable attribute, it can be considered that the data of the target memory region has non-reusability or has no reusability, and the probability of being accessed again in the short term is relatively low, and cache can be skipped and data access can be performed in the main memory.

[0067] Optionally, if the determined cache attribute of the target memory region is adjusted from the cacheable attribute to the non-cacheable attribute, in the case that the cache entry corresponding to the target memory region exists in the cache, the cache entry corresponding to the target memory region can be marked as invalid, or the cache entry corresponding to the target memory region is cleared, or the cache entry corresponding to the target memory region is marked as invalid and then it is determined whether to write back to the main memory according to the need, which helps to release the cache space in time.

[0068] Optionally, if the determined cache attribute of the target memory region is adjusted from the non-cacheable attribute to the cacheable attribute, in the case that the cache entry corresponding to the target memory region does not exist in the cache, the cache entry corresponding to the target memory region can be created in the cache to utilize the cache to improve the data access speed.

[0069] By applying the method provided in the embodiments of the present application, the target access feature of the target memory region in the running process of the target program is obtained, and then the cache attribute corresponding to the target memory region is determined according to the target access feature. If the cache attribute corresponding to the target memory region is the cacheable attribute, the data access is performed according to the cache process, and if the cache attribute corresponding to the target memory region is the non-cacheable attribute, the cache is skipped and the data access is performed in the main memory. The cache attribute corresponding to the target memory region is not pre-configured statically, but is determined dynamically based on the target access feature of the target memory region, so that the data access of the corresponding process can be performed according to the dynamically determined cache attribute of the target memory region, which helps to improve the cache resource utilization efficiency and the data access efficiency. For example, for a large block of data, if the dynamically determined cache attribute of the memory region where the data is located is the non-cacheable attribute, the cache can be skipped and the data access is directly performed in the main memory, which reduces the data access delay, improves the data access efficiency, reduces the cache loading overhead, and at the same time, can avoid occupying the cache space that can be used for high-frequency access data, thereby improving the utilization efficiency of the cache resources.

[0070] In some embodiments of the present application, the step S120 of determining the cache attribute corresponding to the target memory region according to the target access feature can include the following steps:

[0071] determining whether the target memory region meets a target condition according to the target access feature;

[0072] if the target condition is met, determining that the cache attribute corresponding to the target memory region is the non-cacheable attribute;

[0073] if the target condition is not met, determining that the cache attribute corresponding to the target memory region is the cacheable attribute;

[0074] wherein the target condition includes:

[0075] the target memory region is a continuous memory region;

[0076] The address length of the target memory region is greater than or equal to a first threshold value;

[0077] The access time interval of the target memory region is greater than or equal to a second threshold value.

[0078] For the convenience of description, the above steps are combined for description.

[0079] In the embodiments of the present application, after the target access feature of the target memory region in the running process of the target program is acquired, whether the target memory region meets the target condition can be determined according to the target access feature.

[0080] The target access feature can include an access address feature, an access block size feature, and an access time feature.

[0081] By analyzing the access address feature, whether the target memory region is a continuous memory region can be determined. Alternatively, whether the target memory region is a continuous memory region can be determined by the following steps:

[0082] In the case that in the target memory region, every two continuous access operations, the starting address of the latter access operation is equal to the starting address of the former access operation plus the access data block size of the former access operation, it is determined that the target memory region is a continuous memory region.

[0083] In the case that in the target memory region, every two continuous access operations, the starting address of the latter access operation is not equal to the starting address of the former access operation plus the access data block size of the former access operation, it is determined that the target memory region is not a continuous memory region.

[0084] It can be understood that if for any two continuous access operations in the target memory region, the starting address of the latter access operation is equal to the starting address of the former access operation plus the access data block size of the former access operation, it can be considered that the current memory access has continuity, such as array traversal, batch data reading, etc., and it can be determined that the target memory region is a continuous memory region.

[0085] If for any two continuous access operations in the target memory region, there is a case that the starting address of the latter access operation is not equal to the starting address of the former access operation plus the access data block size of the former access operation, it can be considered that the current memory access does not have continuity, and it can be determined that the target memory region is not a continuous memory region.

[0086] For example, a single access operation includes a start address addr and a data block size size (i.e., data in the interval [addr, addr+size) is accessed). If a start address of a first access operation is addr_1, a data block size is size_1 (i.e., data in the interval [addr_1, addr_1+size_1) is accessed), a start address of a second access operation is addr_2, and a data block size is size_2 (i.e., data in the interval [addr_2, addr_2+size_2) is accessed), if addr_2 = addr_1+size_1, the two access operations are continuous memory regions, and if addr_2 ≠ addr_1+size_1, the two access operations are not continuous memory regions.

[0087] The access block size feature can be represented by the address length of the target memory region. By analyzing the access block size feature, it can be determined whether the address length of the target memory region is greater than or equal to a first threshold. If the address length of the target memory region is greater than or equal to the first threshold, it can be considered that there is currently large block data transmission. If the address length of the target memory region is less than the first threshold, it can be considered that there is currently no large block data transmission.

[0088] The access time feature can be represented by an access time interval, which can be understood as a time locality feature. By analyzing the access time feature, it can be determined whether the access time interval of the target memory region is greater than or equal to a second threshold. If the access time interval of the target memory region is greater than or equal to the second threshold, it can be considered that the data of the target memory region is not reused in the short term, or the data of the target memory region is one-time access data (long-term no reuse).

[0089] The target condition can include that the target memory region is a continuous memory region, the address length of the target memory region is greater than or equal to the first threshold, and the access time interval of the target memory region is greater than or equal to the second threshold.

[0090] If the target memory region satisfies the target condition, i.e., the target memory region is a continuous memory region, the address length of the target memory region is greater than or equal to the first threshold, and the access time interval of the target memory region is greater than or equal to the second threshold, it can be considered that the data of the target memory region is one-time access large block data and has no reuse demand in the short term. It can be determined that the cache attribute corresponding to the target memory region is an uncachable attribute, so as to avoid waste of cache resources and performance degradation.

[0091] If the target memory region does not satisfy the target condition, that is, the target memory region is not a continuous memory region, or the address length of the target memory region is less than the first threshold, or the access time interval of the target memory region is less than the second threshold, it can be considered that the data of the target memory region may have reusability and is not suitable for skipping caching, and the cache attribute corresponding to the target memory region can be determined as a cacheable attribute to improve the access speed by using caching.

[0092] Optionally, the first threshold and / or the second threshold can be dynamically configured based on the current application scenario. It can be understood that in different application scenarios, the data access mode can be different, and the first threshold and / or the second threshold can be dynamically configured to adapt to various application scenarios and meet the corresponding application requirements.

[0093] In some embodiments of the present application, after determining the cache attribute corresponding to the target memory region, the method can further include the following steps:

[0094] Updating the cache attribute corresponding to the target memory region in the cache attribute metadata table.

[0095] In the embodiments of the present application, after determining the cache attribute corresponding to the target memory region according to the target access feature, the cache attribute corresponding to the target memory region can be further updated in the cache attribute metadata table. In this way, the cache attribute corresponding to each memory region can be accurately obtained by querying the cache attribute metadata table, which facilitates global management and monitoring of the system.

[0096] The cache attribute metadata table can be understood as a memory attribute extension table.

[0097] In some embodiments of the present application, in the case of data access including data reading, data access according to the cache process can include the following steps:

[0098] Reading the data of the target memory region from the cache;

[0099] In the case of cache hit, returning the data read in the cache to the target program;

[0100] In the case of cache miss, reading the data of the target memory region from the main memory, and after loading the data read in the main memory to the cache, returning the data to the target program.

[0101] For convenience of description, the above steps are combined for description.

[0102] In the embodiments of the present application, in the case of data reading, if the cache attribute corresponding to the target memory region is determined as a cacheable attribute according to the target access feature, it can be considered that the data of the target memory region has a high probability in the cache, and the data reading operation can be performed from the cache.

[0103] If the cache hit, it means that the data of the target memory region is stored in the cache, and the data read in the cache can be returned to the target program, i.e. the requester. In this way, the data access efficiency can be improved.

[0104] If the cache miss, it means that the data of the target memory region is not stored in the cache, or the previously stored data of the target memory region in the cache has been replaced. The data of the target memory region can be read from the main memory, and then loaded into the cache and returned to the target program, so as to improve the cache hit rate when accessing the data of the target memory region next time.

[0105] In some embodiments of the present application, in the case of data access including data write, the data access according to the cache process can include the following steps:

[0106] Write the data into the position corresponding to the target memory region in the cache;

[0107] Update the data in the main memory according to the cache consistency protocol.

[0108] For convenience of description, the above steps are combined for description.

[0109] In the embodiments of the present application, in the case of data write, if the cache attribute corresponding to the target memory region is determined to be the cacheable attribute according to the target access characteristics, the data can be first written into the position corresponding to the target memory region in the cache, so that the corresponding data can be read in the cache during subsequent access. At the same time, the data in the main memory can be updated in time according to the cache write strategy and the cache consistency protocol, so as to ensure the consistency of the data in the cache and the main memory, and improve the system stability and reliability.

[0110] For convenience of understanding, the data access system shown in Figure 2 , and the data access process shown in Figure 3 are taken as examples to further describe the technical solutions provided by the embodiments of the present application.

[0111] The data access system can include a processor, a memory access characteristic monitoring unit, a dynamic cache attribute decision unit, a cache controller, a multi-level cache, and a main memory.

[0112] The memory access characteristic monitoring unit and the dynamic cache attribute decision unit can be initialized after the system is started or during the running of the target program. The initialization of the dynamic cache attribute decision unit includes the initialization of the related threshold parameters.

[0113] After the processor initiates the memory region access request, the memory access characteristic monitoring unit can acquire the target access characteristic of the target memory region in the target program running process. Optionally, if the data of the target memory region is a new data block, the statistical information is initialized to determine the target access characteristic based on the initialized statistical information, and if the data of the target memory region is not a new data block, the statistical information is updated to determine the target access characteristic based on the updated statistical information.

[0114] The dynamic cache attribute decision unit determines the cache attribute corresponding to the target memory region according to the target access characteristic, updates the cache attribute corresponding to the target memory region in the cache attribute metadata table, maintains the cache attribute metadata table, and outputs the cache attribute determination result corresponding to the target memory region to the cache controller.

[0115] The cache controller performs data access according to the current access request and the cache attribute determination result of the target memory region output by the dynamic cache attribute decision unit. Optionally, if the cache attribute corresponding to the target memory region is a cacheable attribute, data access is performed according to a normal cache process (a traditional cache process), and the state of the multi-level cache is updated, and if the cache attribute corresponding to the target memory region is a non-cacheable attribute, data access is directly performed on the main memory.

[0116] The above describes the technical solutions provided by the embodiments of the present application, and the embodiments of the present application are described below by comparison with related technologies.

[0117] In the related art, for an artificial intelligence (AI) accelerator, its core computing unit (such as matrix operation, convolution operator, etc.) involves large-scale data scheduling, including frequent reading and writing of intermediate results such as weight parameters and activation values. The access characteristics of these data have differences. For example, the weight parameters may be repeatedly used in multiple iterations, having the characteristics of high-frequency access and strong spatial locality, while the activation values are part of the intermediate calculation results, and are only accessed once in a single operator execution (such as the convolution layer output being directly input to the next layer, without reuse requirement in the short term), having the characteristics of continuous address, large block access, and low reuse rate. In an AI task, the activation values output by the same operator may need to be partially reused (such as cross-channel shared data) and partially transmitted only once (such as a temporary intermediate buffer). Dynamic data scheduling strategies (such as pipeline parallelism and data blocking) cause real-time changes in memory access patterns, and static configuration of cache attributes cannot match real-time requirements. Moreover, for special address spaces such as peripheral registers and direct memory access (DMA) buffers, if they are statically configured as non-cacheable attributes, although inconsistency with data in the cache can be avoided, data in the main memory with similar access characteristics (such as temporary tensors in AI calculation) are not covered, which will cause waste of cache resources in general computing scenarios.

[0118] Embodiments of the present application break through the traditional static preset cache attribute mode and construct an intelligent management mechanism of real-time analysis of access characteristics-dynamic decision of cache attributes. Unlike traditional fixed cache strategies (such as full cache or full non-cache, offline static analysis and preset, and coarse-grained address range division), the dynamic determination of cache attributes is realized at runtime of the program by real-time monitoring of data access characteristics (access address characteristics, access block size characteristics, and access time characteristics). For example, for data in a memory region with continuous address, large block access, and no reuse in the short term, the cache attribute is dynamically determined, and the cache is not forced, which can reduce invalid cache loading overhead. It can effectively avoid the decrease of cache hit rate of high-frequency access data (such as temporarily reused activation values) due to non-reusable data occupying cache entries, and optimize the allocation of cache entries by dynamically marking and releasing invalid cache space.

[0119] Embodiments of the present application can determine the cache attribute in units of data blocks (rather than the entire address space or page table), which can be as small as the cache line level or the operator-level intermediate result granularity. In view of the diversity of data scheduling in AI accelerators (such as differences in data reuse between operators, part of which is cacheable and part of which is non-cacheable), the same operator supports differential caching of part of the data, maximizing the utilization rate of cache resources.

[0120] The embodiments of the present application can realize automatic monitoring through the built-in access characteristic monitoring unit (such as an access interval counter and an address jump amplitude analyzer) and automatic decision making through a dynamic cache attribute decision unit, without manual intervention or code annotation.

[0121] The embodiments of the present application provide a universal solution for cache-sensitive scenarios such as high-performance computing and AI acceleration, and have high technical value and industrial application prospects in improving computing efficiency and optimizing resource utilization.

[0122] In summary, the embodiments of the present application can realize the improvement of core performance:

[0123] 1) Optimization of cache resource utilization efficiency. By dynamically identifying one-time data (continuous large block access and short-term non-reuse) and marking it as non-cacheable attribute, invalid cache loading is avoided. The "pollution" of one-time data to cache entries is eliminated, and the cache hit rate of high-frequency access data (such as AI operator weight parameters) is improved; the phenomenon of cache thrashing is reduced, especially in the data block scheduling scenario, the cache replacement frequency is reduced, and the cache level data reuse efficiency is improved.

[0124] 2) Access delay reduction. For one-time data, directly bypass the cache access main memory, avoid redundant operations such as cache lookup and invalidation processing. The delay of single large block data access is reduced, especially in the scene of DMA data transfer and operator intermediate result transmission, which has good effect; the cache coherence maintenance overhead (such as write-back and invalidate operation) is eliminated, further optimizing the write operation delay of non-reuse data.

[0125] The embodiments of the present application can also realize the special benefits of AI accelerators:

[0126] 1) Fine adaptation of operator-level data scheduling. Support for differentiated cache attribute configuration (partially cacheable / partially non-cacheable) of different data blocks within the same operator, for example, in the activation value of the convolution layer output, the normalization parameter that is reused across batches is marked as cacheable, and the temporary intermediate buffer is marked as non-cacheable, so that the end-to-end operator execution time is shortened.

[0127] 2) Adapt to dynamic data block strategy (such as tensor slicing and pipeline parallelism). By matching the access characteristics in real time, the problems of "over-caching" or "insufficient caching" under traditional fixed strategies are avoided.

[0128] The embodiments of the present application can also realize system-level benefits:

[0129] 1) Power consumption and hardware resource optimization. Reducing invalid cache operations reduces the power consumption of the cache controller and the storage interface, especially in mobile terminals, edge AI chips and other energy-sensitive scenarios. The dynamic management mechanism can reduce the power consumption of the cache subsystem; the released cache space can support larger-scale temporary storage of intermediate data, indirectly reducing the dependence on off-chip storage and reducing hardware design costs (such as reducing off-chip bandwidth requirements and reducing cache capacity configuration).

[0130] 2) General-purpose and compatibility enhancement. Not dependent on specific hardware architecture, can be implemented through software driver or firmware (such as extending the memory management unit (Memory Management Unit, MMU) memory attribute configuration interface, adding memory access characteristic monitoring unit), compatible with mainstream architectures such as ARM, x86, RISC-V (an open source instruction set architecture); support seamless cooperation with existing cache consistency protocols (such as MESI (a cache consistency protocol, the first letter abbreviation of Modified, Exclusive, Shared and Invalid) and MOESI (a cache consistency protocol, the first letter abbreviation of Modified, Owned, Exclusive, Shared and Invalid)), optimize protocol execution efficiency through dynamic attribute marking, and avoid redundant operations of the protocol under traditional static configuration.

[0131] Corresponding to the above method embodiments, the embodiments of the present application also provide a data access device. The data access device described below can be referred to each other corresponding to the data access method described above.

[0132] Referring to Figure 4 As shown in the figure, the data access device 400 includes:

[0133] The acquisition module 410 is configured to acquire a target access feature of a target memory region in a target program running process.

[0134] The determination module 420 is configured to determine a cache attribute corresponding to the target memory region according to the target access feature.

[0135] The first access module 430 is configured to perform data access according to a cache flow in a case where the cache attribute corresponding to the target memory region is a cacheable attribute.

[0136] The second access module 440 is configured to skip cache and perform data access in the main memory in a case where the cache attribute corresponding to the target memory region is an uncachable attribute.

[0137] The device provided in the embodiment of the present application is used to obtain the target access feature of the target memory region in the running process of the target program, determine the cache attribute corresponding to the target memory region according to the target access feature, perform data access according to the cache process if the cache attribute corresponding to the target memory region is the cacheable attribute, and perform data access in the main memory if the cache attribute corresponding to the target memory region is the non-cacheable attribute. The cache attribute corresponding to the target memory region is not pre-configured statically, but is determined dynamically based on the target access feature of the target memory region, so that the data access of the corresponding process can be performed according to the dynamically determined cache attribute corresponding to the target memory region, which helps to improve the cache resource utilization efficiency and the data access efficiency. For example, if the cache attribute of the memory region where a large block of data is located is determined to be the non-cacheable attribute, the cache can be skipped and the data access can be directly performed in the main memory, which reduces the data access delay, improves the data access efficiency, reduces the cache loading overhead, and at the same time, avoids occupying the cache space for high-frequency access data, and improves the utilization efficiency of the cache resource.

[0138] In some embodiments of the present application, the determining module 420 is specifically configured to:

[0139] determine whether the target memory region meets a target condition according to the target access feature;

[0140] if the target condition is met, determine that the cache attribute corresponding to the target memory region is the non-cacheable attribute;

[0141] if the target condition is not met, determine that the cache attribute corresponding to the target memory region is the cacheable attribute;

[0142] The target condition includes:

[0143] the target memory region is a continuous memory region;

[0144] the address length of the target memory region is greater than or equal to a first threshold value;

[0145] the access time interval corresponding to the target memory region is greater than or equal to a second threshold value.

[0146] In some embodiments of the present application, the determining module 420 is further configured to determine whether the target memory region is a continuous memory region by the following steps:

[0147] if the starting address of the latter access operation is equal to the starting address of the former access operation plus the access data block size of the former access operation in the case that every two continuous access operations in the target memory region, the starting address of the latter access operation is equal to the starting address of the former access operation plus the access data block size of the former access operation;

[0148] In the case that the start address of the second access operation in the target memory region is not equal to the start address of the first access operation plus the access data block size of the first access operation, it is determined that the target memory region is not a continuous memory region.

[0149] In some embodiments of the present application, the first threshold value and / or the second threshold value are dynamically configured based on a current application scenario.

[0150] In some embodiments of the present application, the data access apparatus 400 further comprises an updating module, configured to:

[0151] After determining the cache attribute corresponding to the target memory region, the cache attribute corresponding to the target memory region is updated in the cache attribute metadata table.

[0152] In some embodiments of the present application, the first access module 430 is specifically configured to:

[0153] In the case that the data access comprises data reading, the data of the target memory region is read from the cache;

[0154] In the case of cache hit, the data read from the cache is returned to the target program;

[0155] In the case of cache miss, the data of the target memory region is read from the main memory, and after the data read from the main memory is loaded into the cache, it is returned to the target program.

[0156] In some embodiments of the present application, the first access module 430 is specifically configured to:

[0157] In the case that the data access comprises data writing, the data is written into the position corresponding to the target memory region in the cache;

[0158] According to the cache consistency protocol, the data in the main memory is updated.

[0159] As to the apparatus in the above embodiments, the specific manners in which the various modules perform operations have been described in detail in the embodiments of the method, and will not be described in detail here.

[0160] Corresponding to the above method embodiments, the embodiments of the present application further provide an electronic device, comprising:

[0161] A memory, configured to store a computer program;

[0162] A processor, configured to execute the computer program to implement the steps of the above data access method.

[0163] As Figure 5As shown in the figure, it is a schematic diagram of a constituent structure of an electronic device, which can include a processor 10, a memory 11, a communication interface 12 and a communication bus 13. The processor 10, the memory 11 and the communication interface 12 can complete communication with each other through the communication bus 13.

[0164] In the embodiment of the present application, the processor 10 can be a central processing unit (CPU), an application specific integrated circuit, a digital signal processor, a field programmable gate array or other programmable logic device, etc.

[0165] The processor 10 can invoke a program stored in the memory 11, and specifically, the processor 10 can perform the operations in the embodiment of the data access method.

[0166] The memory 11 is used to store one or more programs, and the program can include program code including computer operation instructions. In the embodiment of the present application, the memory 11 at least stores a program for implementing the following functions:

[0167] Obtaining a target access feature of a target memory region in a target program running process;

[0168] According to the target access feature, determining a cache attribute corresponding to the target memory region;

[0169] In the case that the cache attribute corresponding to the target memory region is a cacheable attribute, performing data access according to a cache process;

[0170] In the case that the cache attribute corresponding to the target memory region is a non-cacheable attribute, skipping the cache and performing data access in the main memory.

[0171] In a possible implementation, the memory 11 can include a program storage area and a data storage area, wherein the program storage area can store an operating system and at least one application program required by a function; and the data storage area can store data created in the use process.

[0172] In addition, the memory 11 can include a high-speed random access memory, and can also include a non-volatile memory, such as at least one magnetic disk storage device or other volatile solid-state storage device.

[0173] The communication interface 12 can be an interface of a communication module, used to connect with other devices or systems.

[0174] Of course, it needs to be explained that, Figure 5 The structure shown does not constitute a limitation on the electronic device in the embodiment of the present application, and the electronic device can include more or fewer components than those shown in the figure, or combine some components in actual application. Figure 5 The structure shown does not constitute a limitation on the electronic device in the embodiment of the present application, and the electronic device can include more or fewer components than those shown in the figure, or combine some components in actual application.

[0175] Corresponding to the above method embodiments, the embodiments of the present application further provide a computer readable storage medium, and the computer readable storage medium stores a computer program. The computer program is executed by a processor to implement the steps of the above data access method.

[0176] In addition, it should be noted that the embodiments of the present application also provide a computer program product or a computer program. The computer program product or the computer program can include computer instructions, which can be stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer readable storage medium, and the processor can execute the computer instructions to enable the computer device to perform the description of the data access method in the foregoing embodiments. Therefore, the description will not be repeated here. In addition, the description of the beneficial effects of using the same method will not be repeated. For technical details that are not disclosed in the embodiments of the computer program product or the computer program, please refer to the description of the method embodiments of the present application.

[0177] The embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts of each embodiment can be referred to each other.

[0178] It should be noted that in this document, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of additional same elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to the order of performing the functions shown or discussed, but can also include performing the functions in a substantially simultaneous manner or in a reverse order, for example, the described method can be performed in an order different from the described order, and various steps can also be added, omitted or combined. In addition, the features described with reference to some examples can be combined in other examples.

[0179] Those skilled in the art can clearly understand the units and algorithm steps of each example described in connection with the embodiments disclosed in the specification that are presented in a way of flowchart and / or an algorithm diagram. The units and algorithm steps of each example can be realized in electronic hardware, computer software, or a combination of both. The purpose of general description of each example in the specification is to clarify the interchangeability of hardware and software. Whether the functions are performed in hardware or software depends on the particular application and design constraints. Those skilled in the art can use different methods to implement the described functions for each particular application, but the implementation should not be considered to be beyond the scope of the present application.

[0180] The steps of the methods or algorithms described in connection with the embodiments disclosed in the specification can be directly implemented by hardware, a software module executed by a processor, or a combination of both. The software module can be located in a random access memory (RAM), a memory, a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), a register, a hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of storage medium known in the art, including a number of instructions for executing the methods described in the embodiments of the present application.

[0181] The embodiments of the present application are described above in connection with the accompanying drawings, and the above description of the embodiments is only used to help understand the technical solutions of the present application and the core ideas thereof. It should be noted that the present application is not limited to the above specific embodiments, and the above specific embodiments are only illustrative, but not restrictive. Those skilled in the art can make many forms of implementation without departing from the scope of the present application and the protection scope of the claims, and can make some improvements and modifications to the present application, and these implementation, improvements and modifications all belong to the protection scope of the present application.

Claims

1. A data access method, characterized by, The method comprises the following steps: obtaining target access characteristics of a target memory region in the running process of a target program; determining a cache attribute corresponding to the target memory region according to the target access characteristics; if the cache attribute corresponding to the target memory region is a cacheable attribute, performing data access according to a cache process; if the cache attribute corresponding to the target memory region is an uncacheable attribute, skipping cache and performing data access in main memory; the step of determining the cache attribute corresponding to the target memory region according to the target access characteristics comprises the following steps: determining whether the target memory region meets a target condition according to the target access characteristics; if the target condition is met, determining that the cache attribute corresponding to the target memory region is an uncacheable attribute; if the target condition is not met, determining that the cache attribute corresponding to the target memory region is a cacheable attribute; the target condition comprises the following conditions: the target memory region is a continuous memory region; the address length of the target memory region is greater than or equal to a first threshold value; the access time interval corresponding to the target memory region is greater than or equal to a second threshold value.

2. The method of claim 1, wherein, whether the target memory region is a continuous memory region is determined through the following steps: if, in the target memory region, the starting address of a second access operation is equal to the starting address of a first access operation plus the access data block size of the first access operation, it is determined that the target memory region is a continuous memory region; if, in the target memory region, the starting address of a second access operation is not equal to the starting address of a first access operation plus the access data block size of the first access operation, it is determined that the target memory region is not a continuous memory region.

3. The method of claim 1, wherein, The first threshold value and / or the second threshold value are dynamically configured based on the current application scenario.

4. The method of claim 1, wherein, After the cache attribute corresponding to the target memory region is determined, the method further comprises the following steps: updating the cache attribute corresponding to the target memory region in a cache attribute metadata table.

5. The method according to any one of claims 1 to 4, characterized in that, if the data access comprises data reading, the step of performing data access according to the cache process comprises the following steps: reading data of the target memory region from the cache; if the cache hits, returning the data read from the cache to the target program; if the cache misses, reading data of the target memory region from the main memory, loading the data read from the main memory to the cache, and then returning to the target program.

6. The method according to any one of claims 1 to 4, characterized in that, if the data access comprises data writing, the step of performing data access according to the cache process comprises the following steps: writing data to the position corresponding to the target memory region in the cache; updating the data in the main memory according to the cache consistency protocol.

7. A data access device, characterized by The method comprises the following steps: an obtaining module, configured to obtain target access characteristics of a target memory region in the running process of a target program; a determining module, configured to determine a cache attribute corresponding to the target memory region according to the target access characteristics; a first access module, configured to perform data access according to a cache process if the cache attribute corresponding to the target memory region is a cacheable attribute; The second access module is configured to, in a case where the cache attribute corresponding to the target memory region is the non-cacheable attribute, perform data access in the main memory by skipping cache; The determining module is further configured to: determine whether the target memory region satisfies a target condition according to a target access feature; if the target condition is satisfied, determine that the cache attribute corresponding to the target memory region is the non-cacheable attribute; if the target condition is not satisfied, determine that the cache attribute corresponding to the target memory region is the cacheable attribute; wherein the target condition comprises: the target memory region is a continuous memory region; the address length of the target memory region is greater than or equal to a first threshold value; and the access time interval corresponding to the target memory region is greater than or equal to a second threshold value.

8. An electronic device, comprising: The computer program is stored in the memory and executed by the processor to implement the steps of the data access method according to any one of claims 1 to 6. The computer program is stored in the memory and executed by the processor to implement the steps of the data access method according to any one of claims 1 to 6. The computer program is stored in the memory and executed by the processor to implement the steps of the data access method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, ​

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