Data transmission method, memory controller, chip and electronic equipment

Abstract

The invention discloses a data transmission method and device, a memory controller, a chip and electronic equipment, and belongs to the technical field of computers. The method comprises the following steps: receiving a memory read-write request from a processor of computer equipment; under the condition that the memory read-write request indicates that the lock step mode is adopted, splitting the memory read-write request into a plurality of read-write transactions; and transmitting the plurality of read-write transactions to the memory based on the different phases, respectively. According to the scheme, the memory read-write request in the lock step mode is divided into the read-write transactions and distributed to the different pseudo channels based on the different phases, the characteristic that the pseudo channels support concurrency is fully utilized, it is ensured that the transactions are accurately routed to the corresponding memory modules through a phase indication mechanism, the data reliability can be ensured, and meanwhile the data reliability is improved. And the time consumption of data transmission is reduced, so that the data transmission efficiency is remarkably improved on the premise that the data integrity is not changed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a data transmission method, a memory controller, a chip and an electronic device. BACKGROUND

[0002] Memory is a key component in modern computer systems. In order to ensure the reliability of reading and writing data, lockstep mode is usually used for memory reading and writing. Lockstep mode refers to making two or more independent channels or ranks (memory columns) completely synchronized to perform the same operation, and detecting and correcting errors by comparing the running results in real time. Rank refers to a collection of memory chips, and a memory can include one or more ranks.

[0003] At present, when data transmission is performed, the memory controller usually splits the read and write requests, and then sends two independent read and write transactions to two ranks, and each read and write transaction can only access half of the data.

[0004] However, in standard DDR (Double Data Rate) memory, the data pins of multiple ranks are connected to the same data line at the physical layer, and if two ranks drive the data line at the same time, signal level conflict will occur, which results in that read and write transactions cannot be sent to two ranks at the same time, and data transmission can only be performed in two times, which is low in data transmission efficiency. Therefore, there is an urgent need for a new data transmission method to improve data transmission efficiency while ensuring data reliability. SUMMARY

[0005] The embodiments of the present application provide a data transmission method, a memory controller, a chip and an electronic device, which can improve data transmission efficiency while ensuring data reliability. The technical solution is as follows:

[0006] On the one hand, a data transmission method is provided, which is applied to a memory controller, the memory controller is used for connecting with a memory of a computer device, the memory includes a plurality of pseudo channels and a plurality of memory modules, the plurality of pseudo channels are used for accessing the plurality of memory modules, and the method comprises the following steps:

[0007] receiving a memory read and write request from a processor of the computer device;

[0008] in a case where the memory read and write request indicates to use lockstep mode, splitting the memory read and write request into a plurality of read and write transactions;

[0009] transmit the multiple read-write transactions to the memory respectively based on different phases, so that, when the memory receives the multiple read-write transactions, the memory transmits corresponding read-write transactions to corresponding memory modules in the pseudo channel indicated by the phase;

[0010] The phase is used to indicate a pseudo channel used for transmitting a corresponding read-write transaction.

[0011] In some embodiments, when the memory read-write request indicates that the lockstep mode is used, the memory read-write request is split into multiple read-write transactions, including:

[0012] When the memory read-write request indicates that the lockstep mode is used, if the memory read-write request is a memory write request, the memory write request is split into multiple write transactions, and the write transactions are used to write data into the memory.

[0013] When the memory read-write request indicates that the lockstep mode is used, if the memory read-write request is a memory read request, the memory read request is split into multiple read transactions, and the read transactions are used to read data from the memory.

[0014] In some embodiments, the multiple read-write transactions are transmitted to the memory respectively based on different phases, including:

[0015] For any read-write transaction, the read-write transaction is stored in a position corresponding to a phase identifier carried by the read-write transaction in a linear shift queue, and the linear shift queue is used to transmit the read-write transaction to the memory based on a phase indicated by the phase identifier.

[0016] In some embodiments, the method further includes:

[0017] For any write transaction, error correction data is generated based on data to be written by the write transaction.

[0018] The error correction data is cached.

[0019] When a response of the memory to the write transaction is received, the error correction data is sent to the memory.

[0020] In some embodiments, the method further includes:

[0021] When the memory read-write request indicates that the independent mode is used, a target pseudo channel corresponding to a read-write transaction of the memory read-write request is determined.

[0022] transmit the read-write transaction to the memory, so that the memory, upon receiving the read-write transaction, transmits the read-write transaction to a corresponding memory module in the memory through the target pseudo-channel.

[0023] In some embodiments, the transmitting the read-write transaction to the memory comprises:

[0024] For any read-write transaction, the read-write transaction is transmitted through a phase indicated by a phase identifier corresponding to the target pseudo-channel based on the phase identifier.

[0025] In some embodiments, the method further comprises:

[0026] For any read transaction, the memory acquires data and performs error correction based on the target pseudo-channel.

[0027] In another aspect, a data transmission apparatus configured in a memory controller is provided, the memory controller being configured to connect with a memory of a computer device, the memory comprising a plurality of pseudo-channels and a plurality of memory modules, the plurality of pseudo-channels being configured to access the plurality of memory modules, the apparatus comprising:

[0028] a request receiving module configured to receive a memory read-write request from a processor of the computer device;

[0029] a request splitting module configured to split the memory read-write request into a plurality of read-write transactions if the memory read-write request indicates a lockstep mode;

[0030] a transaction transmitting module configured to transmit the plurality of read-write transactions to the memory based on different phases respectively, so that the memory, upon receiving the plurality of read-write transactions, transmits corresponding read-write transactions to corresponding memory modules in the memory through pseudo-channels indicated by the phases;

[0031] The phase is configured to indicate a pseudo-channel used when transmitting a corresponding read-write transaction.

[0032] In some embodiments, the request splitting module is configured to, if the memory read-write request indicates the lockstep mode, split the memory write request into a plurality of write transactions if the memory read-write request is a memory write request, the write transactions being configured to write data into the memory; and split the memory read request into a plurality of read transactions if the memory read-write request is a memory read request, the read transactions being configured to read data from the memory.

[0033] In some embodiments, the transaction transmission module is configured to, for any read-write transaction, store the read-write transaction into a position corresponding to a phase identifier carried by the read-write transaction in a linear shift queue, and transmit the read-write transaction to the memory based on a phase indicated by the phase identifier.

[0034] In some embodiments, the transaction transmission module is further configured to, for any write transaction, generate error correction data based on data to be written indicated by the write transaction, cache the error correction data, and send the error correction data to the memory upon receiving a response of the memory to the write transaction.

[0035] In some embodiments, the transaction transmission module is further configured to, in a case where the memory read-write request indicates to adopt the independent mode, determine a target pseudo channel corresponding to a read-write transaction of the memory read-write request, and transmit the read-write transaction to the memory so that the memory transmits the read-write transaction to a corresponding memory module in the memory through the target pseudo channel upon receiving the read-write transaction.

[0036] In some embodiments, the transaction transmission module is further configured to, for any read-write transaction, transmit the read-write transaction through a phase indicated by a phase identifier corresponding to the target pseudo channel.

[0037] In some embodiments, the transaction transmission module is further configured to, for any read transaction, acquire data based on the target pseudo channel and perform error correction by the memory.

[0038] In another aspect, a memory controller is provided, which is configured to connect with a memory of a computer device, the memory comprising a plurality of pseudo channels and a plurality of memory modules, the plurality of pseudo channels being configured to access the plurality of memory modules, the memory controller comprising a first interface and an arbitration module.

[0039] The first interface is configured to receive a memory read-write request from the processor.

[0040] The arbitration module is configured to, in a case where the memory read-write request indicates to adopt the lockstep mode, split the memory read-write request into a plurality of read-write transactions, and transmit the plurality of read-write transactions to the memory based on different phases respectively, so that the memory transmits corresponding read-write transactions to corresponding memory modules in the memory through pseudo channels indicated by the phases upon receiving the plurality of read-write transactions.

[0041] The phase is configured to indicate a pseudo channel to be adopted when transmitting a corresponding read-write transaction.

[0042] In some embodiments, the arbitration module comprises a phase indication module and an arbitration module, the phase indication module is connected with the arbitration module;

[0043] The phase indication module is configured to output phase identifiers of multiple phases to the arbitration module in turn;

[0044] The arbitration module is configured to split the memory read-write request into multiple read-write transactions in the case that the memory read-write request indicates to adopt the lockstep mode, and transmit the multiple read-write transactions to the memory in phases indicated by the phase identifiers of the multiple phases based on the phase identifiers of the multiple phases output by the phase indication module.

[0045] In some embodiments, the arbitration module comprises an arbitration unit and a linear shift queue, the arbitration unit is connected with the phase indication module, the arbitration unit is connected with the linear shift queue, and the linear shift queue is connected with the second interface;

[0046] The arbitration unit is configured to store the multiple read-write transactions into positions corresponding to phase identifiers of the multiple read-write transactions in the linear shift queue based on the phase identifiers;

[0047] The linear shift queue is configured to transmit the multiple read-write transactions to the memory in phases indicated by the phase identifiers.

[0048] In some embodiments, the memory controller further comprises a command queue, a command information module, and an error correction module, the command queue is connected with the first interface and the arbitration module respectively, and the command information module is connected with the first interface and the arbitration module respectively;

[0049] The command queue is configured to store the memory read-write request received from the processor;

[0050] The command information module is configured to store tag information of the memory read-write request, the tag information comprising a working mode adopted by the memory read-write request;

[0051] The error correction module is configured to perform data error correction and cache data to be written.

[0052] In some embodiments, the error correction module comprises an error correction unit and a cache unit;

[0053] The error correction unit is configured to split the data to be written into multiple error correction data;

[0054] The cache unit is configured to store the multiple error correction data.

[0055] In some embodiments, the error correction unit is further configured to correct errors of the data obtained from the memory.

[0056] In some embodiments, the arbitration module is further configured to, in a case where the memory read-write request indicates the independent mode, determine a target pseudo channel corresponding to a read-write transaction of the memory read-write request, and transmit the read-write transaction to the memory, so that the memory transmits the read-write transaction to a corresponding memory module in the memory through the target pseudo channel in a case where the memory receives the read-write transaction.

[0057] In some embodiments, the arbitration module comprises a phase indication module and an arbitration module, and the phase indication module is connected to the arbitration module.

[0058] The phase indication module is configured to output phase identifiers of a plurality of phases to the arbitration module in turn.

[0059] The arbitration module is configured to transmit the read-write transaction through a phase indicated by the phase identifier based on a phase identifier corresponding to the target pseudo channel.

[0060] Embodiments of the present application provide a data transmission scheme, which splits a memory read-write request in a lockstep mode into a plurality of read-write transactions and allocates the read-write transactions to different pseudo channels based on different phases, to provide a new memory lockstep structure. The memory lockstep structure fully utilizes the concurrent feature supported by the pseudo channel. When writing data, the corresponding pseudo channel in the memory is indicated by a phase, so that different data can be alternately transmitted to the memory through different phases, and the received data can be accurately routed to the corresponding memory module by different pseudo channels in the memory. That is, in the lockstep mode, the data is split into two parts by the ECC algorithm, and the memory can transmit the two parts of data at the same time, without transmitting one part first and then transmitting the other part, thereby reducing the time consumption of data transmission, ensuring data reliability and data integrity, and significantly improving data transmission efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0061] Figure 1 is an implementation environment schematic diagram of a data transmission method according to an embodiment of the present application;

[0062] Figure 2 is a structure schematic diagram of a memory according to an embodiment of the present application;

[0063] Figure 3 is a flow schematic diagram of a data transmission method according to an embodiment of the present application;

[0064] Figure 4 is a flow schematic diagram of another data transmission method according to an embodiment of the present application;

[0065] Figure 5 is a schematic diagram of a data transmission apparatus provided by an embodiment of the present application. DETAILED DESCRIPTION

[0066] For the purpose of making the objects, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0067] The terms "first", "second", and the like are used to distinguish between similar items or items that perform substantially the same function, and it should be understood that there is no logical or chronological dependency between "first", "second", and "n", nor does it limit the number and execution order. It should also be understood that although the following description uses the terms first, second, and the like to describe various elements, these elements should not be limited by the terms.

[0068] These terms are only used to distinguish one element from another. For example, without departing from the scope of various examples, a first element can be referred to as a second element, and similarly, a second element can also be referred to as a first element. The first element and the second element can both be elements, and in some cases, can be separate and distinct elements.

[0069] At least one refers to one or more than one, for example, at least one element can be one element, two elements, three elements, or any integer greater than or equal to one. At least two refers to two or more than two, for example, at least two elements can be two elements, three elements, or any integer greater than or equal to two.

[0070] The application provides a data transmission method, which can be applied to a memory controller. The data transmission method combines ECC (Error Correction Code) and MRMIM (Multiplexed Rank Dual In-Line Memory Module), and makes full use of the characteristics of MRMIM working in MUX (Multiplexer Mode) and supporting concurrent transmission of ranks distributed in two different pseudo-channels. In the lockstep mode, read and write transactions are transmitted simultaneously through two pseudo-channels. Taking a write transaction as an example, in the lockstep mode, the memory controller generates ECC check bits of data to be written based on the ECC, and then splits the data into two parts and sends them to pseudo-channel 0 and pseudo-channel 1 of the MRMIM. Since the MRMIM supports concurrency, the MRMIM can transmit the lower half of the data and the lower half of the ECC check bits through pseudo-channel 0, and transmit the upper half of the data and the upper half of the ECC check bits through pseudo-channel 1, and the two pseudo-channels are transmitted synchronously, so that the write transaction on the MRMIM side only needs to spend one transmission time to complete the write transaction which needs two transmissions in the prior art.

[0071] wherein the MRMIM is a new high-performance memory technology designed to improve the bandwidth and capacity efficiency of memory while maintaining compatibility with traditional DDR5 DIMM (Dual In-Line Memory Module). The MRMIM is proposed by JEDEC (Joint Electron Device Engineering Council) based on the DDR5 standard, and is mainly used to cope with the increasing demand for memory bandwidth and capacity in scenarios such as data centers, high-performance computing and artificial intelligence. The MRMIM uses TDM (Time-Division Multiplexing) technology to combine the data of multiple memory ranks into the same data bus for transmission. The application refers to the memory rank as a memory module.

[0072] The pseudo-channel is a memory architecture technology mainly used to improve the utilization rate of memory bandwidth. The working principle of the pseudo-channel is to logically divide a single physical channel into multiple independent sub-channels, each of which can operate independently to a certain extent and can improve parallel processing capability.

[0073] A rank refers to a set of memory chips that can be accessed simultaneously by a memory controller. A rank has multiple DRAM (Dynamic Random Access Memory) chips that can collectively respond to a memory access command.

[0074] In order to make the memory control-based data transmission method provided by the present application easier to understand, the data transmission method is further described below.

[0075] 1. ECC is described.

[0076] In the field of computer technology, the requirements for the accuracy and integrity of data are increasingly high. In order to ensure the reliability of data, an ECC-based error correction algorithm (hereinafter referred to as ECC algorithm) is usually used to detect and correct errors that may occur in the storage or transmission process of data. For example, when a memory controller writes data into a memory, the memory controller can calculate the check bits of the data through the ECC algorithm, and store the check bits of the data into the memory together with the data. When reading data from the memory, the memory controller can recalculate the check bits through the ECC algorithm after obtaining the data, and then compare and verify with the check bits stored in the memory. If the check bits are inconsistent, it indicates that there is an error in the data, at which time the memory controller can attempt to correct the error through the ECC algorithm to ensure the accuracy of the data.

[0077] However, due to the design limitations of the ECC algorithm itself, when the errors of the data exceed the error correction capability of the ECC algorithm, the memory controller cannot correct the errors through the ECC algorithm, at which time the lockstep mode is introduced.

[0078] 2. The lockstep mode is described below.

[0079] Memory Lockstep is a distribution mode of a cache line in multiple channels of a memory. In the lockstep mode, the memory can evenly split a single cache line (usually 64 bytes) into two physical ranks. Taking a write transaction as an example, before the memory controller sends the check bits of data and the data to the memory, the memory controller divides an ECC symbol (usually 144 bits, corresponding to 128 bits of data + 16 bits of ECC check code) into two parts: a first half (such as the lower 72 bits) and a second half (such as the upper 72 bits). After the memory controller sends the first half and the second half to the memory, the memory stores the first half in the physical Rank 0 and stores the second half in the physical Rank 1. In the lockstep mode, if a single DRAM (Dynamic Random Access Memory) particle of the memory fails, the data of the single DRAM particle will be affected, for example, an X4 particle will lose 8 bits of data (that is, 8 bits of data stored in the first half of Rank 0 or 8 bits of data stored in the second half of Rank 1), and the remaining data remains intact. In the traditional working mode, if a single DRAM particle fails, double data will be affected, for example, an X4 particle will lose 16 bits of data. Therefore, compared with the traditional working mode, the lockstep mode halves the error data, that is, the lockstep mode achieves the effect of halving the error data.

[0080] As can be seen, the lockstep mode can improve the reliability of the computer device to a certain extent while ensuring the reliability of reading and writing data.

[0081] Thirdly, the lockstep mode needs to be implemented through a memory lockstep structure, and the existing memory lockstep structure is introduced below.

[0082] In the existing memory lockstep structure, taking a memory write request as an example, after the memory controller receives the memory write request, the memory controller can split the memory write request into two write transactions. Then, the two write transactions are sent to the memory in turn. The memory performs two independent data write operations on the two physical ranks. One data write operation can write half of the data, that is, through two data write operations, the data can be completely stored in the memory. Similarly, for a memory read request, the memory controller splits the memory read request into two read transactions, and then the two read transactions are sent to the memory in turn. The memory performs two independent data read operations on the two physical ranks. One data read operation can read half of the data, and the memory sends the data read this time to the memory controller for caching. The memory reads the remaining half of the data again and sends it to the memory controller, and the memory controller combines the data received twice.

[0083] For example, for a memory write request, the memory controller can generate 8-bit ECC check bits for 64-bit data to be written, and then send the first half (e.g., the lower 36 bits) of the data and the first half (e.g., the lower 4 bits) of the ECC check bits to the physical Rank 0, and send the second half (e.g., the upper 36 bits) of the data and the second half (e.g., the upper 4 bits) of the ECC check bits to the physical Rank 1. And for a memory read request, the memory controller can read the first half of the data and the first half of the ECC check bits from the physical Rank 0 of the memory and buffer them in the read data buffer of the memory controller, and then read the second half of the data and the second half of the ECC check bits from the physical Rank 1 of the memory and buffer them in the read data buffer of the memory controller. Finally, the memory controller combines the data and performs error correction on the read data through the ECC algorithm.

[0084] Therefore, in the lockstep mode, whether reading data from the memory or writing data to the memory, the existing memory lockstep structure needs to perform two data transmissions to complete, i.e., half of the data is transmitted each time. Since in the standard DDR memory, the data pins of multiple physical Ranks are connected to the same data line at the physical layer, i.e., share a data bus, this results in the read and write operations of the two physical Ranks cannot be performed simultaneously, i.e., half of the data needs to be transmitted first, and after the data interface is idle, the other half of the data is transmitted. And since the data is transmitted in two times, when the memory controller reads data from the memory, an additional read data buffer mentioned above needs to be introduced in the memory controller to temporarily store the read data, resulting in an additional area overhead in the memory controller.

[0085] 3. To solve the above problems, the present application provides a data transmission scheme to improve data transmission efficiency while ensuring data reliability. The data transmission scheme provided by the present application and the memory controller used to implement the data transmission scheme are introduced below.

[0086] Referring to Figure 1 as shown, Figure 1 is an implementation environment schematic diagram of a data transmission method according to an embodiment of the present application. As shown in Figure 1As shown, the implementation environment includes a computer device, which can be a smartphone, a tablet computer, a notebook computer, a desktop computer, a smart speaker, a smart home appliance, a vehicle terminal, and the like, and the embodiments of the present application do not limit this. The computer device includes a CPU (Central Processing Unit) 01, a memory 02, and a memory controller 03 disposed in the CPU 10. The memory controller 03 is connected to the memory 02 of the computer device through a memory bus. It should be noted that the embodiments of the present application take the memory controller 10 disposed in the processor 20 as an example for description. Alternatively, the memory controller 03 can also be disposed outside the processor 01 and connected to the processor 01 and the memory 02 respectively. The memory lockstep structure constituted by the memory controller and the memory is relatively simple in design, and has good compatibility with mainstream general memory controller structures, so that the design cost and migration cost can be greatly reduced.

[0087] 3.1 For the convenience of description, the CPU 01 is referred to as the processor 01 hereinafter. The processor 01 is a core component for performing calculation and logical operation. When the processor 01 needs to write data into the memory 02, the processor 01 can send a memory write request to the memory controller 03 to write data into the memory 02 through the memory controller 03. Similarly, when the processor 01 needs to read data from the memory 02, the processor 01 can send a memory read request to the memory controller 03 to read data from the memory 02 through the memory controller 03.

[0088] 3.2 The memory 02 is used to temporarily store data and programs being processed by the CPU. In the embodiments of the present application, the memory 02 is taken as an M RDIMM for description. In the embodiments of the present application, the memory 02 includes a plurality of pseudo channels (Pseudo Channel) and a plurality of memory modules (Rank).

[0089] Referring to Figure 2 As shown, Figure 2 is a structural schematic diagram of a memory according to an embodiment of the present application. As Figure 2 shown, the memory 02 includes an MRCD (Multiplexed Rank Control Device) 201, an MDB (Multiplexed Data Buffer) 202, and a plurality of DRAMs 203.

[0090] The MDB 202 is responsible for dynamically switching data channels among multiple physical Ranks, and merging data of different Ranks onto the same group of DQs (Data Signals) for transmission. The MRCD 201 is responsible for coordinating access requests of multiple physical Ranks, and determining which physical Rank can occupy the data bus in the current cycle. The MRCD 201 can receive memory read / write commands from the memory controller 03, and convert them into operations on physical Ranks.

[0091] 3.3 The memory controller 03 comprises a first interface 101, an arbitration module 102, a command information module 103, a command queue 104, and an error correction module 105. The arbitration module 102 comprises a phase indication module 1021, an arbitration module 1022, and a protocol check module 1023. Optionally, the arbitration module 1022 comprises an arbitration unit 1022-1 and a linear shift queue 1022-2. The error correction module 105 comprises an error correction unit 1051 and a cache unit 1052. Optionally, the memory controller further comprises a second interface 106. The first interface 101 is connected to the processor 01. The arbitration module 102 is connected to the command information module 103, the command queue 104, and the second interface 106. The command information module 103 is connected to the first interface 101 and the arbitration module 102. The command queue 104 is connected to the first interface 101 and the arbitration module 102. The error correction module 105 is connected to the first interface 101 and the second interface 106. The second interface 106 is connected to the memory 02 and the memory controller 03. The phase indication module 1021 is connected to the arbitration module 1022. The arbitration module 1022 is connected to the command information module 103, the command queue 104, the phase indication module 1021, the protocol check module 1023, and the second interface 106. The arbitration unit 1022-1 is connected to the command information module 103, the command queue 104, the phase indication module 1021, the protocol check module 1023, and the linear shift queue 1022-2. The linear shift queue 1022-2 is connected to the command queue 104, the arbitration unit 1022-1, and the second interface 106.

[0092] 3.3.1 The first interface 101 is used to receive memory read / write requests from the processor 01. Optionally, the first interface 101 can comprise a protocol conversion function, by which the memory controller 03 can convert the internal bus protocol of the processor 01 into the protocol used by the memory controller 03.

[0093] 3.3.2 The arbitration module 102 is used to split the memory read / write request into multiple read / write transactions when the memory read / write request indicates to use the lockstep mode, and transmit the multiple read / write transactions to the memory 02 through the second interface 106 based on different phases indicated by the phase indication module 1021.

[0094] In the embodiment of the present application, the phase is a periodic signal, and the frequency of the phase is half of the frequency of the MDB command port. The phase is used to indicate which command (transaction) is currently used to send the command. For example, when the phase is 0 at a certain moment, it represents that the command of the pseudo channel 0 is currently used to send the command, and if the phase is 1, it represents that the command of the pseudo channel 1 is currently used to send the command. Moreover, the pseudo channel corresponding to each command is specified by the tag information corresponding to the command. The tag information will be introduced below.

[0095] When the memory controller 03 writes data into the memory 02, the memory controller 03 can actively control the phase of the clock signal and the data signal, and generally uses the edge of the clock signal to align with the center of the data signal. When the memory controller 03 reads data from the memory 02, the clock signal and the data signal returned by the memory 02 are edge-aligned, and the memory controller 03 needs to dynamically adjust the phase to re-align.

[0096] 3.3.2.1 The arbitration module 102 is further described below.

[0097] The phase indication module 1021 in the arbitration module 102 is used to output the phase identifiers of multiple phases to the arbitration module 1022 in turn. For example, the phase indication module 1021 outputs the phase identifiers that continuously flip in the running state to the arbitration module 1022.

[0098] The arbitration module 1022 in the arbitration module 102 is used to split the memory read / write request into multiple read / write transactions when the memory read / write request indicates to use the lockstep mode, and transmit the multiple read / write transactions to the memory 02 through the second interface 106 based on the phases indicated by the phase identifiers of the multiple phases output by the phase indication module 1021.

[0099] The protocol checking module 1023 in the arbitration module 102 is used to check whether the read / write transaction can be sent legally at the current moment according to the requirements of the MRCD / MDB / DDR5 standard protocol. If not, the read / write transaction is shielded, and if yes, the arbitration module 1022 is informed to further process the read / write transaction.

[0100] 3.3.2.1.1 The arbitration module 1022 is described as follows.

[0101] The arbitration unit 1022-1 in the arbitration module 1022 is configured to store the read-write transactions into the linear shift queue 1022-2 at positions corresponding to the phase identifiers carried by the read-write transactions based on the phase identifiers. The arbitration unit 1022-1 is connected with the phase indication module 1021 and the linear shift queue 1022-2.

[0102] The linear shift queue 1022-2 in the arbitration module 1022 is configured to transmit the read-write transactions to the memory 02 through the second interface 106 based on the phases indicated by the phase identifiers. The linear shift queue 1022-2 is connected with the second interface 106.

[0103] The command information module 103 is configured to store the tag information of the memory read-write requests. The command information module 103 is connected with the first interface 101 and the arbitration module 102 respectively. After receiving the memory read-write request sent by the processor 01, the memory controller 03 can parse and convert the memory read-write request to obtain the tag information and the memory read-write command of the memory read-write request.

[0104] The tag information provided by the embodiments of the present application includes four attributes, i.e., the index, the priority, the working mode and the target pseudo channel of the memory read-write command.

[0105] The index is used to indicate the position of the memory read-write command in the command queue 104. The priority is used to realize the differentiated processing of memory read-write commands of different levels and prevent blocking. The working mode includes the lockstep mode and the independent mode. Optionally, the memory controller 03 can limit the lockstep mode to be used when accessing data in a continuous memory address. The target pseudo channel is used to indicate which pseudo channel on the memory 02 is accessed when the data is accessed in the independent mode.

[0106] 3.3.4 The command queue 104 is used to store memory read / write commands converted based on memory read / write requests received from the processor. The memory read / write commands to be sent in the command queue 104 are stored in the form of a queue. The command queue 104 is connected with the first interface 101 and the arbitration module 102 respectively. The memory read / write commands in the command queue 104 are determined by the arbitration module 102 to determine the execution order. That is, the arbitration unit 1022-1 in the arbitration module 102 determines the memory read / write command to be sent, and sends the index of the memory read / write command to the command queue 104. The command queue 104 sends the corresponding memory read / write command to the linear shift queue 1022-2 in the arbitration module 102 based on the index, and the linear shift queue 1022-2 sends the memory read / write command to the memory 02.

[0107] 3.3.5 The error correction module 105 is used for data error correction and buffering data to be written. The error correction module 105 is connected with the first interface 101 and the second interface 106 respectively.

[0108] 3.3.5.1 The error correction module 105 is further described below.

[0109] In the scenario of writing data into the memory 02, the error correction unit 1051 is used to split the data to be written into a plurality of error correction data. The buffering unit 1052 is used to store the plurality of error correction data.

[0110] In the scenario of reading data from the memory 02, the error correction unit 1051 is used to modify the data obtained from the memory 02. It should be noted that in this scenario, the memory controller 03 can directly obtain complete data from the memory 02, and therefore does not need to buffer the data read step by step from the memory 02 through the buffering unit.

[0111] 3.3.6 The second interface 106 is used to connect the memory 02 and the memory controller 03. Optionally, the second interface 106 includes a command bus and a data bus.

[0112] The structure of the memory controller and the memory is introduced above, and the data transmission method provided by the embodiment of the application is described below by taking the scenario of sending a memory write request by the processor to write data into the memory as an example. Referring to Figure 3 , Figure 3 is a flowchart of a data transmission method according to an embodiment of the application. The data transmission method includes the following steps.

[0113] 301. The processor sends a memory write request to the memory controller through the first interface.

[0114] In the embodiments of the present application, when the processor executes a certain program, the processor can send a memory write request to the memory controller. For example, the write request can be "please write data 0xABCD into memory address 0x2000".

[0115] 302. The memory controller receives the memory write request from the processor through the first interface.

[0116] In the embodiments of the present application, the memory controller can parse the memory write request to obtain the tag information of the memory write request. The memory controller stores the tag information into the command information module. The memory controller can also convert the memory write request into a memory write command and put the memory write command into the command queue. The data to be written is sent by the memory controller into the error correction module.

[0117] 303. In the case where the memory write request indicates to use the lockstep mode, the memory controller splits the memory write command into multiple write transactions.

[0118] In the embodiments of the present application, the memory controller can determine the working mode of the memory write request through the tag information in the command information module. If the working mode is the lockstep mode, this step is executed.

[0119] The protocol checking module in the memory controller checks whether the memory write command corresponding to the memory write request meets the requirements of the MRCD / MDB / DDR5 protocol. If it meets, it reports to the arbitration unit in the memory controller.

[0120] The phase indication module in the memory controller sends the phase identifier of the current time to the arbitration unit.

[0121] The arbitration unit in the memory controller determines the index of the memory write command when the current phase is an even phase according to the arbitration algorithm, and sends the index to the command queue in the memory controller to take out the memory write command from the command queue. The arbitration unit can split the memory write command into two write transactions. The number of write transactions obtained by splitting is consistent with the number of pseudo-channels in the memory.

[0122] 304. The memory controller stores the write transaction into the position corresponding to the phase identifier in the linear shift queue based on the phase identifier carried by the write transaction, and the linear shift queue is used to transmit the write transaction to the memory based on the phase indicated by the phase identifier.

[0123] In the embodiments of the present application, the write transaction in the lockstep mode usually occupies two continuous spaces in the linear shift queue, i.e., position 0 and position 1, to ensure that the write transaction is continuously sent to the memory, which is the main function of the linear shift queue. The memory controller loads the above two write transactions to position 0 and position 1 of the linear shift queue. Among them, the write transaction at position 0 is sent to the pseudo channel 0 of the memory, and the write transaction at position 1 is sent to the pseudo channel 1 of the memory.

[0124] 305、The memory controller transmits a plurality of write transactions to the memory based on the linear shift queue and different phases respectively, so that the memory transmits the corresponding write transaction to the corresponding memory module in the pseudo channel indicated by the phase when receiving the plurality of write transactions.

[0125] In the embodiments of the present application, the linear shift queue first sends the write transaction at position 0, and then the arbitration unit reserves a clock cycle to instruct the linear shift queue to send the write transaction at position 1 in the next clock cycle, so as to avoid bus conflict.

[0126] It should be noted that the above describes the process of splitting the memory write command and storing it in the linear shift queue and sending it to the memory. Since the memory write command needs to write data to the memory, the memory controller can also perform error correction on the data to be written (hereinafter referred to as first data) through the error correction unit. Correspondingly, the error correction unit generates the ECC check bit of the first data based on the ECC algorithm. The memory controller combines the ECC check bit and the first data to obtain second data. Then, since the memory write request instruction adopts the lockstep mode, the memory controller splits the second data into two third data with the same size. The splitting method can refer to the above description of the lockstep mode, which will not be repeated here. The memory controller stores the two third data in the cache unit. After the two write transactions corresponding to the two third data are selected by the arbitration unit and sent to the memory by the linear shift queue, the memory controller sends the two third data with the ECC check bit in the cache unit to the memory.

[0127] Alternatively, for any one third data, the memory controller sends the third data to the memory in multiple times through multiple burst transmissions based on the phase corresponding to the third data, such as the odd phase, and sends a part of the third data each time. At the same time, the memory controller sends another third data to the memory in multiple times through multiple burst transmissions based on the phase corresponding to the other third data, such as the even phase, and sends a part of the other third data each time. Since the two pseudo channels of the memory support parallel processing, the memory can alternately obtain different third data from different phases and store the above two third data in the memory module through the corresponding pseudo channel at the same time.

[0128] For example, the second data is 64-bit data, and each of the third data is 32-bit data. The memory controller can transmit 4-bit data in the first third data in the even phase, transmit 4-bit data in the second third data in the odd phase, and then transmit 4-bit data in the first third data in the even phase again, that is, transmit different third data in the even and odd phases alternately. That is, the memory controller transmits two third data, and the two third data are distributed in the even and odd phases respectively, and then stored in the memory modules corresponding to two different pseudo channels. In the prior art, since there is no pseudo channel, 32-bit data of one third data is transmitted to the memory for multiple times, and then 32-bit data of another third data is transmitted. Obviously, the prior art takes twice as long as the scheme provided in the present application when transmitting 64-bit data.

[0129] It should be further noted that the above embodiments are described by taking the scenario that the memory write request indicates the lockstep mode as an example. The memory controller provided in the present application supports the non-lockstep mode, that is, the independent mode, in addition to the lockstep mode. For the independent mode, the write transaction only needs to be selected from the command queue according to the phase indication and placed in position 0 of the linear shift queue.

[0130] Correspondingly, in the case that the memory write request indicates the independent mode, the arbitration unit determines the value of the target pseudo channel corresponding to the memory write command (write transaction) of the memory write request according to the tag information of the memory write request. Then, the arbitration unit instructs the linear shift queue to load the memory write command in the corresponding position according to the value of the target pseudo channel, and correspondingly sends the memory write command to the memory in the phase.

[0131] The data transmission method provided in the embodiments of the present application will be described below by taking the scenario that the processor sends a memory read request to read data from the memory as an example. Referring to Figure 4 , Figure 4 is a flow diagram of another data transmission method provided in the embodiments of the present application. The data transmission method comprises the following steps.

[0132] 401. The processor sends a memory read request to the memory controller through the first interface.

[0133] In the embodiments of the present application, when the processor executes a certain program, the processor can send a memory read request to the memory controller. For example, the read request (Read Request) can be "please send me the data at the memory address 0x1000".

[0134] 402. The memory controller receives the memory read request from the processor through the first interface.

[0135] In the embodiment of the present application, the memory controller can parse the memory read request to obtain the tag information of the memory read request. The memory controller stores the tag information into the command information module. The memory controller can also convert the memory read request into a memory read command and put the memory read command into the command queue.

[0136] 403、In the case where the memory read request indicates to use the lockstep mode, the memory controller splits the memory read command into multiple read transactions.

[0137] In the embodiment of the present application, the memory controller can determine the working mode of the memory write request through the tag information in the command information module. If the working mode is the lockstep mode, the present step is executed.

[0138] The protocol checking module in the memory controller checks whether the memory read command corresponding to the memory read request meets the requirements of the MRCD / MDB / DDR5 protocol. If it meets, the protocol checking module reports to the arbitration unit in the memory controller.

[0139] The phase indication module in the memory controller sends the phase identifier of the current time to the arbitration unit.

[0140] The arbitration unit in the memory controller determines the index of the memory read command according to the arbitration algorithm when the phase of the current time is the even phase, and sends the index to the command queue in the memory controller to take out the memory read command from the command queue. The arbitration unit can split the memory read command into two read transactions. The number of read transactions obtained by splitting is consistent with the number of pseudo-channels in the memory.

[0141] 404、The memory controller stores the read transaction into the position corresponding to the phase identifier in the linear shift queue based on the phase identifier carried by the read transaction. The linear shift queue is used to transmit the read transaction to the memory based on the phase indicated by the phase identifier.

[0142] In the embodiment of the present application, the read transaction of the lockstep mode usually occupies two consecutive spaces in the linear shift queue, i.e. position 0 and position 1, to ensure that the read transaction is continuously sent to the memory, which is the main function of the linear shift queue. The memory controller loads the above two read transactions into position 0 and position 1 of the linear shift queue. The read transaction of position 0 is sent to the pseudo-channel 0 of the memory, and the read transaction of position 1 is sent to the pseudo-channel 1 of the memory.

[0143] 405、The memory controller transmits multiple read transactions to the memory based on different phases based on the linear shift queue, so that the memory transmits the corresponding read transaction to the corresponding memory module in the memory through the pseudo-channel indicated by the phase when receiving multiple read transactions.

[0144] In the embodiment of the present application, the linear shift queue first sends the read transaction at position 0, and then the arbitration unit reserves a clock cycle to instruct the linear shift queue to send the read transaction at position 1 in the next clock cycle, so as to avoid bus conflict.

[0145] Optionally, the memory controller can read data from the memory by multiple burst transmissions, such as 16 burst transmissions. When reading data, different data is transmitted by alternately transmitting data in odd and even phases, that is, two pieces of data are respectively dispersed in the odd and even phases, so as to obtain complete data including error correction code. There is no need to wait for one piece of data to be transmitted completely before transmitting another piece of data, which significantly improves the efficiency of data reading. The memory controller can also correct the complete data including error correction code by the error correction unit. If there is no error, the data is returned to the processor.

[0146] It should be further noted that the above embodiment is described by taking the scenario of using the lockstep mode as an example. The memory controller provided in the present application supports the non-lockstep mode, that is, the independent mode, in addition to the lockstep mode.

[0147] Correspondingly, in the case of using the independent mode, the arbitration unit determines the value of the target pseudo-channel corresponding to the memory read command (read transaction) of the memory read request according to the tag information of the memory read request. Then, the arbitration unit instructs the linear shift queue to load the memory read command at the corresponding position and send the memory read command to the memory in the corresponding phase according to the value of the target pseudo-channel.

[0148] It should be noted that for special types of commands such as MRR commands, the memory requires an interval of more than 1 clock cycle between two commands in the lockstep mode. The linear shift queue loads the MRR command to position 0 and position n according to the working mode and command type sent by the arbitration unit, where n is the interval required by the command type.

[0149] Figure 5 is a schematic diagram of a data transmission device according to an embodiment of the present application. The data transmission device is configured in a memory controller, and the memory controller is used to connect with a memory of a computer device. The memory includes a plurality of pseudo-channels and a plurality of memory modules, and the plurality of pseudo-channels are used to access the plurality of memory modules. The device includes a request receiving module 501, a request splitting module 502, and a transaction transmission module 503.

[0150] The request receiving module 501 is configured to receive a memory read / write request from a processor of the computer device.

[0151] The request splitting module 502 is configured to split the memory read-write request into a plurality of read-write transactions in a case where the memory read-write request indicates that the lockstep mode is adopted.

[0152] The transaction transmission module 503 is configured to transmit the plurality of read-write transactions to the memory based on different phases respectively, so that the memory transmits the corresponding read-write transaction to the corresponding memory module in the memory through the pseudo channel indicated by the phase in a case where the memory receives the plurality of read-write transactions.

[0153] The phase is used to indicate the pseudo channel adopted when the corresponding read-write transaction is transmitted.

[0154] In some embodiments, the request splitting module 502 is configured to split the memory write request into a plurality of write transactions in a case where the memory read-write request indicates that the lockstep mode is adopted, and the write transaction is used to write data into the memory; and split the memory read request into a plurality of read transactions in a case where the memory read-write request indicates that the lockstep mode is adopted, and the read transaction is used to read data from the memory.

[0155] In some embodiments, the transaction transmission module 503 is configured to store the read-write transaction into a position corresponding to the phase identifier in the linear shift queue based on the phase identifier carried by the read-write transaction for any read-write transaction, and the linear shift queue is used to transmit the read-write transaction to the memory based on the phase indicated by the phase identifier.

[0156] In some embodiments, the transaction transmission module 503 is further configured to generate error correction data based on the data to be written indicated by the write transaction for any write transaction, cache the error correction data, and send the error correction data to the memory in a case where a response of the memory to the write transaction is received.

[0157] In some embodiments, the transaction transmission module 503 is further configured to determine a target pseudo channel corresponding to the read-write transaction of the memory read-write request in a case where the memory read-write request indicates that the independent mode is adopted, and transmit the read-write transaction to the memory, so that the memory transmits the read-write transaction to the corresponding memory module in the memory through the target pseudo channel in a case where the read-write transaction is received.

[0158] In some embodiments, the transaction transmission module 503 is further configured to transmit the read-write transaction through the phase indicated by the phase identifier corresponding to the target pseudo channel based on the phase identifier for any read-write transaction.

[0159] In some embodiments, the transaction transmission module 503 is further configured to acquire data based on the target pseudo channel and perform error correction by the memory for any read transaction.

[0160] The embodiment of the present application provides a data transmission device, by splitting the memory read-write request in the lockstep mode into multiple read-write transactions and distributing the read-write transactions to different pseudo channels based on different phases, a new memory lockstep structure is provided, the memory lockstep structure fully utilizes the concurrent characteristics supported by the pseudo channels, when writing data, the corresponding pseudo channel in the memory is indicated by using the phase, so that different data can be alternately sent to the memory through different phases, and the received data is accurately routed to the corresponding memory module by different pseudo channels in the memory. That is, in the lockstep mode, after the data is split into two parts by the ECC algorithm, the memory can transmit the two parts of data at the same time, without first transmitting one part and then transmitting the other part, thereby reducing the time consumption of data transmission, while ensuring the data reliability and the data integrity, the data transmission efficiency is significantly improved.

[0161] The above only describes optional embodiments of the present application and is not used to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A data transmission method, characterized in that, An application is made to a memory controller for connecting to the memory of a computer device, the memory including multiple pseudo-channels and multiple memory modules, the multiple pseudo-channels being used to access the multiple memory modules, the method comprising: Receive memory read / write requests from the processor of the computer device; If the memory read / write request indication adopts lockstep mode, the memory read / write request is split into multiple read / write transactions; The multiple read and write transactions are transmitted to the memory based on different phases, so that when the memory receives the multiple read and write transactions, it transmits the corresponding read and write transactions to the corresponding memory modules in the memory through the pseudo-channel indicated by the phase. The phase is used to indicate the pseudo-channel used when transmitting the corresponding read / write transaction.

2. The method according to claim 1, characterized in that, When the memory read / write request indication adopts lockstep mode, the memory read / write request is split into multiple read / write transactions, including: When the memory read / write request indication adopts lockstep mode, if the memory read / write request is a memory write request, the memory write request is split into multiple write transactions, and the write transactions are used to write data into the memory; When the memory read / write request indication adopts lockstep mode, if the memory read / write request is a memory read request, the memory read request is split into multiple read transactions, and the read transactions are used to read data from the memory.

3. The method according to claim 1, characterized in that, The step of transferring the multiple read and write transactions to the memory based on different phases includes: For any read / write transaction, based on the phase identifier carried by the read / write transaction, the read / write transaction is stored in the linear shift queue at the position corresponding to the phase identifier. The linear shift queue is used to transfer the read / write transaction to the memory based on the phase indicated by the phase identifier.

4. The method according to claim 3, characterized in that, The method further includes: For any write transaction, error correction data is generated based on the data to be written as indicated by the write transaction; Cache the error correction data; Upon receiving a response from the memory for the write transaction, the error correction data is sent to the memory.

5. The method according to any one of claims 1-4, characterized in that, The method further includes: When the memory read / write request indication adopts the independent mode, the target pseudo-channel corresponding to the read / write transaction of the memory read / write request is determined; The read / write transaction is transmitted to the memory, so that when the memory receives the read / write transaction, it transmits the read / write transaction to the corresponding memory module in the memory through the target pseudo-channel.

6. The method according to claim 5, characterized in that, The step of transferring the read / write transaction to the memory includes: For any read / write transaction, the read / write transaction is transmitted through the phase indicated by the phase identifier corresponding to the target pseudo-channel.

7. The method according to claim 6, characterized in that, The method further includes: For any read transaction, data is obtained from the memory based on the target pseudo-channel and error correction is performed.

8. A memory controller, characterized in that, The memory controller is used to connect to the memory of a computer device. The memory includes multiple pseudo-channels and multiple memory modules. The multiple pseudo-channels are used to access the multiple memory modules. The memory controller includes: a first interface and an arbitration module. The first interface is used to receive memory read / write requests from the processor; The arbitration module is used to split the memory read / write request into multiple read / write transactions when the memory read / write request indication adopts lockstep mode, and transmit the multiple read / write transactions to the memory based on different phases, so that when the memory receives the multiple read / write transactions, it can transmit the corresponding read / write transactions to the corresponding memory module in the memory through the pseudo-channel indicated by the phase. The phase is used to indicate the pseudo-channel used when transmitting the corresponding read / write transaction.

9. The memory controller according to claim 8, characterized in that, The arbitration module includes a phase indicator module and an arbitration module, wherein the phase indicator module is connected to the arbitration module. The phase indication module is used to output phase identifiers of multiple phases to the arbitration module in turn; The arbitration module is used to split the memory read / write request into multiple read / write transactions when the memory read / write request indication adopts lockstep mode, and to transmit the multiple read / write transactions to the memory respectively based on the phase identifiers of the multiple phases output by the phase indication module and the phases indicated by the phase identifiers of the multiple phases.

10. The memory controller according to claim 9, characterized in that, The arbitration module includes an arbitration unit and a linear shift queue. The arbitration unit is connected to the phase indication module and the linear shift queue. The arbitration unit is used to store the multiple read and write transactions into the position corresponding to the phase identifier in the linear shift queue based on the phase identifier carried by the multiple read and write transactions; The linear shift queue is used to transfer the plurality of read and write transactions to the memory based on the phase indicated by the phase identifier.

11. The memory controller according to any one of claims 8-10, characterized in that, The memory controller further includes a command queue, a command information module, and an error correction module. The command queue is connected to the first interface and the arbitration module, respectively. The command information module is also connected to the first interface and the arbitration module, respectively. The command queue is used to store memory read / write requests received from the processor; The command information module is used to store the tag information of the memory read / write request, and the tag information includes the working mode adopted by the memory read / write request; The error correction module is used for data error correction and caching of data to be written.

12. The memory controller according to claim 11, characterized in that, The error correction module includes an error correction unit and a cache unit; The error correction unit is used to split the data to be written into multiple error correction data; The cache unit is used to store the plurality of error correction data.

13. The memory controller according to claim 12, characterized in that, The error correction unit is also used to correct errors in the data obtained through the memory.

14. The memory controller according to any one of claims 8-10, characterized in that, The arbitration module is also used to determine the target pseudo-channel corresponding to the read / write transaction of the memory read / write request when the memory read / write request indication adopts independent mode, and transmit the read / write transaction to the memory, so that when the memory receives the read / write transaction, it transmits the read / write transaction to the corresponding memory module in the memory through the target pseudo-channel.

15. The memory controller according to claim 14, characterized in that, The arbitration module includes a phase indicator module and an arbitration module, wherein the phase indicator module is connected to the arbitration module. The phase indication module is used to output phase identifiers of multiple phases to the arbitration module in turn; The arbitration module is used to transmit the read / write transaction based on the phase identifier corresponding to the target pseudo-channel, through the phase indicated by the phase identifier.

16. A chip, characterized in that, The chip includes the memory controller according to any one of claims 8-15.

17. A computer device, characterized in that, The computer device includes a processor and a memory, the processor including a chip configured with a memory controller as described in any one of claims 8-15, the memory storing a computer program, the computer program being loaded and executed by the processor to implement the data transmission method as described in any one of claims 1-7.

18. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which is loaded and executed by a processor to implement the data transmission method as described in any one of claims 1 to 7.

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