Special computing chip resource allocation method and device, Ray framework and equipment
By constructing a dedicated computing chip topology information tree, the combination of dedicated computing chips with the lowest communication overhead is determined and allocated, which solves the problem of resource allocation affecting computing performance in the prior art, improves computing performance and resource utilization efficiency, and is suitable for large-scale distributed training and real-time inference.
Patent Information
- Application Number
- CN202511098636.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-06
- Publication Date
- 2025-11-21
Smart Images
Figure CN120994378A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and more specifically, to a method, apparatus, Ray framework, and device for allocating resources for a dedicated computing chip. Background Technology
[0002] When a node in the Ray framework initiates a task, that node will select a suitable node from all nodes in the Ray framework to execute the task.
[0003] Once the selected node receives the task, if the task requires dedicated computing chip resources, it will allocate a corresponding number of idle dedicated computing chips from among the selected nodes in sequence to the task. However, this allocation method of dedicated computing chips may affect computing performance and resource utilization efficiency. Summary of the Invention
[0004] This application provides a method, apparatus, Ray framework, and device for allocating dedicated computing chip resources, in order to solve the problem that the existing methods of allocating dedicated computing chip resources may affect computing performance and resource utilization efficiency.
[0005] In a first aspect, this application provides a method for allocating dedicated computing chip resources, applied to a target electronic device having multiple dedicated computing chips. The method includes: in response to receiving a task to be executed and task requirement information of the task to be executed, determining a target dedicated computing chip combination for executing the task to be executed based on the idle state of each of the dedicated computing chips; wherein the target dedicated computing chip combination is: a combination of dedicated computing chips that includes a number of dedicated computing chips that meets the number of dedicated computing chips required in the task requirement information and has the lowest communication overhead; all dedicated computing chips in the target dedicated computing chip combination are idle dedicated computing chips; and allocating the target dedicated computing chip combination to the task to be executed.
[0006] In this embodiment, when allocating dedicated computing chips, the combination of dedicated computing chips with the lowest communication overhead is selected as the target dedicated computing chip combination and allocated to the task to be executed. Since the communication overhead between this target dedicated computing chip combination is minimal, the communication efficiency between different dedicated computing chips is high when executing the task, thereby improving data transmission efficiency and ultimately improving computing performance. When allocating the same number of dedicated computing chips to the task to be executed, existing technologies typically allocate a corresponding number of idle dedicated computing chips sequentially from selected nodes. This allocation method does not consider the overhead between different dedicated computing chips. Compared to the dedicated computing chip allocation method adopted in this application, the computing performance of this allocation method is generally higher than that of existing allocation methods, thereby improving the utilization efficiency of dedicated computing chip resources.
[0007] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, determining a target dedicated computing chip combination for executing the task to be executed based on the idle state of each of the dedicated computing chips includes: determining all idle dedicated computing chips based on the idle state of each of the dedicated computing chips; constructing a dedicated computing chip topology information tree based on all the idle dedicated computing chips in the target electronic device; the dedicated computing chip topology information tree includes the communication overhead between any two idle dedicated computing chips; determining the overhead corresponding to each dedicated computing chip combination based on the dedicated computing chip topology information tree; wherein, the number of dedicated computing chips included in the dedicated computing chip combination is determined according to the task requirement information of the task to be executed; and determining the dedicated computing chip combination with the minimum overhead as the target dedicated computing chip combination.
[0008] In this embodiment, a topology information tree is constructed from all identified idle dedicated computing chips, allowing the determination of the communication overhead between any two idle dedicated computing chips. This enables the accurate identification of the dedicated computing chip combination with the lowest overhead.
[0009] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, a dedicated computing chip topology information tree is constructed based on all idle dedicated computing chips in the target electronic device, including: obtaining attribute information of each idle dedicated computing chip, the attribute information including topology information of the interconnection between the idle dedicated computing chip and other idle dedicated computing chips; and constructing the dedicated computing chip topology information tree based on the attribute information of each idle dedicated computing chip.
[0010] In this embodiment, by using attribute information including topology information of interconnections between idle dedicated computing chips and other idle dedicated computing chips, the topology structure between different idle dedicated computing chips can be accurately determined based on the attribute information, thereby improving the accuracy of the constructed topology information tree.
[0011] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, after allocating the target dedicated computing chip assembly to the task to be executed, the method further includes: marking the dedicated computing chips included in the target dedicated computing chip assembly as non-idle dedicated computing chips.
[0012] In this embodiment of the application, after the target dedicated computing chip combination is allocated to the task to be executed, all dedicated computing chips in the target dedicated computing chip combination are no longer idle chips. Therefore, they need to be marked as non-idle dedicated computing chips to prevent them from being repeatedly allocated.
[0013] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, before determining the target combination of dedicated computing chips for executing the task to be executed based on the idle state of each of the dedicated computing chips, the method further includes: determining that the number of dedicated computing chips required by the task to be executed is less than the number of idle dedicated computing chips in the target electronic device.
[0014] In this embodiment, when the number of dedicated computing chips required by the task to be executed is greater than or equal to the number of idle dedicated computing chips in the target electronic device, it is usually necessary to allocate all dedicated computing chips to the task. In this case, there is only one combination of dedicated computing chips, and there is no need to determine communication overhead. Therefore, by determining that the number of dedicated computing chips required by the task to be executed is less than the number of idle dedicated computing chips in the target electronic device, unnecessary communication overhead determinations can be eliminated, reducing workload.
[0015] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, before determining the target combination of dedicated computing chips for executing the task to be executed based on the idle state of each of the dedicated computing chips, the method further includes: determining that the task to be executed needs to be executed: determining the target combination of dedicated computing chips for executing the task to be executed based on the idle state of each of the dedicated computing chips.
[0016] In this embodiment, there may be allocation methods where the task to be executed does not require the execution of the dedicated computing chip of this solution. Therefore, before determining the target dedicated computing chip combination for executing the task to be executed, the step of determining the target dedicated computing chip combination for executing the task to be executed based on the idle state of each dedicated computing chip is used to filter out the tasks to be executed that do not need to be executed.
[0017] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, the target electronic device pre-stores a complete topology information tree, which includes the communication overhead between any two dedicated computing chips in the target electronic device; based on the idle state of each dedicated computing chip, a target dedicated computing chip combination for executing the task to be executed is determined, including: based on the idle state of each dedicated computing chip, determining all idle dedicated computing chips; based on the complete topology information tree, calculating the communication overhead between any two idle dedicated computing chips; based on the communication overhead between any two idle dedicated computing chips, obtaining the total communication overhead of each dedicated computing chip combination; wherein, all dedicated computing chips included in any dedicated computing chip combination are idle dedicated computing chips; and determining the dedicated computing chip combination with the minimum total communication overhead as the target dedicated computing chip combination.
[0018] In this embodiment, by pre-configuring a complete topology information tree, the total communication overhead of each dedicated computing chip combination can be quickly determined based on this tree. This eliminates the need to construct the topology information tree each time, improving the efficiency of determining the target dedicated computing chip combination.
[0019] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, the target electronic device pre-stores the communication overhead between any two dedicated computing chips in the target electronic device; based on the idle state of each dedicated computing chip, a target dedicated computing chip combination for executing the task to be executed is determined, including: based on the idle state of each dedicated computing chip, determining all idle dedicated computing chips; based on the pre-stored communication overhead between any two dedicated computing chips, determining the total communication overhead of each dedicated computing chip combination; wherein, all dedicated computing chips included in any dedicated computing chip combination are idle dedicated computing chips; and determining the dedicated computing chip combination with the minimum total communication overhead as the target dedicated computing chip combination.
[0020] In this embodiment, since the communication overhead between any two dedicated computing chips within the target electronic device has been pre-stored, once an idle dedicated computing chip is identified, the total communication overhead of each dedicated computing chip combination can be quickly determined directly based on the pre-stored communication overhead between any two dedicated computing chips. This improves the efficiency of identifying the target dedicated computing chip combination.
[0021] In a second aspect, this application provides a dedicated computing chip resource allocation device, deployed in a target electronic device having multiple dedicated computing chips. The device includes: a determining module and an allocation module. The determining module is configured to, in response to receiving a task to be executed and task requirement information of the task to be executed, determine a target dedicated computing chip combination for executing the task to be executed based on the idle state of each dedicated computing chip. The target dedicated computing chip combination is defined as a combination of dedicated computing chips whose number of dedicated computing chips meets the requirement in the task requirement information and whose communication overhead is minimized. All dedicated computing chips in the target dedicated computing chip combination are idle dedicated computing chips. The allocation module is configured to allocate the target dedicated computing chip combination to the task to be executed.
[0022] Thirdly, this application provides a dedicated computing chip resource allocation method applied to a designated task node in the Ray framework. The Ray framework further includes at least one other task node, and the designated task node is the task node in the Ray framework that initiates a task to be executed. Different task nodes are interconnected. The method includes: obtaining the task to be executed and its task requirement information; selecting a target task node from all the task nodes to execute the task to be executed; and sending the task to be executed and its task requirement information to the target task node, so that the target task node executes the method described in the first aspect and / or in combination with any possible implementation of the first aspect.
[0023] Fourthly, this application provides a Ray framework, comprising: multiple task nodes interconnected; a designated task node for acquiring a task to be executed and task requirement information of the task to be executed; selecting a target task node from the multiple task nodes to execute the task to be executed; sending the task to be executed and the task requirement information of the task to be executed to the target task node; wherein the designated task node is the task node in the Ray framework that initiates the task to be executed; the target task node, in response to receiving the task to be executed and the task requirement information of the task to be executed, determines a target combination of dedicated computing chips for executing the task to be executed based on the idle state of each dedicated computing chip; wherein the target combination of dedicated computing chips is a combination of dedicated computing chips whose number of dedicated computing chips meets the number of dedicated computing chips required in the task requirement information and whose communication overhead is minimal; all dedicated computing chips in the target combination of dedicated computing chips are idle dedicated computing chips; and allocating the target combination of dedicated computing chips to the task to be executed.
[0024] Fifthly, this application provides an electronic device comprising: a memory, a processor, and at least two dedicated computing chips, wherein the memory and the processor are connected, and the processor is communicatively connected to each of the dedicated computing chips; the memory is used to store a program; and the processor is used to invoke the program stored in the memory to execute the method described in the first aspect and / or in combination with any possible implementation of the first aspect. Attached Figure Description
[0025] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0026] Figure 1 This is a schematic diagram illustrating the composition of a Ray Cluster according to an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a Ray frame as shown in an embodiment of this application; Figure 3 This is a flowchart illustrating the first dedicated computing chip resource allocation method according to an embodiment of this application; Figure 4 This is a schematic diagram illustrating the structure of a topology information tree according to an embodiment of this application; Figure 5This is a flowchart illustrating a second method for allocating resources for a dedicated computing chip, as shown in an embodiment of this application. Figure 6 This is a schematic diagram illustrating the structure of a dedicated computing chip resource allocation device according to an embodiment of this application; Figure 7 This is a flowchart illustrating a third dedicated computing chip resource allocation method according to an embodiment of this application; Figure 8 This is a schematic diagram illustrating the structure of a Ray framework capable of topology awareness, as shown in an embodiment of this application. Figure 9 This is a structural block diagram of an electronic device shown in an embodiment of this application. Detailed Implementation
[0027] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.
[0028] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.
[0029] The technical solution of this application will now be described in detail with reference to the accompanying drawings.
[0030] like Figure 1 As shown, a Ray Cluster (a distributed computing cluster feature provided by the Ray framework, supporting efficient execution of computing tasks in a multi-node environment) is a distributed computing cluster consisting of one Head Node and any number of Worker Nodes. It is used to run Ray applications and supports distributed execution and management of tasks and data. The number of worker nodes can be automatically scaled according to the application requirements specified in the Ray cluster configuration.
[0031] GCS (Global Control Service) is a global service that manages object storage, ensuring data consistency and availability in a distributed environment.
[0032] Ray is a high-performance computing framework for building distributed applications.
[0033] Existing Ray frameworks such as Figure 2 As shown, a Task is the smallest unit of execution initiated by a Driver or Worker. When user code calls a remote function, the Driver or Worker submits the Task to the local Raylet. The Raylet is responsible for registering the Task with the global GCS.
[0034] In the Ray framework, a Task refers to a remotely executable function call unit, which is the basic granularity for Ray's distributed task scheduling and execution. Each Task typically corresponds to a user-defined remote function, which is asynchronously submitted by the Driver or Worker and executed asynchronously on a node in the cluster.
[0035] The Driver (also known as the Driver Process) is the client process in Ray that controls the task execution flow, responsible for initiating tasks and retrieving results. The Driver process typically runs on the Head Node.
[0036] The Driver process can submit Tasks to Raylet, and Raylet assigns Tasks to Worker Processes.
[0037] A Worker (or Worker Process) is a process in Ray that executes Tasks. A Worker Process can also submit Tasks to Raylets, which then distribute the Tasks to other Worker Processes.
[0038] Raylet is a system process that runs on each Ray node and is responsible for task scheduling (selecting a suitable Worker node to run the Task) and resource allocation (allocating specific resources according to the resource requests of the Task) on that node. Task scheduling is handled by the Scheduler module in Raylet.
[0039] GCS is responsible for global coordination, recording task metadata and the overall Ray cluster resource status. The specific scheduling of tasks is handled by the Scheduler inside the Raylet on the node that initiated the task. It selects a suitable target node and an available Worker to execute the task based on the global resource view. After receiving the task, the Raylet on the selected target node puts it into its local queue and selects an idle Worker process to execute the task.
[0040] Throughout the process, the Global Control Service manages the data objects required for the task, ensuring efficient data transfer and sharing across different nodes. This entire process demonstrates Ray's efficient task scheduling, fine-grained resource management, and distributed execution capabilities.
[0041] However, for tasks that require dedicated computing chips such as GPUs (Graphics Processing Units), Raylet currently makes scheduling decisions based solely on the number and basic attributes of GPUs when allocating dedicated computing chip resources for such tasks. This may result in tasks being assigned to multiple GPUs that are physically far apart or have low communication efficiency, thereby affecting computing performance and resource utilization efficiency.
[0042] Please see Figure 3 , Figure 3 This is a flowchart illustrating a dedicated computing chip resource allocation method according to an embodiment of this application. The method is applied to a target electronic device with multiple dedicated computing chips. The following will describe the method in conjunction with... Figure 3 The steps involved are explained.
[0043] S110: In response to receiving the task to be executed and the task requirement information of the task to be executed, the target combination of dedicated computing chips for executing the task is determined based on the idle state of each dedicated computing chip.
[0044] The target dedicated computing chip combination is defined as follows: the combination of dedicated computing chips that includes the number of dedicated computing chips required in the task requirements information and has the lowest communication overhead; all dedicated computing chips in the target dedicated computing chip combination are idle dedicated computing chips.
[0045] Specialized computing chips are computing chips other than general-purpose computing chips such as CPUs (Central Processing Units).
[0046] For example, dedicated computing chips can be GPUs, NPUs (embedded neural network processors), AI (Artificial Intelligence) computing chips, etc. Dedicated computing chips are not limited to the types of chips exemplified here.
[0047] Optionally, the dedicated computing chip in this solution is a GPU.
[0048] Based on the idle state of each dedicated computing chip, the specific way to determine the target dedicated computing chip combination for executing the task to be executed can be implemented in the following ways.
[0049] In the first implementation, the method for determining the target dedicated computing chip combination for executing the task based on the idle state of each dedicated computing chip can be as follows: First, all idle dedicated computing chips are identified based on their idle states. Then, a dedicated computing chip topology information tree is constructed based on all idle dedicated computing chips in the target electronic device; the dedicated computing chip topology information tree includes the communication overhead between any two idle dedicated computing chips. Next, based on the dedicated computing chip topology information tree, the overhead corresponding to each dedicated computing chip combination is determined; wherein the number of dedicated computing chips included in a dedicated computing chip combination is determined according to the task requirements information of the task to be executed. Finally, the dedicated computing chip combination with the lowest overhead is determined as the target dedicated computing chip combination.
[0050] By constructing a topology tree of all identified idle dedicated computing chips, the communication overhead between any two idle dedicated computing chips can be determined based on this topology tree. This allows for the accurate identification of the dedicated computing chip combination with the lowest overhead.
[0051] Optionally, the topology information tree can describe the overhead information of each functional module that appears in the path that communication between all idle dedicated computing chips needs to pass through. Subsequently, based on the overhead of each module that passes through in the communication path between two idle dedicated computing chips, the communication overhead between any two idle dedicated computing chips can be calculated.
[0052] For example, if communication between two idle dedicated computing chips requires the CPU, the topology tree will describe the communication overhead required by the CPU. The communication overhead between the two idle dedicated computing chips can be obtained by summing the communication overhead of all functional modules involved in the communication between them.
[0053] The functional modules can be any functional modules that require communication overhead, such as CPU, Switch, gateway, or communication bus. There are no restrictions on their specific types.
[0054] Optionally, the topology information tree can also directly record the communication overhead between any two idle dedicated computing chips. In this case, the communication overhead between any two dedicated computing chips can be directly read from this topology information tree.
[0055] Optionally, the method for constructing a dedicated computing chip topology information tree based on all idle dedicated computing chips in the target electronic device can be as follows: First, obtain the attribute information of each idle dedicated computing chip, including the topology information of the interconnections between the idle dedicated computing chip and other idle dedicated computing chips. Then, construct the dedicated computing chip topology information tree based on the attribute information of each idle dedicated computing chip.
[0056] Among them, the attribute information can be the physical deployment information of the dedicated computing chips on the current target electronic device and their topological connection relationships (such as PCIe (a high-speed serial computer expansion bus standard) bus topology, NVLink (a bus and its communication protocol) connection topology, etc.) obtained through system device management tools (such as lspci).
[0057] If the dedicated computing chip is a GPU, the attribute information can also be obtained through GPU management tools, which can be used to obtain the physical deployment information of the GPUs on the current target electronic device and their topological connections (such as PCIe bus topology, NVLink connection topology, etc.).
[0058] For example, if the GPU is an Nvidia GPU, then the GPU management tool could be nvidia-smi. It is understood that different GPUs may require different GPU management tools; therefore, no specific type of GPU management tool is restricted here.
[0059] The constructed topology tree displays the hardware (such as buses, CPUs, etc.) required for a connection between any two dedicated computing chips, as well as the communication overhead for each piece of hardware. Based on this, the communication overhead between any two dedicated computing chips can be calculated.
[0060] Optionally, the method for determining the overhead of each dedicated computing chip combination based on the dedicated computing chip topology information tree can be as follows: First, calculate the communication overhead between any two idle dedicated computing chips based on the dedicated computing chip topology information tree. Then, for each dedicated computing chip combination, pairwise combine the dedicated computing chips in that combination and determine the communication overhead of each pair of dedicated computing chips (i.e., the dedicated computing chips in each pairwise combination). Finally, sum the communication overhead of all pairs of dedicated computing chips in that dedicated computing chip combination to obtain the communication overhead of that dedicated computing chip combination.
[0061] For ease of understanding, Figure 4 The following explanation uses a dedicated computing chip topology information tree as an example.
[0062] If each dedicated computing chip combination includes 3 dedicated computing chips, then Figure 4 The GPUs 3, 4, 5, 6, and 7 shown have various dedicated computing chip combinations. First, the communication overhead between any two dedicated computing chips can be calculated. For example, the communication overhead between GPU 3 and GPU 4 is 10; between GPU 3 and GPU 5 is 220; between GPU 3 and GPU 6 is 220; between GPU 3 and GPU 7 is 220; between GPU 4 and GPU 5 is 220; between GPU 4 and GPU 6 is 220; between GPU 4 and GPU 7 is 220; between GPU 5 and GPU 6 is 70; between GPU 5 and GPU 7 is 70; and between GPU 6 and GPU 7 is 10.
[0063] For a dedicated computing chip combination including GPU3, GPU4, and GPU5, the total communication overhead is GPU3-4 communication overhead + GPU3-5 communication overhead + GPU4-5 communication overhead = 10 + 220 + 220 = 450. Correspondingly, the total communication overhead for GPU3,4,6 is 10 + 220 + 220 = 450; for GPU3,4,7 it is 10 + 220 + 220 = 450; for GPU4,5,6 it is 220 + 220 + 70 = 510; for GPU4,5,7 it is 220 + 220 + 70 = 510; and for GPU5,6,7 it is 70 + 70 + 10 = 150. The total communication overhead for all dedicated computing chip combinations is not shown here.
[0064] Optionally, determining the overhead of each dedicated computing chip combination based on the dedicated computing chip topology information tree can also be done as follows: First, identify all computing chip combinations based on the dedicated computing chip topology information tree. Then, for each computing chip combination, pair up the dedicated computing chips in that combination and determine the communication overhead of each pair of dedicated computing chips according to the dedicated computing chip topology information tree. Finally, sum the communication overhead of all pairs of dedicated computing chips in that dedicated computing chip combination to obtain the communication overhead of that dedicated computing chip combination.
[0065] For ease of understanding, Figure 4 The following explanation uses a dedicated computing chip topology information tree as an example.
[0066] If each dedicated computing chip combination includes 3 dedicated computing chips, then it can be determined that there are 10 dedicated computing chip combinations.
[0067] Then, for each dedicated computing chip combination, its corresponding total communication overhead is determined. Taking a dedicated computing chip combination including GPU3, GPU4, and GPU5 as an example, the communication overhead between GPU3 and GPU4 can be determined as 10 based on the dedicated computing chip topology information tree; the communication overhead between GPU3 and GPU5 is 220; and the communication overhead between GPU4 and GPU5 is 220. These three communication overheads are then summed to determine the total communication overhead of this dedicated computing chip combination as 10 + 220 + 220 = 450. The calculation method for the total communication overhead between other dedicated computing chips is the same, and will not be described in detail here.
[0068] In the second implementation, a complete topology information tree may be pre-stored within the target electronic device, and the complete topology information tree may include the communication overhead between any two dedicated computing chips in the target electronic device.
[0069] Accordingly, the method for determining the target dedicated computing chip combination for executing the task can be as follows, based on the idle state of each dedicated computing chip: First, identify all idle dedicated computing chips based on their idle state. Then, calculate the communication overhead between any two idle dedicated computing chips based on the complete topology information tree. Next, obtain the total communication overhead for each dedicated computing chip combination based on the communication overhead between any two idle dedicated computing chips; wherein all dedicated computing chips included in any dedicated computing chip combination are idle dedicated computing chips. Finally, determine the dedicated computing chip combination with the minimum total communication overhead as the target dedicated computing chip combination.
[0070] The complete topology information tree includes not only the communication overhead between idle dedicated computing chips, but also the overhead between active non-idle dedicated computing chips and other dedicated computing chips.
[0071] The specific methods for calculating the communication overhead between any two idle dedicated computing chips, and for obtaining the total communication overhead of each dedicated computing chip combination based on the communication overhead between any two idle dedicated computing chips, have been clearly described above and will not be repeated here for the sake of brevity.
[0072] Optionally, in this implementation, if the topology within the target electronic device changes, the pre-stored complete topology information tree within the target electronic device needs to be updated to ensure the accuracy of the complete topology information tree.
[0073] In the third implementation, the communication overhead between any two dedicated computing chips in the target electronic device is pre-stored in the target electronic device.
[0074] Accordingly, the specific method for determining the target dedicated computing chip combination for executing the task to be executed, based on the idle state of each dedicated computing chip, can be as follows: First, based on the idle state of each dedicated computing chip, identify all idle dedicated computing chips. Then, based on the pre-stored communication overhead between any two dedicated computing chips, determine the total communication overhead of each dedicated computing chip combination; wherein all dedicated computing chips included in any dedicated computing chip combination are idle dedicated computing chips. Finally, determine the dedicated computing chip combination with the minimum total communication overhead as the target dedicated computing chip combination.
[0075] The specific method for obtaining the total communication overhead of each dedicated computing chip combination based on the communication overhead between any two idle dedicated computing chips has been clearly described above, and will not be repeated here for the sake of brevity.
[0076] Optionally, the communication overhead between any two dedicated computing chips in the target electronic device can be stored in the form of a table or similar format.
[0077] In one implementation, before determining the target combination of dedicated computing chips for executing the task to be executed based on the idle state of each dedicated computing chip, it can also be determined that the number of dedicated computing chips required by the task to be executed is less than the number of idle dedicated computing chips in the target electronic device.
[0078] When the number of dedicated computing chips required by a task to be executed is greater than or equal to the number of idle dedicated computing chips in the target electronic device, it is usually necessary to allocate all dedicated computing chips to the task. In this case, only one combination of dedicated computing chips exists, and there is no need to determine communication overhead. Therefore, by determining that the number of dedicated computing chips required by the task to be executed is less than the number of idle dedicated computing chips in the target electronic device, unnecessary communication overhead determinations can be eliminated, reducing workload.
[0079] In one implementation, before determining the target dedicated computing chip combination for executing the task to be executed based on the idle state of each dedicated computing chip, it can also be determined that the task to be executed needs to be executed: determining the target dedicated computing chip combination for executing the task to be executed based on the idle state of each dedicated computing chip.
[0080] In practical applications, there may be allocation methods where the tasks to be executed do not require the dedicated computing chips specified in this solution. Therefore, before determining the target dedicated computing chip combination for executing the tasks, we first need to determine the tasks that need to be executed: based on the idle state of each dedicated computing chip, we determine the target dedicated computing chip combination for executing the tasks. This step is used to filter out tasks that do not need to be executed in this step.
[0081] Optionally, the task requirement information of the task to be executed may include a variable pre-configured to indicate whether the step of "determining the target combination of dedicated computing chips for executing the task based on the idle status of each dedicated computing chip" needs to be performed. Upon receiving the task to be executed and its task requirement information, the variable can be used to determine whether the step of "determining the target combination of dedicated computing chips for executing the task based on the idle status of each dedicated computing chip" needs to be performed. If not, dedicated computing chips are allocated according to existing technology. If so, step S110 is executed.
[0082] In one implementation, a component may be configured in the target electronic device to perform the above-described S110.
[0083] For example, S110 described above can be executed through the RayTAGS component. RayTAGS is an independently running system process that works in parallel with Raylet without affecting the original scheduling logic. RayTAGS can be integrated without modifying the Ray core logic, offering good portability and maintainability. Future expansion will also support more hardware topology information (such as heterogeneous computing devices, RDMA networks, etc.).
[0084] Optionally, RayTAGS can perceive the physical deployment information of GPUs on each node and the topological connections between them, and construct a GPU topology tree, so that GPU allocation no longer depends solely on the number of GPUs and basic attributes, but comprehensively considers the physical structure and overhead of the communication path.
[0085] S120: Assigns the target dedicated computing chip combination to the task to be executed.
[0086] Once the target dedicated computing chip is identified, it can be allocated to the task to be executed, so that the computing resources of the target dedicated computing chip can be utilized when the task is executed.
[0087] In one implementation, after allocating the target dedicated computing chip assembly to the task to be executed, the dedicated computing chips included in the target dedicated computing chip assembly can also be marked as non-idle dedicated computing chips.
[0088] After the target dedicated computing chip bundle is assigned to the task to be executed, all dedicated computing chips in the target dedicated computing chip bundle are no longer idle chips. Therefore, they need to be marked as non-idle dedicated computing chips to prevent them from being assigned repeatedly.
[0089] This solution can allocate tasks to dedicated computing chips (such as GPUs) with high communication efficiency and short physical distance, thereby improving task execution speed, reducing idle waiting time, and ultimately improving the utilization and throughput of dedicated computing chips in the entire cluster.
[0090] As existing models continue to grow in size, the demand for multi-GPU parallelism is increasing. This solution is suitable for communication-sensitive applications such as large-scale distributed training and real-time inference, and helps the Ray framework better support these emerging applications.
[0091] To facilitate understanding of the dedicated computing chip resource allocation method described above, the following will use... Figure 5 Let's take an example to illustrate. Figure 5 This is merely one implementation of the dedicated computing chip resource allocation method provided in this application; the implementation of the dedicated computing chip resource allocation method is not limited to this. Figure 5 As shown in the diagram.
[0092] like Figure 5 As shown, the Driver / Worker on the target electronic device first submits a task containing GPU resource requests to Raylet (a system process running on the target electronic device, responsible for task scheduling and resource allocation on that device) and creates a Task Spec (task requirement information for the task). Raylet then selects the most suitable scheduling node X (i.e., the task execution node in the Ray framework) to execute the task based on the global resource status.
[0093] If the selected node X is not the target electronic device, a failure message is returned, and node X will subsequently allocate GPU resources for the task to be executed.
[0094] If the selected node X is the target electronic device, then GPU resources are allocated on this node for the task to be executed.
[0095] When allocating resources for a task to be executed, first determine whether the task needs to consider GPU topology awareness (i.e., whether to use the method described in S110 for GPU resource allocation) based on the task's requirements. If not, allocate resources according to the existing GPU resource allocation method.
[0096] If necessary, the Ray TAGS component is invoked to allocate GPU resources for topology awareness. The Ray TAGS component is the one used to execute S110 described above.
[0097] The specific working logic of the Ray TAGS component is as follows: Ray TAGS requests a list of all available GPUs on the current node from Raylet. It also retrieves the task requirements for the task to be executed, including the number of GPUs required, GPU type (e.g., Tesla, RTX), and whether specific computing capabilities are supported.
[0098] Ray TAGS obtains the physical deployment information of GPUs on the current node and their topological connections (such as PCIe bus topology, NVLink connection topology, etc.) through system device management tools (such as lspci) or GPU management tools (e.g., nvidia-smi if the GPU is an Nvidia GPU). Based on this information, a topology tree of all available GPUs on the current node is constructed. The leaf nodes of the topology tree are individual GPUs, and the non-leaf nodes are the physical devices that GPU communication needs to pass through: for example, GPU communication under the same GPUSwitch needs to go through Switch communication, and GPU communication under different GPUSwitch needs to go through the CPU, or even through the PCIe bus. The meaning of the non-leaf node value in the diagram is the amount of overhead for GPU communication through this node (the overhead is calculated from various factors such as communication latency and bandwidth).
[0099] by Figure 4 The [CPU 1:50] tree node shown is used as an example: CPU 1 indicates that GPU communication needs to go through CPU 1, and 50 indicates that the communication overhead is 50 units. That is, each GPU that needs to communicate through CPU 1 needs to incur an additional 50 units of communication overhead when communicating through CPU 1.
[0100] RayTAGS makes topology-aware GPU allocation decisions based on the resource requirements of the task to be executed and factors such as the communication overhead between GPUs in the topology. The goal is to select an optimal set of GPUs to meet task requirements and maximize performance, that is, to minimize the communication overhead between GPUs. In other words, the selected GPU combination must be the one with the lowest total communication overhead between GPUs.
[0101] Total communication overhead between GPUs = Sum (communication overhead between any two GPUs). Example: The current node has GPUs 1-8, of which GPUs 3-7 are idle GPUs. Figure 4 The topology tree shown requires 3 GPUs for the task to be executed. Ray TAGS calculates the total cost of each combination using various methods: The total cost of GPUs 3, 4, and 5 is calculated as follows: GPU 3-4 cost + GPU 3-5 cost + GPU 4-5 cost = 10 + 220 + 220 = 450. The total cost of GPUs 3, 4, and 6 is calculated as follows: GPU 3, 4, and 6 cost = 10 + 220 + 220 = 450. The total cost of GPUs 3, 4, and 7 is calculated as follows: GPU 3, 4, and 7 cost = 10 + 220 + 220 = 450. The total cost of GPUs 4, 5, and 6 is calculated as follows: GPU 4, 5, and 7 cost = 220 + 220 + 70 = 510. The total cost of GPUs 5, 6, and 7 is calculated as follows: GPU 5 + 70 + 10 = 150. After comparison, the combination of G5, 6, and 7 with the minimum total communication is selected. Therefore, GPUs 5, 6, and 7 are determined as the target GPU combination.
[0102] Finally, the target GPU combination is returned to Raylet so that Raylet can assign the target GPU combination to the task to be executed.
[0103] After Raylet successfully allocates the target GPU combination, Raylet updates the Available GPU list of the current node (target electronic device), removes the allocated GPUs (GPUs within the target GPU combination), and ensures that subsequent task scheduling uses the latest resource status.
[0104] In cases where the most suitable node cannot be selected or GPU allocation on the current node fails, a failure message is returned.
[0105] Based on the same technical concept, this application also provides a dedicated computing chip resource allocation device, which is deployed in a target electronic device having multiple dedicated computing chips. Figure 6As shown, the dedicated computing chip resource allocation device 100 includes a determination module 110 and an allocation module 120.
[0106] The determining module 110 is configured to, in response to receiving a task to be executed and task requirement information of the task to be executed, determine a target combination of dedicated computing chips for executing the task to be executed based on the idle state of each dedicated computing chip; wherein, the target combination of dedicated computing chips is: a combination of dedicated computing chips that includes a number of dedicated computing chips that meets the number of dedicated computing chips required in the task requirement information and has the lowest communication overhead; and all dedicated computing chips in the target combination of dedicated computing chips are idle dedicated computing chips.
[0107] The allocation module 120 is used to allocate the target dedicated computing chip combination to the task to be executed.
[0108] The determining module 110 is specifically used to determine all idle dedicated computing chips based on the idle state of each dedicated computing chip; construct a dedicated computing chip topology information tree based on all the idle dedicated computing chips in the target electronic device; the dedicated computing chip topology information tree includes the communication overhead between any two idle dedicated computing chips; determine the overhead corresponding to each combination of dedicated computing chips based on the dedicated computing chip topology information tree; wherein, the number of dedicated computing chips included in the dedicated computing chip combination is determined according to the task requirement information of the task to be executed; and determine the dedicated computing chip combination with the lowest overhead as the target dedicated computing chip combination.
[0109] The determination module 110 is specifically used to obtain the attribute information of each of the idle dedicated computing chips, the attribute information including the topology information of the interconnection between the idle dedicated computing chips and other idle dedicated computing chips; and to construct the dedicated computing chip topology information tree based on the attribute information of each of the idle dedicated computing chips.
[0110] The dedicated computing chip resource allocation device 100 further includes a processing module, which is used to mark the dedicated computing chips included in the target dedicated computing chip combination as non-idle dedicated computing chips after allocating the target dedicated computing chip combination to the task to be executed.
[0111] Before determining the target combination of dedicated computing chips for executing the task to be executed based on the idle state of each of the dedicated computing chips, the processing module is further configured to determine that the number of dedicated computing chips required by the task to be executed is less than the number of idle dedicated computing chips in the target electronic device.
[0112] Before determining the target combination of dedicated computing chips for executing the task to be executed based on the idle state of each of the dedicated computing chips, the processing module is further configured to determine that the task to be executed needs to be executed: determining the target combination of dedicated computing chips for executing the task to be executed based on the idle state of each of the dedicated computing chips.
[0113] The target electronic device pre-stores a complete topology information tree, which includes the communication overhead between any two dedicated computing chips in the target electronic device. The determining module 110 is specifically used to determine all idle dedicated computing chips based on their idle states; calculate the communication overhead between any two idle dedicated computing chips based on the complete topology information tree; obtain the total communication overhead for each dedicated computing chip combination based on the communication overhead between any two idle dedicated computing chips; wherein all dedicated computing chips included in any dedicated computing chip combination are idle dedicated computing chips; and determine the dedicated computing chip combination with the minimum total communication overhead as the target dedicated computing chip combination.
[0114] The target electronic device pre-stores the communication overhead between any two dedicated computing chips in the target electronic device; the determining module 110 is specifically used to determine all idle dedicated computing chips based on the idle state of each dedicated computing chip; to determine the total communication overhead of each dedicated computing chip combination based on the pre-stored communication overhead between any two dedicated computing chips; wherein, all dedicated computing chips included in any dedicated computing chip combination are idle dedicated computing chips; and to determine the dedicated computing chip combination with the minimum total communication overhead as the target dedicated computing chip combination.
[0115] The dedicated computing chip resource allocation device 100 provided in this application embodiment has the same implementation principle and technical effect as the aforementioned dedicated computing chip resource allocation method embodiment. For the sake of brevity, any parts not mentioned in the device embodiment can be referred to the corresponding content in the aforementioned dedicated computing chip resource allocation method embodiment.
[0116] Based on the same technical concept, this application also provides a method for allocating dedicated computing chip resources for any task node in the Ray framework. The Ray framework includes multiple task execution nodes, with a designated task node being the one initiating the task to be executed within the Ray framework. Different task nodes communicate and connect with each other. The following will combine... Figure 7 The steps involved are explained.
[0117] S210: Obtain the task to be executed and the task requirements information of the task to be executed.
[0118] The task to be executed and its task requirements are obtained from the Driver or Worker within the specified task node. That is, when user code calls a remote function, the Driver or Worker will initiate the task to be executed and submit it to the local Raylet, thereby obtaining the task to be executed and its task requirements.
[0119] S220: Select the target task node from all task nodes to execute the task to be executed.
[0120] The method for selecting the target task node from all task nodes to execute the task has been clearly described above, and will not be repeated here for the sake of brevity.
[0121] Optionally, the target task node can be the specified task node that initiated the task to be executed, or it can be another task node in the Ray framework.
[0122] S230: Send the task to be executed and the task requirement information of the task to be executed to the target task node, so that the target task node can use the aforementioned dedicated computing chip resource allocation method applied to the target electronic device.
[0123] The aforementioned target electronic device is the target task node. The specific implementation of the dedicated computing chip resource allocation method applied to the target electronic device can be found in the preceding text and will not be described in detail here.
[0124] The method of sending the task to be executed and its task requirements to the target task node has been clearly described above, and will not be repeated here for the sake of brevity.
[0125] Based on the same technical concept, this application also provides a Ray framework. The Ray framework includes multiple task nodes, which communicate and connect with each other.
[0126] In the Ray framework, the task node that initiates the task to be executed is the designated task node.
[0127] A designated task node is used to obtain the task to be executed and its task requirements information; from the plurality of task nodes, a target task node is selected to execute the task to be executed; the task to be executed and its task requirements information are sent to the target task node; wherein, the designated task node is the task node in the Ray framework that initiates the task to be executed.
[0128] A target task node, in response to receiving a task to be executed and its task requirement information, determines a target combination of dedicated computing chips for executing the task, based on the idle status of each dedicated computing chip; wherein, the target combination of dedicated computing chips is: a combination of dedicated computing chips whose number of dedicated computing chips meets the number of dedicated computing chips required in the task requirement information, and whose communication overhead is minimized; all dedicated computing chips in the target combination of dedicated computing chips are idle dedicated computing chips; and the target combination of dedicated computing chips is allocated to the task to be executed.
[0129] The specific working principles of the designated task node and the target task node have been clearly described above, and will not be repeated here for the sake of brevity.
[0130] The Ray framework includes task nodes that can be electronic devices with data processing capabilities, such as computers and servers.
[0131] Optionally, each node in the Ray framework includes a component for executing the aforementioned method S100 for allocating dedicated computing chip resources for a target electronic device. After determining the target dedicated computing chip combination through this component, the node allocates the target dedicated computing chip combination to the task to be executed. For easier understanding, please refer to [link to relevant documentation]. Figure 8 .
[0132] For example, S110 described above can be executed through the RayTAGS component. The specific implementation of the RayTAGS component has been clearly described above and will not be repeated here for the sake of brevity.
[0133] Please see Figure 9 This is an electronic device 200 provided in an embodiment of this application. The electronic device 200 includes: a processor 210, a memory 220, and at least two dedicated computing chips 230.
[0134] The memory 220, processor 210, and dedicated computing chip 230 are electrically connected directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines. The memory 220 is used to store computer programs, such as those containing... Figure 6The software functional module shown is the dedicated computing chip resource allocation device 100. The dedicated computing chip resource allocation device 100 includes at least one software functional module that can be stored in the memory 220 in the form of software or firmware or embedded in the operating system (OS) of the electronic device 200. The processor 210 is used to execute executable modules stored in the memory 220, such as the software functional module or computer program included in the dedicated computing chip resource allocation device 100. At this time, the processor 210, in response to receiving a task to be executed and task requirement information of the task to be executed, determines a target dedicated computing chip combination for executing the task to be executed based on the idle state of each dedicated computing chip; wherein the target dedicated computing chip combination is: a dedicated computing chip combination whose number of dedicated computing chips meets the number of dedicated computing chips required in the task requirement information, and whose communication overhead is minimal; all dedicated computing chips in the target dedicated computing chip combination are idle dedicated computing chips; and the target dedicated computing chip combination is allocated to the task to be executed.
[0135] The memory 220 can be, but is not limited to, RAM (Random Access Memory), ROM (Read Only Memory), PROM (Programmable Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electric Erasable Programmable Read-Only Memory), etc.
[0136] Processor 210 may be an integrated circuit chip with signal processing capabilities. The aforementioned processor can be a general-purpose processor, including a CPU, NP (Network Processor), etc.; it can also be a DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor, or processor 210 can be any conventional processor.
[0137] Specialized computing chips may include GPUs, NPUs, AI computing chips, etc.
[0138] Among them, the aforementioned electronic devices 200 include, but are not limited to, personal computers, servers, etc.
[0139] This application also provides a computer-readable storage medium (hereinafter referred to as the storage medium) storing a computer program. When the computer program is run by a computer, such as the electronic device 200 described above, it executes the dedicated computing chip resource allocation method described above. The computer-readable storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory, a random access memory, a magnetic disk, or an optical disk.
[0140] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A method for allocating resources for a dedicated computing chip, characterized in that, The method, applied to a target electronic device having multiple dedicated computing chips, includes: In response to receiving a task to be executed and its task requirement information, a target combination of dedicated computing chips for executing the task is determined based on the idle status of each dedicated computing chip. The target combination of dedicated computing chips is defined as the combination whose number of dedicated computing chips meets the requirement in the task requirement information and has the lowest communication overhead. All dedicated computing chips in the target combination are idle dedicated computing chips. The target dedicated computing chip assembly is assigned to the task to be executed.
2. The method according to claim 1, characterized in that, Based on the idle state of each of the dedicated computing chips, a target combination of dedicated computing chips for executing the task to be executed is determined, including: Based on the idle state of each dedicated computing chip, all idle dedicated computing chips are identified; Based on all the idle dedicated computing chips in the target electronic device, a dedicated computing chip topology information tree is constructed; the dedicated computing chip topology information tree includes the communication overhead between any two idle dedicated computing chips; Based on the dedicated computing chip topology information tree, the overhead corresponding to each dedicated computing chip combination is determined; wherein, the number of dedicated computing chips included in the dedicated computing chip combination is determined according to the task requirement information of the task to be executed; The dedicated computing chip combination with the lowest overhead is determined as the target dedicated computing chip combination.
3. The method according to claim 2, characterized in that, Based on all idle dedicated computing chips in the target electronic device, a dedicated computing chip topology information tree is constructed, including: Obtain attribute information for each of the idle dedicated computing chips, the attribute information including topology information of the interconnection between the idle dedicated computing chips and other idle dedicated computing chips; Based on the attribute information of each of the idle dedicated computing chips, a topology information tree of the dedicated computing chips is constructed.
4. The method according to claim 1, characterized in that, After allocating the target dedicated computing chip assembly to the task to be executed, the method further includes: The dedicated computing chips included in the target dedicated computing chip assembly are marked as non-idle dedicated computing chips.
5. The method according to claim 1, characterized in that, Before determining the target combination of dedicated computing chips for executing the task to be executed based on the idle state of each of the dedicated computing chips, the method further includes: The number of dedicated computing chips required for the task to be executed is determined to be less than the number of idle dedicated computing chips in the target electronic device.
6. The method according to any one of claims 1-5, characterized in that, Before determining the target combination of dedicated computing chips for executing the task to be executed based on the idle state of each of the dedicated computing chips, the method further includes: Determine the task to be executed: Based on the idle state of each dedicated computing chip, determine the target dedicated computing chip combination for executing the task to be executed.
7. The method according to claim 1, characterized in that, The target electronic device has a complete topology information tree pre-stored inside it, and the complete topology information tree includes the communication overhead between any two dedicated computing chips in the target electronic device. Based on the idle state of each of the dedicated computing chips, a target combination of dedicated computing chips for executing the task to be executed is determined, including: Based on the idle state of each dedicated computing chip, all idle dedicated computing chips are identified; Based on the complete topology information tree, calculate the communication overhead between any two idle dedicated computing chips; Based on the communication overhead between any two idle dedicated computing chips, the total communication overhead of each dedicated computing chip combination is obtained; wherein, all dedicated computing chips included in any dedicated computing chip combination are idle dedicated computing chips; The dedicated computing chip combination with the minimum total communication overhead is identified as the target dedicated computing chip combination.
8. The method according to claim 1, characterized in that, The target electronic device pre-stores the communication overhead between any two dedicated computing chips in the target electronic device; Based on the idle state of each of the dedicated computing chips, a target combination of dedicated computing chips for executing the task to be executed is determined, including: Based on the idle state of each dedicated computing chip, all idle dedicated computing chips are identified; Based on the pre-stored communication overhead between any two dedicated computing chips, the total communication overhead of each dedicated computing chip combination is determined; wherein, all dedicated computing chips included in any dedicated computing chip combination are idle dedicated computing chips; The dedicated computing chip combination with the minimum total communication overhead is identified as the target dedicated computing chip combination.
9. A dedicated computing chip resource allocation device, characterized in that, Deployed in a target electronic device having multiple dedicated computing chips, the device includes: A determining module is configured to, in response to receiving a task to be executed and task requirement information of the task to be executed, determine a target combination of dedicated computing chips for executing the task to be executed based on the idle state of each dedicated computing chip; wherein, the target combination of dedicated computing chips is: a combination of dedicated computing chips that includes the number of dedicated computing chips required in the task requirement information and has the lowest communication overhead; and all dedicated computing chips in the target combination of dedicated computing chips are idle dedicated computing chips; An allocation module is used to allocate the target dedicated computing chip combination to the task to be executed.
10. A method for allocating resources for a dedicated computing chip, characterized in that, A designated task node is applied to the Ray framework, which also includes at least one other task node. The designated task node is the task node in the Ray framework that initiates the task to be executed, and different task nodes communicate and connect with each other. The method includes: Obtain the tasks to be executed and their task requirements; From all the task nodes, select the target task node for executing the task to be executed; The task to be executed and its task requirement information are sent to the target task node so that the target task node executes the method described in any one of claims 1-8.
11. A Ray framework, characterized in that, include: Multiple task nodes, with communication and connections between different task nodes; Specify a task node to obtain the task to be executed and its task requirements; From the plurality of task nodes, a target task node is selected for executing the task to be executed; the task to be executed and its task requirement information are sent to the target task node; wherein, the designated task node is the task node in the Ray framework that initiates the task to be executed; The target task node is configured to, in response to receiving a task to be executed and its task requirement information, determine a target dedicated computing chip combination for executing the task to be executed based on the idle status of each dedicated computing chip; wherein, the target dedicated computing chip combination is: a combination of dedicated computing chips that includes the number of dedicated computing chips required in the task requirement information and has the lowest communication overhead; all dedicated computing chips in the target dedicated computing chip combination are idle dedicated computing chips; and the target dedicated computing chip combination is allocated to the task to be executed.
12. An electronic device, characterized in that, include: The system includes a memory, a processor, and at least two dedicated computing chips, wherein the memory and the processor are connected, and the processor is communicatively connected to each of the dedicated computing chips. The memory is used to store programs; The processor is configured to invoke a program stored in the memory to execute the method as described in any one of claims 1-8.