Chip verification method, system and device and readable storage medium

Abstract

The invention discloses a chip verification method, system and device and a readable storage medium. The method comprises the following steps: filling excitation from an interface of a to-be-verified module, and carrying out first-batch regression test on the to-be-verified module; acquiring coverage rate data of the to-be-verified module in the regression test, wherein the coverage rate data comprises a code coverage rate and / or a function coverage rate; packaging a functional region corresponding to a part which does not accord with a preset condition in the coverage rate data into an independent logic block, and establishing a breakpoint excitation input interface for the logic block; and taking the logic block as a new to-be-verified module, inputting excitation from the breakpoint excitation inlet, and performing a new batch of regression test. Compared with the prior art, the method effectively solves the problem that a traditional method cannot deeply cover internal complex logic, and ensures that key functions, boundary conditions and abnormal states of a high-complexity area can be directly and efficiently excited and verified.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuit verification, and particularly relates to a chip verification method, system, device and readable storage medium. BACKGROUND

[0002] Chip verification is a core link in the semiconductor industry, and its importance increases exponentially with the complexity of chips. Modern chip design contains hundreds of millions or even tens of billions of transistors, and the amount of hardware description language code is huge.

[0003] In addition to the increasing complexity of chips, the failure cost of chips is also extremely high. The cost of tape-out of advanced process nodes is extremely high. One failed tape-out means huge financial loss and time delay. In the field of infrastructure, chip failure even binds the life and property safety of people. Therefore, strict requirements should be put forward for chip verification.

[0004] In the field of integrated circuit verification, the coverage-driven verification method has become an industry standard process. The existing technology generally uses regression testing based on random excitation combined with static coverage rate as the basis for judging the completeness of verification. This scheme cannot effectively complete full coverage of complex logic code and functions. In the process of supplementary testing, traditional random excitation has blindness, which leads to a large number of repeated excitations covering the same logic path, and cannot effectively touch the boundary conditions such as exception handling. In the current chip verification, which is becoming more and more strict and pursuing efficiency, it is difficult to meet the needs of enterprises.

[0005] Therefore, in view of the above technical problems, it is necessary to provide a chip verification method, system, device and readable storage medium.

[0006] The information disclosed in this BACKGROUND section is only intended to increase an understanding of the general context in which the present application can be practiced. It is not admitted that the information disclosed in this BACKGROUND section constitutes prior art to the present application. SUMMARY

[0007] The purpose of the present application is to provide a chip verification method, system, device and readable storage medium, which can effectively complete full coverage of complex logic code and functions, thereby improving the quality of chip verification.

[0008] In order to achieve the above-mentioned purpose, the technical scheme provided by an embodiment of the present application is as follows:

[0009] In a first aspect, the present application provides a chip verification method, which comprises:

[0010] Filling excitation from the interface of the module to be verified, and performing first batch regression testing on the module to be verified;

[0011] acquire coverage data of the to-be-verified module in the regression test, the coverage data including code coverage and / or function coverage;

[0012] encapsulate a function area corresponding to a part of the coverage data not meeting a preset condition as an independent logic block, and build a breakpoint excitation input interface for the logic block;

[0013] take the logic block as a new to-be-verified module, input excitation from the breakpoint excitation input interface, and perform a new batch of regression tests.

[0014] In one or more embodiments of the present application, the method further comprises:

[0015] construct a granularity tree with code nodes and / or function points as leaf nodes and levels and function types of the to-be-verified module as intermediate nodes;

[0016] based on the importance degree, assign a weight value to each child node in the granularity tree, and the sum of weight values of child nodes belonging to the same parent node is the weight value of the parent node;

[0017] acquire coverage data of the to-be-verified module in the regression test, and based on weighted average aggregation, calculate the coverage of each parent node and root node layer by layer.

[0018] In one or more embodiments of the present application, the method further comprises:

[0019] based on the weight of a node in the granularity tree and the coverage value of the node, calculate a risk index of the corresponding node;

[0020] if the risk index of the node is greater than or equal to a preset threshold value, send an alarm signal, encapsulate the corresponding function area corresponding to the node into an independent logic block, and perform a new batch of regression tests.

[0021] In one or more embodiments of the present application, the method further comprises:

[0022] when the object of the current regression test is the re-encapsulated independent logic block, calculate the coverage of each code node and / or function point and the change rate of the coverage of the corresponding code node and / or function point in the adjacent last batch of regression tests;

[0023] if the change rate is greater than or equal to a preset first threshold value, increase the amount of regression tests and update the coverage values of each node in the granularity tree based on the test results.

[0024] In one or more embodiments of the present application, acquiring the coverage data of the to-be-verified module in the regression test comprises:

[0025] configuring a type of coverage expected to be acquired;

[0026] In the regression test, record the code nodes and / or function points executed in the module to be verified;

[0027] Based on the number of code nodes and / or function points executed in the regression test, calculate the code coverage and / or function coverage required to be acquired.

[0028] In one or more embodiments of the present application, the method further comprises:

[0029] Removing unreachable or constrained excluded code nodes and / or function points;

[0030] Collecting coverage information of each preset code node and / or function point in the regression test, and labeling the coverage information based on the object of the regression test.

[0031] In one or more embodiments of the present application, the iteration termination condition comprises:

[0032] The number of batches of training reaches a preset second threshold; or

[0033] The code coverage and / or function coverage reaches a preset third threshold.

[0034] In a second aspect, the present application provides a chip verification system, comprising:

[0035] A test module for filling in stimuli from the interface of a module to be verified to perform the first batch of regression test on the module to be verified;

[0036] An acquisition module for acquiring coverage data of the module to be verified in the regression test, the coverage data comprising code coverage and / or function coverage;

[0037] A packaging module for packaging a function area corresponding to a part of the coverage data not meeting a preset condition as an independent logic block, and building a breakpoint stimulus input interface for the logic block;

[0038] An iteration module for taking the logic block as a new module to be verified, inputting stimuli from the breakpoint stimulus input interface, and performing a new batch of regression test.

[0039] In a third aspect, the present application provides a computer device, comprising a memory and a processor, which are communicatively connected with each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the chip verification method.

[0040] In a fourth aspect, the present application provides a computer readable storage medium storing computer instructions for causing a computer to execute the chip verification method.

[0041] Compared with the prior art, the chip verification method provided by the present application introduces a granularity tree model, completely eliminates the coverage distortion problem, effectively solves the problem that the traditional method cannot deeply cover the internal complex logic, and ensures that the key functions, boundary conditions and abnormal states of the high complexity region can be directly and efficiently triggered and verified. For the region with high logic complexity, the breakpoint is opened and the excitation is poured in, which avoids the situation that the excitation cannot effectively cover the internal complex logic when the excitation is sent from the chip entrance, avoids the invalid excitation propagation path and the internal scene difficult to trigger by repeated debugging, greatly reduces the time required for debugging and reproducing specific problems, accelerates the verification convergence process, and shortens the verification period. The closed-loop verification process of "test-analysis-optimization" significantly improves the coverage collection efficiency of complex logic and improves the completeness of the chip verification system. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments described in the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0043] Figure 1 is a schematic diagram of the implementation scene of the chip verification method in an embodiment of the present application;

[0044] Figure 2 is a flowchart of the chip verification method in an embodiment of the present application;

[0045] Figure 3 is a structural block diagram of the chip verification system in another embodiment of the present application;

[0046] Figure 4 is a structural block diagram of the electronic device in an embodiment of the present application;

[0047] Figure 5 is a schematic diagram of the granularity tree in a specific embodiment of the present application. DETAILED DESCRIPTION

[0048] In order for those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the scope of protection of the present application.

[0049] Unless otherwise clearly indicated, in the entire specification and claims, the term "comprise" or its variants such as "comprises" or "comprising" shall be understood to include the stated elements or components, but not to exclude other elements or components.

[0050] In one technical solution, the method for chip or integrated circuit verification adopts a random stimulus generation strategy such as the rand variable randomization of UVM. Large-scale regression testing is performed through random stimulus, expecting full coverage of the code logic. However, due to the lack of correlation between existing coverage quantization indicators, it is difficult to effectively identify the coverage black hole area according to the coverage data stored in isolation. With the increasing complexity of chips, the blindness of traditional random stimulus in testing often leads to a large number of repeated coverage of the same logic path, and cannot effectively touch the boundary conditions such as exception handling, nor can it perform limited disposal on the high-priority area in the complex chip.

[0051] The present inventors found the main shortcomings of the prior art, and based on the shortcomings of the prior art, proposed a new technical implementation idea: optimizing the original repeated direct stimulus pouring method from the module interface, first storing the corresponding coverage information through a limited number of tests, then generating a coverage granularity table of the module based on the sample comprehensive analysis, creating a breakpoint interface for the part with low coverage collection granularity, and constructing a constrained stimulus to meet the logic that needs to be covered, and finally pouring the stimulus from the breakpoint for coverage collection, thereby improving the coverage collection efficiency of the area with high logic complexity, and further improving the verification quality.

[0052] Please refer to Figure 1 , which shows an application scenario schematic diagram of the chip verification method provided by the present application in an embodiment, and the scenario specifically includes a test unit 101, a collection unit 102, and a recombination unit 103.

[0053] It should be noted that the test unit 101, the collection unit 102, and the recombination unit 103 are all provided with communication connections. The communication network extended by the above communication connections can include various connection types, including but not limited to wired connection, wireless connection, or optical fiber cable connection, etc. At the same time, the communication network can be a local area network, a metropolitan area network, a wide area network, or any combination of the three.

[0054] It should be noted that the test unit 101 is configured to generate excitation and inject the excitation into the to-be-verified module based on a preset excitation input port to perform regression testing.

[0055] The collection unit 102 is configured to collect and calculate the coverage data in the regression testing process to obtain the code coverage and function coverage of each code node and preset function point.

[0056] The recombination unit 103 is configured to recombine a function area in the to-be-verified module, in which the coverage rate does not meet a preset condition, into a new logic block based on the code coverage and / or function coverage calculated by the aforementioned collection unit 102, and set an independent breakpoint excitation input interface for the logic block. Based on the breakpoint excitation input interface, regression testing is performed on the logic block to make up for the problem of insufficient test coverage in the specific area.

[0057] It should be noted that the chip verification method of the embodiment of the present application can be applied to the chip verification system of the embodiment of the present application. The chip verification system can be configured in a terminal. The terminal can include, but is not limited to, a PC (Personal Computer), a PDA (tablet computer), a smart phone, a smart wearable device, and the like.

[0058] It should be noted that the chip verification method of the embodiment of the present application can be applied to the chip verification system of the embodiment of the present application. The chip verification system can be configured in a terminal. The terminal can include, but is not limited to, a PC (Personal Computer), a PDA (tablet computer), a smart phone, a smart wearable device, and the like.

[0059] Please refer to FIG. 1, Figure 2 The chip verification method specifically includes the following steps:

[0060] S201: Inject excitation from the interface of the to-be-verified module to perform the first batch of regression testing on the to-be-verified module;

[0061] It should be noted that the to-be-verified module in the present application generally refers to an integrated circuit design unit that needs to be functionally tested and verified based on the chip verification method of the present application, which can include but is not limited to a data processing unit, a control logic unit, an interface protocol unit, a storage management unit, etc. Since the first batch of regression tests are generally directed to the integrated circuit design unit as a whole; at this time, when the to-be-verified module is stimulated and filled, the interface of the to-be-verified module is generally the external port of the to-be-verified module. In contrast, as described in the embodiments below, in subsequent batches of regression tests, the object is generally the functional unit whose coverage is lower than the user's demand in the adjacent previous batch of regression tests, and the interface for stimulation and filling is a dynamic breakpoint interface that can be directly inserted into the internal critical path of the module.

[0062] Further, in the present application, the stimulus is a combination of signals input to the to-be-verified module for activating specific functional logic. The stimulus is one of the important components of a test case, and each test case corresponds to a set of random stimuli for activating different logic paths in the design. The test case also includes expected output, environment configuration, etc., and is the smallest execution unit of the verification process.

[0063] S202: Obtain coverage data of the to-be-verified module in the regression test, the coverage data including code coverage and / or functional coverage;

[0064] It should be noted that the coverage data in the present application is a core indicator of the chip verification closed loop, and can include code coverage, functional coverage, etc. Specifically, the code coverage is used to objectively measure the proportion of the executed part of the code, and to verify whether all executable logic is activated. The code coverage can be further divided into line coverage, score coverage, condition coverage, state machine coverage, and flip-flop coverage; the functional coverage is mainly used to verify whether the actual specification is implemented, and is used to measure the coverage degree of the expected function of the design. The functional coverage can also be further divided into function point coverage, data value coverage, timing coverage, and cross coverage.

[0065] Since the types of coverage tend to be diversified, the type of coverage to be collected should be determined when building the experimental scene. The type of coverage to be collected can dynamically change depending on the specific experimental scene, and can be a combination of one or more of the above-mentioned coverage types, and the present application does not limit the specific selection of coverage.

[0066] Furthermore, in an exemplary embodiment, obtaining coverage typically includes: generating markers for code execution, i.e., code nodes and / or function points; inputting test cases, and in regression testing, recording the code nodes and / or function points executed in the module to be verified; and calculating the required code coverage and / or function coverage based on the number of code nodes and / or function points executed in the regression test.

[0067] Taking condition coverage in code coverage as an example, the condition items in the code should be marked as code nodes, and the number of condition combinations covered during regression testing should be recorded. Based on the total number of condition combinations in the code, the condition coverage rate is calculated as follows:

[0068]

[0069] In one specific embodiment, test cases can be executed via simulation, and the VSC tool can be used to record code execution and generate corresponding code coverage data. The command-line options for the VSC tool are shown in the following example:

[0070]

[0071] In the command Used to instruct the design code to be compiled into a simulable format; Used to specify compilation Code; Used to specify the coverage type Indicates line coverage (whether each line of code is executed). Indicates condition coverage. This represents the coverage of the finite state machine. Indicates branch coverage; Used to specify the data storage path for coverage data.

[0072] The overall process implemented based on the above commands is as follows: Based on preset compilation design rules and the test platform, simulation test cases are run, and in the corresponding... , During test case execution, the VCS tool will sample and generate coverage data according to the test cases. Data from different test cases can be merged. During coverage collection, the VCS tool will summarize the data according to the design files, that is, it will collect coverage information for the current design files and then summarize the data. The coverage information is specified, and the coverage data is stored in a predefined database. For further analysis.

[0073] Different from code nodes, the function points need to be manually defined. By disassembling the function points of the module to be verified, the function points are taken as the definition basis of the function coverage, and the coverage model is formulated according to the function points sorted above. Specifically, whether a specific function is executed (such as "register configuration"); whether the range of data values is covered (such as "input data 0~1023"); whether a specific timing relationship is verified (such as "after signal A is set, signal B must respond within 5 cycles"); whether the combination of multiple conditions is covered (such as "when MODE=1, all instructions need to be executed"). By defining the coverage points by statements, the judgment of the coverage degree of the design expected function points is implemented. In the simulation environment, the design file needs to be bound to the design file, and if the corresponding function points are covered in the running test case, the sampling will be triggered, and the coverage rate data is generated according to the test case. The data of different cases can be merged.

[0074] It should be noted that in integrated circuit design, there are inevitably coverage points that can never be activated due to design logic contradictions or physical limitations. Therefore, in an embodiment, after each batch of regression testing is completed, the code nodes or function points with low coverage rates can be investigated, and unreachable or constrained excluded code nodes and / or function points can be removed through formal verification, logic cone analysis, etc. to improve the efficiency of subsequent chip verification. Alternatively, depending on the number of nodes to be investigated and the difficulty, the areas with low coverage rates for consecutive multiple times can also be screened for unreachable or constrained exclusion after multiple batches of regression testing; at the same time, the total number of screenings and the range of each screening can also be limited, and the present embodiment does not limit this.

[0075] In addition, in an embodiment, since the regression testing is divided into multiple batches for experiments, after collecting the coverage rate information of each preset code node and / or function point in the regression testing, the coverage rate information should be labeled based on the object of the regression testing.

[0076] S203: encapsulating the function area corresponding to the part not meeting the preset condition in the coverage rate data as an independent logic block, and building a breakpoint excitation input interface for the logic block;

[0077] It can be understood that the coverage rate is an important indicator for measuring whether the chip code or the function point corresponding area is sufficiently tested and verified. Therefore, if the coverage rate of a certain function area is less than a preset threshold, it means that the area needs to be supplemented.

[0078] Since the incentive infusion has blindness, it is difficult to reach the area with low coverage rate. Therefore, the application encapsulates the functional area corresponding to the code node with a coverage value less than a preset first threshold into an independent logic block, and builds a breakpoint incentive input interface for the logic block. At this time, the logic block encapsulated forms a to-be-verified module for the next round of testing.

[0079] It should be noted that with the complication and diversification of modules in the chip, there is a natural priority in application or verification level between different modules. Meanwhile, the chip to be verified can be further divided into multiple vertical or overlapping levels. In order to maintain high efficiency and good order in the chip verification process, and to scientifically implement the priority verification strategy, the application also provides the following embodiments:

[0080] In an exemplary embodiment, the chip verification method provided by the application further comprises: taking the code node and / or function point as a leaf node, taking the level and function type of the to-be-verified module as an intermediate node, and constructing a granularity tree; based on the importance degree, assigning a weight value to each child node in the granularity tree, and the sum of the weight values of the child nodes belonging to the same parent node is the weight value of the parent node; obtaining the coverage rate data of the to-be-verified module in the regression test, and based on weighted average aggregation, calculating the coverage rate of each parent node and root node layer by layer.

[0081] As Figure 5 As shown in an exemplary embodiment of the application, a schematic diagram of a granularity tree, each code node / function point is taken as a coverage point with the finest granularity, and the chip to be verified is constructed step by step upwards. By configuring a priority weight for each leaf node, the weight of the parent node to which the other leaf node belongs can be derived from bottom to top. After a batch of regression tests, the risk index of the corresponding node can be calculated based on the weight value corresponding to each node and the coverage rate value of the node. Preferably, the product of the weight value and the coverage rate can be taken as the risk index of the corresponding node. The risk index can intuitively reflect the urgency of supplementing the regression test for the current node to improve the corresponding coverage rate.

[0082] Further, the user can set a threshold value, if the risk index of the node is greater than or equal to the preset threshold value, an alarm signal is sent, and the corresponding functional area corresponding to the node is encapsulated into an independent logic block for a new batch of regression tests. If the risk index of the node is less than the preset threshold value, it is considered that the node has been tested enough and meets the required coverage rate.

[0083] S204: inputting incentives from the breakpoint incentive entry for the new to-be-verified module, and performing a new batch of regression tests.

[0084] It should be noted that in the embodiments of the present application, in order to ensure that each batch of regression experiments can hit the to-be-verified module in the current test as much as possible, each batch should ensure a certain number of regression tests, but the number of regression experiments for a specific batch should be determined by the specific implementation environment. The embodiments of the present application do not limit this.

[0085] It should also be noted that in an exemplary embodiment, in order to further improve the efficiency of chip verification, the amount of effective coverage rate brought by unit simulation resources can be used as an index to quantify the efficiency of chip verification in the regression test of the present application. When the object of the current regression test is a re-packaged independent logic block, that is, in the process of non-first batch regression test, the change rate of the coverage rate of each code node and / or function point and the corresponding code node and / or function point coverage rate in the adjacent last batch regression test can be calculated; if the change rate is greater than or equal to a preset first threshold, the regression test amount is increased and the coverage rate value of each node in the granularity tree is updated based on the test result; on the contrary, if the coverage rate improvement stagnates or major changes are added, the engineer should be prompted to intervene in analysis or adjust the verification plan. In this way, the final coverage rate collection data can reach 100% after excluding redundant logic.

[0086] In addition, the experiment termination condition can be that the number of batches of training reaches a preset second threshold; or the code coverage rate and / or the function coverage rate reaches a preset third threshold. The setting of each threshold of the present application needs to be combined with the actual experimental scene and customized by the user. The specific numerical value is not limited.

[0087] Please refer to Figure 3 Based on the same inventive concept as the foregoing chip verification method, an embodiment of the present application provides a chip verification system 300, which includes a test module 301, an acquisition module 302, a packaging module 303, and an iteration module 304.

[0088] Specifically, the test module 301 is configured to input stimuli from the interface of the to-be-verified module and perform multiple regression tests on the to-be-verified module; the acquisition module 302 is configured to acquire coverage rate data of the to-be-verified module in the regression test, the coverage rate data including code coverage rate and / or function coverage rate; the packaging module 303 is configured to package a function region whose coverage rate value is less than a preset threshold, or a function region corresponding to a code node whose coverage rate value is less than a preset first threshold, into an independent logic block, and build a breakpoint stimulus input interface for the logic block; and the iteration module 304 is configured to use the logic block as a new to-be-verified module, input stimuli from the breakpoint stimulus input interface, and perform a new batch of regression tests until a preset condition is reached.

[0089] Please refer to Figure 4As shown, the embodiment of the present application further provides an electronic device 400, which comprises at least one processor 401, a memory 402 (for example, a non-volatile memory), a memory 403 and a communication interface 404, and the at least one processor 401, the memory 402, the memory 403 and the communication interface 404 are connected together via an internal bus 405. The at least one processor 401 is configured to invoke at least one program instruction stored or encoded in the memory 402, so as to enable the at least one processor 401 to perform various operations and functions of the chip verification method described in various embodiments of the present application.

[0090] In the embodiments of the present application, the electronic device 400 can include, but is not limited to, a personal computer, a server computer, a workstation, a desktop computer, a laptop computer, a notebook computer, a mobile electronic device, a smart phone, a tablet computer, a cellular phone, a personal digital assistant (PDA), a handheld device, a messaging device, a wearable electronic device, a consumer electronic device, and the like.

[0091] The embodiment of the present application further provides a computer readable medium, which carries computer execution instructions, and the computer execution instructions, when executed by a processor, can be used to implement various operations and functions of the chip verification method described in various embodiments of the present application.

[0092] The computer readable medium in the present application can be a computer readable signal medium or a computer readable storage medium or any combination of the two. The computer readable storage medium may, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination of the above. More specific examples of the computer readable storage medium can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, the computer readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device or apparatus.

[0093] In this case, the computer readable program code can be implemented in a high level processor or object oriented programming language to communicate with a computer system. However, the computer readable program code can be implemented in assembly or machine language, if desired. The computer readable program code can be stored in any appropriate computer readable storage medium including, but not limited to, semiconductor memory, optical or magnetic disk, or the like. The computer readable program code can be downloaded from an external source via a computer readable signal. A computer readable signal includes, but is not limited to, data signals, carrier waves, and the like. The computer readable signal can be transmitted via a communication media, such as a metal wire, twisted pair, coaxial cable, optical fiber, or the like.

[0094] Those skilled in the art will appreciate that embodiments of the present application can be devised for a variety of computer readable media that can store computer readable program code. The computer readable program code can also be embodied in a computer readable signal medium that can communicate the program code to a processor for execution. Examples of a computer readable signal medium include, but are not limited to, a data transmission that can employ a carrier wave or other propagated signal to convey the program code.

[0095] The present application is described in reference to the drawings, which are as follows. Figure 1 Figure 1 The present application is described in reference to the drawings, which are as follows.

[0096] The foregoing description of specific exemplary embodiments of the application has been presented for the purposes of illustration and description. It is not intended to be a limitation on the broad concepts of the application. Obviously, many modifications and variations of the specific exemplary embodiments described herein are possible in light of this disclosure, which is intended to be protected not only by the forms described but also by any alternative forms to which the principles disclosed can be applied. The exemplary embodiments were chosen and described in order to explain the principles of the application and its practical application and to allow others skilled in the art to understand the application for various exemplary embodiments with various modifications as are suited to the particular use contemplated.

[0097] ​It will be obvious to a person skilled in the art that the application is not limited to the details of the foregoing exemplary embodiments and can be implemented in other concrete forms without departing from the spirit or essential characteristics of the application. The embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. No reference signs in the claims should be considered as limiting the scope of the claims to the identity of the reference signs therein.

[0098] Furthermore, it should be understood that although the description is made on the basis of the embodiments, not every embodiment contains only one independent technical solution, and the description of the specification is only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that those skilled in the art can understand.

Claims

1. A chip verification method characterized by, The method comprises the following steps: pumping excitation from an interface of a to-be-verified module, and performing a first batch of regression tests on the to-be-verified module; obtaining coverage data of the to-be-verified module in the regression tests, wherein the coverage data comprises code coverage and / or function coverage; encapsulating a function area corresponding to a part of the coverage data that does not meet a preset condition into an independent logic block, and building a breakpoint excitation input interface for the logic block; taking the logic block as a new to-be-verified module, pumping excitation from the breakpoint excitation input interface, and performing a new batch of regression tests.

2. The chip verification method according to claim 1, wherein The method further comprises the following steps: constructing a granularity tree with code nodes and / or function points as leaf nodes and hierarchical types and function types of the to-be-verified module as intermediate nodes; based on importance, assigning weight values to each sub-node in the granularity tree, and the sum of weight values of sub-nodes belonging to the same parent node is the weight value of the parent node; obtaining coverage data of the to-be-verified module in the regression tests, and calculating coverage rates of each parent node and the root node layer by layer based on weighted average aggregation.

3. The chip verification method according to claim 2, wherein The method further comprises the following steps: based on the weight of a node in the granularity tree and the coverage rate of the node, calculating a risk index of the corresponding node; if the risk index of the node is greater than or equal to a preset threshold value, sending an alarm signal, and encapsulating a corresponding function area corresponding to the node into an independent logic block to perform a new batch of regression tests.

4. The chip verification method of claim 1, wherein, The method further comprises the following steps: when the object of the current regression test is the re-encapsulated independent logic block, calculating the coverage rate of each code node and / or function point and the change rate of the coverage rate of the corresponding code node and / or function point in the last batch of regression tests; if the change rate is greater than or equal to a preset first threshold value, increasing the amount of regression tests and updating the coverage rate of each node in the granularity tree based on the test results.

5. The chip verification method of claim 1, wherein, The method further comprises the following steps: configuring a type of coverage expected to be obtained; during the regression tests, recording the code nodes and / or function points executed in the to-be-verified module; based on the number of code nodes and / or function points executed in the regression tests, calculating the code coverage and / or function coverage required to be obtained.

6. The chip verification method of claim 1, wherein, The method further comprises the following steps: removing unreachable or constrained excluded code nodes and / or function points; collecting coverage information of each preset code node and / or function point in the regression tests, and labeling the coverage information based on the object of the regression tests.

7. The chip verification method of claim 1, wherein, The iteration termination conditions comprise: the number of batches of training reaches a preset second threshold value; or the code coverage and / or function coverage reaches a preset third threshold value.

8. A chip verification system applying the chip verification method according to any one of claims 1 to 7, characterized by, The method comprises the following steps: a test module for pumping excitation from an interface of a to-be-verified module, and performing a first batch of regression tests on the to-be-verified module; an obtaining module for obtaining coverage data of the to-be-verified module in the regression tests, wherein the coverage data comprises code coverage and / or function coverage; an encapsulating module for encapsulating a function area corresponding to a part of the coverage data that does not meet a preset condition into an independent logic block, and building a breakpoint excitation input interface for the logic block; An iteration module is configured to take the logic block as a new to-be-verified module, input stimuli from the breakpoint stimuli entry, and perform a new batch of regression tests.

9. A computer device, comprising: The chip verification method comprises the following steps: A memory and a processor are in communication connection, the memory stores computer instructions, and the processor executes the computer instructions to perform the chip verification method in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions for causing a computer to perform the chip verification method in any one of claims 1-7.

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