SRAM controller

Abstract

The invention provides an SRAM (Static Random Access Memory) controller. The SRAM controller comprises a cache control module, n caches, a read-write control module, a data merging module and an SRAM, the cache is used for temporarily buffering CPU write-in data and informing the CPU that write operation is completed in advance; meanwhile, the cache write-back operation and the subsequent write-in operation of the CPU are carried out at the same time, and the time required by cache write-back is effectively hidden. The access delay is effectively reduced, and the system performance is remarkably improved. According to the method, n caches and corresponding control logics are introduced, and a data writing process is optimized through a cache mechanism, so that the writing delay of a CPU (Central Processing Unit) is reduced from 3 clock cycles to 1 cycle in most application scenarios, and the efficiency of small-granularity writing operation is remarkably improved. The chip area is obviously reduced, and the overall resource overhead is obviously reduced. According to the method, occupation of hardware resources is effectively controlled, and the access efficiency and the data reliability are remarkably improved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit manufacturing technology, and specifically relates to an SRAM controller. Background Technology

[0002] In automotive-grade chip design, SRAM storage contents need to be protected by ECC (Error Correction Code) logic to improve data reliability. A common storage format is to store the ECC checksum along with the data. For example, 1 byte of data can use a 5-bit ECC checksum for error detection and correction, thus requiring a total of 13 bits (8 data bits + 5 ECC bits) for storage or transmission. Similarly, 2 bytes of data can use a 6-bit ECC checksum, requiring a total of 22 bits (16 data bits + 6 ECC bits). 4 bytes of data can use a 7-bit ECC checksum, requiring a total of 39 bits (32 data bits + 7 ECC bits). 8 bytes of data can use an 8-bit ECC checksum, requiring a total of 72 bits (64 data bits + 8 ECC bits). As the data bit width increases, the proportion of bits used for ECC checksums in the total bit width gradually decreases.

[0003] In MCU or SoC architectures, PSRAM (Program SRAM) is a critical storage unit used to store CPU instructions and data. Since the CPU requires the smallest read / write granularity to be one byte, PSRAM needs to support byte enable functionality to improve access efficiency. This allows each access to read or write only a single byte, thus completing byte-level operations within one clock cycle.

[0004] The PSRAM accessed by the CPU typically has a large storage capacity. In typical MCU and SoC sensor projects, commonly used SRAM specifications include 128KB and 256KB. There are generally two feasible solutions for implementing PSRAM memory with ECC protection:

[0005] Method 1: Each byte is protected against errors using an independent 5-bit ECC checksum. Accordingly, the minimum read / write unit of SRAM is adjusted to 13 bits (8 bits of data + 5 bits of ECC), assuming the CPU's maximum data width is 32 bits (i.e., one word). Advantages of Method 1: The CPU can write to / read from SRAM within one cycle, achieving optimal efficiency. Disadvantages of Method 1: This method consumes more SRAM resources, resulting in a 62.5% increase in overall storage capacity, placing significant pressure on area and cost.

[0006] Method 2: Each 32-bit word is protected against errors using a 7-bit ECC checksum. Accordingly, the SRAM data width is extended to 39 bits (32-bit data + 7-bit ECC), and globally enabled SRAM is employed. The specific workflow of Method 2 is as follows...Figure 1 As shown, this method involves 5 steps. Compared to Method 1, Method 2 has the following advantages: it is more efficient in utilizing storage resources, increasing memory capacity by only 21.88% and saving significant area overhead. The disadvantages of Method 2 are: while it supports writing words within a single clock cycle, it does not support writing bytes or half-words within a single cycle. For unaligned write operations, data updates must be completed through a multi-cycle process, requiring a total of 3 clock cycles: steps 1 and 2 are executed in the first cycle, step 3 in the second cycle, and the remaining operations are completed in the third cycle. Therefore, byte or half-word write operations will generate a 3-cycle access latency, significantly reducing the efficiency of small-granularity writes. Summary of the Invention

[0007] The purpose of this invention is to provide an SRAM controller that effectively reduces access latency and significantly improves system performance. It introduces n caches and corresponding control logic, optimizing the data write process through a caching mechanism. This reduces CPU write latency from 3 clock cycles to 1 cycle in most application scenarios, significantly improving the efficiency of fine-grained write operations. It also significantly reduces chip area and overall resource overhead. This invention effectively controls hardware resource usage while significantly improving access efficiency and data reliability.

[0008] This invention provides an SRAM controller, comprising:

[0009] The system comprises a cache control module, n caches, a read / write control module, a data merging module, and SRAM; the SRAM can be a globally enabled SRAM, allowing the CPU or DMA master device to access the SRAM controller byte-by-byte. The SRAM controller processes the byte access before reading or writing to the SRAM. The area of ​​a globally enabled SRAM is smaller than that of a byte-enabled SRAM. The n caches include: a first cache and a second cache; n ≥ 2, where n is an integer.

[0010] The cache control module is responsible for receiving write data sent by the CPU or pausing the CPU's write operation;

[0011] The n caches are used to temporarily buffer the data written by the CPU and to notify the CPU in advance that the write operation has been completed; at the same time, the cache write-back operation is performed simultaneously with the subsequent write operation of the CPU.

[0012] The read / write control module is used to control write operations from the n caches to the SRAM, and read operations from the SRAM to the CPU and the n caches;

[0013] The data merging module is used to select or merge cached data and SRAM data, and output the result data to the CPU.

[0014] Furthermore, the cache control module is responsible for pausing the CPU's write operation, specifically including: when both the first cache and the second cache are full, and the current write address is different from the address stored in the n caches, and none of the caches is performing the SRAM write-back operation, the cache control module will pause the CPU's write operation by pulling up a wait signal until one of the caches is released.

[0015] Furthermore, the read / write control module is also used for the generation and verification of error correction codes; if the error correction code verification bit stored in the SRAM does not match the corresponding data, an error correction code error report will be triggered.

[0016] Furthermore, the SRAM controller supports read and write operations for any of the following: bytes, half-words, and words.

[0017] Furthermore, each cache has two flag bits: a valid flag bit and a ready flag bit. When the valid flag bit is 1, it indicates that the data in the cache is valid. When the cache has never been written to after a reset, it is invalid, the valid flag bit is 0, and the data merging module cannot provide the cached data to the CPU. When the ready flag bit is 1, it indicates that the cache is not full and can be used to store the written data.

[0018] Each of the caches has a tag and a byte select signal; the tag is the address information of the written data, word-aligned; the byte select signal is used to indicate which bytes have been updated in the cache.

[0019] Furthermore, when all bits of the byte selection signal are 1, it indicates that the data in the cache has been completely updated; if the SRAM is idle at this time, a write-back operation will be performed to write the cached data into the SRAM; subsequently, the ready flag will change from full to ready, indicating that the cache can be used again.

[0020] Furthermore, the SRAM controller performs data write operations including:

[0021] The first method: In the current write operation, if any of the tags in the cache is the same as the write address sent by the CPU, then it is determined that the cache has been hit.

[0022] The second scenario: all n caches are missed, but at least one of the caches is in a ready state;

[0023] 2a. If the current write operation is a byte or half-word and no write-back operation is performed to the SRAM, then read data from the SRAM and merge the data read from the SRAM with the write data into the cache;

[0024] 2b. If the current write operation is a byte or half-word, and there is a write-back operation to the SRAM, then the SRAM is in an unreadable state, the cache control module directly overwrites the cached data, waits for the SRAM to be idle, and then reads and merges the data.

[0025] 2c. If the current write operation is a word, the cache control module cache_ctrl directly overwrites the data into the cache.

[0026] Furthermore, the SRAM controller's data write operation also includes:

[0027] The third scenario: All caches miss, and all caches are not in a ready state; one of the caches is writing data back to the SRAM, directly overwriting the data in the cache, because the cache will be ready in the next cycle;

[0028] The fourth scenario: All caches miss, and all caches are not in a ready state; none of the caches are currently writing back data, so the wait signal needs to be pulled high until one of the caches completes the write-back operation.

[0029] Furthermore, the SRAM controller performs the data readout operation by including:

[0030] Option 1: If the cache_valid flag of all the caches is invalid, it means that there is no valid data available for reading in the current cache. In this case, the CPU's read request will bypass the cache and directly obtain the required data from the SRAM.

[0031] Furthermore, the SRAM controller's data readout operation also includes:

[0032] The second scenario: If the cache_valid flag is valid,

[0033] 2a. If the address read by the CPU does not match any of the tags in the cache, it indicates that the data currently being accessed is not in the cache, and the CPU will bypass the cache and directly read the required data from the SRAM;

[0034] 2b. If the address read by the CPU matches the tag of one of the caches, and the required data is already fully present in the cache, then the CPU will read the data directly from the cache without accessing the SRAM;

[0035] 2c. The address read by the CPU matches the tag of one of the caches, and the required data part exists in the cache. The CPU reads data from the cache and the SRAM. The data merging module merges the data in the cache and the data in the SRAM and outputs it to the CPU.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] This invention provides an SRAM controller, comprising: a cache control module, n caches, a read / write control module, a data merging module, and SRAM; the n caches include: a first cache and a second cache; the cache control module is responsible for receiving write data sent by the CPU or pausing the CPU's write operation; the n caches are used to temporarily buffer the CPU's write data and notify the CPU in advance that the write operation is complete; simultaneously, the cache write-back operation is performed concurrently with the CPU's subsequent write operation, effectively hiding the time required for cache write-back. The read / write control module is used to control write operations from the n caches to the SRAM, and read operations from the SRAM to the CPU and the n caches; the data merging module is used to select or merge cached data and SRAM data, and output the result data to the CPU.

[0038] This invention effectively reduces access latency and significantly improves system performance. It introduces n caches and corresponding control logic, optimizing the data write process through a caching mechanism. This reduces CPU write latency from 3 clock cycles to 1 cycle in most application scenarios, significantly improving the efficiency of fine-grained write operations. This invention also significantly reduces chip area and overall resource overhead. This invention achieves a good trade-off between chip area and system performance, effectively controlling hardware resource usage while significantly improving access efficiency and data reliability. Attached Figure Description

[0039] Figure 1 The flowchart of the SRAM controller for the improved Method 2.

[0040] Figure 2 This is a block diagram of an SRAM controller structure according to an embodiment of the present invention.

[0041] Figure 3 A schematic diagram of an SRAM controller write operation according to an embodiment of the present invention.

[0042] Figure 4 A schematic diagram of an SRAM controller read operation according to an embodiment of the invention.

[0043] Figure 5 This is a schematic diagram comparing the area of ​​the present invention with that of the previous methods one and two.

[0044] Figure 6 A schematic diagram comparing the performance of the present invention with that of the previous methods one and two. Detailed Implementation

[0045] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0046] For ease of description, some embodiments of this application may use spatially relative terms such as “above,” “below,” “top,” and “under” to describe the relationship between one element or component and another (or more) elements or components as shown in the accompanying drawings. It should be understood that, in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device during use or operation. For example, if the device in the drawings is flipped, it is described as an element or component “below” or “under” other elements or components, and will subsequently be positioned “above” or “on” other elements or components. The terms “first,” “second,” etc., used below are used to distinguish between similar elements and are not necessarily used to describe a particular order or temporal sequence. It should be understood that these terms, as used, may be replaced where appropriate.

[0047] In this invention, the modules of the controller according to the invention can be implemented using software, hardware, firmware, or a combination thereof. When a module is implemented using software, its function can be implemented through computer program flow. For example, the module can be implemented using code segments (such as code segments in languages ​​like C and C++) stored in a storage device (such as a hard disk, memory, etc.), wherein the corresponding function of the module can be implemented when the code segment is executed by a processor. When a module is implemented using hardware, its function can be implemented by setting a corresponding hardware structure. For example, the module's function can be implemented by hardware programming a programmable device such as a field-programmable gate array (FPGA), or by designing an application-specific integrated circuit (ASIC) including multiple transistors, resistors, capacitors, and other electronic devices. When a module is implemented using firmware, the module's function can be written into a read-only memory such as an EPROM or EEPROM in the form of program code, and the corresponding function of the module can be implemented when the program code is executed by a processor.

[0048] This invention provides an SRAM controller, such as... Figure 2 As shown, it includes:

[0049] The system includes a cache control module, n caches, a read / write control module, a data merging module, and SRAM; the n caches include a first cache and a second cache; the explanation is based on an example with n=2.

[0050] The cache control module is responsible for receiving write data sent by the CPU or pausing the CPU's write operation;

[0051] n caches are used to temporarily buffer data written to the CPU and notify the CPU in advance that the write operation is complete; at the same time, the cache write-back operation is performed concurrently with the subsequent CPU write operation.

[0052] The read / write control module is used to control write operations from n caches to SRAM, and read operations from SRAM to the CPU and n caches;

[0053] The data merging module is used to select or merge cached data and SRAM data, and output the result data to the CPU.

[0054] Specifically, the cache control module is responsible for receiving write data wdata_i sent by the CPU. When both the first and second caches are full, and the current write address is different from the address stored in the n caches, and no cache is currently performing an SRAM write-back operation, the cache control module will pause the CPU's write operation by raising the wait_o signal until one of the caches is released. Considering that the CPU rarely writes to different addresses consecutively, this mechanism almost never causes CPU blocking, effectively reducing access latency and significantly improving system performance. The wait_o signal is usually a status signal; raising the wait_o signal is equivalent to telling the CPU "memory is full, pause data transmission".

[0055] In this invention, n caches are used for temporary buffering of data wdata_i written by the CPU. The cache capacity is designed based on the bus width; this embodiment uses a 32-bit word as an example. The SRAM controller supports read and write operations of any type: byte, half-word, and word.

[0056] The read / write control module controls write operations from n caches to SRAM, and read operations from SRAM to the CPU and n caches. ECC generation and verification are also performed in the read / write control module. If the ECC check bit stored in SRAM does not match the corresponding data, an ECC error report is triggered. The SRAM controller of this invention can perform byte-by-byte writes while also using ECC algorithms to protect data. This SRAM controller effectively controls hardware resource usage, significantly reduces chip area, and substantially lowers overall resource overhead under conditions requiring byte-by-byte writes and data protection.

[0057] The simplified workflow of this invention for writing bytes or half-words includes:

[0058] S1. The CPU is ready to write a byte or half-word to SRAM.

[0059] S2. Check if at least one of the n caches is in a ready state or can be overwritten; if so, notify the CPU to overwrite and write data to the ready cache; if not, wait for one cycle before writing to the cache and notifying the CPU to overwrite.

[0060] S3, the SRAM controller reads data from the SRAM;

[0061] S4, the SRAM controller merges data and calculates error correction codes;

[0062] S5, the SRAM controller writes error correction code data to SRAM.

[0063] The core idea of ​​this invention is to use a cache to buffer the CPU's write data and notify the CPU in advance that the write operation is complete. Simultaneously, the cache write-back operation occurs concurrently with the subsequent CPU write operation, effectively hiding the time required for cache write-back.

[0064] Each cache has two flags: a validity flag (cache_valid) and a readiness flag (cache_ready). A validity flag of 1 indicates that the data in the cache is valid.

[0065] The cache is invalid until it has been written to after a reset, and the validity flag is 0. The data merging module cannot provide cached data to the CPU. When the readiness flag is 1, it indicates that the cache is not full and can be used to store write data wdata_i.

[0066] Each cache has a tag and a byte select signal `byte_sel`. The tag is the address information of the data `wdata_i` to be written, word-aligned. The byte select signal indicates which bytes have been updated in the cache. When all bits of the byte select signal are 1, it means that all data in the cache has been updated. If the SRAM is idle at this time, a write-back operation will be performed to write the data from the cache to the SRAM. Subsequently, the `cache_ready` flag will change from full to ready, indicating that the cache can be used again.

[0067] The cache of this invention can cache incomplete word write data from the CPU and then notify the CPU that the data has been successfully received. Even if the cache misses, retrieving data from SRAM will not slow down the access speed.

[0068] A cache hit occurs when the data requested by the application happens to be stored in the cache and can be successfully retrieved.

[0069] A cache miss occurs when the data requested by the application is not in the cache. The system must then retrieve the data from the primary data source (such as a database or SRAM). This invention ensures that retrieving data from SRAM during a cache miss does not slow down access speed.

[0070] The SRAM controller of this invention performs data write operations in the following ways: Figure 3 A continuous write operation will only make the CPU wait once:

[0071] Type 1 (Write 1): In the current write operation, if any cache tag (cache_tag) is the same as the write address sent by the CPU, it is determined as a cache hit.

[0072] The second scenario: all n caches fail, but at least one cache is ready.

[0073] 2a (Write 2a): If the current write operation is a byte or half-word and no write-back operation is performed to SRAM, then read the data from SRAM and merge the data read from SRAM with the written data wdata_i into the cache.

[0074] 2b (Write 2b): If the current write operation is a byte or half-word and a write-back operation is performed to SRAM, the SRAM is in an unreadable state. The cache control module cache_ctrl directly overwrites the cached data and waits for the SRAM to become idle before reading the data and merging it.

[0075] 2c (Write 2c): If the current write operation is a word, the cache control module cache_ctrl directly overwrites the data into the cache.

[0076] The third scenario (write 3): All caches miss, and all caches are not in the ready state; one of the caches is writing data back to SRAM, directly overwriting the data in the cache, because the cache will be ready in the next cycle;

[0077] Type 4 (Write 4): All caches miss, and all caches are not in the ready state; no cache is currently writing back data, so the wait_o signal needs to be pulled high until one of the caches completes the write-back operation.

[0078] The SRAM controller performs data read operations in the following ways: (Combined with...) Figure 4 As shown:

[0079] Type 1 (Read 1): If all cache valid flags are invalid, it means that there is no valid data available for reading in the current cache. In this case, the CPU's read request will bypass the cache and directly obtain the required data from SRAM.

[0080] The second scenario: If the cache validity flag (cache_valid) is valid,

[0081] 2a (read 2a) The address read by the CPU does not match any of the cache tags, indicating that the data being accessed is not in the cache. The CPU will bypass the cache and read the required data directly from SRAM.

[0082] If the address read by the CPU matches the tag of one of the caches and the required data is already fully present in that cache (i.e., all required bytes have been cached), then the CPU will read the data directly from the cache without accessing SRAM.

[0083] 2c (read 2c): The address read by the CPU matches the tag of one of the caches, and the required data part exists in the cache. The CPU reads data from the cache and SRAM. The data merging module merges the data cache_data in the cache and the data sram_data in the SRAM and outputs it to the CPU through the rdata_o signal.

[0084] The SRAM used in this invention can be a globally enabled SRAM. Through the design of the SRAM controller, from the CPU's perspective, it can achieve the effect of a byte-enabled SRAM. For example, a globally enabled SRAM can be 39 bits (32-bit word data + 7-bit ECC). A standard SRAM chip has a single write enable (WE_n) pin. When this pin is active, all bits on the data bus are written to the specified address at once. Byte-enabled SRAM adds finer control on top of this. It typically has multiple byte enable pins (BE_n) (e.g., four BE_n pins for a 32-bit wide SRAM). Each BE_n signal controls the write operation of one byte (8-bit) segment of the data bus. This allows the controller to write only specific bytes in memory without affecting other bytes at the same address.

[0085] Advantages of byte-enabled SRAM: Finer granularity of writes: A single byte within a 32-bit word can be modified without performing a "read-modify-write" operation. Reduced power consumption and bandwidth: Only the portion of the byte that needs to be changed undergoes actual circuit flipping. Simplified software operation: The CPU can directly execute byte or half-word store instructions without additional hardware or software steps.

[0086] This invention designs an SRAM controller with ECC protection that allows byte-level access, using a normally globally enabled SRAM; byte-level access functionality can be achieved through control. This controller supports efficient single-cycle byte-level read and write operations and provides data integrity guarantees. This invention introduces n caches and corresponding control logic, optimizing the data write process through the caching mechanism, thereby reducing the CPU write latency from 3 clock cycles to 1 cycle in most application scenarios, significantly improving the efficiency of small-granularity write operations. Compared to the previous method, this invention significantly reduces the chip area and overall resource overhead. This invention achieves a good trade-off between chip area and system performance, effectively controlling hardware resource usage while significantly improving access efficiency and data reliability.

[0087] like Figure 5 As shown, this invention has an area advantage, consisting of only n cache modules, a globally enabled SRAM, and corresponding control logic. Compared to the actual byte-enabled SRAM used in traditional implementations, this invention has a significant advantage in chip area. Figure 5 This paper presents a comparison of the area of ​​three different implementation methods, and analyzes a PSRAM based on a 40nm process with an effective storage capacity of 128KB as an example. Figure 5The data shows that the total area of ​​this invention is only 73.4% of that of Method 1. The total area of ​​this invention is only 2.8% larger than that of Method 2, but the write efficiency is significantly improved. If the storage capacity of SRAM increases, this ratio will decrease further.

[0088] like Figure 6 As shown, this invention has performance advantages. When the CPU writes data into the PSRAM, this invention rarely makes the CPU wait. This invention has lower write latency and higher write efficiency and performance. Figure 6 The diagram illustrates the number of cycles required for the CPU to perform four consecutive byte writes and the number of cycles required for the CPU to boot into the PSRAM and write 75 bytes consecutively to that PSRAM. In examples involving writing small amounts of data, the present invention and Method 1 have the same number of write cycles, exhibiting equal efficiency. In examples involving writing large amounts of data, the present invention has a slightly higher number of write cycles than Method 1, but significantly fewer than Method 2.

[0089] This invention employs a caching method if byte-based and word-based writes have the same efficiency. In the previous method (method two), byte-based writes were at least 50% slower than word-based writes. This invention reduces chip area and improves write operation efficiency.

[0090] In summary, this invention provides an SRAM controller, comprising: a cache control module, n caches, a read / write control module, a data merging module, and SRAM; the n caches include: a first cache and a second cache; the cache control module is responsible for receiving write data sent by the CPU or pausing the CPU's write operation; the n caches are used to temporarily buffer the CPU's write data and notify the CPU in advance that the write operation is complete; simultaneously, the cache write-back operation is performed concurrently with the subsequent CPU write operation, effectively hiding the time required for cache write-back. The read / write control module is used to control write operations from the n caches to the SRAM, and read operations from the SRAM to the CPU and the n caches; the data merging module is used to select or merge cached data and SRAM data, and output the result data to the CPU. This invention effectively reduces access latency and significantly improves system performance. This invention introduces n caches and corresponding control logic, optimizing the data write process through a caching mechanism, thereby reducing the CPU's write latency from 3 clock cycles to 1 cycle in most application scenarios, significantly improving the efficiency of small-granularity write operations. This invention significantly reduces chip area and overall resource overhead. This invention achieves a good trade-off between chip area and system performance, effectively controlling the occupation of hardware resources while significantly improving access efficiency and data reliability.

[0091] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The methods disclosed in the embodiments are described simply because they correspond to the devices disclosed in the embodiments; relevant details can be found in the method section.

[0092] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. An SRAM controller, characterized in that, include: The system includes a cache control module, n caches, a read / write control module, a data merging module, and SRAM. The n caches include: a first cache and a second cache; n ≥ 2, where n is an integer; The cache control module is responsible for receiving write data sent by the CPU or pausing the CPU's write operation; The n caches are used to temporarily buffer the data written by the CPU and to notify the CPU in advance that the write operation has been completed; at the same time, the cache write-back operation is performed simultaneously with the subsequent write operation of the CPU. The read / write control module is used to control write operations from the n caches to the SRAM, and read operations from the SRAM to the CPU and the n caches; The data merging module is used to select or merge cached data and SRAM data, and output the result data to the CPU.

2. The SRAM controller as described in claim 1, characterized in that, The cache control module is responsible for pausing the CPU's write operation. Specifically, when both the first cache and the second cache are full, and the current write address is different from the address stored in the n caches, and none of the caches is performing the SRAM write-back operation, the cache control module will pause the CPU's write operation by pulling a high wait signal until one of the caches is released.

3. The SRAM controller as described in claim 1, characterized in that, The read / write control module is also used for generating and verifying error correction codes; if the error correction code verification bit stored in the SRAM does not match the corresponding data, an error correction code error report will be triggered.

4. The SRAM controller as described in claim 1, characterized in that, The SRAM controller supports read and write operations of any type: byte, half-word, and word.

5. The SRAM controller as described in claim 1, characterized in that, Each cache has two flag bits: a valid flag bit and a ready flag bit. When the valid flag bit is 1, it indicates that the data in the cache is valid. When the cache has never been written to after a reset, it is invalid, the valid flag bit is 0, and the data merging module cannot provide the cached data to the CPU. When the ready flag bit is 1, it indicates that the cache is not full and can be used to store the written data. Each cache has a tag and a byte select signal; the tag is the address information of the written data, word-aligned. The byte selection signal is used to indicate which bytes have been updated in the cache.

6. The SRAM controller as described in claim 5, characterized in that, When all bits of the byte selection signal are 1, it indicates that the data in the cache has been completely updated. If the SRAM is idle at this time, a write-back operation will be performed to write the cached data into the SRAM. Subsequently, the ready flag will change from full to ready, indicating that the cache can be used again.

7. The SRAM controller as described in claim 5, characterized in that, The SRAM controller performs data write operations including: The first method: In the current write operation, if any of the tags in the cache is the same as the write address sent by the CPU, then it is determined that the cache has been hit. The second scenario: all n caches are missed, but at least one of the caches is in a ready state; 2a. If the current write operation is a byte or half-word and no write-back operation is performed to the SRAM, then read data from the SRAM and merge the data read from the SRAM with the write data into the cache; 2b. If the current write operation is a byte or half-word, and there is a write-back operation to the SRAM, then the SRAM is in an unreadable state, the cache control module directly overwrites the cached data, waits for the SRAM to be idle, and then reads and merges the data. 2c. If the current write operation is a word, the cache control module cache_ctrl directly overwrites the data into the cache.

8. The SRAM controller as described in claim 5, characterized in that, The SRAM controller's data write operation also includes: The third scenario: All caches miss, and all caches are not in a ready state; one of the caches is writing data back to the SRAM, directly overwriting the data in the cache, because the cache will be ready in the next cycle; The fourth scenario: All caches miss, and all caches are not in a ready state; none of the caches are currently writing back data, so the wait signal needs to be pulled high until one of the caches completes the write-back operation.

9. The SRAM controller as described in claim 5, characterized in that, The SRAM controller performs data readout operations including: Option 1: If the cache_valid flag of all the caches is invalid, it means that there is no valid data available for reading in the current cache. In this case, the CPU's read request will bypass the cache and directly obtain the required data from the SRAM.

10. The SRAM controller as claimed in claim 5, characterized in that, The SRAM controller's data readout operation also includes: The second scenario: If the cache_valid flag is valid, 2a. If the address read by the CPU does not match any of the tags in the cache, it indicates that the data currently being accessed is not in the cache, and the CPU will bypass the cache and directly read the required data from the SRAM; 2b. If the address read by the CPU matches the tag of one of the caches, and the required data is already fully present in the cache, then the CPU will read the data directly from the cache without accessing the SRAM; 2c. The address read by the CPU matches the tag of one of the caches, and the required data part exists in the cache. The CPU reads data from the cache and the SRAM. The data merging module merges the data in the cache and the data in the SRAM and outputs it to the CPU.

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