High-robustness high-speed serial transmission data sampling method
By traversing the number of delay module taps to determine the optimal number of delay taps for phase alignment, the problem of inaccurate data sampling points in high-speed serial transmission is solved, and highly robust data transmission is achieved.
Patent Information
- Application Number
- CN202511091673.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-05
- Publication Date
- 2025-11-21
AI Technical Summary
In existing high-speed serial data sampling, the sampling point is often not the optimal sampling point or even the wrong sampling point, which leads to data errors.
By determining the maximum number of delay taps n in the delay module, traversing all taps in the delay module, collecting parallel data multiple times and forming indicator bits, and using n+1 indicator bits to determine the maximum number of consecutive 1s and the ending position, the optimal number of delay taps is found for phase alignment.
High-precision phase alignment is achieved, ensuring that the sampling point is the optimal sampling point, improving the robustness of data transmission, and avoiding the problem of inaccurate sampling points in existing methods.
Smart Images
Figure CN120994599A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application relates to a serial transmission data phase alignment method, in particular to a high-robustness high-speed serial transmission data sampling method. BACKGROUND
[0002] High-speed serial data transmission is widely used in multi-channel data transmission such as image sensor or data transmission of ADC and FPGA. However, the difference between the chip internal or PCB wiring leads to the phase difference between the data of different channels and the synchronous sampling clock. Direct sampling will lead to sampling data error due to the improper sampling position. Therefore, the high-speed serial transmission data needs to be phase aligned with the synchronous sampling clock before sampling, so as to find the best sampling position.
[0003] At present, the commonly used high-speed serial transmission data phase alignment method is to sequentially find the start and end positions of the valid sampling window, and take the center position of the valid sampling window as the best sampling point. However, this method only focuses on the first found valid sampling window and ignores other valid sampling windows. When the first found valid sampling window is poor in quality, the found sampling point may not be the best sampling point or even an error sampling point. SUMMARY
[0004] The application aims to solve the technical problem that the sampling point is not the best sampling point or even an error sampling point in the existing high-speed serial transmission data sampling, and provides a high-robustness high-speed serial transmission data sampling method.
[0005] In order to achieve the above-mentioned purpose, the technical scheme provided by the application is as follows:
[0006] A high-robustness high-speed serial transmission data sampling method, which is characterized by comprising the following steps:
[0007] Step 1, determining the maximum delay tap number n of the delay module, the clock period required for collecting parallel data once, and the number M of clock periods required from the time when the delay tap number is changed to the time when the latest parallel data is collected;
[0008] Step 2, the sending end of the high-speed serial transmission data continuously sends a training word, so that the receiving end continuously receives serial data, and converts the received serial data into parallel data;
[0009] Step 3, the delay tap number of the delay module is taken as any value in 0 tap to n tap, and after waiting for M clock periods, the parallel data is collected multiple times; if the multiple collected parallel data are consistent and are a kind of shift form of the training word, the corresponding indication bit is recorded as 1, otherwise the indication bit is recorded as 0;
[0010] Step 4, repeat step 3 until all the delay taps of the delay module are traversed to obtain corresponding n indication bits;
[0011] Step 5, determine the optimal delay setting of the phase alignment of the high-speed serial transmission data;
[0012] Step 5.1, traverse the n+1 indication bits obtained in steps 3 and 4 to find the maximum number of consecutive 1s, record it as max_one, and record the end position of the maximum consecutive 1s as end_one;
[0013] Step 5.2, if max_one is odd, the optimal delay tap number of the phase alignment of the high-speed serial transmission data is end_one-(max_one-1) / 2; if max_one is even, the optimal delay tap number of the phase alignment of the high-speed serial transmission data is end_one-max_one / 2;
[0014] Step 6, according to the optimal delay tap number of the phase alignment of the high-speed serial transmission data determined in step 5.2, the phase alignment of the high-speed serial transmission data is realized, and the high-speed serial transmission data after phase alignment is sampled.
[0015] Further, in step 5.1, traversing the n+1 indication bits obtained in steps 3 and 4 is specifically:
[0016] The n+1 indication bits obtained in steps 3 and 4 form an indication bit sequence, and the indication bit sequence is traversed in the order from front to back or from back to front.
[0017] Further, in step 1, the delay module is a delay module in FPGA or a delay module in ASIC.
[0018] Compared with the prior art, the beneficial effects of the present application are as follows:
[0019] 1、The high-robustness high-speed serial transmission data sampling method provided by the present application fully utilizes the delay range of the delay module, traverses all the delay taps of the delay module to obtain n+1 indication bits, then traverses the n+1 indication bits to determine the maximum number of consecutive 1s and the end position of the maximum consecutive 1s, and then finds the optimal sampling point in the maximum effective sampling window through the parity to obtain the optimal delay tap number required for phase alignment. The sampling method of the present application is simple and efficient, and has high alignment accuracy, thereby ensuring the high robustness of data transmission and effectively avoiding the problem that the obtained is not the optimal sampling window when only the first effective sampling window is found during the sampling of the existing high-speed serial transmission data.
[0020] 2、The high-robustness high-speed serial transmission data sampling method can be modularly called, and is easy to realize in an FPGA or an ASIC chip and easy to popularize and apply on a large scale.
[0021] 3、The high-robustness high-speed serial transmission data sampling method can traverse in an arbitrary order when traversing all delay taps of the delay module and the n+1 indication bits, and is convenient to operate and has higher execution flexibility. BRIEF DESCRIPTION OF DRAWINGS
[0022] Figure 1 FIG. 1 is a flowchart of the high-robustness high-speed serial transmission data sampling method;
[0023] Figure 2 FIG. 2 is a diagram of the relationship between the delay tap number and the data bit period in step 1 of the embodiment of the present application;
[0024] Figure 3 FIG. 5 is a diagram of the process of determining the optimal delay tap number of the 16-channel high-speed serial transmission data phase alignment in step 5 of the embodiment of the present application. DETAILED DESCRIPTION
[0025] The advantages and characteristics of the present application will be more apparent from the following detailed description of the present application in combination with the accompanying drawings and specific embodiments.
[0026] As shown in FIG. 1, a high-robustness high-speed serial transmission data sampling method specifically includes the following steps: Figure 1
[0027] Step 1, determine the maximum delayable tap number n of the delay module, and then the delay tap number of the delay module is from 0 tap to ntap, i.e., 0 tap, 1 tap, 2 tap,..., ntap, and n=64 in this embodiment. The tap is a basic delay unit of the delay module, and the relationship between the delay tap number and the data bit period is as shown in FIG. 2. Figure 2 As shown in FIG. 2, the maximum delayable tap number n can cover multiple data bit periods.
[0028] The delay module can be a delay module in an FPGA or a delay module in an ASIC, and is a delay module in an FPGA in this embodiment.
[0029] At the same time, determine the clock period required for collecting parallel data once and the clock period number M required from the moment of changing the delay tap number to the moment of collecting the latest parallel data, and M=5 in this embodiment.
[0030] Step 2, the sending end of the high-speed serial transmission data continuously sends the same training word, so that the receiving end continuously receives serial data and converts the received serial data into parallel data.
[0031] Step 3, set the initial delay tap number of the delay module to any value from 0 tap to n tap, wait for five clock cycles, and collect parallel data multiple times; if the parallel data collected multiple times are consistent and are a shift form of the training word, then record the corresponding indication bit as 1, otherwise record the indication bit as 0.
[0032] Step 4, repeat step 3, each time, the delay tap number takes any untraversed value from 0 tap to n tap, until all delay tap numbers of the delay module are traversed, and 65 indication bits are obtained.
[0033] Step 5, determine the optimal delay setting for phase alignment of high-speed serial transmission data.
[0034] Step 5.1, form an indication bit sequence from the 65 indication bits, traverse the 65 indication bits in the indication bit sequence in the order from front to back, find the maximum number of consecutive 1s, record it as max_one, and record the end position of the maximum number of consecutive 1s as end_one. In other embodiments of the present application, the traversal can also be in the order from back to front, or in other pre-set orders, which are not limited herein, as long as the maximum number of consecutive 1s and the end position can be found.
[0035] Step 5.2, if max_one is odd, then the optimal delay tap number for phase alignment of high-speed serial transmission data is end_one-(max_one-1) / 2, that is, the sampling point is at the position of delay
end_one-(max_one-1) / 2
end_one-max_one / 2
[0036] As Figure 3The figure shows a process diagram for determining the optimal delay tap number of 16-channel high-speed serial transmission data phase alignment, wherein the white area is the window area, the blue area is the unstable area, 8e, a3, 47, d1, etc. are a shift form of the training word, and ce, d3, 67, 9d, 1f, etc. are the critical values of the unstable area. The optimal delay tap number determined by the application is the middle point of the largest window (i.e. the window with the longest middle white area), while the optimal delay tap number determined by the prior art is the middle point of the first window on the left or other critical points, and the non-optimal position is even an error position.
[0037] Step 6: Realize high-speed serial transmission data phase alignment according to the optimal delay tap number of high-speed serial transmission data phase alignment determined in step 5.2, and finally sample the high-speed serial transmission data after phase alignment.
[0038] The high-speed serial transmission data phase alignment method of the application fully utilizes the delay range of the delay module, finds the optimal sampling point in the largest valid sampling window by traversing all delay tap numbers of the delay module, and thus determines the optimal delay required for phase alignment. The method can be modularly called, or can be integrated into FPGA or ASIC on a large scale.
[0039] The above description is only used to illustrate the technical solutions of the application, and not to limit them. For ordinary skilled persons in the art, the specific technical solutions described in the above embodiments can be modified, or some technical features can be replaced by equivalents, and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions protected by the application.
Claims
1. A high-robustness high-speed serial transmission data sampling method, characterized in that, The method comprises the following steps: Step 1, determining the maximum number of taps n of the delay module, the clock cycle required for collecting parallel data once, and the number M of clock cycles required from the time when the number of taps is changed to the time when the latest parallel data is collected; Step 2, the sending end of the high-speed serial transmission data continuously sends a training word, so that the receiving end continuously receives serial data and converts the received serial data into parallel data; Step 3, the number of taps of the delay module is set to any value from 0 tap to n tap, and after waiting for M clock cycles, the parallel data is collected multiple times; if the parallel data collected multiple times are consistent and are a shift form of the training word, the corresponding indication bit is recorded as 1, otherwise the indication bit is recorded as 0; Step 4, repeating step 3 until all the remaining taps of the delay module are traversed, and n indication bits are obtained; Step 5, determining the optimal delay setting for phase alignment of high-speed serial transmission data; Step 5.1, traversing the n+1 indication bits obtained in steps 3 and 4 to find the maximum number of consecutive 1s, recording the maximum number of consecutive 1s as max_one, and recording the end position of the maximum number of consecutive 1s as end_one; Step 5.2, if max_one is odd, the optimal delay tap number for phase alignment of high-speed serial transmission data is end_one-(max_one-1) / 2; if max_one is even, the optimal delay tap number for phase alignment of high-speed serial transmission data is end_one-max_one / 2; Step 6, according to the optimal delay tap number for phase alignment of high-speed serial transmission data determined in step 5.2, the phase alignment of high-speed serial transmission data is realized, and the data sampling of the phase-aligned high-speed serial transmission data is performed.
2. The high-robustness high-speed serial transmission data sampling method according to claim 1, wherein: In step 5.1, the traversal of the n+1 indication bits obtained in steps 3 and 4 is specifically: The n+1 indication bits obtained in steps 3 and 4 form an indication bit sequence, and the indication bit sequence is traversed in the order from front to back or from back to front.
3. The high-robustness high-speed serial transmission data sampling method according to claim 2, wherein: In step 1, the delay module is a delay module in FPGA or a delay module in ASIC.