Read-write speed acquisition method, performance detection method, storage device and electronic device

Abstract

The invention discloses a read-write speed acquisition method, a performance detection method, storage equipment and an electronic device. The speed acquisition method is applied to the host, the host is arranged in the electronic device, the electronic device further comprises a storage device, the host is connected with the storage device to perform data interaction with the storage device, and the storage device comprises a control unit and a storage unit. The speed acquisition method comprises the following steps: a host sends a speed acquisition instruction to a storage device in response to a speed acquisition command; the host receives a speed data packet sent by a control unit of the storage device; wherein the speed data packet comprises the read-write speed of the storage unit; and the host analyzes the speed data packet based on an analysis rule corresponding to the speed acquisition instruction to acquire the target read-write speed. In this way, the read-write speed of the storage device can be accurately obtained.

Description

Technical Field

[0001] This application relates to the field of storage, and in particular to a method for obtaining read / write speed, a performance testing method, a storage device, and an electronic device. Background Technology

[0002] With technological advancements, the demand for storage products in production and daily life is increasing. Taking certain surveillance scenarios as an example, the write speed of storage devices directly impacts the functionality of the surveillance equipment. If the write speed of the storage device is lower than the data stream requirements of the surveillance equipment, it will lead to malfunctions. Typically, the speed of a storage device is sometimes like a black box; external devices cannot obtain the read and write speed of the storage device. It is generally represented to some extent by the cache on the external controller chip. Summary of the Invention

[0003] The main purpose of this application is to provide a method for obtaining read / write speed, a performance testing method, a storage device, and an electronic device that can accurately obtain the read / write speed of the storage device.

[0004] To address the aforementioned technical problems, the first technical solution adopted in this application is: providing a method for obtaining read / write speeds. This method is applied to a host computer, which is located within an electronic device. The electronic device also includes a storage device, and the host computer is connected to the storage device for data interaction. The storage device includes a control unit and storage units. The method includes: the host computer responding to a speed acquisition command by sending a speed acquisition instruction to the storage device; the host computer receiving a speed data packet sent by the control unit of the storage device; wherein the speed data packet includes the read / write speed of the storage unit; and the host computer parsing the speed data packet based on a parsing rule corresponding to the speed acquisition instruction to obtain the target read / write speed.

[0005] To address the aforementioned technical problems, the second technical solution adopted in this application is: providing a method for obtaining read / write speed. This method is applied to a storage device, which includes a control unit and storage units. The storage device is housed within an electronic device, which also includes a host computer connected to the storage device for data interaction. The method includes: the control unit of the storage device, in response to receiving a speed acquisition command, acquiring the read / write speed of the storage units; the control unit generating a speed data packet based on the read / write speed and sending the speed data packet to the host computer, so that the host computer parses the speed data packet to obtain the target read / write speed.

[0006] To address the aforementioned technical problems, the third technical solution adopted in this application is: providing a storage device performance testing method. This method is applied to an electronic device, which includes a host and a storage device, the host connecting to the storage device for data interaction. The method includes the host acquiring a target read / write speed of the storage device, the target read / write speed being obtained by the read / write speed acquisition method in the first and / or second technical solutions; in response to the target read / write speed being lower than the host's required read / write speed, the host providing an alarm message to remind the user to replace the storage device.

[0007] To solve the aforementioned technical problems, the fourth technical solution adopted in this application is to provide a storage device. This storage device includes a control unit and a storage unit, which are connected to implement the method described in the second counting scheme.

[0008] To solve the aforementioned technical problems, the fifth technical solution adopted in this application is: to provide an electronic device. This electronic device includes a host computer and a storage device. The host computer is connected to the storage device to implement the method provided by any one or a combination of the first, second, and third technical solutions.

[0009] The beneficial effects of this application are as follows: In an electronic device, when the host receives a speed acquisition command, it sends a speed acquisition instruction to the storage device. The storage device then generates a speed data packet containing the read and write speeds of the storage units based on the speed acquisition instruction. The host receives this speed data packet and performs corresponding data packet parsing to obtain the read and write speeds of the storage units. Through this method, the host can obtain the read and write speeds of the storage units in the storage device at any time and accurately, thereby accurately determining whether to continue subsequent operations based on the read and write speeds of the storage units. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a flowchart illustrating the first embodiment of the read / write speed acquisition method of this application;

[0012] Figure 2 This is a flowchart illustrating the second embodiment of the read / write speed acquisition method of this application;

[0013] Figure 3 This is a flowchart illustrating the third embodiment of the read / write speed acquisition method of this application;

[0014] Figure 4 This is a flowchart illustrating the fourth embodiment of the read / write speed acquisition method of this application;

[0015] Figure 5 This is a flowchart illustrating the fifth embodiment of the read / write speed acquisition method of this application;

[0016] Figure 6 This is a schematic diagram of the structure of an embodiment of the storage device of this application;

[0017] Figure 7 This is a schematic diagram of the structure of an embodiment of the electronic device of this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0019] The terms "first," "second," etc., used in this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0020] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0021] Reference Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the read / write speed acquisition method of this application. The method is applied to a host computer, which is located in an electronic device. The electronic device also includes a storage device. The host computer is connected to the storage device to interact with it for data exchange. The storage device includes a control unit and a storage unit. This method may include, but is not limited to, the following steps.

[0022] S11: The host responds to the speed acquisition command by sending a speed acquisition instruction to the storage device.

[0023] The speed acquisition command is a command used to obtain the read and write speeds of a storage device. The host sends a speed acquisition instruction to the storage device based on this command. This speed acquisition command can be generated on the local host or sent from another host to the local host.

[0024] S12: The host receives the speed data packet sent by the control unit of the storage device.

[0025] The speed data packet includes the read and write speed of the storage unit.

[0026] S13: The host parses the speed data packet based on the parsing rules corresponding to the speed acquisition command in order to obtain the target read / write speed.

[0027] In this embodiment, when the host receives a speed acquisition command in the electronic device, it sends a speed acquisition instruction to the storage device. The storage device then generates a speed data packet containing the read and write speeds of the storage units based on the speed acquisition instruction. The host receives this speed data packet and performs corresponding data packet parsing to obtain the read and write speeds of the storage units. Through this method, the host can obtain the read and write speeds of the storage units in the storage device accurately and at any time, thereby accurately determining whether to continue subsequent operations based on the read and write speeds of the storage units.

[0028] The storage devices mentioned in this application include memory card-type storage devices, such as SD memory cards. This is because, when using such storage cards, the host typically cannot obtain read / write speed status information. Only when the storage device's read / write speed fails to meet requirements, causing malfunctions in the host's corresponding functions, can the user become aware that the storage device's read / write speed is problematic and cannot meet current needs. Furthermore, even then, the user only knows that the device does not meet the host's current requirements, without knowing the specific read / write speed of the storage device.

[0029] To enable information exchange between the host and the storage device regarding read / write speed data, this application proposes the following method.

[0030] In one embodiment, the host and storage device are directly connected via an interface, and the speed acquisition command includes a custom CMD command.

[0031] For example, a host communicates with a storage device via an SD / SPI interface. A custom CMD command A is configured between the host and the storage device. The host sends CMD command A to the storage device. Upon receiving CMD command A, the storage device sends a speed data packet to the host. This speed data packet stores the read / write speed of the storage device in the corresponding mode at the corresponding positions according to a preset format. For example, the speed data packet can be 512 bytes in size, divided into 32 rows and 16 columns. The read / write speed of the storage device in the first mode can be stored in the first row and columns 1-4, and the read / write speed of the storage device in the second mode can be stored in the first row and columns 5-8. The capacity of the speed data packet does not necessarily need to be entirely used to store read / write data; redundant capacity can be configured for subsequent adjustments. This redundant capacity can be used to store invalid data during packet transmission.

[0032] In one embodiment, the host and storage device are connected via a bridging chip, and the speed acquisition instructions include a sequence of read instructions.

[0033] In many use cases, the host and storage device do not establish a direct communication connection; instead, they communicate through a bridging chip. However, the bridging chip may not always support custom-configured CMD commands. Therefore, in such cases, reading the instruction sequence is chosen as a method to determine the read / write speed of the storage device.

[0034] Conventional logical reads involve reading data from the logical address of the storage product, which is user data. However, this application uses a sequence of read instructions as the read acquisition instructions. As long as the sequence of read instructions sent by the host to the storage product matches the pre-set sequence of read instructions corresponding to the speed acquisition instructions, the storage device will not output the user data corresponding to the logical address at the output position of the last read instruction. Instead, it will output a speed data packet.

[0035] The read instruction sequence described in this application includes at least two read instructions arranged in sequence, and the read logical addresses corresponding to the at least two read instructions are all different. Each read instruction corresponds to a read logical address; for example, the read instruction sequence could be CMD17 logical address A-CMD17 logical address B-CMD17 logical address C-CMD17 logical address D. CMD17 is the read command. If the storage product receives this read instruction sequence, the storage device outputs a speed data packet at the output location of CMD17 logical address D, instead of outputting user data at logical address D.

[0036] Reference Figure 2 , Figure 2This is a flowchart illustrating the second embodiment of the read / write speed acquisition method of this application. This method is a further extension of step S13, and includes, but is not limited to, the following steps.

[0037] S21: The host obtains the target driver mode and the target clock frequency.

[0038] S22: The host determines the location of the target data in the speed data packet based on the target drive mode, target clock frequency, and parsing rules.

[0039] S23: Parse the data at the target data location to obtain the target read / write speed.

[0040] Because the speed data packets store the write speed of the storage device in the corresponding mode in the corresponding location according to a preset format, and the storage device mode can include both driver mode and clock frequency, the host can directly parse the speed data packets to obtain the read and write speeds of the storage device in each mode, or it can obtain only the corresponding read and write speeds based on the mode information.

[0041] If it's not necessary to obtain read / write speeds across all modes, the speed can be obtained by parsing specific locations within the data packet. The host determines the corresponding driver mode and clock frequency for the mode requiring the speed, using these as the target driver mode and target clock frequency. Then, based on the target driver mode, target clock frequency, and parsing rules, the storage location of the read / write speed within the speed data packet is determined—the aforementioned target data location. The parsing rules include the preset format used when generating the speed data packet; this format determines the corresponding storage location for different mode read / write speeds. After obtaining the data at the corresponding location, further parsing yields the read / write speed.

[0042] Reference Figure 3 , Figure 3 This is a flowchart illustrating the third embodiment of the read / write speed acquisition method of this application. The method is applied to a storage device, which includes a control unit and a storage unit. The storage device is disposed within an electronic device, which also includes a host computer connected to the storage device for data interaction. The method includes, but is not limited to, the following steps.

[0043] S31: The control unit of the storage device responds to the received speed acquisition command and acquires the read and write speed of the storage unit.

[0044] S32: The control unit generates a speed data packet based on the read / write speed and sends the speed data packet to the host so that the host can parse the speed data packet to obtain the target read / write speed.

[0045] The host establishes a communication connection with the control unit of the storage device. After receiving the speed acquisition command, the control unit of the storage device acquires the read and write speeds of the storage device in each mode according to the modes included in the speed data packet. After acquisition, the read and write speed data is packaged and sent according to a preset format.

[0046] The speed acquisition instructions in this application may include custom CMD instructions or read instruction sequences. Similar content can be found in the above embodiments, and will not be repeated here.

[0047] Reference Figure 4 , Figure 4 This is a flowchart illustrating the fourth embodiment of the read / write speed acquisition method of this application. This method is a further extension of the above embodiments, including but not limited to the following steps.

[0048] S41: The control unit receives at least two target read commands.

[0049] S42: The control unit recognizes at least two target read commands as speed acquisition commands in response to the fact that the order of receiving at least two target read commands matches the order of reading commands in the read command sequence.

[0050] When the speed acquisition instruction is a read instruction sequence, and the read instruction sequence includes at least two read instructions arranged in sequence, and the read logical addresses corresponding to the at least two read instructions are all different, after the control unit of the storage device receives at least two target read instructions, it compares the receiving order of the target read instructions with the read instruction sequence corresponding to the speed acquisition instruction. If the two match, it is considered that the received at least two target read instructions are speed acquisition instructions.

[0051] For example, if the read instruction sequence corresponding to the speed acquisition instruction is CMD17 logical address A-CMD17 logical address B-CMD17 logical address C-CMD17 logical address D, and the received target read instruction sequence is CMD17 logical address A-CMD17 logical address B-CMD17 logical address C-CMD17 logical address D, then it is considered that a speed acquisition instruction has been received. If the received target read instruction sequence is CMD17 logical address B-CMD17 logical address A-CMD17 logical address C-CMD17 logical address D, then this sequence is not a speed acquisition instruction.

[0052] S43: When the control unit receives the last target read instruction among at least two target read instructions that are identified as speed acquisition instructions, it sends a speed data packet to the host to replace the stored data at the logical address corresponding to the last target read instruction.

[0053] After confirming that a speed acquisition command has been received, the speed data packet is output at the output position of the last read command in the read command sequence corresponding to the speed acquisition command.

[0054] Reference Figure 5 , Figure 5 This is a flowchart illustrating the fifth embodiment of the storage device performance testing method of this application. This method is applied to an electronic device, which includes a host and a storage device. The host is connected to the storage device to interact with it for data exchange. This method includes, but is not limited to, the following steps.

[0055] S51: The host obtains the target read / write speed of the storage device.

[0056] The target read / write speed is obtained by the read / write speed acquisition method described in the above embodiments.

[0057] The host can obtain the read and write speed of the storage device, either by using a speed acquisition command input by the user in real time, or by using a pre-set speed acquisition program. Every preset time interval, the speed acquisition program sends a speed acquisition command to the host, and the host sends a speed acquisition instruction to the storage device based on the speed acquisition command.

[0058] S52: In response to the target read / write speed being lower than the host's required read / write speed, the host displays an alarm message to remind the user to replace the storage device.

[0059] After reading the target read / write speed, it is compared with the read / write speed required by the host in the same mode. If the target read / write speed is greater than the required read / write speed, it means that the storage device can meet the host's storage needs in the corresponding mode. If the target read / write speed is less than the required read / write speed, it means that the storage device cannot meet the host's storage needs in the corresponding mode. The host needs to issue an alarm message to remind the user to replace the storage device to prevent it from affecting subsequent data storage.

[0060] In one embodiment, in response to the target read / write speed being greater than the required read / write speed, and the difference between the target read / write speed and the required read / write speed being less than a preset threshold, the host displays a warning message to remind the user whether to continue using the current storage device.

[0061] A speed threshold can be reserved for the required read and write speeds, providing users with advance notice so they can prepare to replace their storage devices. Users can choose to replace the storage device in advance or continue using it until it no longer meets their storage needs.

[0062] The read / write speed acquisition method described above in this application allows the host to display the read / write speed and alarm information through a display device connected to the host, or to provide voice prompts through an audio device, so that the user is aware of the read / write speed and alarm information.

[0063] This application also proposes a storage device. (See reference...) Figure 6 , Figure 6 This is a schematic diagram of the structure of an embodiment of the storage device of this application.

[0064] The storage device includes a control unit 110 and a storage unit 120.

[0065] Control unit 110 controls the operation of the storage device. Control unit 110 can also be referred to as a CPU (Central Processing Unit). Control unit 110 may be an integrated circuit chip with signal sequence processing capabilities. Control unit 110 can also be a general-purpose processor, digital signal sequence processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component. The general-purpose processor can be a microprocessor or any conventional processor.

[0066] The control unit 110 is communicatively connected to the storage unit 120 to implement the method provided in any of the third and fourth embodiments of the read / write speed acquisition method of this application, and possible combinations thereof.

[0067] This application also proposes an electronic device. (See reference...) Figure 7 , Figure 7 This is a schematic diagram of the structure of an embodiment of the electronic device of this application.

[0068] The electronic device includes a host 210 and a storage device 220. The host 210 is connected to the storage device 220 to implement the methods provided in any embodiment and possible combination of the above-described read / write speed acquisition method and / or storage device performance testing method of this application.

[0069] Storage device 220 may include memory card type storage devices.

[0070] In summary, in an electronic device, when the host receives a speed acquisition command, it sends a speed acquisition instruction to the storage device. The storage device then generates a speed data packet containing the read and write speeds of the storage units based on the speed acquisition instruction. The host receives this speed data packet and parses it accordingly to obtain the read and write speeds of the storage units. Through this method, the host can obtain the read and write speeds of the storage units in the storage device accurately and at any time, thereby accurately determining whether to continue subsequent operations based on the read and write speeds of the storage units.

[0071] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0072] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0073] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0074] If the integrated units in the other embodiments described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0075] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for obtaining read / write speed, applied to a host computer, the host computer being disposed in an electronic device, the electronic device further comprising a storage device, the host computer being connected to the storage device for data interaction with the storage device, the storage device comprising a control unit and a storage unit, characterized in that, The method includes: In response to the speed acquisition command, the host sends a speed acquisition instruction to the storage device; The host receives a speed data packet sent by the control unit of the storage device; wherein the speed data packet includes the read and write speeds of the storage unit; The host parses the speed data packet based on the parsing rules corresponding to the speed acquisition command in order to obtain the target read / write speed.

2. The method according to claim 1, characterized in that, The host and the storage device are directly connected via an interface, and the speed acquisition command includes a custom CMD command.

3. The method according to claim 1, characterized in that, The host and the storage device are connected via a bridging chip, and the speed acquisition instruction includes a read instruction sequence.

4. The method according to claim 3, characterized in that, The read instruction sequence includes at least two read instructions arranged in sequence, and the read logical addresses corresponding to the at least two read instructions are all different.

5. The method according to claim 1, characterized in that, The host parses the speed data packet based on the parsing rules corresponding to the speed acquisition command to obtain the target read / write speed, including: The host obtains the target drive mode and the target clock frequency; The host determines the location of the target data in the speed data packet based on the target driving mode, the target clock frequency, and the parsing rules. The data at the target data location is parsed to obtain the target read / write speed.

6. A method for obtaining read / write speed, applied to a storage device, the storage device including a control unit and a storage unit, the storage device being disposed in an electronic device, the electronic device further including a host, the host being connected to the storage device to perform data interaction with the storage device, characterized in that, The method includes: The control unit of the storage device, in response to receiving a speed acquisition command, acquires the read and write speed of the storage unit; The control unit generates a speed data packet based on the read / write speed and sends the speed data packet to the host so that the host can parse the speed data packet to obtain the target read / write speed.

7. The method according to claim 6, characterized in that, The read instruction sequence, which is the speed acquisition instruction, includes at least two read instructions arranged in sequence, wherein the read logical addresses corresponding to the at least two read instructions are all different. The control unit of the storage device, in response to receiving the speed acquisition instruction, includes: The control unit receives at least two target read commands; The control unit, in response to the fact that the receiving order of the at least two target reading instructions matches the arrangement order of the reading instructions in the reading instruction sequence, identifies the at least two target reading instructions as the speed acquisition instructions; Sending the speed data packet to the host includes: When the control unit receives the last target read instruction among the at least two target read instructions identified as the speed acquisition instruction, it sends the speed data packet to the host to replace the stored data at the logical address corresponding to the last target read instruction.

8. A method for testing the performance of a storage device, applied to an electronic device, the electronic device comprising a host and a storage device, the host being connected to the storage device for data interaction with the storage device, characterized in that, The method includes: The host obtains the target read / write speed of the storage device, and the target read / write speed is obtained by the read / write speed acquisition method according to any one of claims 1-7; In response to the target read / write speed being lower than the host's required read / write speed, the host issues an alarm message to remind the user to replace the storage device.

9. A storage device, characterized in that, It includes a control unit and a storage unit, the control unit and the storage unit being connected to implement the method as described in any one of claims 6-7.

10. An electronic device, characterized in that, It includes a host and a storage device, wherein the host is connected to the storage device to implement the method as described in any one of claims 1-8.

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