Memory controller with speculative predecessor commands

Abstract

A memory controller includes a command scheduler, a timer, and an interface configured to send memory access commands including a primary predecessor memory access command and a secondary predecessor memory access command to a memory. The command scheduler selects a memory access command associated with a memory access request. The timer indicates expiration of the first time period and the second time period. The first time period is shorter than the second time period by a specified amount, and the second time period is greater than or equal to a minimum time between a previous memory access command and an auxiliary predecessor memory access command of the memory. The command scheduler allows selection of a primary predecessor memory access command when the first time period has expired, and allows selection of a secondary predecessor memory access command when the second time period has expired.

Description

Background Technology

[0001] The memory controller provides the interface between the requesting device (such as a central processing unit (CPU) or input / output (I / O) device) and the memory device. Typically, the requesting device and the memory device are manufactured on separate dies or chips. Several protocols have been developed to facilitate communication with memory devices. Various standard protocols can be used to access memory such as Dynamic Random Access Memory (DRAM). These protocols specify the set of commands used to control the memory device and the physical interface to that memory device for transmitting commands and transferring data. Additionally, communication with the memory device must meet several timing constraints.

[0002] In many memory devices, memory cells are arranged as multiple two-dimensional arrays or banks of memory. In a DRAM device, reading data stored at an address requires a series of operations. These include selecting the bank, pre-charging the column lines, selecting the row based on the row address, sensing the row charge, and then reading the column based on the column address. These operations are performed in response to commands from the memory controller. Specifically, the read command for the column address must follow one or more preceding commands.

[0003] The memory controller can optimize data throughput by selecting the order in which it processes memory access requests received from the requesting device. This process is called scheduling. Additionally, commands from the memory controller to the memory device can be scheduled to optimize data throughput within the timing constraints of the memory device. Attached Figure Description

[0004] The accompanying drawings provide a visual representation that will be used to more fully describe various representative embodiments and can be used by those skilled in the art to better understand the disclosed representative embodiments and their inherent advantages. In these drawings, similar reference numerals denote corresponding or similar elements.

[0005] Figure 1 It is a simplified block diagram of a data processing system based on various representative implementation schemes.

[0006] Figure 2 It is a schematic diagram of the precursor command based on various representative implementation schemes.

[0007] Figure 3 It is a diagrammatic illustration of the sequence of commands being scheduled.

[0008] Figure 4 It is a diagrammatic illustration of the sequence of commands to be scheduled based on various representative implementation schemes.

[0009] Figure 5 It is a block diagram of a memory controller based on various representative implementation schemes.

[0010] Figure 6 It is a block diagram of timers / counters based on various representative implementation schemes.

[0011] Figure 7 It is a flowchart of the operation method of timer / counter based on various representative implementation schemes.

[0012] Figure 8 This is a flowchart of a command scheduler method based on various representative implementation schemes.

[0013] Figure 9 This is a block diagram showing the components of a memory controller according to various representative embodiments.

[0014] Figure 10 It is a table showing the sequence of commands scheduled according to various representative implementation schemes.

[0015] Figure 11 It is a table showing the sequence of commands that are being scheduled.

[0016] Figure 12 It is a diagrammatic illustration of the sequence of commands to be scheduled based on various representative implementation schemes.

[0017] Figure 13 It is a diagrammatic illustration of the sequence of commands to be scheduled based on various representative implementation schemes.

[0018] Figures 14 to 16 A schematic diagram of another scheduled command sequence according to various representative implementation schemes is shown. Detailed Implementation

[0019] The various devices and apparatuses described herein provide mechanisms for improving the performance of memory controllers based on the generation of speculative predecessor commands.

[0020] While this disclosure can have many different embodiments, specific embodiments are shown in the accompanying drawings and will be described in detail herein. It should be understood that the embodiments shown and described herein should be considered as examples providing the principles of this disclosure, and are not intended to limit this disclosure to the specific embodiments shown and described. In the following description, similar reference numerals are used to describe the same, similar, or corresponding parts in several views of the drawings. For simplicity and clarity, reference numerals may be repeated in the drawings to indicate corresponding or similar elements.

[0021] The implementation schemes shown and described herein relate to... Speculative predecessor commands are used in low-power double data rate dynamic random access memory (LPDDR DRAM) operating under the LPDDR5 or LPDDR5X standard protocols. However, the mechanism described herein is applicable to other types of memory operating under other protocols. Various implementations involve memory operations in which the memory controller issues a sequence of two or more commands to perform a requested operation—such as a read or write operation. When the command sequence can be “split” because it can be interleaved with other commands, the disclosed mechanism provides additional flexibility to the memory controller’s command scheduler. This, in turn, enables improved performance while still meeting the timing constraints of the memory device.

[0022] Figure 1 This is a simplified block diagram of a data processing system 100 according to various representative embodiments. The data processing system 100 includes a requesting device 102, a memory controller 104, and a memory device 106. The memory controller 104 provides an interface between the requesting device 102 (such as a processing unit or input / output (I / O) device) and the memory device 106. In practice, the data processing system may include one or more requesting devices 102, one or more memory controllers 104, and one or more memory devices 106. Typically, the requesting device 102 and the memory device 106 are fabricated on separate chips. Several protocols have been developed to facilitate communication with the memory device. For example, a standard protocol for accessing Dynamic Random Access Memory (DRAM) has been developed by the Solid State Technology Association of the Electronic Industries Alliance (EIA). (Published by the Joint Electronic Equipment Committee). These protocols specify the physical interface to the memory device, the command set used to control the memory device, and the data interface. Additionally, communication with the memory device must meet several timing constraints.

[0023] In many memory devices, memory cells are arranged as multiple two-dimensional arrays or memory banks 108. For example, in a DRAM device, reading data stored at an address requires a series of operations. These include selecting the memory bank, pre-charging the column lines, selecting a row based on the row address, sensing the row charge, and then reading the column based on the column address. These operations are performed by control circuitry 110 in response to commands from a memory controller. Specifically, the read command for the column address must follow one or more preceding commands.

[0024] The memory controller 104 includes a read and write data queue 112 for storing memory access requests received from the requesting device 102, and a command generator and scheduler 113 for generating memory access commands to serve the requests and scheduling the commands to be transmitted to the memory device 106 via the physical interface (PHY) 116. The read and write data queue 112 may also store information, such as the identity of the requesting device, so that read data can be returned to the requesting device.

[0025] A request signal can be sent from the requesting device 102 to the memory controller 104 on the request line "REQ". Data can be transmitted between the requesting device 102 and the memory controller 104 on the data bus "DATA" in sync with the clock signal on the line "CLK". Various interface architectures can be utilized.

[0026] In the illustrated implementation, physical interface 116 is coupled to a 7-bit wide command bus and address bus "CA," which transmits command signals synchronously with the command clock signal on clock line "CK." The command clock signal can be a differential signal. A write clock signal is transmitted on write clock line "WCK." Write data is transmitted to the memory device synchronously with the write clock signal on a 16-bit wide bidirectional data bus "DQ." Read data is also transmitted on the bidirectional data bus "DQ," but synchronously with the data strobe signal on line "RDQS." The data strobe signal is derived from the write clock on line WCK. For low-power applications, only the WCK clock signal is generated when data is to be transmitted; in this case, a short synchronization sequence can be transmitted before the data is transmitted along with a synchronization command. The synchronization command can be considered another preceding command.

[0027] The memory controller can optimize data throughput by selecting the order in which it processes memory access requests received from the requesting device. This process is called scheduling. Additionally, commands from the memory controller to the memory device can be scheduled to optimize data throughput within the timing constraints of the memory device.

[0028] LPDDR5 and LPDDR5X typically refer to the same protocol specification, but differ only in the supported speed levels and the non-substantive specification of the mainline memory configuration in 16-bank mode and bank group (BG) mode.

[0029] The LPDDR5 protocol specification defines a set of commands, such as: DES, NOP, PDE, ACT-1, ACT-2, PRE, REF, MWR, WR, WR32, RD, RD32, CAS, etc.

[0030] Commands are sent from the memory controller on the command bus synchronously with the command clock. Most commands last for one command clock cycle. However, the ACTIVATE procedure, used to open a memory bank and make rows available for reading and writing, requires two command clock cycles.

[0031] The ACTIVATE procedure is completed by following an ACT-1 command with an ACT-2 command. Therefore, in LPDDR5, the ACT-1 and ACT-2 commands are the precursor commands for read and write operations.

[0032] The LPDDR5 specification allows ACT-2 commands to be spaced exactly one clock cycle after an ACT-1 command, or optionally, multiple clock cycles in a so-called "split ACT". Typically, all read / write critical memory banks in the memory controller enable timing tracking of ACT-2 commands because both ACT-1 and ACT-2 are required to initiate a read or write operation. Furthermore, the scheduling of the ACTIVATE procedure relative to the previous command is relative to the issuance of the ACT-2 command. In this document, "tRRD" represents the minimum time between consecutive ACT-2 commands specified for the memory controller. tRRD must be greater than or equal to the corresponding minimum time specified for the memory device. In one implementation, tRRD may refer to multiple command clock cycles.

[0033] The memory controller can select a memory command in each command clock cycle. This selection can be designed to maximize performance, such as memory bus utilization. In some implementations, the selection of a command in a clock cycle can be independent of the selection made in the previous or next clock cycle. In this case, two or more independent selections can be made to select the predecessor command. For example, in LDDDR5, two independent selections (ACT-1 and ACT-2) can be made to complete the ACTIVATION procedure.

[0034] Figure 2 This is a schematic diagram illustrating the precursor command according to various representative implementations. The command is transmitted synchronously with the command clock signal 202. A double data rate is used, where the signal is sampled on both the rising and falling edges of the command clock, as indicated by the arrows in signal 202. In this example, the command bus and address bus CA are 7 bits wide. Signal 204 shows the signal on each of the seven wires (CA0 to CA6) of the CA bus. In the figure, vertical alignment indicates time alignment. Therefore, the signal in column 206 is sampled at the rising edge of the clock, and the signal in column 208 is sampled at the falling edge of the clock. At the rising edge of the clock, lines CA0 to CA2 indicate the command type.

[0035] The 14 signal bits transmitted on the CA bus 204 are represented as the pre-order command ACT1 (210). ACT1 indicates row address bits R14 to R17 on the rising edge and row address bits R11 to R13, and memory bank identifier bits BA0, BA1, BG0, and BG1 on the falling edge. The pre-order command ACT2 (212) indicates row address bits R7 to R10 on the rising edge and row address bits R0 to R6 on the falling edge. Therefore, both the ACT1 and ACT2 pre-order commands are required to specify the 18-bit row address (R0 to R17) and the memory bank. For read commands, the activation command together senses the charge level of the identified row.

[0036] The read command RD(214) specifies the 6-bit column address C0 to C5 and identifies the memory bank to be accessed. The AP bit is set if automatic precharge is to be performed. Setting the automatic precharge bit in read and write commands indicates to the memory device that the read or write command is the last access to the currently open row. The memory device then closes or precharges the currently accessed page. Subsequent accesses to the same memory bank are faster because the controller does not need to precharge the memory bank before activating the next row to be accessed.

[0037] The synchronization command CAS(216) specifies the type of clock synchronization to be performed. WS_WR bit synchronization is used for write operations, WS_RD bit synchronization is used for read operations, and WS_FS bit synchronization is used for either read or write operations.

[0038] The write command RD(218) specifies the 6-bit column address C0 to C5 and identifies the memory bank to be accessed (BA0, BA1, BG0, BG1). If automatic precharge is requested, the AP bit is set.

[0039] Other precursor commands include "PRE", which requests that the specified memory bank be precharged in preparation for access.

[0040] Generally, timing constraints are associated with various memory commands. These memory commands include: ACT2, precharge, auto-precharge read, auto-precharge write, refresh, power-down exit, and self-refresh exit. The memory controller may maintain one or more counters and multiple comparators to ensure that timing constraints are met. Different memory devices may have different timing constraints.

[0041] Figure 3This is a schematic diagram of the scheduled command sequence. The command clock CK is shown as 202, where time flows from left to right. The command clock segment is represented as "tCK" (302). In the example command sequence 304, ACT1 is followed by ACT2. To satisfy the timing constraints imposed by the memory device, the subsequent ACT2 command cannot be transmitted until the time period tRRD (306) has elapsed. Therefore, in time period 308, if the corresponding ACT1 has been selected during this period, the command scheduler is allowed to select another ACT2 command.

[0042] Figure 4 This is a diagrammatic illustration of the scheduled command sequence based on various representative implementation schemes. (As shown above...) Figure 3 As described above, if the corresponding ACT1 has been selected during this period, the subsequent ACT2 command can be selected during time period 308. However, according to one aspect of this disclosure, selection of the ACT1 command is permitted after time period 402 has elapsed. Therefore, selection of the ACT1 command is permitted during time period 404. In one embodiment, time period 404 begins multiple (N) command clock cycles prior to time period 308. Therefore, time period 404 begins at a time tRRD-N×tCK after the previous ACT2 command has been selected. Allowing ACT1 to be transmitted earlier (i.e., prepared in advance or ahead of time) increases the flexibility of the command scheduler in selecting commands. For example, the ACT2 command can immediately follow a read or write command.

[0043] Figure 5 This is a block diagram of a memory controller 500 according to various representative embodiments. The memory controller 500 couples a signal 502 between the memory device and the physical interface 112. The memory controller 500 also includes a host interface 504 that couples the memory controller to the requesting host device. A memory access request 506 is buffering read and write queues 116, while a configuration control signal 508 is coupled to configuration control logic 510. Data 512 is transferred between the requesting host device and the memory controller's data buffer 514.

[0044] The timing control of the physical interface 112 and the timer / counter 516 is provided by one or more clocks 518. When the ACT2 command is selected by the command scheduler 114, the timer / counter 518 is reset by signal 520 and measures the elapsed time thereafter. In one embodiment, the timer / counter 518 sets a first logic value "en1" to active after a first time tRRD-N×tCK has elapsed, and sets a second logic value "en2" to active after a second time tRRD has elapsed. Logic values ​​en1 and en2 can be indicated by setting the values ​​of registers 522 and 524, respectively. Alternatively, logic values ​​en1 and en2 can be indicated by activating a signal coupled to the command scheduler 114.

[0045] The en1 indicator can be active for a specified number of clock cycles (or time periods) before the en2 indicator takes effect. When en1 takes effect, the command scheduler can selectively select and issue the ACT1 command. Furthermore, it is not necessary to issue the ACT2 command one clock cycle after issuing ACT1. In this respect, when the ACT1 command is issued two or more cycles before the ACT2 command, the ACTIVATE command is "split," and the ACT1 command is referred to as "specular." In other words, an ACT1 command issued before the tRRD expires is referred to as "early." Any clock cycles between the ACT1 and ACT2 commands can be optimally utilized to select high-priority commands, such as read (RD) or write (WR) commands. In many cases, if RD or WR is not optimally selected on these specific clock cycles, the effective bandwidth is significantly lower than the potential maximum theoretical bandwidth.

[0046] Generally, when tRRD = M × tCK, ACT1 can be issued N clock cycles before ACT2 is issued, where N is less than M.

[0047] Figure 6 This is a block diagram of a timer / counter 516 according to various representative embodiments. An input clock 602 is supplied to an edge detector 604, which in turn updates a counter 606. The counter 606 is enabled and reset by control logic circuitry 608. A reset signal 520 from a command scheduler indicates when a reset is required. A comparator 612 compares the value of counter 606 with a first value stored in a comparison register 614 and updates the en1 register 522 upon a match. In an alternative embodiment, the signal is enabled instead of setting the register value. A comparator 616 compares the value of counter 606 with a second value stored in a comparison register 618 and updates the en2 register 524 upon a match. Again, in an alternative embodiment, the signal is enabled instead of setting the register value. The first and second comparison values ​​can be set by a configuration signal 620. For example, these values ​​can be configured by the designer or user software.

[0048] exist Figure 6 In the example shown, there are two comparison values ​​corresponding to the predecessor commands ACT1 and ACT2. Generally, any number of predecessor commands with a corresponding number of comparison values ​​and comparators can exist. Other implementations will be apparent to those skilled in the art. For example, a separate counter can be used for each time period. The counter can count upwards from zero starting from the comparison value, or count downwards from the comparison value to zero.

[0049] Figure 7This is a flowchart of a timer / counter operation method 700 according to various representative embodiments. At block 702, the timer / counter is configured by setting a first comparison value and a second comparison value. At block 704, the en1 and en2 registers are cleared. In an alternative embodiment, the en1 and en2 signals are invalidated. At block 706, the counter value is reset in response to a reset signal from the command scheduler. For example, the reset signal may indicate the selection of the ACT2 predecessor command. At block 708, the counter value "C" is updated in response to a clock edge. For example, this could be the edge of the command clock. If the counter value C equals the first comparison value, as depicted from the affirmative branch of decision block 710, the en1 register is set at block 712 (or the en1 signal is active). If the counter value C equals the second comparison value, as depicted from the affirmative branch of decision block 714, the en2 register is set at block 716 (or the en2 signal is active). The method then waits at decision box 718 until the ACT2 command has been transmitted (e.g., signaled by the command scheduler), as depicted by the positive branch from decision box 718. The en2 register is then cleared at box 720, and the flow returns to box 706. If the counter value has not yet reached the second comparison value, as depicted by the negative branch from decision box 714, the flow continues to decision box 722. If the ACT1 command has been transmitted but the en1 register has not yet been cleared, the en1 register is cleared at box 724, and the flow returns to box 708. If the ACT1 command has not been transmitted or the en1 register has not been set, as depicted by the negative branch from decision box 722, the flow returns to box 708.

[0050] Figure 8This is a flowchart of a command scheduler method 800 according to various representative implementations. At block 802, a timer / counter is signaled to reset the values ​​of en1 and en2. These values ​​can be signaled values ​​or stored values. When en1 is active, as depicted from the affirmative branch of decision block 804, the scheduler is configured at block 806 to allow selection of the ACT1 command. If en2 is active and the ACT1 command has been transmitted, as depicted from the affirmative branch of decision block 808, the scheduler is configured at block 810 to allow selection of the ACT2 command. At block 812, the scheduler selects the next command to be transmitted to the memory device. If the ACT2 command has been transmitted, as depicted from the affirmative branch of decision block 814, the flow returns to block 802, and a timer / counter is signaled to indicate that a new measurement cycle should begin. If en1 is inactive, as depicted from the negative branch of decision block 804, the flow continues to block 816. If ACT1 has been transmitted (i.e., en1 is invalid), the flow continues to decision block 808. Otherwise, the process continues to box 812. If en2 is not active or ACT1 has not been transmitted, as depicted in the negative branch from decision box 808, the process continues to box 812. In this way, the scheduling of memory commands is controlled by the values ​​of en1 and en2, which in turn are controlled by the timer / counter circuitry.

[0051] In one implementation, commands for each bank are stored in a first-in, first-out (FIFO) buffer. In this case, ACT1 precedes ACT2 in the FIFO, and it is not necessary to check whether ACT1 has been transmitted at boxes 808 and 816 because ACT2 cannot be transmitted before ACT1.

[0052] Figure 9This is a block diagram illustrating components of a memory controller according to various representative embodiments. Command generator 902 receives memory access requests from request queue 118 and generates memory access commands based on these requests. Specifically, memory addresses are decoded to identify the corresponding bank number, row address, and column address in the memory. Generator commands are buffered in FIFO command buffers 904. Although only six FIFO command buffers are shown in the figures, the number of buffers should match the number of banks in the memory. For example, for a memory with 16 banks, there would be 16 FIFO buffers. Banks can be accessed in parallel within the memory device. However, the command bus and data bus can only transmit for one bank at a time. In each cycle of the command clock, command selector 906 selects a command from one of the FIFO command buffers and transmits it to the PHY physical interface 112. The command is transmitted to the memory device via connection 914. Command selector 906 is subject to several constraints. First, in each block of eight commands, read and write commands can only be transmitted in cycles 0 and 2. Therefore, a cycle counter 908 is provided. Secondly, the time between certain preceding commands (such as ACT2 to ACT1 and ACT2-ACT2) is constrained to at least a minimum value. Appropriate timing information is provided by the link timer 910. Thirdly, the time between an ACT2 command and a read or write command to the same memory bank is constrained to at least a minimum value. Appropriate timing information is provided by the per-memory timer 912. As described above, one aspect of this disclosure provides an ACT2 to ACT1 timer that increases the number of cycles for which ACT1 commands can be selected. For example, this increased flexibility allows the memory controller to better utilize the data bus.

[0053] Figure 10This is a table showing the scheduled command sequences according to various representative implementations. Column 1002 shows the selected memory commands for multiple clock cycles. Column 1004 shows the memory bank specified in the command. Column 1006 shows the value of the en1 indicator (1 = active, 0 = inactive). Column 1008 shows the value of the en2 indicator (1 = active, 0 = inactive). In this example, the minimum time tRRD between ACT2 commands is set to four command clock cycles. That is, tRRD = 4 × tCK, as indicated by arrow 1010. In addition, the ACT1 enable indicator en1 is active 3 cycles before en2 is active, as indicated by arrow 1012. In the example shown, the selection of ACT1 is enabled in cycle -2 (as indicated by en1 = 1), and ACT1 is selected in that cycle. ACT2 is not enabled until cycle 1 (i.e., after three cycles). Therefore, ACT1 is advanced. This allows the command scheduler to select a read command for memory bank 0 in cycle 0 and a read command for memory bank 1 in cycle 2. Similarly, since the ACT2 command is not allowed until cycle 9, the ACT1 command in cycle 7 is advanced.

[0054] exist Figure 10 In the example shown, the minimum time between activating a row and reading a row is 15 cycles. Therefore, the row in memory bank 2 activated at cycle 1 cannot be read until cycle 16. An append read is performed on the row in memory bank 2 at cycle 18.

[0055] For comparison, Figure 11 This is a table showing the sequence of scheduled commands for the same command set when advance or speculative selection of ACT1 commands is not permitted. For example... Figure 10 As shown, ACT2 is not enabled until cycle 1. Therefore, ACT1 is not selected until cycle 0. However, to maximize throughput, a pending read command (RD) is selected in cycle 0. ACT1 for memory bank 2 is selected in cycle 1. To maximize throughput, a pending read command (RD) is selected in cycle 2, thus delaying the ACT2 command for memory bank 2 until cycle 3. Since the minimum time between activating a row and reading a row is 15 cycles, rows of memory bank 2 activated in cycle 3 cannot be read until cycle 18. Therefore, additional reads of rows in memory bank 2 are delayed until cycle 24. Therefore, with Figure 10 Compared to the command sequence shown, the read latency increases. Additionally, in Figure 10 In this context, all cycles (0, 2, 8, 10, 16, and 18) available for reading commands are utilized, while... Figure 11 In this context, time slot 16 is used for the ACT2 command. Therefore, Figure 10 The command sequence in the code makes better use of the data bus.

[0056] Figure 12 It is a diagrammatic illustration of the sequence of commands to be scheduled based on various representative implementation schemes. Figure 12 Command clock signal 1202 and command sequence 1204 are shown. In this example, the minimum time tRRD between ACT2 commands is set to four command clock cycles. That is, tRRD = 4 × tCK. Additionally, the ACT1 enable indicator en1 is set to tRRD - 2 × tCK = 2 × tCK. In this example, tRRD expires before clock cycle 3, as indicated by the en12 indicator going high. This allows the command scheduler to select the ACT2 command for cycle 3. The ACT1 command is selected two cycles before cycle 1. Indicator en1 goes high two cycles before indicator en2 goes high, indicating that the ACT1 command can be selected. When ACT1 is selected, indicator en1 goes low again. In previous systems, the ACT1 command could not be selected until cycle 2, as indicated by command 1206. According to the memory device protocol, read and write commands can only be transmitted in cycle n, where n modulo 8 equals zero or two. Therefore, read commands can be transmitted in cycles 0, 2, 8, and 10 in the figures. In the example shown, the first two read commands are transmitted in cycles 0 and 2. In the previous system, if the ACT1 command were placed in cycle 2, the read command would be delayed by a certain number of cycles. Conversely, if the read (RD) command is placed in cycle 2, the ACT1 and ACT2 commands would be delayed—thus delaying the read commands associated with them. This allows the ACT1 command to be transmitted earlier or "speculatedly," resulting in reduced read latency. Similarly, the third ACT1 command in sequence 1204 is transmitted earlier (in cycle 9), freeing up a cycle for the appended read (RD) command. The ACT1 and ACT2 commands are "split" and spaced apart by the read (RD) command.

[0057] Figure 13 It is a diagrammatic illustration of the sequence of commands to be scheduled based on various representative implementation schemes. Figure 13Command clock signal 1302 and command sequence 1304 are shown. In this example, the minimum time tRRD between ACT2 commands is again set to four command clock cycles, and the ACT1 indicator en1 becomes active after the ACT2 command at time tRRD - 2 × tCK = 2 × tCK. In this example, the ACT1 command selected in cycle 1 is either advanced or speculative, as it is transmitted one cycle earlier. Without speculative selection of the ACT1 command, the ACT1 command would be transmitted in cycle 2, as indicated by 1306. Note that the en1 indicator becomes active after cycle 4 and remains active until after the ACT1 command is selected in cycle 9. Then, the en1 indicator is deactivated to prevent the command scheduler from selecting the ACT1 command for a different memory bank.

[0058] Figures 14 to 16 A schematic diagram of another scheduled command sequence according to various representative implementation schemes is shown.

[0059] exist Figure 14 In this process, the ACT2 command is enabled in cycles 1 and 9. The ACT1 command in cycles -1 and 7 is advanced by N=2, thereby freeing up the cycles used for the read command (RD) in cycles 0, 2, 8 and 10.

[0060] exist Figure 15 In cycle 1, the ACT2 command is enabled. The ACT1 command in cycle 2 is advanced by N=3, and the ACT2 command in cycle 3 is delayed by 2 cycles. This allows synchronization (CAS) commands to be transmitted in cycle 1 and cycle 2, and write (WR) commands to be transmitted in cycle 0 and cycle 2.

[0061] exist Figure 16 In this configuration, the ACT2 command is enabled in cycle 0. The ACT1 command in cycle 2 is advanced by N=2, and the ACT2 command in cycle 3 is delayed by 3 cycles. Similarly, this allows the transmission of synchronization (CAS) commands in cycles 1 and 2, and the transmission of write (WR) commands in cycles 0 and 2.

[0062] In this way, the ACT1 command can be performed earlier, thus improving the efficiency of memory access.

[0063] The above description discloses a method for accessing memory by a memory controller. The method includes: indicating the expiration of a first time period and indicating the expiration of a second time period. The first time period is shorter than the second time period by a specified amount, and the second time period is greater than or equal to a specified minimum time between a previous memory access command and a secondary predecessor memory access command of a memory access protocol, the memory access protocol including a primary predecessor memory access command and a secondary predecessor memory access command. When the first time period has expired, a command scheduler of the memory controller is enabled to allow selection of a primary predecessor memory access command, and when the second time period has expired, the command scheduler is enabled to allow selection of a secondary predecessor memory access command. The command scheduler selects a memory access command and transmits it to the memory. The first time period and the second time period begin when a previous predecessor memory access command has been transmitted to the memory.

[0064] In one embodiment, indicating the expiration of the first time period includes setting a first register, and indicating the expiration of the second time period includes setting a second register. The method includes clearing the first register and the second register when a secondary predecessor memory access command has been transmitted to the memory.

[0065] In one implementation, the memory controller buffers memory access requests received from the host processor and generates memory access commands based on the access requests.

[0066] For example, the primary predecessor memory access command and the secondary predecessor memory access command can specify the memory bank and the row address to be activated in the memory bank.

[0067] Enabling the command scheduler to allow the selection of the secondary predecessor memory access command may also depend on one or more additional memory operations.

[0068] Following the auxiliary predecessor memory access command, a read command, write command, synchronization command and read command, synchronization command and write command, or a combination thereof, of the memory access protocol can be selected.

[0069] The primary predecessor memory access command and the secondary predecessor memory access command may be separated by read commands, write commands, synchronization commands and read commands, synchronization commands and write commands, or combinations thereof, of the memory access protocol.

[0070] In one embodiment, indicating the expiration of the first time period and the second time period includes: updating a counter value in each cycle of the memory controller clock; comparing the counter value with a first value; indicating the expiration of the first time period when the counter value equals the first value; comparing the counter value with a second value; and indicating the expiration of the second time period when the counter value equals the second value.

[0071] The above description also discloses a memory controller including a command scheduler, a timer, and an interface configured to send memory access commands to a memory. The command scheduler is configured to select a memory access command associated with a memory access request received via a host interface. The timer is configured to indicate to the command scheduler the expiration of a first time period and the expiration of a second time period. The first time period is shorter than the second time period by a specified amount, and the second time period is greater than or equal to a minimum time between a previous memory access command and a secondary predecessor memory access command in a memory access protocol having a primary predecessor memory access command and a secondary predecessor memory access command. The first time period and the second time period begin when the previous memory access command is transmitted to the memory. When the first time period has expired, the command scheduler allows selection of the primary predecessor memory access command, and when the second time period has expired and the corresponding primary predecessor memory access command has been transmitted to the memory, the command scheduler allows selection of the secondary predecessor memory access command.

[0072] In one implementation, the interface includes a physical interface to a dynamic random access memory (DRAM) device, a static dynamic random access memory (SDRAM) device, a double data rate static dynamic random access memory (DDR SDRAM) device, or a low power double data rate static dynamic random access memory (LPDDR SDRAM) device, wherein the memory access protocol is a protocol for DRAM, SDRAM, DDR SDRAM, or LPDDR SDRAM devices.

[0073] In one implementation, the command scheduler includes a memory access command generator configured to generate one or more memory access commands based on memory access requests for storage.

[0074] The memory controller may also include a first register and a second register coupled to the timer. The content of the first register is set to a first value (e.g., 1) when the first time period expires, and is set to a second value (e.g., 0) when the auxiliary predecessor memory access command has been delivered to the memory. The content of the second register is set to a third value (e.g., 1) when the second time period expires, and is set to a fourth value (e.g., 0) when the auxiliary predecessor memory access command has been delivered to the memory.

[0075] In one implementation, the primary predecessor memory access command and the secondary predecessor memory access command specify the memory bank and the row address to be activated in the memory bank, and the command scheduler is further configured to: select a precharge command for the row address in the memory bank, and disable the selection of the secondary predecessor memory access command until the precharge command has been transmitted.

[0076] The timer may include: a counter configured to update a counter value based on a clock of the memory controller; a first comparator configured to compare the counter value with a first value and indicate the expiration of a first time period when the counter value equals the first value; and a second comparator configured to compare the counter value with a second value and indicate the expiration of a second time period when the counter value equals the second value. Alternatively, the timer may include: a first counter configured to update a first counter value based on a clock of the memory controller; a first comparator configured to compare the first counter value with a first value and indicate the expiration of a first time period when the first counter value equals the first value; a second counter configured to update a second counter value based on a clock of the memory controller; and a second comparator configured to compare the second counter value with a second value and indicate the expiration of a second time period when the second counter value equals the second value.

[0077] Embodiments of this disclosure provide a non-transitory computer-readable medium for storing computer-readable code for manufacturing a memory controller. The memory controller includes a command scheduler, a timer, and a physical interface. The command scheduler is configured to select a memory access command associated with a memory access request received via a host interface. The timer is configured to indicate to the command scheduler the expiration of a first time period and the expiration of a second time period. The physical interface is configured to send the memory access command to the memory. The first time period is shorter than the second time period by a specified amount, and the second time period is greater than or equal to a minimum time between a previous memory access command and a secondary predecessor memory access command in a memory access protocol having a primary predecessor memory access command and a secondary predecessor memory access command. The first time period and the second time period begin when the previous memory access command is transmitted to the memory. When the first time period has expired, the command scheduler allows selection of the primary predecessor memory access command, and when the second time period has expired and the corresponding primary predecessor memory access command has been transmitted to the memory, the command scheduler allows selection of the secondary predecessor memory access command.

[0078] The timer may include: a counter configured to update a counter value based on a clock of the memory controller; a first comparator configured to compare the counter value with a first value and indicate the expiration of a first time period when the counter value equals the first value; and a second comparator configured to compare the counter value with a second value and indicate the expiration of a second time period when the counter value equals the second value.

[0079] In this document, relational terms such as first and second, top and bottom, etc., are used only to distinguish one entity or action from another entity or action, and do not necessarily require or imply any actual such relationship or order between such entities or actions. The terms “comprising,” “including,” “containing,” “having,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but may also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element preceded by “comprising…one” does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes that element, unless further limited.

[0080] Throughout this document, the terms “an embodiment,” “certain embodiments,” “implementation,” “specific implementation,” “aspect,” or similar terms refer to a particular feature, structure, or characteristic described in connection with that embodiment, which is included in at least one embodiment of this disclosure. Therefore, the appearance of such phrases in various places throughout this specification does not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics can be combined in any suitable manner without limitation in one or more embodiments.

[0081] As used herein, the term “or” will be interpreted inclusively as any one or any combination. Thus, “A, B, or C” means “any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition will only occur if the combination of elements, functions, steps, or actions is inherently mutually exclusive in some way.

[0082] As used herein, when applied to a component, the term "configured to" means that the component can be designed or constructed to perform a specified function, or has the necessary structure to enable it to be reconfigured or adapted to perform that function.

[0083] Numerous details are set forth to provide an understanding of the embodiments described herein. These embodiments may be practiced without these details. In other instances, well-known methods, procedures, and components have not been described in detail to avoid obscuring the embodiments described. This disclosure should not be construed as limiting the scope to the embodiments described herein.

[0084] Those skilled in the art will recognize that this disclosure has been described with the aid of examples. This disclosure may be implemented using hardware component equivalents such as dedicated hardware and / or dedicated processors, which are equivalents of the disclosure as described and claimed. Similarly, dedicated processors and / or dedicated hardwired logic may be used to construct alternative equivalent embodiments of this disclosure.

[0085] Specialized or reconfigurable hardware components used to implement the disclosed mechanisms can be described, for example, by instructions in a hardware description language (HDL), such as VHDL, Verilog, or RTL (Register Transfer Language), or by a netlist of components and connectivity. Instructions can be at the functional or logical level, or a combination thereof. Instructions or netlists can be input into automated design or manufacturing processes (sometimes called high-level synthesis), which interpret the instructions and create digital hardware that implements the described functions or logic.

[0086] HDL instructions or netlists may be stored on non-transitory computer-readable media, such as electrically erasable programmable read-only memory (EEPROM); non-volatile memory (NVM); mass storage devices, such as hard disk drives, floppy disk drives, optical disk drives; and, without departing from this disclosure, optical storage elements, magnetic storage elements, magneto-optical storage elements, flash memory, magnetic core memory, and / or other equivalent storage technologies. Such alternative storage devices should be considered equivalents.

[0087] The concepts described herein may be embodied in computer-readable code used to create devices embodying the described concepts. For example, the computer-readable code may be used at one or more stages of the semiconductor design and fabrication process, including the electronic design automation (EDA) stage, to create integrated circuits that include devices embodying these concepts. The aforementioned computer-readable code may additionally or alternatively enable the definition, modeling, simulation, verification, and / or testing of devices embodying the concepts described herein.

[0088] For example, computer-readable code used to create a device embodying the concepts described herein may be embodied in code that defines the hardware description language (HDL) representation of these concepts. For instance, the code may define a register-transfer level (RTL) abstraction of one or more logic circuits for defining a device embodying these concepts. The code may define an HDL representation of one or more logic circuits embodying the device using Verilog, SystemVerilog, Chisel, or VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language) and intermediate representations such as FIRRTL. Computer-readable code may provide definitions of the concepts or other behavioral representations of the concepts embodying the concepts using system-level modeling languages ​​such as SystemC and SystemVerilog, which can be interpreted by a computer to enable simulation, functional and / or formal verification and testing of the concepts.

[0089] Additionally or alternatively, computer-readable code may define a low-level description of an integrated circuit component embodying the concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. Other computer-readable representations of one or more netlists or integrated circuit components may be generated by applying one or more logic synthesis processes to the RTL representation to generate a definition for fabricating a device embodying the invention. Alternatively or additionally, one or more logic synthesis processes may be generated from computer-readable code to be loaded into a field-programmable gate array (FPGA) to configure the FPGA as a bitstream embodying the concepts. The FPGA may be deployed for the purpose of verifying and testing the concepts prior to fabrication of an integrated circuit, or the FPGA may be deployed directly in a product.

[0090] Computer-readable code may include a mixture of code representations used for making a device, such as one or more of RTL representations, netlist representations, or other computer-readable definitions used in the semiconductor design and fabrication process for making a device embodying the present invention. Alternatively or additionally, the concept may be defined in a combination of computer-readable definitions used in the semiconductor design and fabrication process for making a device and computer-readable code defining instructions that will be executed by the defined device once it is manufactured.

[0091] Such computer-readable code can be contained in any known transient computer-readable medium (such as wired or wireless transmission of code over a network) or non-transitory computer-readable medium such as semiconductors, magnetic disks, or optical disks. Integrated circuits made using computer-readable code may include components such as one or more of the following: a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or other components that embody the concept individually or collectively.

[0092] The various embodiments described herein are implemented using dedicated hardware, configurable hardware, or a programmable processor that executes programming instructions, which are broadly described in flowchart form and can be stored on any suitable electronic storage medium or transmitted via any suitable electronic communication medium. Combinations of these elements may be used. Those skilled in the art will understand that the above processes and mechanisms can be implemented in any number of variations without departing from this disclosure. For example, the order of certain operations performed can typically be changed, additional operations can be added, or operations can be deleted without departing from this disclosure. Such variations are conceivable and considered equivalent.

[0093] Various representative embodiments described in detail herein are given by way of example rather than limitation. Those skilled in the art will understand that various changes can be made to the form and details of the described embodiments to obtain equivalent embodiments that remain within the scope of the appended claims.

Claims

1. A method for accessing memory by a memory controller, the method comprising: Indicates the expiration of the first time period; Indicates the expiration of the second time period, in which: The first time period is shorter than the second time period by a specified amount; and The second time period is greater than or equal to the specified minimum time between the previous memory access command and the secondary predecessor memory access command of the memory access protocol. The memory access protocol has multiple memory access commands, including primary predecessor memory access commands and secondary predecessor memory access commands; When the first time period has expired, the command scheduler of the memory controller is enabled to allow the selection of the primary predecessor memory access command; When the second time period has expired and the corresponding primary predecessor memory access command has been transmitted to the memory, the command scheduler is enabled to allow the selection of the secondary predecessor memory access command. The command scheduler selects the memory access command; Send the selected memory access command to the memory; and The first time period and the second time period begin when the previous memory access command has been transmitted to the memory.

2. The method of claim 1, wherein indicating the expiration of the first time period includes setting a first register, and indicating the expiration of the second time period includes setting a second register, the method further comprising: When an auxiliary predecessor memory access command has been transmitted to the memory, the first register and the second register are cleared.

3. The method according to claim 1, further comprising the memory controller performing the following actions: Buffer memory access requests received from the host processor; and Generate a memory access command based on the access request.

4. The method according to claim 1, wherein the primary predecessor memory access command and the secondary predecessor memory access command specify the memory bank and the row address to be activated in the memory bank.

5. The method of claim 1, wherein the second time period depends on a memory device time constraint associated with at least one of the following: Previous auxiliary predecessor memory access command; The memory access protocol's "precharge" command, The memory access protocol's "automatic precharge read" command, The memory access protocol's "automatic precharge write" command, The "refresh" command of the memory access protocol, The memory access protocol's "power-off exit" command, or The memory access protocol's "self-refresh exit" command.

6. The method of claim 1, wherein the selected memory access command is the secondary predecessor memory access command, and wherein after selecting the secondary predecessor memory access command, at least one of the following is selected: The read command of the memory access protocol; The write command of the memory access protocol; The memory access protocol's synchronization commands and read commands; or The memory access protocol includes synchronization and write commands.

7. The method of claim 1, wherein the primary predecessor memory access command and the secondary predecessor memory access command are spaced apart by at least one of the following: The read command of the memory access protocol; The write command of the memory access protocol; The memory access protocol's synchronization commands and read commands; or The memory access protocol includes synchronization and write commands.

8. The method of claim 1, wherein indicating the expiration of the first time period and the second time period comprises: Update the counter value in each cycle of the memory controller clock; Compare the counter value with the first value; When the counter value equals the first value, it indicates the expiration of the first time period; Compare the counter value with the second value; as well as When the counter value equals the second value, it indicates the expiration of the second time period.

9. A memory controller for a memory, the memory controller comprising: A command scheduler configured to select a memory access command associated with a memory access request received via a host interface; A timer, configured to indicate to the command scheduler the expiration of a first time period and the expiration of a second time period, wherein: The first time period is shorter than the second time period by a specified amount; The second time period is greater than or equal to the minimum time between a previous memory access command and a secondary predecessor memory access command in the memory access protocol, which includes a primary predecessor memory access command and a secondary predecessor memory access command; and The first time period and the second time period begin when the previous memory access command is transmitted to the memory; and An interface configured to send the memory access command to the memory; When the first time period has expired, the command scheduler allows the selection of a primary predecessor memory access command, and when the second time period has expired and the corresponding primary predecessor memory access command has been transmitted to the memory, the command scheduler allows the selection of a secondary predecessor memory access command.

10. The memory controller of claim 9, wherein the interface includes a physical interface to a dynamic random access memory (DRAM) device, a static dynamic random access memory (SDRAM) device, a double data rate static dynamic random access memory (DDR SDRAM) device, or a low power double data rate static dynamic random access memory (LPDDR SDRAM) device, and wherein the memory access protocol is a protocol for DRAM, SDRAM, DDR SDRAM, or LPDDR SDRAM devices.

11. The memory controller of claim 9, wherein the command scheduler includes a memory access command generator configured to generate one or more memory access commands based on memory access requests from the storage.

12. The memory controller according to claim 9, further comprising: A first register, coupled to the timer, is set to a first value when the first time period expires, and to a second value when the auxiliary predecessor memory access command has been transmitted to the memory; and A second register, coupled to the timer, is set to a third value when the second time period expires, and to a fourth value when the auxiliary predecessor memory access command has been transmitted to the memory.

13. The memory controller of claim 9, wherein the primary predecessor memory access command and the secondary predecessor memory access command specify the memory bank and the row address to be activated in the memory bank.

14. The memory controller of claim 9, wherein the second time period further depends on a memory device time constraint associated with at least one of the following: Previous auxiliary predecessor memory access commands, The memory access protocol's "precharge" command, The memory access protocol's "automatic precharge read" command, The memory access protocol's "automatic precharge write" command, The "refresh" command of the memory access protocol, The memory access protocol's "power-off exit" command, or The memory access protocol's "self-refresh exit" command.

15. The memory controller of claim 9, wherein the command scheduler is configured to select the secondary predecessor memory access command, and after selecting the secondary predecessor memory command, select at least one of the following: The read command of the memory access protocol; The write command of the memory access protocol; The memory access protocol's synchronization commands and read commands; or The memory access protocol includes synchronization and write commands.

16. The memory controller of claim 9, wherein the command scheduler is configured to: Select the primary predecessor memory access command; After selecting the primary predecessor memory command, at least one of the following is selected as the access sequence: The read command of the memory access protocol; The write command of the memory access protocol; The memory access protocol's synchronization commands and read commands; or The memory access protocol's synchronization commands and write commands; and After selecting the access sequence, select the auxiliary predecessor memory command.

17. The memory controller of claim 9, wherein the timer comprises: A counter, configured to update its value based on the clock of the memory controller; A first comparator is configured to compare the counter value with a first value, and when the counter value equals the first value, indicate the expiration of the first time period. and A second comparator is configured to compare the counter value with a second value, and when the counter value equals the second value, indicate the expiration of the second time period.

18. The memory controller of claim 9, wherein the timer comprises: A first counter, configured to update its value based on the clock of the memory controller; A first comparator is configured to compare a first counter value with a first value, and when the first counter value equals the first value, indicate the expiration of the first time period. A second counter, configured to update its value based on the clock of the memory controller; and A second comparator is configured to compare the second counter value with a second value, and when the second counter value equals the second value, indicate the expiration of the second time period.

19. A non-transitory computer-readable medium for storing computer-readable code for manufacturing a memory controller, the memory controller comprising: A command scheduler configured to select a memory access command associated with a memory access request received via a host interface; A timer, configured to indicate to the command scheduler the expiration of a first time period and the expiration of a second time period, wherein: The first time period is shorter than the second time period by a specified amount; The second time period is greater than or equal to the minimum time between a previous memory access command and a secondary predecessor memory access command in the memory access protocol, which includes a primary predecessor memory access command and a secondary predecessor memory access command; and The first time period and the second time period begin when the previous memory access command is transmitted to the memory; and A physical interface configured to send the memory access command to the memory. When the first time period has expired, the command scheduler allows the selection of a primary predecessor memory access command, and when the second time period has expired and the corresponding primary predecessor memory access command has been transmitted to the memory, the command scheduler allows the selection of a secondary predecessor memory access command.

20. The non-transitory computer-readable medium of claim 19, wherein the timer comprises: A counter, configured to update its value based on the clock of the memory controller; A first comparator is configured to compare the counter value with a first value, and when the counter value equals the first value, indicate the expiration of the first time period. and A second comparator is configured to compare the counter value with a second value, and when the counter value equals the second value, indicate the expiration of the second time period.

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