PCIe adapter plate, test apparatus, and test method
By expanding the PCIe signal through a PCIe adapter board, the problem of the limited number of PCIe interfaces is solved, the testing efficiency is improved and the cost is reduced, and more efficient hard drive testing is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI LONGSYS DIGITAL TECH CO LTD
- Filing Date
- 2024-05-15
- Publication Date
- 2026-06-26
AI Technical Summary
In the prior art, the testing of solid-state drives equipped with high-speed serial computer expansion bus standard interfaces is limited by the number of PCIe interfaces configured in the test equipment, resulting in low testing efficiency.
By using a PCIe adapter board, multiple signal selectors, clock buffer chips, switching chips, and expansion chips are used to expand the differential pair signals of PCIe signals, forming multiple PCIe signals. This supports the connection of more hard drives under test, enabling testing using consumer-grade PCs, reducing costs, and avoiding PCIe channel contention.
It improves hard drive testing efficiency, reduces testing costs, and effectively expands the number of PCIe interfaces through time-sharing multiplexing, avoiding competition among multiple PCIe channels.
Smart Images
Figure CN121009042B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of hard disk testing technology, specifically to a PCIe adapter board, testing equipment, and testing method. Background Technology
[0002] Testing solid-state drives (SSDs) equipped with Peripheral Component Interconnect Express (PCIe) interfaces suffers from low efficiency due to limitations in the number of PCIe interfaces available on the testing equipment. PCIe interfaces are used to transmit PCIe signals, which include differential pairs. Expanding these differential pairs is crucial for extending the PCIe interface. Summary of the Invention
[0003] In view of this, this application provides a PCIe adapter board, a test device, and a test method, aiming to solve the problem of how to expand the differential pair signals included in the PCIe signal.
[0004] A first aspect of this application provides a PCIe adapter board, which includes a first signal connector, a second signal connector, a controller, and multiple signal selectors. Each signal selector includes a multiplexer and a demultiplexer. The first signal connector is electrically connected to a test machine and is used to receive PCIe signals from the test machine. Multiple signal selectors are connected in series between the first and second signal connectors and are used to receive PCIe signals from the first signal connector and to expand a single differential pair signal contained in the PCIe signal into multiple differential pair signals through the multiplexer and demultiplexer. The second signal connector is used to receive the multiple differential pair signals, which are used to form corresponding sets of PCIe signals. The controller is electrically connected to the first signal connector, the second signal connector, and the multiple signal selectors and is used to receive instructions from the test machine and process the PCIe signals according to the instructions.
[0005] In this embodiment, the PCIe adapter board uses multiple signal selectors to form a multi-level signal expansion, expanding a single differential pair signal within the PCIe signal into multiple differential pairs. These multiple differential pairs are used to form multiple sets of PCIe signals, each corresponding to multiple drive bays. This allows for the connection of more hard drives under test, thereby improving testing efficiency. Furthermore, a consumer-grade PC can be used as the testing machine, resulting in lower testing costs. The testing machine controls the PCIe adapter board to perform PCIe channel selection, expansion, and merging, thus employing a time-division multiplexing approach to test multiple hard drives under test, which helps avoid contention among multiple PCIe channels.
[0006] In one embodiment, the PCIe adapter board further includes a clock buffer chip. The clock buffer chip is electrically connected to a first signal connector and a second signal connector, and is used to receive PCIe signals from the first signal connector, expand one reference clock signal contained in the PCIe signal into multiple reference clock signals, and send the multiple reference clock signals to the second signal connector.
[0007] In another embodiment, the PCIe adapter board further includes a switching chip. The switching chip is electrically connected to a first signal connector and a second signal connector, and is used to receive PCIe signals from the first signal connector, expand one SMBus signal contained in each group of PCIe signals into multiple SMBus signals, and send multiple SMBus signals to the second signal connector.
[0008] In another embodiment, the PCIe adapter board further includes an expansion chip. The expansion chip is electrically connected to a first signal connector and a second signal connector, and is used to receive PCIe signals from the first signal connector, expand one status indication signal or disk insertion detection signal contained in each group of PCIe signals into multiple status indication signals or disk insertion detection signals, and send the multiple status indication signals or disk insertion detection signals to the second signal connector.
[0009] In another embodiment, the second signal connector is electrically connected to the first signal connector, and the second signal connector is used to receive PCIe signals from the first signal connector and expand one reset signal or clock request signal contained in the PCIe signal into multiple reset signals or clock request signals.
[0010] In another embodiment, the plurality of signal selectors includes a first signal selector, a second signal selector, and a third signal selector. The first signal selector is electrically connected to a first signal connector and is used to receive PCIe signals from the first signal connector, and to expand one differential pair signal contained in the PCIe signal into two differential pair signals through a multiplexer and a demultiplexer. The second signal selector is electrically connected to the first signal selector and is used to receive the two differential pair signals from the first signal selector, and to expand the two differential pair signals into four differential pair signals through a multiplexer and a demultiplexer. The third signal selector is electrically connected to the second signal selector and is used to receive the four differential pair signals from the second signal selector, and to expand the four differential pair signals into eight differential pair signals through a multiplexer and a demultiplexer.
[0011] In another embodiment, both the multiplexer and demultiplexer of the first signal selector include a signal booster. The signal booster is used to enhance the PCIe signal.
[0012] In another embodiment, the differential pair signal includes a transmitted signal and a received signal. A multiplexer is used to extend the received signal. A demultiplexer is used to extend the transmitted signal.
[0013] The second aspect of this application provides a testing device, which includes a testing machine and a PCIe adapter board provided in the first aspect, wherein the PCIe adapter board is electrically connected to the testing machine.
[0014] A third aspect of this application provides a testing method applied to the testing device provided in the second aspect. The testing method includes: based on the testing device being powered on and determining that each hard drive under test is inserted into its corresponding drive bay, obtaining the identifier of each hard drive under test; selecting the Nth group of PCIe lanes according to the identifiers of each hard drive under test, and performing disk recognition detection on the hard drive under test corresponding to the Nth group of PCIe lanes; performing functional testing on the hard drive under test corresponding to the Nth group of PCIe lanes based on successful disk recognition detection; and controlling the testing device to power down based on determining that N equals M. Wherein, N is an integer greater than 0 and less than or equal to M, M = T / 4, and T is the total number of drive bays.
[0015] It is understood that the technical effects of the test equipment provided in the second aspect and the test method provided in the third aspect of the embodiments of this application are roughly the same as the technical effects of the PCIe adapter board provided in the first aspect, and will not be repeated here. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of the structure of a test device provided in one embodiment of this application.
[0017] Figure 2 This is a schematic diagram of a PCIe adapter board provided as an example.
[0018] Figure 3 This is a schematic diagram of differential pair signal expansion or merging provided as an example.
[0019] Figure 4 This is a schematic diagram illustrating the extension or merging of a reference clock signal as provided in one example.
[0020] Figure 5 This is a schematic diagram illustrating the expansion or merging of a reset signal or clock request signal, as provided in one example.
[0021] Figure 6 This is a schematic diagram illustrating an example of SMBus signal extension or merging.
[0022] Figure 7 This is a schematic diagram illustrating the expansion or merging of a status indication signal or disk detection signal provided as an example.
[0023] Figure 8 This is a schematic diagram of a test device provided as an example.
[0024] Figure 9 This is a flowchart of a testing method provided in one embodiment of this application. Detailed Implementation
[0025] It should be noted that in the embodiments of this application, "multiple" and "multi-path" refer to two or more, or two or more paths. The terms "first," "second," and "third," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects, not to describe a specific order or sequence.
[0026] It should also be noted that the methods disclosed in the embodiments of this application or the methods shown in the flowcharts include one or more steps for implementing the method. Without departing from the scope of the claims, the execution order of multiple steps can be interchanged, and some steps can also be deleted.
[0027] Testing SSDs equipped with PCIe interfaces is limited by the number of PCIe interfaces on the test equipment, resulting in lower testing efficiency. PCIe interfaces include, but are not limited to, M.2 and U.2 interfaces.
[0028] The following example uses an SSD with an M.2 interface.
[0029] In one approach, the test equipment includes a server motherboard equipped with a server Central Processing Unit (CPU). Since the server CPU supports a large number of PCIe lanes, with each four PCIe lanes corresponding to one M.2 interface, the test equipment can support the expansion of more M.2 interfaces. For example, in a scenario where the server CPU supports 112 PCIe lanes, and each SSD corresponds to four PCIe lanes, the test equipment can support parallel testing of up to 28 SSDs. However, since each SSD corresponds to one M.2 slot on the server motherboard, the number of SSDs that can be tested in parallel is limited by the number of M.2 slots on the server motherboard. PCIe defines slots of various widths, such as X1, X4, X8, X12, X16, and X32. In a scenario where the server motherboard is configured with 6 PCIe x16 slots, an adapter board is used to convert each PCIe x16 slot into 4 M.2 slots. As a result, the server motherboard supports 24 M.2 slots, and the test device supports 24 M.2 drive bays, thus supporting the parallel testing of 24 SSDs.
[0030] In another approach, the test equipment includes a consumer-grade CPU equipped with a PCIe switch chip. Since the PCIe switch chip supports a large number of PCIe lanes, the test equipment can support the expansion of more M.2 interfaces. For example, in a scenario where the PCIe switch chip supports 52 PCIe lanes, the consumer-grade CPU can be configured with one set of uplink PCIe signals and eight sets of downlink PCIe signals via the PCIe switch chip. This allows the test equipment to expand one PCIe x16 slot into eight M.2 drive bays, thus supporting parallel testing of more SSDs.
[0031] In the above solutions, both using a server motherboard and a consumer-grade CPU equipped with a PCIe switching chip result in high testing costs. Using a consumer-grade personal computer (PC) can reduce testing costs, but since consumer-grade PCs typically support a maximum of 20 PCIe lanes, testing equipment using consumer-grade PCs can only support a limited number of expanded PCIe interfaces. Furthermore, all downlink lanes expanded by a consumer-grade PC share the bandwidth of a single uplink lane, leading to lower data transfer rates.
[0032] Based on this, embodiments of this application provide a PCIe adapter board, a testing device, and a testing method, aiming to solve the problem of how to expand the number of drive bays.
[0033] Figure 1 This is a schematic diagram of the structure of a test device provided in one embodiment of this application.
[0034] like Figure 1 As shown, the test equipment 10 includes a test unit 100 and a PCIe adapter board 200. The test unit 100 includes a PCIe interface for outputting PCIe signals. These PCIe signals include differential pair signals, a reference clock signal, a reset signal, a clock request signal, a System Management Bus (SMBus) signal, a status indication signal, and a disk insertion detection signal. The differential pair signals include either a transmit (TX) signal or a receive (RX) signal.
[0035] The PCIe adapter board 200 electrically connects the test machine 100 and the hard drive under test 300. It expands each set of PCIe signals from the test machine 100 into multiple sets of PCIe signals, thereby providing more drive bays to the hard drive under test 300. For the expansion of each set of PCIe signals, differential pair signals can be expanded using a multiplexer (Mux) and a demultiplexer (Demux). The multiplexer is used for the expansion of the RX signal, and the demultiplexer is used for the expansion of the TX signal. The reference clock signal can be expanded using a clock buffer chip. The reset signal and clock request signal can be expanded using a direct connection. The SMBus signal can be expanded using a switching chip, such as an Inter-Integrated Circuit (IIC) switching chip. The status indication signal and drive insertion detection signal can be expanded using an expansion chip, such as an IIC (General Purpose Input Output) expansion chip.
[0036] In this embodiment, the test machine 100 can be a consumer-grade PC. This allows for the expansion of more PCIe interfaces at a lower testing cost.
[0037] The following example uses the PCIe adapter board 200 to expand each group of PCIe signals into 8 groups of PCIe signals.
[0038] Figure 2 This is a schematic diagram of a PCIe adapter board provided as an example.
[0039] like Figure 2 As shown, the PCIe adapter board 200 includes a first signal connector 211, a second signal connector 212, a first signal selector 221, a second signal selector 222, a third signal selector 223, a clock buffer chip 230, a switching chip 240, an expansion chip 250, a communication interface 260, a controller 270, and a power interface 280.
[0040] In this embodiment, the signal connector includes a SlimSAS interface, which is used to receive PCIe signals from the test machine 100. For example, the first signal connector 211 is a SlimSAS 4I connector, which supports outputting one set of PCIe signals. The second signal connector 212 is a SlimSAS 8I connector, which supports outputting two sets of PCIe signals.
[0041] The signal selector includes a demultiplexer and a multiplexer. In some embodiments, both the demultiplexer and the multiplexer include a signal amplifier (e.g., a redriver) to amplify the signal amplitude to compensate for signal transmission loss.
[0042] The first signal connector 211 is electrically connected to the tester 100 and is used to receive PCIe signals from the tester 100.
[0043] The first signal selector 221 is electrically connected to the first signal connector 211 and is used to receive PCIe signals from the first signal connector 211, and to expand the four differential pairs of signals contained in each PCIe signal into eight differential pairs of signals through a multiplexer and a demultiplexer, thereby forming a first-level signal expansion.
[0044] The second signal selector 222 is electrically connected to the first signal selector 221 and is used to receive 8 sets of differential pairs of signals from the first signal selector 221, and to expand the 8 sets of differential pairs of signals into 16 sets of differential pairs of signals through a multiplexer and a demultiplexer, thereby forming a second-level signal expansion.
[0045] The third signal selector 223 is electrically connected to the second signal selector 222 and is used to receive 16 differential pairs of signals from the second signal selector 222, and to expand the 16 differential pairs of signals into 32 differential pairs of signals through a multiplexer and a demultiplexer, thereby forming a third-level signal expansion.
[0046] The second signal connector 212 is electrically connected to the third signal selector 223 for receiving 32 sets of differential pairs of signals from the third signal selector 223.
[0047] In this embodiment, the PCIe adapter board 200 is configured with four first signal connectors 211 and sixteen second signal connectors 212. Since one PCIe interface of the test machine 100 outputs one set of PCIe signals, and one first signal connector 211 supports outputting one set of PCIe signals, the four first signal connectors 211 respectively receive four sets of PCIe signals from the four PCIe interfaces of the test machine 100. Since one second signal connector 212 supports outputting two sets of PCIe signals, and one third signal selector 223 outputs 32 sets of differential pairs of signals, and one set of PCIe signals contains four sets of differential pairs of signals, the four second signal connectors 212 respectively receive 32 sets of differential pairs of signals from one third signal selector 223. Thus, the 16 second signal connectors 212 respectively receive 128 sets of differential pairs of signals from the four third signal selectors 223, thereby supporting the expansion of the 16 sets of differential pairs of signals contained in the four sets of PCIe signals into 128 sets of differential pairs of signals.
[0048] The clock buffer chip 230 is electrically connected to the first signal connector 211 and the second signal connector 212, and is used to receive PCIe signals from the first signal connector 211, expand the 1 reference clock signal contained in each group of PCIe signals into 8 reference clock signals, and send 8 reference clock signals to the second signal connector 212.
[0049] In this embodiment, the PCIe adapter board 200 is equipped with four clock buffer chips 230. The four clock buffer chips 230 respectively receive four sets of PCIe signals from four first signal connectors 211, and expand the four reference clock signals contained in the four sets of PCIe signals into 32 reference clock signals.
[0050] The switching chip 240 is electrically connected to the first signal connector 211 and the second signal connector 212, and is used to receive PCIe signals from the first signal connector 211, expand the 1 SMBus signal contained in each group of PCIe signals into 8 SMBus signals, and send 8 SMBus signals to the second signal connector 212.
[0051] In this embodiment, the PCIe adapter board 200 is configured with four switching chips 240. The four switching chips 240 respectively receive four sets of PCIe signals from four first signal connectors 211, and expand the four SMBus signals contained in the four sets of PCIe signals into 32 SMBus signals.
[0052] The expansion chip 250 is electrically connected to the first signal connector 211 and the second signal connector 212, and is used to receive PCIe signals from the first signal connector 211, expand the 1 status indication signal (or disk insertion detection signal) contained in each group of PCIe signals into 8 status indication signals (or disk insertion detection signals), and send 8 status indication signals (or disk insertion detection signals) to the second signal connector 212.
[0053] In this embodiment, the PCIe adapter board 200 is configured with eight expansion chips 250. Four of the expansion chips 250 receive four sets of PCIe signals from four first signal connectors 211, respectively, and expand the four status indication signals contained in the four sets of PCIe signals into 32 status indication signals. The other four expansion chips 250 receive four sets of PCIe signals from the four first signal connectors 211, respectively, and expand the four disk drive detection signals contained in the four sets of PCIe signals into 32 disk drive detection signals.
[0054] The first signal connector 211 and the second signal connector 212 are electrically connected. The second signal connector 212 receives PCIe signals from the first signal connector 211 and expands the 1 reset signal (or clock request signal) contained in each group of PCIe signals into 8 reset signals (or clock request signals).
[0055] In this embodiment, each first signal connector 211 is electrically connected to four second signal connectors 212, and each second signal connector 212 receives two sets of PCIe signals including two reset signals (or clock request signals).
[0056] The communication interface 260 is electrically connected to the test machine 100 and is used to receive instructions from the test machine 100.
[0057] The controller 270 is electrically connected to the first signal connector 211, the second signal connector 212, the first signal selector 221, the second signal selector 222, the third signal selector 223, the clock buffer chip 230, the switching chip 240, the expansion chip 250, and the communication interface 260. It receives instructions from the test machine 100 through the communication interface 260 and controls the corresponding components according to the instructions to process the PCIe signals, thereby enabling the selection, expansion, and merging of PCIe channels. The controller 270's control of PCIe channel selection helps avoid contention among multiple downlink channels.
[0058] The power interface 280 electrically connects to the first signal connector 211, the second signal connector 212, the first signal selector 221, the second signal selector 222, the third signal selector 223, the clock buffer chip 230, the switching chip 240, the expansion chip 250, and the controller 270, and is used to connect to the power supply to provide power to each component.
[0059] It is understood that in other embodiments, the PCIe adapter board 200 may include more or fewer signal selectors, thereby expanding more or fewer differential pair signals. Accordingly, the number of channels configured in the clock buffer chip 230, switching chip 240, and expansion chip 250 may be adaptively changed according to the number of differential pair signals.
[0060] The following section provides a detailed explanation of the expansion or merging of the various signals included in the PCIe signal.
[0061] Figure 3 This is a schematic diagram of differential pair signal expansion or merging provided as an example.
[0062] like Figure 3As shown, the first signal selector 221 includes one demultiplexer (Demux) and one multiplexer (Mux), both of which include a signal booster (Redriver). The second signal selector 222 includes two demultiplexers (Demux) and two multiplexers (Mux). The third signal selector 223 includes four demultiplexers (Demux) and four multiplexers (Mux).
[0063] In the scenario of extended differential pair signals, the first signal selector 221 receives one set of differential pair signals PCIe X4TX / RX, and uses the demultiplexer (Demux) to extend the one set of transmit signals PCIe X4TX contained in the one set of differential pair signals PCIe X4TX / RX into two sets of transmit signals PCIe X4TX, and uses the multiplexer (Mux) to extend the one set of receive signals PCIe X4RX contained in the one set of differential pair signals PCIe X4TX / RX into two sets of receive signals PCIe X4RX. The second signal selector 222 receives two sets of differential pair signals PCIe X4TX / RX, and uses the demultiplexer (Demux) to extend the two sets of transmit signals PCIe X4TX contained in the two sets of differential pair signals PCIe X4TX / RX into four sets of transmit signals PCIe X4TX, and uses the multiplexer (Mux) to extend the two sets of receive signals PCIe X4RX contained in the two sets of differential pair signals PCIe X4TX / RX into four sets of receive signals PCIe X4RX. The third signal selector 223 receives four sets of differential pair signals PCIe X4TX / RX, and uses the demultiplexer Demux to expand the four sets of transmit signals PCIe X4TX contained in the four sets of differential pair signals PCIe X4TX / RX into eight sets of transmit signals PCIe X4TX, and uses the multiplexer Mux to expand the four sets of receive signals PCIe X4RX contained in the four sets of differential pair signals PCIe X4TX / RX into eight sets of receive signals PCIe X4RX.
[0064] In the scenario of combining differential pair signals, the third signal selector 223 receives eight sets of differential pair signals PCIe X4TX / RX, and uses a multiplexer (Mux) to combine the eight sets of received PCIe X4RX signals contained in the eight sets of differential pair signals PCIe X4TX / RX into four sets of received PCIe X4RX signals. Similarly, the demultiplexer (Demux) combines the eight sets of transmitted PCIe X4TX signals contained in the eight sets of differential pair signals PCIe X4TX / RX into four sets of transmitted PCIe X4TX signals. The second signal selector 222 receives four sets of differential pair signals PCIe X4TX / RX, and uses a multiplexer (Mux) to combine the four sets of received PCIe X4RX signals contained in the four sets of differential pair signals PCIe X4TX / RX into two sets of received PCIe X4RX signals. Likewise, the demultiplexer (Demux) combines the four sets of transmitted PCIe X4TX signals contained in the four sets of differential pair signals PCIe X4TX / RX into two sets of transmitted PCIe X4TX signals. The first signal selector 221 receives two sets of differential pair signals PCIe X4TX / RX, and uses a multiplexer Mux to combine the two sets of receive signals PCIe X4RX contained in the two sets of differential pair signals PCIe X4TX / RX into one set of receive signals PCIe X4RX. It also uses a demultiplexer Demux to combine the two sets of transmit signals PCIe X4TX contained in the two sets of differential pair signals PCIe X4TX / RX into one set of transmit signals PCIe X4TX.
[0065] Figure 4 This is a schematic diagram illustrating the extension or merging of a reference clock signal as provided in one example.
[0066] like Figure 4 As shown, in the scenario of expanding the reference clock signal, the clock buffer chip 230 receives one reference clock signal PCIeREFCLK and expands it into eight reference clock signals PCIeREFCLK. In the scenario of merging the reference clock signals, the clock buffer chip 230 receives eight reference clock signals PCIeREFCLK and merges them into one reference clock signal PCIeREFCLK.
[0067] Figure 5 This is a schematic diagram illustrating the expansion or merging of a reset signal or clock request signal, as provided in one example.
[0068] like Figure 5As shown, in scenarios involving extended reset or clock request signals, one reset signal PCIePERST0# (or clock request signal PCIeCLKREQ#) is directly connected to expand into eight reset signals PCIePERST0# (or clock request signal PCIeCLKREQ#). In scenarios involving merging reset or clock request signals, eight reset signals PCIePERST0# (or clock request signal PCIeCLKREQ#) are directly connected to merge into one reset signal PCIePERST0# (or clock request signal PCIeCLKREQ#).
[0069] Figure 6 This is a schematic diagram illustrating an example of SMBus signal extension or merging.
[0070] like Figure 6 As shown, in the scenario of expanding SMBus signals, the switching chip 240 receives one SMBus signal PCIeSMBus and expands it into eight SMBus signals PCIeSMBus. In the scenario of merging SMBus signals, the switching chip 240 receives eight SMBus signals PCIeSMBus and merges them into one SMBus signal PCIeSMBus.
[0071] Figure 7 This is a schematic diagram illustrating the expansion or merging of a status indication signal or disk detection signal provided as an example.
[0072] like Figure 7 As shown, in scenarios involving extended status indication signals or disk drive detection signals, the expansion chip 250 receives one status indication signal PCIeActivity (or disk drive detection signal PCIePRSNT) and expands it into eight status indication signals PCIeActivity (or disk drive detection signal PCIePRSNT). In scenarios involving merging status indication signals or disk drive detection signals, the expansion chip 250 receives eight status indication signals PCIeActivity (or disk drive detection signal PCIePRSNT) and merges them into one status indication signal PCIeActivity (or disk drive detection signal PCIePRSNT).
[0073] The following section uses the components of an integrated testing machine as an example to illustrate the testing equipment in detail.
[0074] Figure 8This is a schematic diagram of a test device provided as an example.
[0075] like Figure 8 As shown, the test device 10 includes a power button 101, a reset button 102, a cooling fan 103, a motherboard 104, a motherboard power supply 105, a motherboard memory module 106, a SlimSAS interface adapter board 107, a motherboard system hard drive 108, a power board 109, a heat insulation baffle 110, a cable hole 111, a hard drive under test 300, a PCIe interface board 112, a PCIe adapter board 200, and a module power supply 113.
[0076] The power button 101 is electrically connected to the motherboard power supply 105 and the module power supply 113, and is used to control the motherboard power supply 105 and the module power supply 113 to start or stop.
[0077] The reset button 102 is electrically connected to the motherboard 104 and is used to control the motherboard 104 to generate a reset command. The reset command is used to instruct the corresponding component to reset.
[0078] The cooling fan 103 is electrically connected to the motherboard power supply 105 and is used to dissipate heat from the internal space of the test device 10 when the motherboard power supply 105 is started. In some embodiments, the test device 10 is configured with multiple fan slots, and each fan slot can be equipped with one cooling fan 103.
[0079] The motherboard 104 is electrically connected to the motherboard memory module 106, the SlimSAS interface adapter board 107, the motherboard system hard disk 108, and the communication interface 260 of the PCIe adapter board 200. It is used to coordinate the motherboard memory module 106 and the motherboard system hard disk 108 to perform various data or instruction processing and storage. It is electrically connected to the first signal connector 211 of the PCIe adapter board 200 through the SlimSAS interface adapter board 107, and sends instructions to the communication interface 260 of the PCIe adapter board 200, thereby controlling the PCIe adapter board 200 to perform PCIe channel selection, expansion, and merging.
[0080] The motherboard power supply 105 is electrically connected to the motherboard 104, the motherboard memory module 106, and the motherboard system hard drive 108, and is used to supply power to each component.
[0081] The motherboard memory module 106 is used to provide memory space for the motherboard 104.
[0082] SlimSAS interface adapter board 107 is used to convert the PCIe interface of motherboard 104 into a SlimSAS interface.
[0083] The motherboard system hard drive 108 is used to provide storage space for the motherboard 104.
[0084] The power board 109 is electrically connected to the hard drive under test 300 and is used to connect to the module power supply 113 to supply power to the hard drive under test 300. In some embodiments, the motherboard 104 is electrically connected to the power board 109 and is used to control the power supply of the power board 109 to the hard drive under test 300.
[0085] The heat insulation baffle 110 is disposed between the hard drive under test 300 and the internal space of the test device 10 to isolate the hard drive under test 300 from the internal space of the test device 10, thereby providing heat insulation for the hard drive under test 300.
[0086] A wire hole 111 is provided on the heat insulation baffle 110 for passing through data lines from the second signal connector 212 of the PCIe adapter board 200 and power lines from the power board 109.
[0087] The PCIe interface board 112 electrically connects the power board 109 and the second signal connector 212 of the PCIe adapter board 200 to provide an expanded PCIe interface for accessing more hard drives 300 under test.
[0088] The module power supply 113 is electrically connected to the power board 109 and is used to supply power to the power board 109.
[0089] In this embodiment, the test device 10 integrates all the components of the test machine, thereby possessing complete PC functions. It also controls the PCIe adapter board 200 through the motherboard 104 to perform PCIe channel selection, expansion, and merging, thereby performing tests on multiple hard drives 300 under test in a time-division multiplexing manner, which helps to avoid competition for multiple PCIe channels.
[0090] It is understood that the structure illustrated in the embodiments of this application does not constitute a specific limitation on the test device 10. In other embodiments, the test device 10 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements.
[0091] The testing method is explained in detail below.
[0092] Figure 9 This is a flowchart of a testing method provided in one embodiment of this application.
[0093] The test method is applied to the test equipment, for example Figure 1 or Figure 8 The test equipment shown. (As shown) Figure 9 As shown, the test method includes the following steps:
[0094] S101, based on the power-on of the test equipment, detects the disk insertion detection signal of each disk slot within a predetermined time period.
[0095] In this embodiment, the testing device determines whether the hard drive under test is inserted into the corresponding drive bay based on whether a drive insertion detection signal is detected within a predetermined time period. If the testing device detects a drive insertion detection signal within the predetermined time period, it determines that the hard drive under test is inserted into the corresponding drive bay. If the testing device does not detect a drive insertion detection signal within the predetermined time period, it determines that the hard drive under test is not inserted into the corresponding drive bay. The predetermined time period can be set as needed.
[0096] S102, determine whether disk insertion detection signals for each disk bay have been detected.
[0097] If yes, proceed to step S103; otherwise, return to step S101.
[0098] S103, based on determining that each hard drive under test is inserted into the corresponding drive bay, obtain the identifier of each hard drive under test.
[0099] The identifier for each hard drive under test is used to distinguish it from the others. This identifier is unique and may include the hard drive's identification code or serial number.
[0100] In this embodiment, the testing device can store the identifiers of each hard drive under test and query the identifiers of each hard drive under test before starting the test.
[0101] S104: Select the Nth group of PCIe channels according to the identifier of each hard drive under test, and perform disk identification detection on the hard drive under test corresponding to the Nth group of PCIe channels.
[0102] Where N is an integer greater than 0 and less than or equal to M, M = T / 4, and T is the total number of disk slots.
[0103] In this embodiment, each PCIe lane corresponds to 4 disk bays. Disk recognition testing is used to determine whether the basic functions of the hard drive under test are normal. These basic functions may include read / write and storage capabilities. If the disk recognition test is successful, the basic functions of the hard drive under test are determined to be normal. If the disk recognition test fails, the basic functions of the hard drive under test are determined to be abnormal.
[0104] It is understood that this embodiment does not limit the method of disk recognition detection.
[0105] S105, confirm whether the disk recognition test was successful.
[0106] If yes, proceed to step S106; otherwise, proceed to step S108.
[0107] S106, Perform functional testing on the hard drive under test corresponding to the Nth PCIe channel.
[0108] Functional testing may include interface plug-in / plug-out testing or aging testing of the hard drive under test.
[0109] It is understood that this embodiment does not limit the items and methods of functional testing.
[0110] S107, determine whether N is equal to M.
[0111] If yes, proceed to step S108; otherwise, return to step S104.
[0112] In this embodiment, if N equals M, it means that the testing of all hard drives under test has been completed. If N is less than M, it means that the testing of all hard drives under test has not been completed.
[0113] S108, power off the control test equipment.
[0114] In this embodiment, the testing equipment tests more hard drives under test based on the expanded disk bays of the PCIe adapter board, and the testing machine controls the testing of each hard drive under test.
[0115] The embodiments of this application have been described in detail above with reference to the accompanying drawings. However, this application is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of this application.
Claims
1. A PCIe adapter board, characterized in that, The PCIe adapter board includes a first signal connector, a second signal connector, a controller, and multiple signal selectors; wherein, the signal selector includes a multiplexer and a demultiplexer; The first signal connector is electrically connected to the tester and is used to receive PCIe signals from the tester; The plurality of signal selectors are connected in series between the first signal connector and the second signal connector for receiving the PCIe signal from the first signal connector, and for expanding one differential pair signal contained in the PCIe signal into multiple differential pair signals through the multiplexer and the demultiplexer. The second signal connector is used to receive the multi-path differential pair signals, which are used to form corresponding multiple sets of PCIe signals; The controller is electrically connected to the first signal connector, the second signal connector, and the plurality of signal selectors, and is used to receive instructions from the test machine and process the PCIe signals according to the instructions.
2. The PCIe adapter board as described in claim 1, characterized in that, The PCIe adapter board also includes a clock buffer chip; The clock buffer chip is electrically connected to the first signal connector and the second signal connector, and is used to receive the PCIe signal from the first signal connector, expand one reference clock signal contained in the PCIe signal into multiple reference clock signals, and send the multiple reference clock signals to the second signal connector.
3. The PCIe adapter board as described in claim 1, characterized in that, The PCIe adapter board also includes a switching chip; The switching chip is electrically connected to the first signal connector and the second signal connector, and is used to receive the PCIe signal from the first signal connector, expand one SMBus signal contained in each group of PCIe signals into multiple SMBus signals, and send the multiple SMBus signals to the second signal connector.
4. The PCIe adapter board as described in claim 1, characterized in that, The PCIe adapter board also includes an expansion chip; The expansion chip is electrically connected to the first signal connector and the second signal connector, and is used to receive the PCIe signal from the first signal connector, expand one status indication signal or disk insertion detection signal contained in each group of PCIe signals into multiple status indication signals or disk insertion detection signals, and send the multiple status indication signals or disk insertion detection signals to the second signal connector.
5. The PCIe adapter board as described in claim 1, characterized in that, The second signal connector is electrically connected to the first signal connector. The second signal connector is used to receive the PCIe signal from the first signal connector and expand one reset signal or clock request signal contained in the PCIe signal into multiple reset signals or clock request signals.
6. The PCIe adapter board as described in any one of claims 1 to 5, characterized in that, The plurality of signal selectors includes a first signal selector, a second signal selector, and a third signal selector; The first signal selector is electrically connected to the first signal connector and is used to receive the PCIe signal from the first signal connector, and to expand the one differential pair signal contained in the PCIe signal into two differential pair signals through the multiplexer and the demultiplexer. The second signal selector is electrically connected to the first signal selector and is used to receive the two differential pairs of signals from the first signal selector, and to expand the two differential pairs of signals into four differential pairs of signals through the multiplexer and the demultiplexer. The third signal selector is electrically connected to the second signal selector and is used to receive the four differential pair signals from the second signal selector, and to expand the four differential pair signals into eight differential pair signals through the multiplexer and the demultiplexer.
7. The PCIe adapter board as described in claim 6, characterized in that, Both the multiplexer and the demultiplexer of the first signal selector include a signal amplifier; The signal booster is used to enhance the PCIe signal.
8. The PCIe adapter board as described in claim 1, characterized in that, The differential pair signal includes a transmitted signal and a received signal; The multiplexer is used to extend the received signal; The demultiplexer is used to extend the transmitted signal.
9. A testing device, characterized in that, The testing equipment includes a testing machine and a PCIe adapter board as described in any one of claims 1 to 8, wherein the PCIe adapter board is electrically connected to the testing machine.
10. A testing method, characterized in that, The test method is applied to the test equipment as described in claim 9, and the test method includes: Based on the power-on of the test equipment and the determination that each hard drive under test is inserted into the corresponding drive bay, the identifier of each hard drive under test is obtained; The Nth group of PCIe channels is selected based on the identifier of each of the hard drives under test, and the hard drives under test corresponding to the Nth group of PCIe channels are identified and detected. Based on the successful disk recognition detection, perform functional testing on the hard drive under test corresponding to the Nth PCIe channel; Based on the determination that N equals M, the test equipment is powered off. Wherein, N is an integer greater than 0 and less than or equal to M, M = T / 4, and T is the total number of disk positions.