Digital circuit design system, digital circuit full-automatic design method and related products

Abstract

The application provides a digital circuit design system, a digital circuit full-automatic design method and related products. The digital circuit design system converts a metal layer rule into a process parameter template represented by a coefficient of a process minimum line width unit through a process abstraction interface module, thereby reducing process migration cost. The digital circuit full-automatic design method can automatically obtain a physical implementation result of a target digital circuit from a function description of the target digital circuit, realize full-flow automatic design of a chip, and reduce design difficulty of the digital circuit.

Description

Technical Field

[0001] This application relates to the field of digital circuit design technology, and more specifically, to a digital circuit design system, a fully automated digital circuit design method, and related products. Background Technology

[0002] The current mainstream technology in digital integrated circuit design is a phased design flow based on discrete toolchains. One of its core architectures is a physical implementation mechanism tightly coupled with the process technology. This mechanism is deeply tied to the specific process design kit (PDK) for each process node. During process migration, the physical design rule mapping needs to be rewritten. However, this mechanism is costly in terms of process migration. For example, 7nm process migration adaptation requires rewriting more than 65% of the physical design rule mapping code. Summary of the Invention

[0003] The purpose of this application is to provide a digital circuit design system, a fully automated digital circuit design method, and related products to solve the problem of high process migration costs caused by the strong coupling between EDA (Electronic Design Automation) tools and processes.

[0004] This application provides a digital circuit design system, including: a process abstraction interface module, used to: obtain the PDK of the target process used by the target digital circuit; parse the metal layer rules from the PDK; convert the metal layer rules into coefficients of the minimum linewidth unit of the process to obtain a process parameter template; and generate physical design rules and rule checking scripts corresponding to the target process based on the process parameter template.

[0005] In the above implementation scheme, metal layer rules are parsed from the PDK and converted into process parameter templates represented by coefficients in the minimum linewidth unit of the process. Then, physical design rules and rule checking scripts corresponding to the target process are generated based on these templates. In other words, based on this implementation scheme, a process parameter template represented by coefficients in the minimum linewidth unit of the process is constructed for the metal layer rules. This template is independent of the process itself, so during process migration, physical design rules and rule checking scripts are generated directly based on the coefficients in the minimum linewidth unit of the process, eliminating the need to rewrite the physical design rules and reducing process migration costs.

[0006] Optionally, the process abstraction interface module is specifically used to convert the PDK into a text file; and to extract the metal layer rules from the text file using regular expressions.

[0007] In the above implementation, by converting the PDK into a text file and then using regular expressions to extract the metal layer rules from the text file, the machine can automatically extract the metal layer rules without human intervention.

[0008] Optionally, the digital circuit design system further includes: an intelligent constraint transfer module, configured to: receive the netlist file of the target digital circuit and convert it into a constraint map based on the netlist file; extract the metal layer RC (resistance-capacitance) parameters corresponding to different process corners from the PDK; and generate constraint files corresponding to each process corner based on the constraint map and the metal layer RC parameters.

[0009] In traditional phased design flows based on discrete toolchains, heterogeneous toolchain data formats can lead to constraint propagation deviations, affecting the design performance of digital circuits. However, the aforementioned implementation converts the netlist file (containing constraint information) into a constraint graph. This allows specific constraints from tools such as SDC (Synopsys DesignConstraint, used to describe design requirements for timing, area, and power consumption) / CPF (Common Power Format, a low-power design language) within the netlist file to be converted into an intermediate representation of the graph structure. This intermediate representation is then combined with the metal layer RC parameters to generate the constraint file. Thus, through constraint graph conversion, the transmitted constraint files are generated and transmitted using the intermediate representation within the constraint graph, improving constraint consistency and consequently increasing the efficiency of digital circuit design.

[0010] Optionally, the constraint graph is a directed acyclic graph, including: nodes representing design objects, and edges representing timing, power consumption, or physical constraints between the design objects, wherein the edges have attributes that define constraints; the design objects include the modules in the target digital circuit recorded in the netlist file.

[0011] Optionally, the intelligent constraint transfer module is specifically used for: receiving the netlist file of the target digital circuit, converting it into a constraint map based on the netlist file, and detecting whether the constraint map has constraint conflicts; if constraint conflicts exist, sending feedback to the provider of the netlist file to obtain a new netlist file of the target digital circuit, converting it into a new constraint map based on the new netlist file, and detecting whether the new constraint map has constraint conflicts; if the new constraint map does not have constraint conflicts, generating constraint files corresponding to each process corner based on the new constraint map and the RC parameters of the metal layer.

[0012] In the above implementation, constraint conflict detection is performed in the constraint map before generating the constraint files corresponding to each process corner. This improves the usability of the constraint map, thereby improving the usability of the generated constraint files and enhancing the effectiveness of digital circuit design.

[0013] Optionally, the digital circuit design system further includes: an EDA toolchain module, comprising multiple EDA tools that implement different functions of digital circuit design, used to sequentially call each of the EDA tools according to the preset EDA tool calling logic, the constraint file, the physical design rules and the rule checking script to implement the physical implementation of the target digital circuit and output the physical implementation result;

[0014] A multi-objective optimization module is used to: optimize various design parameters to obtain optimized design parameters; the design parameters include chip parameters and process parameters in the physical implementation results, as well as EDA tool parameters of each EDA tool; provide the process parameters in the design parameters to the process abstraction interface module to update the process parameter template; output the chip parameters in the design parameters to the netlist file provider to update the netlist file; and output the EDA tool parameters in the design parameters to the EDA toolchain module to update each EDA tool.

[0015] In the above implementation, multiple EDA tools are linked and scheduled through the EDA toolchain module, and the design parameters are optimized through the multi-objective optimization module. The process parameter template, netlist file, and EDA tool parameters of each EDA tool are updated. By continuously looping and updating the process parameter template, netlist file, and EDA tool parameters of each EDA tool, the reliability of digital circuit design can be continuously improved, making the final digital circuit more reliable.

[0016] Optionally, the EDA tool includes a logic synthesis tool that uses a line load model for logic synthesis; the intelligent constraint transfer module is further configured to: transfer the line length in the physical implementation result to the logic synthesis tool to update the line load model.

[0017] In the above implementation, by passing the line length from the physical implementation result to the logic synthesis tool to update the line load model, dynamic backpropagation of the line length parameter is achieved, thereby improving the reliability of the line load model in the next cycle and making the final digital circuit more reliable.

[0018] Optionally, the multi-objective optimization module uses a GP (Gaussian process)-DKL (deep kernel learning) multi-objective hybrid model to optimize each design parameter.

[0019] In the above implementation, the GP-DKL multi-objective hybrid model is used as a surrogate model for optimization. GP can capture the linear features in the optimization process, while DKL can capture the nonlinear features. Therefore, high-dimensional parameter optimization using the GP-DKL multi-objective hybrid model can capture feature information more comprehensively and improve the optimization effect.

[0020] Optionally, the multi-objective optimization module is specifically used to optimize each design parameter using a GP-DKL multi-objective hybrid model in the following manner: obtaining the constraints of the target digital circuit; defining the search space of the GP-DKL multi-objective hybrid model according to the design parameters and the constraints; performing multiple iterations until a preset iteration stopping condition is reached; wherein, each iteration includes: searching the search space, reducing the dimensionality of the search space according to the search results, and updating the model parameters of the GP-DKL multi-objective hybrid model; wherein, in the initial iteration, the search space is searched using the point in the search space mapped by the initial parameter values ​​of the design parameters as the initial point; outputting the parameter values ​​of each design parameter corresponding to the optimal point searched by the GP-DKL multi-objective hybrid model when the iteration stopping condition is reached; the optimized design parameters are the parameter values ​​of each design parameter corresponding to the optimal point.

[0021] In the above implementation, the search space of the GP-DKL multi-objective hybrid model is constructed by designing parameters and constraints, and the model parameters of the GP-DKL multi-objective hybrid model are continuously optimized iteratively. In the process of iteratively optimizing the GP-DKL multi-objective hybrid model, the dimensionality is continuously reduced, thereby improving the parameter optimization effect and increasing the optimization speed through dimensionality reduction, thus meeting the high-dimensional parameter optimization requirements in the chip design process.

[0022] Optionally, the multi-objective optimization module is specifically used to reduce the dimensionality of the search space based on the search results in the following ways: determining the target model parameters in the model parameters of the GP-DKL multi-objective hybrid model based on the search results; the target model parameters include model parameters whose change magnitude during the update process is lower than a preset change threshold; and merging the design parameters corresponding to the target model parameters into one dimension.

[0023] Optionally, the multi-objective optimization module is specifically used to: determine the UCB (upper bound of the confidence interval) of each search result; and merge the design parameters corresponding to the target model parameters in the model parameters of the GP-DKL multi-objective hybrid model when the UCB is maximized into one dimension.

[0024] In the above implementation, when the UCB is maximized, the design parameters corresponding to the target model parameters in the GP-DKL multi-objective hybrid model are merged into one dimension. This merged dimension is least sensitive to the transformation of the parameters of the GP-DKL multi-objective hybrid model, that is, the merged dimension has the least impact on the search results, thereby reducing the impact of dimension merging on search accuracy and improving the reliability of the final optimization results.

[0025] Optionally, the multi-objective optimization module is further configured to reduce the dimensionality of the search space based on the search results in the following manner: before determining the UCB of each search result, the search space is reduced using a random projection matrix.

[0026] In the above implementation, the dimensionality of the search space is first reduced by using a random projection matrix. Since the random projection matrix method can quickly reduce dimensionality, but the dimensionality reduction accuracy is not high enough, a certain degree of coarse-grained dimensionality reduction can be achieved first, and then UCB can be used to perform more accurate fine-grained dimensionality reduction. In this way, the dimensionality reduction speed can be improved while the dimensionality reduction accuracy can be improved.

[0027] Optionally, the input layer of the GP-DKL multi-objective hybrid model is embedded with an attention module; the random projection matrix is ​​updated according to the attention weight matrix output by the attention module.

[0028] In the above implementation, by embedding an attention module in the input layer of the GP-DKL multi-objective hybrid model, the key parameters in the design parameters can be effectively identified. The random projection matrix is ​​updated according to the attention weight matrix output by the attention module. This allows more key parameter dimensions to be retained each time the random projection matrix is ​​used for dimensionality reduction, so that more key parameter information is retained in the dimensionality-reduced low-dimensional space, the influence of noise dimensions is suppressed, and the optimization accuracy and reliability of the optimized design parameters are improved.

[0029] Optionally, when the multi-objective optimization module performs dimensionality reduction on the search space using the random projection matrix, it outputs a Pareto front. Specifically, the multi-objective optimization module is further configured to: jointly predict the probability distribution of multiple preset chip performance indicators based on the GP-DKL multi-objective hybrid model, calculate the EHVI (Expected Hypervolume Improvement) index; use the EHVI index as a data acquisition function, select candidate points based on the data acquisition function during the random projection dimensionality reduction process, and update the Pareto front based on the candidate points that maximize the EHVI index.

[0030] In the above implementation, updating the Pareto front using the confidence intervals of the EHVI and GP-DKL multi-objective hybrid model can improve the coverage of the Pareto front, thereby enhancing the model's ability to fine-tune design parameters and improving the reliability of the final fine-tuned design parameters.

[0031] Optionally, the digital circuit design system further includes: an input parsing module, used to obtain the functional description of the target digital circuit and generate the netlist file based on the functional description.

[0032] In the above implementation, the functional description of the target digital circuit is obtained by the input parsing module, and a netlist file is generated based on the functional description. This allows users to automatically generate a netlist file simply by inputting the functional description of the target digital circuit they want to design, without requiring users to write the netlist file themselves. This reduces the knowledge requirements for users, lowers the barrier to entry for the system, and improves the system's versatility.

[0033] Optionally, the input parsing module is specifically used to: obtain a behavioral-level parameter model, a system-level parameter model, and an RTL (Register Transfer Level)-level parameter model based on the functional description; the behavioral-level parameter model includes behavioral-level parameters, the system-level parameter model includes system-level parameters, and the RTL-level parameter model includes RTL-level parameters; establish dependencies between the parameters in the behavioral-level parameter model, the system-level parameter model, and the RTL-level parameter model to obtain a chip parameter set; optimize the chip parameter set according to the dependencies to obtain a target chip parameter set that ensures the target digital circuit has no timing violations; and output the netlist file based on the target chip parameter set.

[0034] In the above implementation, dependencies are established between parameters in the behavioral-level parameter model, system-level parameter model, and RTL-level parameter model. Then, the chip parameter set is optimized based on these dependencies. Thus, when optimizing behavioral-level, system-level, and RTL-level parameters, due to these dependencies, adjusting any one of these parameters will automatically adjust the parameters at other related levels, achieving automated cross-level parameter adjustment. For example, using this implementation, the behavioral-level parameter cache line size will be automatically mapped to the burst transmission length parameter of the system-level DDR (Double Data Rate) controller. Adjustments to RTL-level wiring congestion information will also be propagated back to the system-level NoC (Network-on-Chip) topology decision module for parameter updates. This reduces the risk of parameter version inconsistencies, improves the reliability of parameter configuration in the chip, and increases chip design efficiency.

[0035] Optionally, the input parsing module is specifically used to: obtain each system-level parameter according to the functional description; convert each system-level parameter into a data flow graph-level intermediate representation (IR), a loop nesting level IR, and an instruction operation level IR according to their correspondence with data flow graphs, loop nesting level IRs, and instruction operation level IRs; and perform orthogonalization processing on the parameters corresponding to the data flow graph-level IRs, the loop nesting level IRs, and the instruction operation level IRs to obtain the system-level parameter model.

[0036] In the above implementation, for system-level parameters, each system-level parameter is transformed into data flow graph-level IR (Intermediate Representation), loop nesting-level IR, and instruction operation-level IR according to their correspondence with data flow graphs, nested loops, and instruction operations, and then orthogonalized. In the resulting system-level parameter model, each parameter is distinguished through data flow graphs, nested loops, and instruction operations, and the orthogonalization process establishes the dependencies between them. Thus, during subsequent optimization, when any system-level parameter is adjusted, other related types of system-level parameters will also be adjusted, thereby achieving automated linkage optimization of system-level parameters, further improving the reliability of parameter configuration in the chip, and increasing chip design efficiency.

[0037] Optionally, the digital circuit design system further includes: an intelligent control module, connected to the process abstraction interface module, the multi-objective optimization module, the EDA toolchain module, and the intelligent constraint transfer module, respectively, for managing task dependencies based on a directed acyclic graph, capturing the return codes of EDA tools, and triggering constraint rollback or parameter reset for the corresponding EDA tool when the return code indicates an error; wherein, the process abstraction interface module, the multi-objective optimization module, the EDA toolchain module, and the intelligent constraint transfer module jointly realize that one physical implementation result output is one task.

[0038] In the above implementation, the intelligent control module manages the dependencies of tasks based on the directed acyclic graph and captures the return codes of the EDA tools. When the return code indicates an error, it triggers the constraint rollback or parameter reset of the corresponding EDA tool. This can effectively realize the management and recording of each task and the handling of exceptions, thereby improving the reliability of the system.

[0039] This application also provides a fully automated digital circuit design method, comprising: obtaining a functional description of a target digital circuit and generating a netlist file based on the functional description; obtaining a process design package (PDK) for the target process used by the target digital circuit and parsing metal layer rules from the PDK; converting the metal layer rules into coefficients of the minimum linewidth unit of the process to obtain a process parameter template; generating physical design rules and rule checking scripts corresponding to the target process based on the process parameter template; converting the netlist file to obtain a constraint map, and parsing metal layer RC parameters corresponding to different process corners from the PDK; generating constraint files corresponding to each process corner based on the constraint map and the metal layer RC parameters; sequentially calling each EDA tool according to a preset EDA tool calling logic, the constraint files, the physical design rules, and the rule checking scripts to implement the physical implementation of the target digital circuit and obtain the physical implementation result.

[0040] Based on the above implementation scheme, the embodiments of this application can automatically obtain the physical implementation results of the target digital circuit from the functional description of the target digital circuit, realize the full-process automated design of the chip, and reduce the design difficulty of digital circuits.

[0041] Optionally, after outputting the physical implementation results, the method further includes optimizing each design parameter.

[0042] Optionally, after optimizing each design parameter, the method further includes: updating the process parameter template according to the process parameters in the design parameters; updating the netlist file according to the chip parameters in the design parameters; updating each EDA tool according to the EDA tool parameters in the design parameters; regenerating the physical design rules and rule check scripts corresponding to the target process according to the process parameter template; regenerating the constraint map according to the netlist file; and parsing the metal layer RC parameters corresponding to different process corners from the PDK; regenerating the constraint file corresponding to each process corner according to the constraint map and the metal layer RC parameters; re-calling each EDA tool sequentially according to the preset EDA tool calling logic, the constraint file, the physical design rules, and the rule check script to implement the physical implementation of the target digital circuit and obtain the physical implementation result; optimizing each design parameter; determining whether the preset loop termination condition has been met; if not, re-executing the above operations; if met, outputting the physical implementation result after design parameter optimization.

[0043] Optionally, the EDA tool includes a logic synthesis tool that uses a line load model for logic synthesis; if the physical implementation result is obtained and the preset loop termination condition is not met, the method further includes: passing the line length in the physical implementation result to the logic synthesis tool to update the line load model.

[0044] Optionally, the design parameters are optimized, including: obtaining the constraints of the target digital circuit; defining a preset search space for a GP-DKL multi-objective hybrid model based on the design parameters and the constraints; performing multiple iterations until a preset iteration stopping condition is reached; wherein each iteration includes: searching the search space, reducing the dimensionality of the search space based on the search results, and updating the model parameters of the GP-DKL multi-objective hybrid model; wherein, in the initial iteration, the search space is searched using the point in the search space mapped by the initial parameter values ​​of the design parameters as the initial point; outputting the parameter values ​​of each design parameter corresponding to the optimal point found by the GP-DKL multi-objective hybrid model when the iteration stopping condition is reached; the optimized design parameters are the parameter values ​​of each design parameter corresponding to the optimal point.

[0045] Optionally, the search space is dimensionality reduced based on the search results, including: determining the target model parameters in the model parameters of the GP-DKL multi-objective hybrid model based on the search results; the target model parameters include model parameters whose change during the update process is less than a preset change threshold; and merging the design parameters corresponding to the target model parameters into one dimension.

[0046] Optionally, the target model parameters in the model parameters of the GP-DKL multi-objective hybrid model are determined based on the search results, including: determining the upper bound of the confidence interval (UCB) of each search result; and merging the design parameters corresponding to the target model parameters in the model parameters of the GP-DKL multi-objective hybrid model when the UCB is maximized into one dimension.

[0047] Optionally, dimensionality reduction of the search space based on the search results further includes: dimensionality reduction of the search space using a random projection matrix before determining the upper bound of the confidence interval (UCB) of each search result.

[0048] Optionally, the input layer of the GP-DKL multi-objective hybrid model is embedded with an attention module; the random projection matrix is ​​updated according to the attention weight matrix output by the attention module.

[0049] Optionally, when using the random projection matrix to reduce the dimensionality of the search space, a Pareto front is output; the method further includes: calculating the expected hypervolume improvement EHVI index by jointly predicting the probability distribution of multiple preset chip performance indicators based on the GP-DKL multi-objective hybrid model; using the EHVI index as the acquisition function, selecting candidate points based on the acquisition function during the random projection dimensionality reduction process, and updating the Pareto front according to the candidate points that maximize the EHVI index.

[0050] Optionally, generating a netlist file based on the functional description includes: obtaining a behavioral-level parameter model, a system-level parameter model, and an RTL-level parameter model based on the functional description; the behavioral-level parameter model includes behavioral-level parameters, the system-level parameter model includes system-level parameters, and the RTL-level parameter model includes RTL-level parameters; establishing dependencies between the parameters in the behavioral-level parameter model, the system-level parameter model, and the RTL-level parameter model to obtain a chip parameter set; optimizing the chip parameter set based on the dependencies to obtain a target chip parameter set that ensures the target digital circuit has no timing violations; and outputting the netlist file based on the target chip parameter set.

[0051] Optionally, obtaining the system-level parameter model based on the functional description includes: obtaining each system-level parameter based on the functional description; converting each system-level parameter into a data flow graph-level intermediate representation (IR), a loop nesting level IR, and an instruction operation level IR according to their correspondence with data flow graphs, nested loops, and instruction operation levels; and performing orthogonalization processing on the parameters corresponding to the data flow graph-level IR, the nested loop-level IR, and the instruction operation level IR to obtain the system-level parameter model.

[0052] Optionally, parsing the metal layer rules from the PDK includes: converting the PDK into a text file; and extracting the metal layer rules from the text file using regular expressions.

[0053] Optionally, the RC parameters of the metal layer corresponding to different process angles are parsed from the PDK, including: extracting the RC parameters of the metal layer corresponding to different process angles from the text file.

[0054] Optionally, the method further includes: before generating constraint files corresponding to each process corner based on the constraint map and the metal layer RC parameters, detecting whether there are constraint conflicts in the constraint map; if there are constraint conflicts, regenerating a new netlist file based on the functional description, converting the new netlist file to obtain the constraint map, and detecting whether there are constraint conflicts in the constraint map; if there are no constraint conflicts, generating constraint files corresponding to each process corner based on the constraint map and the metal layer RC parameters.

[0055] This application also provides an electronic device, including a processor and a memory, wherein the processor is used to execute one or more program modules stored in the memory to implement any of the above-described fully automated digital circuit design methods.

[0056] This application also provides a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement any of the above-described fully automated digital circuit design methods.

[0057] This application also provides a computer program product, which includes computer program code. When the computer program code is run on a processor, it implements the functions of each module in any of the above-described digital circuit design systems. Attached Figure Description

[0058] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1 A basic structural diagram of a digital circuit design system provided in this application embodiment;

[0060] Figure 2 A schematic diagram of the basic structure of another digital circuit design system provided in this application embodiment;

[0061] Figure 3 A schematic diagram of the basic structure of another digital circuit design system provided in this application embodiment;

[0062] Figure 4 A schematic diagram of a parameter optimization process provided for an embodiment of this application;

[0063] Figure 5 A schematic diagram of a digital circuit design system with an input parsing module provided in this application embodiment;

[0064] Figure 6 This application provides a schematic diagram of the output process of a netlist file.

[0065] Figure 7 A schematic diagram of the structure of a specific digital circuit design system provided in this application embodiment;

[0066] Figure 8 A basic flowchart of a fully automated digital circuit design method provided in this application embodiment;

[0067] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0068] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0069] To facilitate understanding of the solutions and advantages of the embodiments of this application, the relevant technologies will be introduced and explained below:

[0070] The current mainstream technical solution in the field of digital integrated circuit design is a phased design flow based on discrete toolchains. Its core architecture can be summarized into the following three levels:

[0071] 1. Serial collaboration mode of fragmented toolchain. The traditional process adopts a discrete architecture of "logic synthesis - physical implementation - signature verification", involving more than 20 heterogeneous tool modules.

[0072] A typical toolchain includes the following stages: Logic synthesis stage: Design Compiler (DC, an EDA tool) completes the RTL to gate-level netlist conversion, relying on Static Timing Constraints (SDC) and Wire Load Model (WLM) to estimate routing parameters; Physical implementation stage: Innovus / ICC2 (Innovus and ICC2 are each EDA tools) perform placement and routing, passing physical library parameters and placement information through LEF (Library Exchange Format, a file that abstracts and describes standard cell layouts, used by automatic placement and routing tools) / DEF (Module Definition File) files; Sign-off and verification stage: PrimeTime (an EDA tool) performs STA (Static Timing Analysis), StarRC (an EDA tool) extracts parasitic parameters, and RedHawk (an EDA tool) performs power integrity verification. The tools use non-standardized data interfaces. Logic synthesis outputs Verilog (a hardware description language) netlists and SDC constraints, while the place-and-route tools input DEF physical placement files and LEF process library files. The STA tool relies on SPEF (Standard Parasitic Exchange Format, a standardized file used to describe the parasitic parameters (resistance, capacitance, inductance) of interconnects in chip design) parasitic parameter files and SDC timing constraints. In this approach, design data needs to undergo multiple format conversions, and there are systematic deviations in constraint information when it is transferred between tools, making it difficult to guarantee constraint consistency.

[0073] 2. Physical implementation mechanism tightly coupled with process technology. Existing solutions are deeply bound to the PDK of specific process nodes, requiring reconstruction of the physical design rule mapping during process migration. However, this mechanism is costly for process migration. For example, 7nm process migration adaptation requires rewriting more than 65% of the physical design rule mapping code.

[0074] 3. Parameter Optimization Mechanism. Existing technologies employ a hierarchical optimization strategy. In the logic synthesis stage, gate-level optimization is performed based on a cost function with weighted coefficients. In the physical implementation stage, mixed-integer programming is used for cell placement, and routing is performed based on the A* algorithm. In the timing convergence stage, iterative buffer insertion and size adjustment are used to repair violation paths. However, the optimization objectives of each stage are independent of each other, lacking the ability to search for a global Pareto optimal solution.

[0075] In response to the above situation, this application provides a digital circuit design system to solve at least some of the above problems.

[0076] See Figure 1 As shown, a digital circuit design system may include a process abstraction interface module, which is used for:

[0077] Obtain the PDK of the target process used in the target digital circuit; parse the metal layer rules from the PDK; convert the metal layer rules into coefficients of the minimum linewidth unit of the process to obtain the process parameter template; generate the physical design rules and rule check scripts corresponding to the target process based on the process parameter template.

[0078] In this embodiment, the target digital circuit refers to the digital circuit that needs to be designed. The target technology can be specified by the user in the functional description when outputting the relevant functional description of the target digital circuit, or it can be specified separately by the user. If not specified, the default technology in the system can be used as the target technology to obtain the PDK of the target technology.

[0079] In this embodiment, the process abstraction interface module can convert the PDK into a text file and use regular expressions to extract the metal layer rules from the text file.

[0080] For example, the process abstraction interface module can convert the PDK into a text file described in a common language by calling the rule converter.

[0081] In this embodiment of the application, the PDK can be, but is not limited to, TSMC iPDK, and the converted text file includes, but is not limited to, URDL file.

[0082] In addition, in the embodiments of this application, the process abstraction interface module may also use other methods to parse the metal layer rules from the PDK. For example, a trained information extraction model can be used to parse the metal layer rules from the PDK, but this is not a limitation.

[0083] In this embodiment of the application, the process abstraction interface module can be pre-set with a standard parameter template. When converting the metal layer rules into coefficients of the minimum linewidth unit of the process, the rule restrictions of each metal layer can be divided by the minimum linewidth unit of the process according to the metal layer rules to obtain the corresponding system and fill it into the preset parameter template to obtain the process parameter template.

[0084] In this embodiment, the process abstraction interface module can call a rule compiler (such as a DRC (Design Rule Check) rule compiler, an LVS (Layout versus Schematic) rule compiler, etc.) to convert the process parameter template into physical design rules and machine-readable rule check scripts based on the target process.

[0085] In this embodiment, based on the process abstraction interface module, the metal layer rules can be constructed into a process parameter template represented by a coefficient of the minimum linewidth unit of the process. This process parameter template is represented by a coefficient of the minimum linewidth unit of the process and is independent of the process itself. Therefore, when performing process migration, the physical design rules and rule checking scripts are generated directly based on the coefficient of the minimum linewidth unit of the process, without rewriting the physical design rules, which reduces the cost of process migration and thus solves the problem existing in the second level mentioned above to a certain extent.

[0086] In the embodiments of this application, such as Figure 2 As shown, the digital circuit design system may also include: an intelligent constraint transfer module.

[0087] The intelligent constraint transfer module is used to: receive the netlist file of the target digital circuit and convert it into a constraint map based on the netlist file; extract the metal layer RC parameters corresponding to different process corners from the PDK; and generate constraint files corresponding to each process corner based on the constraint map and the metal layer RC parameters.

[0088] In this embodiment, the constraint graph can be a directed acyclic graph, including nodes representing design objects and edges representing timing, power, or physical constraints between the design objects. The edges in the constraint graph have the property of defining constraints, thereby enabling the definition of constraints. The design objects in the constraint graph include the modules in the target digital circuit recorded in the netlist file, and the nodes in the constraint graph can be constructed based on the modules in the target digital circuit recorded in the netlist file.

[0089] In this embodiment, the netlist file of the target digital circuit carries not only component descriptions, connection descriptions, and chip parameter descriptions, but also constraint information to facilitate the construction of constraint images. For example, the netlist file may carry, but is not limited to, SDC constraint information and CPF constraint information.

[0090] In this embodiment, the netlist file can be a group of files, and the constraint information can be located in the netlist file as a separate file.

[0091] Optionally, in this embodiment, the intelligent constraint transfer module can use graph neural networks or other methods to process the netlist file, obtain the constraint relationships in the netlist file, and model them into a constraint graph.

[0092] In this embodiment of the application, each node in the constraint graph can be represented by IR (Intermediate Representation), and recorded in the constraint file based on the constraint graph or the intermediate representation in the constraint graph, so as to facilitate the identification of each EDA tool.

[0093] Optionally, in this embodiment, the intelligent constraint transfer module may extract the RC parameters of the metal layer corresponding to different process angles from the text file converted from PDK.

[0094] In this embodiment, based on the intelligent constraint transfer module, constraint graph conversion ensures that the transferred constraint files are generated and transferred using intermediate representations in the constraint graph, thereby improving constraint consistency and improving the efficiency of digital circuit design, and to some extent solving the problem at the first level mentioned above.

[0095] Optionally, in this embodiment, the intelligent constraint transfer module can also be configured with a verification mechanism to improve the usability of the generated constraint file by detecting whether there are constraint conflicts.

[0096] For example, when the intelligent constraint transfer module receives the netlist file of the target digital circuit and converts it into a constraint map, it can detect whether there are constraint conflicts in the constraint map. If there are constraint conflicts, it sends feedback to the netlist file provider to obtain a new netlist file of the target digital circuit and converts it into a new constraint map. It then checks whether there are constraint conflicts in the new constraint map. If there are no constraint conflicts in the new constraint map, it generates constraint files corresponding to each process corner based on the new constraint map and the RC parameters of the metal layer.

[0097] Optionally, in this embodiment of the application, a graph matching algorithm may be used to detect whether there are constraint conflicts in the constraint graph, but this is not a limitation.

[0098] In some optional embodiments of this application, the netlist file provider can be a user, and the intelligent constraint transfer module can provide the user with constraint conflict information so that the user can adjust the netlist file.

[0099] In addition, in some alternative embodiments, the netlist file provider can also be the input parsing module described later. The intelligent constraint transmission module can feed back constraint conflict information to the input parsing module to trigger the input parsing module to re-execute the netlist file acquisition process. The specific implementation and functions of the input parsing module are described later and will not be repeated here.

[0100] In the embodiments of this application, see Figure 3 As shown, a digital circuit design system may also include an EDA toolchain module and a multi-objective optimization module.

[0101] The EDA toolchain module includes multiple EDA tools that implement different functions of digital circuit design. It is used to sequentially call each EDA tool to implement the physical implementation of the target digital circuit according to the preset EDA tool calling logic, constraint file, physical design rules and rule checking script, and output the physical implementation results.

[0102] Unlike the traditional manual invocation method, this embodiment of the application realizes the linking and scheduling of multiple EDA tools through the EDA toolchain module, realizing the automated serial invocation of each EDA tool, and using constraint maps and metal layer RC parameters to generate constraint files corresponding to each process corner, the intermediate expression is converted into the format requirements of each EDA tool, reducing transmission deviation and improving the constraint consistency in the overall scheduling process.

[0103] In this embodiment of the application, the EDA toolchain module can call all EDA tools used in each stage of logic synthesis, physical implementation, and signature verification.

[0104] In the embodiments of this application, the EDA toolchain module can be pre-set with EDA tool calling logic for different types of digital circuits, and the corresponding EDA tool calling logic can be selected according to the type of the target digital circuit.

[0105] For example, the EDA tool invocation logic can be implemented using TCL (Tool Command Language) scripts.

[0106] For example, in the embodiments of this application, the EDA toolchain module can integrate Genus (an EDA tool) in the logic synthesis stage, perform logic synthesis through Genus, and use the automatic placement and routing engine of OpenROAD (an EDA tool) or innovus (an EDA tool) to perform placement and routing, and use a machine learning model to perform macro cell conflict detection, optimize macro cell placement, and use PrimeTime (an EDA tool) to perform static timing analysis to complete the approval analysis.

[0107] For example, during execution, the EDA toolchain module can retrieve the RTL code from the netlist file, call Genus to perform timing-driven synthesis, and insert clock-gated cells. Then, it uses Innovus to call the dynamic configuration engine to generate power networks according to the PDK and uses a machine learning model to optimize macrocell placement. Next, it calls the path recognition model to identify critical paths, inserts buffers to reduce timing violations, and performs DRC checks. After the DRC check passes, it uses PrimeTime for static timing analysis, completes the approval analysis, outputs an EM / IR report, and enters the multi-objective optimization stage of the multi-objective optimization module.

[0108] In this embodiment, the multi-objective optimization module is used to: optimize the design parameters to obtain optimized design parameters; the design parameters include chip parameters and process parameters in the physical implementation results, as well as EDA tool parameters of each EDA tool; provide the process parameters in the design parameters to the process abstraction interface module to update the process parameter template; output the chip parameters in the design parameters to the netlist file provider to update the netlist file; and output the EDA tool parameters in the design parameters to the EDA toolchain module to update each EDA tool.

[0109] In this embodiment, design parameters are a collective term for all parameters involved in the digital circuit design phase. Chip parameters refer to chip function-related parameters required to obtain the netlist file, such as area, frequency, and bandwidth. Process parameters refer to parameters that cannot be obtained from the netlist file when the process abstraction interface module generates the process parameter template. EDA tool parameters refer to the configuration parameters in various EDA tools.

[0110] In this embodiment, the design parameters are optimized through a multi-objective optimization module, and the process parameter template, netlist file, and EDA tool parameters of each EDA tool are updated. By continuously iterating and updating the process parameter template, netlist file, and EDA tool parameters of each EDA tool, the reliability of the digital circuit design can be continuously improved, making the final digital circuit more reliable.

[0111] In this embodiment, a loop termination condition can be preset. When the loop termination condition is met, the physical implementation result is no longer input into the multi-objective optimization module for optimization, but the final physical implementation result of the target digital circuit is directly output to complete the design.

[0112] For example, loop termination conditions may include: performance metric convergence, such as the combined value of the chip's key performance metric PPA, or the Pareto front's improvement over N consecutive iterations being less than a preset threshold, indicating that the optimization has plateaued and further searches yield little benefit; or resource budget exhaustion, such as reaching the maximum number of iterations or exhausting the total computation time. This ensures that the design flow will inevitably terminate within limited time and computational resources.

[0113] Furthermore, in this embodiment, the multi-objective optimization module optimizes all design parameters uniformly, which differs from the hierarchical optimization strategy used in the prior art. By unifying the optimization objectives of each stage and using a multi-objective optimization approach, the global Pareto optimal solution search capability can be improved.

[0114] In this embodiment, the EDA tool includes a logic synthesis tool that performs logic synthesis using a line load model. The intelligent constraint propagation module can also be used to propagate the line length from the physical implementation result to the logic synthesis tool to update the line load model. This achieves dynamic backpropagation of the line length parameter, thereby improving the reliability of the line load model in the next iteration and making the final digital circuit more reliable.

[0115] With the rapid development of artificial intelligence and big data applications, the number of parameters involved in digital circuit design is increasing exponentially. When optimizing all design parameters in a unified manner, high-dimensional parameter optimization problems are inevitably involved.

[0116] Therefore, in this embodiment, the multi-objective optimization module can use a GP-DKL multi-objective hybrid model to optimize the various design parameters in the physical implementation result. In this way, GP can capture the linear characteristics of the optimization process, while DKL can capture the nonlinear characteristics. Thus, high-dimensional parameter optimization using the GP-DKL multi-objective hybrid model can more comprehensively capture feature information and improve the optimization effect.

[0117] For example, the multi-objective optimization module can be specifically used to achieve optimization through methods such as... Figure 4 The method shown employs a GP-DKL multi-objective hybrid model to optimize each design parameter:

[0118] S401: Obtain the constraints of the target digital circuit.

[0119] In the embodiments of this application, the constraints of the target digital circuit can be manually input by the user or obtained from the netlist file of the target digital circuit.

[0120] S402: Determine the search space of the preset GP-DKL multi-objective hybrid model based on the design parameters and constraints.

[0121] In this embodiment, the multi-objective optimization module can construct a multi-dimensional search space based on the design parameters. For example, assuming there are 100 design parameters, the multi-objective optimization module can construct a 100-dimensional search space based on these 100 design parameters, where each dimension represents a design parameter.

[0122] In this embodiment, the multi-objective optimization module can determine the boundary of the constructed multi-dimensional search space based on constraints, thereby obtaining the final search space. For example, assuming the constraints specify that the design parameter A ranges from A1 to A2, the multi-objective optimization module can limit the range of dimension A in the search space to A1 to A2. For other design parameters, boundaries are constructed in the search space in a similar manner to obtain the final search space.

[0123] S403: Perform multiple iterations until the preset iteration stop condition is met.

[0124] Each iteration includes: searching the search space, reducing the dimensionality of the search space based on the search results, and updating the model parameters of the GP-DKL multi-objective hybrid model.

[0125] In the initial iteration, the search space is searched starting from the point in the search space mapped to the initial parameter values ​​of the design parameters.

[0126] In this embodiment, the multi-objective optimization module continuously searches the search space and updates the model parameters of the GP-DKL multi-objective hybrid model based on the search results. As the GP-DKL multi-objective hybrid model is updated, the search accuracy of the GP-DKL multi-objective hybrid model becomes higher and higher, and it is also easier to find design parameters that meet the optimization objectives, thereby improving the efficiency of parameter optimization.

[0127] In this embodiment, considering the numerous types of design parameters and the high dimensionality of the search space during chip design, iterative optimization using only the GP-DKL multi-objective hybrid model would be extremely time-consuming and unacceptable. Therefore, in this embodiment, during each iteration, the multi-objective optimization module can reduce the dimensionality of the search space based on the search results. This improves both the parameter optimization effect and the optimization speed through dimensionality reduction, thereby meeting the high-dimensional parameter optimization requirements in chip design.

[0128] In this embodiment, when the multi-objective optimization module searches the search space, it can find one or more search points in the search space. Each search point is a point in the search space, and the search results for each search point are calculated using the GP-DKL multi-objective hybrid model. The search results are the chip performance values ​​corresponding to the search points, which are used to characterize the predicted chip performance of the target digital circuit when the chip is designed according to the design parameters corresponding to the search point.

[0129] Optionally, in this embodiment, the chip performance value can be represented by the comprehensive index value PPA of the chip's performance, power consumption, and area.

[0130] In some optional embodiments of this application, the multi-objective optimization module can determine the sensitivity of each design parameter based on the search results and merge design parameters with sensitivity below a preset sensitivity threshold into one dimension. Here, sensitivity characterizes the degree to which changes in each design parameter affect the search results.

[0131] The sensitivity can be calculated using the sensitivity function in the GP-DKL multi-objective mixture model.

[0132] For example, sensitivity can be defined as the reciprocal of the length scale parameter learned based on the ARD kernel function.

[0133] In this way, by determining the sensitivity of each design parameter to the search results during the search process, design parameters with sensitivity below a preset sensitivity threshold are merged into a single dimension. This allows for the continuous merging of dimensions with minimal impact on the search results during dimensionality reduction, thereby reducing the impact of dimension merging on search accuracy and improving the reliability of the final optimization results.

[0134] In some optional embodiments of this application, when reducing the dimensionality of the search space based on the search results, the multi-objective optimization module can also determine the target model parameters in the model parameters of the GP-DKL multi-objective hybrid model based on the search results, and merge the design parameters corresponding to the target model parameters into one dimension. The target model parameters are model parameters whose change during the update process is less than a preset change threshold.

[0135] In one exemplary embodiment of this optional implementation, when the target model parameter in the model parameters of the GP-DKL multi-objective hybrid model is determined based on the search results, the UCB of each search result can be determined. Then, the design parameters corresponding to the target model parameter in the model parameters of the GP-DKL multi-objective hybrid model where the UCB is maximized are merged into one dimension. The target model parameter is the model parameter whose change during the update process is less than a preset change threshold.

[0136] In this way, the merged dimensions are least sensitive to the changes in the parameters of the GP-DKL multi-objective hybrid model, which means that the merged dimensions have the least impact on the search results. This reduces the impact of dimension merging on search accuracy and improves the reliability of the final tuning results.

[0137] In the above optional implementation, the multi-objective optimization module may use an improved multi-armed slot machine algorithm to determine the UCB of each search result, but this is not a limitation.

[0138] In one optional exemplary embodiment of the above-described optional implementation, before determining the upper bound (UCB) of the confidence interval for each search result, the multi-objective optimization module may first use a random projection matrix to reduce the dimensionality of the search space. This allows for a certain degree of coarse-grained dimensionality reduction through the random projection matrix, followed by finer-grained dimensionality reduction using the UCB, thus improving both the speed and accuracy of dimensionality reduction.

[0139] Optionally, in the above-described optional implementation, the input layer of the GP-DKL multi-objective hybrid model can also embed an attention module. The attention weight matrix output by the attention module is used to update the random projection matrix. Thus, by embedding an attention module in the input layer of the GP-DKL multi-objective hybrid model, key parameters in the design parameters can be effectively identified, and the random projection matrix can be updated based on the attention weight matrix output by the attention module. This allows more key parameter dimensions to be retained each time dimensionality reduction is performed using the random projection matrix, preserving more key parameter information in the reduced low-dimensional space, suppressing the influence of noise dimensions, and improving the optimization accuracy and reliability of the optimized design parameters.

[0140] The attention module can be implemented using existing attention networks, which will not be elaborated here.

[0141] In the above optional implementation, when using a random projection matrix to reduce the dimensionality of the search space, a Pareto front can be output (each solution (i.e., candidate point) in the Pareto front reflects the optimal dimensionality reduction method when using the random projection matrix to reduce the dimensionality of the search space; dimensionality reduction is performed based on the solutions in the Pareto front). In this embodiment, the multi-objective optimization module can update the Pareto front based on the EHVI index and the confidence interval of the GP-DKL multi-objective mixture model, thereby performing dimensionality reduction based on the updated Pareto front.

[0142] Optionally, the EHVI index can be calculated by jointly predicting the probability distribution of multiple preset chip performance indicators based on the GP-DKL multi-objective hybrid model; the EHVI index can be used as the acquisition function to select candidate points during the random projection dimensionality reduction process, and the Pareto front can be updated based on the candidate points that maximize the EHVI index.

[0143] For example, the process of updating the Pareto front based on the EHVI metric and the confidence interval of the GP-DKL multi-objective hybrid model can be as follows: First, an independent model is built for each optimization objective. For multiple performance metrics of the chip design, an independent GP-DKL surrogate model is built and trained for each metric. Therefore, for any candidate design parameter point, we can obtain the probability distribution of its performance predictions, i.e., the confidence interval, from multiple models. Second, the EHVI is calculated as the acquisition function. In each iteration, when it is necessary to select the "most valuable" parameter point for the next EDA simulation, the EHVI is used as the acquisition function. The calculation of EHVI utilizes both the currently known Pareto optimal solution set and the GP-DKL model's predicted distribution for new candidate points. It calculates the expected improvement that the true PPA value of a new candidate point can bring to the "hypervolume" enclosed by the current Pareto front through a multidimensional integral. Finally, the candidate point that maximizes the EHVI value is selected as the next point for actual simulation. Once the true PPA value of a candidate point is obtained through simulation using EDA tools, this true PPA point will be used to update the current Pareto optimal solution set. Simultaneously, this new observation data will also be added to the training dataset to update the GP-DKL model.

[0144] In this way, by utilizing the confidence interval information of the GP-DKL model, EHVI can intelligently strike a balance between "exploration" and "utilization," thereby more efficiently pushing the Pareto front towards a better direction. Furthermore, updating the Pareto front using the confidence intervals of the EHVI and GP-DKL multi-objective hybrid model can improve the coverage of the Pareto front, thus enhancing the model's ability to fine-tune design parameters and increasing the reliability of the final optimized design parameters.

[0145] In some optional embodiments of this application, when performing each iteration, the multi-objective optimization module may first obtain the current ROI, and then search within the current ROI to improve search accuracy and reduce the probability of invalid search.

[0146] In this optional implementation, at the end of each round of search, the multi-objective optimization module can also update the current ROI based on the search results.

[0147] For example, in this optional implementation, the current initial value of ROI (i.e. the current ROI used in the first iteration) can be determined according to the SOM tree of design parameters and constraints, so that the initial ROI can be associated with the initial design parameters and constraints, thereby improving search efficiency.

[0148] Optionally, the process can first sample the search space defined by the design parameters and constraints, and then convert the sampled data into a SOM tree representation. In this way, the data is recursively partitioned and mapped to the nodes of the tree, thus reflecting the hierarchical clustering relationship between the design parameters and constraints.

[0149] Optionally, in this optional implementation, the multi-objective optimization module can convert the design parameters and constraints into a SOM tree representation (sampling the search space defined by the design parameters and constraints, and then converting the sampled data into an SOM tree representation), thereby mapping the data to tree nodes through recursive partitioning. The tree nodes represent the hierarchical clustering relationship between the design parameters and constraints, thereby determining the ROI candidate regions corresponding to each cluster based on the clustering, and filtering the ROI candidate regions, such as removing ROI candidate regions corresponding to sparse regions with node density below a threshold, merging ROI candidate regions corresponding to spatially adjacent and similar clusters, etc., to obtain the final initial value of the current ROI.

[0150] In this embodiment, for example, after each iteration, the current ROI is updated based on the latest search results. First, a new optimal region is located by finding the point that optimizes the chip performance from all currently evaluated parameter points. Then, the ROI center is redefined, and this new optimal point is mapped onto the pre-trained SOM grid to find its corresponding new best-matching unit. Finally, the ROI boundary is updated, and with the new best-matching unit as the new center, the ROI used in the next iteration is determined in a similar manner to when the initial ROI was determined.

[0151] Optionally, in this embodiment, when the multi-objective optimization module searches within the current ROI, it can optimize the continuous and discrete parameters in the design parameters within the current ROI to obtain search points, and then calculate the search results for each search point.

[0152] In this way, by optimizing the continuous and discrete parameters in the design parameters separately to obtain the search point, the problem of low accuracy of the search point obtained when using a single method to uniformly optimize the design parameters can be avoided, thus improving the search efficiency.

[0153] For example, the multi-objective optimization module can use an evolutionary algorithm to optimize continuous parameters in the design parameters within the current ROI, and use a hill-climbing method to adjust discrete parameters in the design parameters to obtain the search point. This not only achieves the aforementioned effects but also improves local search efficiency.

[0154] In this embodiment, the multi-objective optimization module can also optimize continuous and discrete parameters to obtain the search point, and this embodiment does not impose any limitations.

[0155] In some optional embodiments of this application, in each iteration, the multi-objective optimization module may update the model parameters of the GP-DKL multi-objective hybrid model only after searching for N search points in the search space. Furthermore, when updating the model parameters of the GP-DKL multi-objective hybrid model, the optimal target search point among the N search points can be used as the benchmark to update the model parameters. N is an integer greater than or equal to 2.

[0156] For example, the GP-DKL multi-objective hybrid model can be analogized to a function F(x), and the model parameters of the GP-DKL multi-objective hybrid model can be denoted as the coefficients corresponding to each variable in the function F(x). Here, each variable in F(x) is a design parameter, and the coefficients are the model parameters of the GP-DKL multi-objective hybrid model. Updating the model parameters of the GP-DKL multi-objective hybrid model, based on the target search point with the best search result among N search points, can be understood as substituting the parameter values ​​of each design parameter corresponding to the target search point with the best search result among N search points into the variables of the function F(x), and using the search result of the target search point as the value of the function F(x), calculating the coefficient values ​​that satisfy the current function F(x).

[0157] In this way, during each iteration, the target search point with the best search result among N search points is taken as the model update benchmark, and the model parameters of the GP-DKL multi-objective hybrid model are updated. The GP-DKL multi-objective hybrid model that is continuously updated in this way has higher accuracy.

[0158] In some optional embodiments of this application, during each iteration, the multi-objective optimization module can search for M search points in parallel, obtaining search results for the M search points. Here, M is a positive integer less than or equal to N. This reduces the risk of resource idleness, improves resource utilization, and enhances parameter optimization efficiency.

[0159] For example, the value of M can be determined based on the current number of licenses in the EDA tool used. Since the number of licenses reflects the current load of the system, this exemplary method can improve the load balancing of the system to some extent.

[0160] For example, a mapping between the number of licenses and M can be pre-built, thereby determining the value of M in that mapping based on the current number of licenses in the EDA tools used. Since a complete physical implementation task (from synthesis to approval) may require calling multiple different EDA tools, the value of M depends on the "bottleneck" tool in the entire process.

[0161] In some optional embodiments of this application, when the multi-objective optimization module reduces the dimensionality of the search space based on the search results, it can reduce the dimensionality of the search space based only on the latest K search results, where K is an integer greater than or equal to 2, for example, K is 200, thereby avoiding the influence of outdated data on the dimensionality reduction operation and reducing the risk of getting trapped in local optima.

[0162] In the above optional implementation, the multi-objective optimization module can retain only the K most recent search results and delete search results other than the K most recent search results to prevent the use of outdated data and reduce data storage pressure.

[0163] For example, the multi-objective optimization module can determine the sensitivity of each design parameter based solely on the latest K search results, and merge design parameters with sensitivity below a preset sensitivity threshold into a single dimension.

[0164] For example, the multi-objective optimization module can determine the UCB of the latest K search results, and merge the design parameters corresponding to the target model parameters in the model parameters of the GP-DKL multi-objective hybrid model when the UCB is maximized into one dimension.

[0165] S404: Outputs the parameter values ​​of each design parameter corresponding to the optimal point searched by the GP-DKL multi-objective hybrid model when the iteration stopping condition is met.

[0166] In one optional embodiment of this application, the iteration stopping condition may include: the chip performance value (i.e., the search result) reaches a preset optimization target.

[0167] In this optional implementation, the optimization target can be extracted from the functional description of the target digital circuit input by the user, or it can be actively input by the engineer or user. The functional description of the target digital circuit refers to the relevant descriptive information describing the design requirements of the target digital circuit.

[0168] In some optional embodiments of this application, the iteration stopping condition may further include at least one of the following: the iteration time reaches a preset time threshold, and the number of iterations reaches a preset number threshold. When any iteration stopping condition is met, the multi-round iteration is stopped.

[0169] For example, the iteration stopping condition may include the chip performance value reaching a preset optimization target and the iteration time reaching a preset time threshold. When either the chip performance value reaches the preset optimization target or the iteration time reaches the preset time threshold, the multi-round iteration is stopped.

[0170] For example, the iteration stopping condition may include the chip performance value reaching a preset optimization target and the number of iterations reaching a preset threshold. When either the chip performance value reaches the preset optimization target or the number of iterations reaches the preset threshold, the multi-round iteration is stopped.

[0171] For example, the iteration stopping conditions may include the chip performance value reaching a preset optimization target, the iteration time reaching a preset time threshold, and the number of iterations reaching a preset number threshold. When any one of the following is satisfied: the chip performance value reaches the preset optimization target, the iteration time reaches the preset time threshold, or the number of iterations reaches the preset number threshold, the multi-round iteration is stopped.

[0172] In this way, by using the iteration time reaching a preset time threshold or the number of iterations reaching a preset number threshold as the iteration termination condition, the risk of falling into an infinite iteration trap can be avoided, as a combination of design parameters that meets the chip optimization goal cannot be found.

[0173] Optionally, in this embodiment of the application, when the multi-objective optimization module searches the search space, it can search the search space according to the current search radius.

[0174] The search radius refers to the number of search points in a single search. In this embodiment, each iteration may involve one search or multiple searches.

[0175] In this embodiment of the application, after performing a search, the multi-objective optimization module can reduce the dimensionality of the search space based on the search results.

[0176] In this embodiment, when the multi-objective optimization module reduces the dimensionality of the search space based on the search results, it can weight each search result according to its freshness, and then use the weighted search results to reduce the dimensionality of the search space. Specifically, the weight of each search result obtained in the current search is higher than the weight of each search result obtained in previous searches. For example, the weight of each search result obtained in previous searches can be set to A (where A is a preset constant value), and the weight of each search result obtained in the current search can be set to 3 times A. This way, during dimensionality reduction, the most recent search results can be highlighted, and their influence can be strengthened.

[0177] Optionally, in this embodiment, the multi-objective optimization module can also determine the current search radius for the current search based on the chip performance values ​​corresponding to each search point during the previous search.

[0178] For example, when the chip performance value continues to improve, the multi-objective optimization module can determine the current search radius as the search radius obtained by reducing the search radius based on the previous search radius; when the chip performance value continues to deteriorate, the current search radius can be determined as the search radius obtained by increasing the search radius based on the previous search radius.

[0179] Thus, if the chip performance continues to improve, the probability of finding the optimal design parameter combination within the current search area is considered high, thereby reducing the search radius and computational redundancy; if the chip performance continues to deteriorate, the probability of finding the optimal design parameter combination within the current search area is considered low, thereby increasing the search radius and improving the probability of finding the optimal design parameter combination.

[0180] In some optional embodiments of this application, such as Figure 5 As shown, the digital circuit design system can also include an input parsing module to obtain the functional description of the target digital circuit and generate a netlist file based on the functional description. This allows users to automatically generate a netlist file simply by inputting the functional description of the target digital circuit they want to design, eliminating the need for users to write the netlist file themselves. This reduces the knowledge requirements for users, lowers the barrier to entry for the system, and improves the system's versatility.

[0181] In the field of digital circuit design, existing technologies for generating netlist files for programmable modules in digital circuits mainly employ hierarchical independent optimization and static template methods. The core process includes three levels: behavioral optimization, system-level planning, and RTL-level implementation. Behavioral optimization primarily uses high-level language descriptions (such as C / C++ / SystemC) for algorithmic functional modeling, extracts critical path features through static timing analysis, and implements functional mapping using a fixed bit-width allocation strategy and a predefined operator library. System-level planning mainly uses a template-based interconnect architecture generation method, allocating bandwidth resources through pre-defined NoC topology templates and using heuristic algorithms for deep configuration of inter-module communication channels. RTL-level implementation relies on EDA (Electronic Design Automation) tools, employing rule-based RTL code generation technology and achieving physical constraint binding through a hard-coded parameter passing mechanism.

[0182] All three levels involve optimizing the chip parameters required for generating the netlist file, and the chip parameters at each level are optimized independently. This means that adjusting chip parameters across levels requires manually synchronizing configurations across multiple levels, which can easily lead to inconsistent chip parameter versions and impact design efficiency.

[0183] To address this issue, in one optional embodiment of this application, the input parsing module can employ, as follows: Figure 6 The netlist file for the target digital circuit is generated by processing it in the following manner:

[0184] S601: Obtain the functional description of the target digital circuit.

[0185] In this embodiment of the application, the functional description of the target digital circuit to be designed can be obtained by the user speaking or inputting text.

[0186] In the embodiments of this application, the functional description may be, but is not limited to, a description in natural language.

[0187] S602: Based on the functional description, obtain the behavioral-level parameter model, system-level parameter model, and RTL-level parameter model.

[0188] In the embodiments of this application, the behavioral-level parameter model includes behavioral-level parameters, the system-level parameter model includes system-level parameters, and the RTL-level parameter model includes RTL-level parameters. Behavioral-level parameters refer to parameters at the behavioral level, i.e., the parameters in the behavioral-level optimization process described above. System-level parameters refer to parameters at the system level, i.e., the parameters in the system-level planning process described above. RTL-level parameters refer to parameters at the RTL level, i.e., the parameters in the RTL-level implementation process described above.

[0189] In this embodiment, the input parsing module can extract behavioral-level features based on the functional description, and then construct a behavioral-level parameter model based on the behavioral-level features. The behavioral-level features represent the features in the functional description related to the functions that the target digital circuit needs to achieve.

[0190] For example, a natural language model can be pre-trained, and the input parsing module can use this natural language model to understand and recognize the functional description, and extract the behavioral features in the functional description.

[0191] For example, suppose a function is described as "a GPU needs to be designed with a frequency no lower than A and an area no greater than B". Then the behavioral features can be extracted as follows: frequency, with a value greater than or equal to A, and area, with a value less than or equal to B.

[0192] In this embodiment of the application, after obtaining each behavior-level feature, the input parsing module can record the behavior-level features in a text file to obtain the behavior-level parameter model.

[0193] In this embodiment, optionally, after the input parsing module constructs the behavioral-level parameter model based on the behavioral-level features, it can also use a static time-series analysis engine to perform legalization analysis on the behavioral-level parameter model, and update the constraint information of the behavioral-level parameter model if the constraint information is invalid. This reduces the risk of invalid constraints and reduces the difficulty of updating subsequent constraints.

[0194] Optionally, in this embodiment, the functional description may also include system-level features (features that can be used to generate a system-level architecture), such as bit width and bandwidth. Optionally, in this embodiment, a system-level template may be preset, including interconnect architecture and NoC topology templates. Based on the system-level template, the system-level features extracted from the functional description are used to generate the system-level architecture, and a system-level parameter model is obtained. For system-level features not present in the functional description, preset default values ​​or preset default algorithms, such as heuristic algorithms, can be used.

[0195] Optionally, in this embodiment, the input parsing module can record system-level parameters in a text file to obtain a system-level parameter model.

[0196] In some feasible embodiments of this application, the input parsing module can further transform each system-level parameter into a data flow graph-level IR, a loop nesting-level IR, and an instruction operation-level IR according to their correspondence with data flow graphs, loop nesting-level IRs, and instruction operation-level IRs. Then, the parameters corresponding to the data flow graph-level IR, loop nesting-level IR, and instruction operation-level IR are orthogonalized to obtain a system-level parameter model. In this system-level parameter model, each parameter is distinguished through data flow graphs, loop nesting, and instruction operations, and the orthogonalization process establishes inter-parameter dependencies. Therefore, during subsequent optimization, if any system-level parameter is adjusted, its associated other types of system-level parameters will also be adjusted, thereby achieving automated, coordinated optimization of system-level parameters, further improving the reliability of parameter configuration in the chip, and increasing chip design efficiency. Furthermore, the hierarchical structure of the system level is relatively complex, usually containing many small modules. In this feasible implementation, the system is divided into three layers: data flow graph, nested loops, and instruction operations, instead of dividing the system-level parameters into corresponding small modules. This allows the entire system-level parameters to be linked together by establishing dependencies, achieving a better representation of the system level and thus improving the reliability of subsequent parameter optimization.

[0197] Optionally, in this embodiment, the input parsing module can use an existing RTL code automatic generation method to generate RTL code based on the functional description, thereby obtaining the RTL-level parameters in the RTL code.

[0198] Optionally, in this embodiment, the input parsing module can record RTL-level parameters in a text file to obtain an RTL-level parameter model.

[0199] S603: Establishes dependencies between parameters in the behavioral-level parameter model, system-level parameter model, and RTL-level parameter model to obtain the chip parameter set.

[0200] Optionally, in this embodiment, the input parsing module can orthogonalize the parameters in the behavioral-level parameter model, system-level parameter model, and RTL-level parameter model to determine whether there are dependencies between parameters at each level, as well as the specific dependencies and the strength of the association (i.e., the strength of the dependencies).

[0201] In this embodiment, the input parsing module can construct a dependency tree for the orthogonalized parameters, and record the dependencies between parameters in each behavior-level parameter model, system-level parameter model and RTL-level parameter model through the dependency tree.

[0202] In some feasible implementations, during orthogonalization, the input parsing module can assign parameters with intersecting relationships from the behavioral-level parameter model, system-level parameter model, and RTL-level parameter model to the same orthogonal subspace, resulting in multiple orthogonal subspaces. A dependency tree is then constructed for the parameters within each orthogonal subspace. Thus, the parameters in each orthogonal subspace are mutually dependent, and by constructing dependency trees for each subspace, all dependencies between parameters can be comprehensively identified.

[0203] In some optional embodiments of this application, the dependency tree may store parameter value ranges, association strengths, and version identifiers.

[0204] The parameter value range can be obtained when converting to the parameter model of each level, and its value can be defined in the function description or the default value of the configuration.

[0205] The version identifier is used to identify the version of the parameters obtained from the current optimization, and it is updated as the optimization process iterates.

[0206] Optionally, in this embodiment, the parameter combinations obtained in each iteration can be saved and the corresponding version identifier can be recorded.

[0207] In this embodiment, the correlation strength refers to the strength of the dependency relationship between two parameters, which can be determined based on the degree of intersection between the two parameters during orthogonal processing. The higher the degree of intersection between the two parameters, the greater the correlation strength.

[0208] In some optional embodiments of this application, during each iteration, the input parsing module can also calculate the hash value of various parameter combinations and store each parameter combination in association with its hash value. This facilitates rapid retrieval of parameter combinations by calculating and storing the hash values ​​of various parameter combinations, and, combined with version identifiers, facilitates version backtracking of parameters.

[0209] Optionally, in this embodiment, before establishing dependencies between parameters in the behavioral-level parameter model, system-level parameter model, and RTL-level parameter model, the input parsing module can also store each parameter according to the division of the smallest functional unit. When storing each parameter, only one instance of the same parameter corresponding to the same smallest functional unit is saved. This reduces the coupling between parameters during the parameter storage stage, eliminates duplicate parameters, thereby reducing the number of parameters involved in subsequent optimization and improving optimization efficiency.

[0210] S604: Optimize the chip parameter set according to the dependency relationship to obtain the target chip parameter set that ensures that the target digital circuit has no timing violations.

[0211] In this embodiment, the input parsing module can generate a configuration strategy matrix containing priority weights, optimization directions, and constraint boundaries based on a preset constraint library, and then optimize each parameter after establishing the dependency relationship according to the dependency relationship and the configuration strategy matrix.

[0212] In this embodiment, the constraint library can be a pre-established library that records the basic constraints of chip design. The basic constraints of chip design refer to the fundamental constraints that all chip designs must follow.

[0213] In this embodiment of the application, the constraint library can also record the constraints updated in each iteration during the optimization process, thereby continuously updating the constraints during the iteration process, making the constraints in each round of optimization more in line with actual needs, improving the reliability of constraints in each round of optimization, and thus improving the optimization effect.

[0214] Optionally, in this embodiment, the input parsing module can also perform formal verification and simulation coverage testing on the optimized parameters to verify the reliability of the optimized parameters.

[0215] Optionally, in this embodiment, if the verification or test results fail, the constraints in the constraint library can be updated based on the verification or test results. This ensures that the constraints better match the optimization requirements in the next iteration, thereby improving the optimization effect.

[0216] For example, if a timing violation (such as a failure to meet setup time requirements) is found on a critical path during simulation coverage testing, the following updates can be made based on the test results: First, locate the specific parameters causing the timing violation, such as the drive strength or delay of one or more logic units on the path; then, in the constraint library, increase the "priority weight" of these specific parameters and tighten their constraint boundaries (e.g., set a stricter maximum delay constraint value for the path). In this way, in the next iteration of optimization, the optimizer will focus on and prioritize adjusting these parameters to resolve the discovered timing issues, thereby more accurately meeting the optimization requirements.

[0217] Optionally, in this embodiment, the initial constraint information may be extracted from the functional description and included as part of the behavioral-level parameter model. The constraint information includes priority weights, optimization directions, and constraint boundaries.

[0218] In the embodiments of this application, priority weight refers to the priority of each parameter during optimization, and its priority is expressed in the form of weight. Priority weight is negatively correlated with the adjustment range of the parameter and positively correlated with the adjustment accuracy of the parameter.

[0219] In this embodiment, the optimization direction refers to the direction in which parameters are optimized within the parameter combination space, and the constraint boundary refers to the boundary in the parameter combination space when searching for the optimal parameter combination. The parameter combination space refers to a multi-dimensional space constructed from the parameters. For example, with 100 parameters, the parameter combination space is a 100-dimensional space, and each point in this space corresponds to a specific combination of these 100-dimensional parameters.

[0220] Optionally, in this embodiment, during the first iteration, a configuration strategy matrix containing priority weights, optimization directions, and constraint boundaries can be generated based on the constraint information contained in the behavioral parameter model and the basic constraints of chip design in the constraint library.

[0221] In this embodiment, the specific method for generating the configuration strategy matrix can be implemented using existing methods, and no restrictions are imposed in this embodiment.

[0222] Optionally, in this embodiment, when the input parsing module performs formal verification on the optimized parameters, it can employ computational tree logic model checking technology to perform formal verification during the optimization process of each parameter. This allows for the completeness verification of the control logic to be completed during the parameter configuration stage, improving the reliability of the final configured parameters.

[0223] Optionally, in this embodiment, when performing simulation coverage testing on the optimized parameters, test cases can be generated using a preset assertion library. The assertion library records the inputs and outputs when simulation fails during each iteration of the optimization process. Test cases can be generated based on the inputs and outputs recorded in the assertion library when simulation fails, and then used to perform simulation coverage testing on the optimized parameters. This enables automated generation of test cases, thereby shortening the chip design verification cycle.

[0224] In this embodiment of the application, when the chip parameter set is obtained after establishing the dependency relationship, the input parsing module can allocate the parameters with dependency relationship to the same parameter combination space according to the parameter situation of the dependency relationship, so as to obtain multiple parameter combination spaces, each parameter combination space contains the parameters with dependency relationship.

[0225] Each time optimization is performed, the input parsing module can perform global parameter tuning on the parameter combination space and obtain the Pareto front solution set.

[0226] Then, gradient optimization is performed on the Pareto front solution set of each parameter combination space.

[0227] Repeat the above process iteratively until the parameters that are optimal in terms of area and power consumption when there are no timing violations are obtained.

[0228] In this way, the Pareto front solution set is selected through global tuning, and local tuning is achieved through gradient optimization to eliminate timing violations as much as possible. This improves the accuracy of parameter optimization, reduces optimization time, and increases optimization efficiency.

[0229] In this embodiment of the application, in order to obtain the parameters that optimize area and power consumption when there are no timing violations, a weighted objective function including timing margin, area cost, and power consumption can be constructed. For example, the objective function can be: ,in To adjust the coefficient, T slack For timing margin, For area cost, P budget For power consumption. The adjustment factor can be preset or dynamically adjusted; for example, the optimal combination of adjustment factors can be determined through Monte Carlo simulation.

[0230] In this embodiment, the input parsing module can calculate the function values ​​of each parameter combination (i.e., each point in the Pareto front solution set) when there are no timing violations based on the above objective function, and select the parameter combination with the optimal function value.

[0231] Optionally, in some feasible embodiments of this application, when performing global parameter tuning on the parameter combination space, the key parameter combination space can be determined first, and then global parameter tuning can be performed on the key parameter combination space. Correspondingly, when performing gradient optimization on the Pareto front solution set of each parameter combination space, gradient optimization can be performed on the Pareto front solution set of each key parameter combination space separately.

[0232] Among them, the key parameter combination space is the parameter combination space that is currently sensitive to parameter adjustments among all parameter combination spaces.

[0233] In this way, global parameter tuning is performed only for the key parameter combination space, and gradient optimization is performed for the Pareto front solution set of the key parameter combination space. This reduces the number of parameter combinations that need to be tuned, thereby reducing the number of parameters that need to be adjusted and improving the efficiency of parameter optimization.

[0234] In this embodiment of the application, after each iteration, the input parsing module can calculate the sensitivity of each parameter combination space after the current parameter adjustment, and determine the parameter combination space with a sensitivity higher than the preset sensitivity threshold as the key parameter combination space.

[0235] The sensitivity can be calculated using the sensitivity function in existing parameter tuning algorithms.

[0236] Optionally, in this embodiment, the input parsing module may use algorithms such as hybrid genetic algorithm and simulated annealing algorithm for global parameter tuning, but this is not a limitation.

[0237] Optionally, in this embodiment, the input parsing module may retain only non-dominated solutions in the obtained Pareto front solution set. This can reduce the risk of premature convergence and the risk of getting trapped in local optima.

[0238] Optionally, in this embodiment, during each iteration, the input parsing module can reduce the adjustment range of parameters involved in the timing violation path during the previous iteration, thereby performing more refined tuning of the parameters involved in the timing violation path and improving the parameter tuning effect.

[0239] Among them, timing violation paths are paths with timing violations discovered during the verification of chip design in the iteration process.

[0240] Optionally, in the embodiments of this application, when the input parsing module performs gradient optimization on the Pareto front solution set of each parameter combination space, it can determine the adjustment range of each parameter based on the correlation strength of each parameter in the parameter combination space, and perform gradient optimization on the Pareto front solution set based on the adjustment range of each parameter.

[0241] For example, the input parsing module can pre-determine the correlation strength of each parameter to establish a corresponding relationship for the adjustment magnitude of each parameter. Based on this correspondence and the correlation strength, the adjustment magnitude of each parameter is determined, and then gradient optimization is performed according to the adjustment magnitude of each parameter during gradient optimization. For instance, in a parameter combination space, there might be parameter A (assumed to be the driving strength of a logic unit), parameter B (assumed to be the threshold voltage of another unit connected to the aforementioned logic unit), and parameter C (assumed to be the operating frequency of another unrelated module). Suppose that, based on physical characteristics or prior knowledge, parameters A and B are determined to have a strong correlation because they jointly determine the delay of a critical path; while parameter C has a weaker correlation with A and B. In this case, the following correspondence can be pre-determined: for strongly correlated parameters, the adjustment magnitude (i.e., the step size of gradient optimization) is 0.5% of the parameter's value range; for weakly correlated parameters, the adjustment magnitude is 2% of the parameter's value range. Therefore, during gradient optimization, the adjustment steps of A and B will be very small to perform a fine-grained collaborative search; while the adjustment step of parameter C will be relatively large to enable faster exploration in the solution space, thereby improving optimization efficiency while ensuring optimization accuracy.

[0242] S605: Outputs a netlist file based on the target chip parameter set.

[0243] In this embodiment, the input parsing module can generate a programmable module configuration package based on the target chip parameter set. The programmable module configuration package may include a parameterized RTL code template and a cross-level parameter linkage table. The parameterized RTL code template is obtained by filling the target chip parameter set into RTL code generated based on the functional description, and the cross-level parameter linkage table can be constructed based on the dependencies described above. The parameterized RTL code template and the cross-level parameter linkage table are output in the form of a netlist file.

[0244] In this embodiment of the application, the input parsing module can also generate a physical implementation constraint file based on the last updated constraint conditions, and output the physical implementation constraint file as part of the netlist file.

[0245] Optionally, in the embodiments of this application, such as Figure 7 As shown, a digital circuit design system may also include an intelligent control module.

[0246] The intelligent control module is connected to the process abstraction interface module, the multi-objective optimization module, the EDA toolchain module, and the intelligent constraint transfer module, respectively. It is used to manage the dependencies of tasks based on the directed acyclic graph and capture the return codes of the EDA tools. If the return code indicates an error, it will trigger the constraint rollback or parameter reset of the corresponding EDA tool.

[0247] Among them, the process abstraction interface module, multi-objective optimization module, EDA toolchain module, and intelligent constraint transfer module work together to output the result of a physical realization as a task.

[0248] In this embodiment of the application, each module in the digital circuit design system is a software functional module that can be stored in a memory or embedded in the operating system of an electronic device having a digital circuit design system in the form of software or firmware.

[0249] In the embodiments of this application, the modules in the digital circuit design system can be provided to the user as a whole, or selectively provided in parts for the user to use.

[0250] In this embodiment of the application, an electronic device, such as a server or host, is also provided, in which the aforementioned digital circuit design system is arranged. Each module of the digital circuit design system is stored in the memory of the electronic device, and its function is implemented by the processor during execution.

[0251] In this application embodiment, an electronic device cluster, such as a server cluster, is also provided. The modules of the aforementioned digital circuit design system are respectively deployed in different electronic devices of the electronic device cluster, so that the processor of the electronic device can implement the functions of each module when it executes.

[0252] In this application embodiment, a cloud service system is also provided, including a cloud and a client. The aforementioned digital circuit design system is deployed in the cloud, and users access the cloud through the client to call and execute various modules.

[0253] As mentioned earlier, the mainstream technical solution in the current field of digital integrated circuit design is a phased design process based on discrete toolchains. Therefore, the design process of a digital circuit requires the participation of different professional and technical personnel in multiple stages such as front-end and back-end, which has a very high design threshold.

[0254] Based on the embodiments of this application Figure 5 and Figure 7 The digital circuit design system shown can be realized by the cooperation between the modules. Users only need to input the functional description of the target digital circuit (such as area requirements, power consumption requirements, frequency requirements, bandwidth requirements, etc.) to realize the fully automated digital circuit design process, which reduces the design difficulty of digital circuits.

[0255] Based on this, this application also provides a fully automated digital circuit design method, see [link to relevant documentation]. Figure 8 As shown, it includes:

[0256] S801: Obtain the functional description of the target digital circuit and generate a netlist file based on the functional description.

[0257] S802: Obtain the process design package (PDK) of the target process used in the target digital circuit, and parse the metal layer rules from the PDK.

[0258] S803: Convert the metal layer rules into coefficients representing the minimum linewidth unit of the process to obtain the process parameter template.

[0259] S804: Generate physical design rules and rule check scripts corresponding to the target process based on the process parameter template.

[0260] S805: Obtain the constraint map from the netlist file, and parse the RC parameters of the metal layer corresponding to different process angles from the PDK.

[0261] S806: Generate constraint files for each process corner based on the constraint map and the RC parameters of the metal layer.

[0262] S807: Following the preset EDA tool call logic, constraint file, physical design rules and rule check script, it sequentially calls each EDA tool to realize the physical implementation of the target digital circuit and obtains the physical implementation result.

[0263] In some optional embodiments of this application, after outputting the physical implementation result, the method may further include: optimizing each design parameter.

[0264] In some optional embodiments of this application, after optimizing the design parameters, the method may further include:

[0265] The process parameters in the design parameters are provided to the process abstraction interface module to update the process parameter template. The chip parameters in the design parameters are output to the netlist file provider to update the netlist file. The EDA tool parameters in the design parameters are output to the EDA toolchain module to update each EDA tool.

[0266] Regenerate the physical design rules and rule check scripts corresponding to the target process based on the process parameter template;

[0267] The constraint map was reconstructed from the netlist file, and the RC parameters of the metal layer corresponding to different process angles were parsed from the PDK.

[0268] Based on the constraint map and the RC parameters of the metal layer, the constraint files corresponding to each process corner are regenerated;

[0269] The system re-follows the preset EDA tool call logic, constraint files, physical design rules, and rule check scripts, sequentially calling each EDA tool to implement the physical implementation of the target digital circuit and obtain the physical implementation results.

[0270] Optimize each design parameter;

[0271] Determine if the preset loop termination condition has been met; if not, repeat the above operation; if it has been met, output the physical implementation result after design parameter optimization.

[0272] In some optional embodiments of this application, the EDA tool includes a logic synthesis tool that performs logic synthesis using a line load model; when the physical implementation result is obtained and the preset loop termination condition is not met, the method may further include: passing the line length in the physical implementation result to the logic synthesis tool to update the line load model.

[0273] In some optional embodiments of this application, the manipulation of optimizing various design parameters may specifically include:

[0274] Obtain the constraints of the target digital circuit;

[0275] The search space of the pre-defined Gaussian process and deep kernel learning GP-DKL multi-objective hybrid model is defined based on the design parameters and constraints.

[0276] Multiple iterations are performed until a preset iteration stopping condition is reached; wherein, each iteration includes: searching the search space, reducing the dimensionality of the search space based on the search results, and updating the model parameters of the GP-DKL multi-objective hybrid model; wherein, in the first iteration, the search space is searched using the points in the search space mapped by the initial parameter values ​​of the design parameters as the initial points;

[0277] Output the parameter values ​​of each design parameter corresponding to the optimal point searched by the GP-DKL multi-objective hybrid model when the iteration stopping condition is met; the optimized design parameters are the parameter values ​​of each design parameter corresponding to the optimal point.

[0278] In some optional embodiments of this application, the process of reducing the dimensionality of the search space based on the search results may include: determining the target model parameters in the model parameters of the GP-DKL multi-objective hybrid model based on the search results; the target model parameters include model parameters whose change during the update process is less than a preset change threshold; and merging the design parameters corresponding to the target model parameters into one dimension.

[0279] In some optional embodiments of this application, determining the target model parameter in the model parameters of the GP-DKL multi-objective hybrid model based on the search results includes: determining the upper bound of the confidence interval (UCB) of each search result; and merging the design parameters corresponding to the target model parameter in the model parameters of the GP-DKL multi-objective hybrid model when the UCB is maximized into one dimension.

[0280] In some optional embodiments of this application, the process of reducing the dimensionality of the search space based on the search results may further include: reducing the dimensionality of the search space using a random projection matrix before determining the upper bound of the confidence interval UCB of each of the search results.

[0281] In some optional embodiments of this application, the input layer of the GP-DKL multi-objective hybrid model is embedded with an attention module; the random projection matrix is ​​updated according to the attention weight matrix output by the attention module.

[0282] In some optional embodiments of this application, when the search space is reduced in dimensionality using the random projection matrix, a Pareto front is output. The method may further include: calculating the desired hypervolume improvement (EHVI) index by jointly predicting the probability distribution of multiple preset chip performance indicators based on the GP-DKL multi-objective hybrid model; using the EHVI index as a sampling function, selecting candidate points based on the sampling function during the random projection dimensionality reduction process, and updating the Pareto front based on the candidate points that maximize the EHVI index.

[0283] In some optional embodiments of this application, the process of generating a netlist file according to the functional description may include:

[0284] Based on the functional description, a behavioral-level parameter model, a system-level parameter model, and an RTL-level parameter model are obtained; the behavioral-level parameter model includes behavioral-level parameters, the system-level parameter model includes system-level parameters, and the RTL-level parameter model includes RTL-level parameters.

[0285] Dependencies are established for parameters in the behavior-level parameter model, the system-level parameter model, and the RTL-level parameter model to obtain a chip parameter set;

[0286] The chip parameter set is optimized based on the dependency relationship to obtain a target chip parameter set that ensures the target digital circuit has no timing violations.

[0287] The netlist file is output based on the target chip parameter set.

[0288] In some optional embodiments of this application, the process of obtaining the system-level parameter model based on the functional description may include:

[0289] The system-level parameters are obtained based on the functional description.

[0290] The system-level parameters are transformed into intermediate representations (IRs) at the data flow graph level, nested loop level, and instruction operation level, according to their correspondence with data flow graphs, nested loops, and instruction operation levels.

[0291] The parameters corresponding to the data flow graph level IR, the nested loop level IR, and the instruction operation level IR are orthogonalized to obtain the system-level parameter model.

[0292] In some optional embodiments of this application, the process of parsing the metal layer rules from the PDK may include: converting the PDK into a text file; and extracting the metal layer rules from the text file using regular expressions.

[0293] In some optional embodiments of this application, the process of parsing the metal layer RC parameters corresponding to different process angles from the PDK may include: extracting the metal layer RC parameters corresponding to different process angles from the text file.

[0294] In some optional embodiments of this application, the method may further include:

[0295] Before generating constraint files for each process corner based on the constraint map and the RC parameters of the metal layer, check whether there are constraint conflicts in the constraint map;

[0296] In the event of a constraint conflict, a new netlist file is generated based on the functional description, and a constraint graph is obtained by converting the new netlist file. The constraint graph is then checked for constraint conflicts.

[0297] In the absence of constraint conflicts, constraint files corresponding to each process corner are generated based on the constraint map and the RC parameters of the metal layer.

[0298] It is understood that the specific entities that perform each operation in the above methods can be found in the description of the specific functions of each module in the previous section on digital circuit design systems, and will not be repeated here.

[0299] The above method can automatically obtain the physical implementation results of the target digital circuit from the functional description of the target digital circuit, realize the full-process automated design of the chip, and reduce the design difficulty of digital circuits.

[0300] It should be understood that, for the sake of brevity, the content described in the previous section on digital circuit design systems will not be repeated in this section on methods, but the relevant content is equally applicable as long as it does not conflict with the methods section.

[0301] Based on the same inventive concept, this application also provides an electronic device, see [link to relevant documentation]. Figure 9 As shown, it includes a processor 901 and a memory 902. Wherein:

[0302] The processor 901 is used to execute one or more programs stored in the memory 902 to implement the above-described fully automated digital circuit design method.

[0303] It is understandable that the processor 901 can be a data processing core such as a GPU (Graphics Processing Unit), CPU (Central Processing Unit), AI (Artificial Intelligence) processor, NPU (Neural Network Processing Unit), ISP (Image Signal Processor), DPU (Display Processing Unit), VPU (Video Processing Unit), or DSP (Digital Signal Processor), or a processor chip used in scenarios involving large-scale data computation. The memory 902 can be RAM (Random Access Memory), ROM (Read-Only Memory), or flash memory. The above are merely examples and should not be construed as limiting this application.

[0304] It's understandable. Figure 9 The structure shown is for illustrative purposes only; the electronic device may also include components that are more advanced than those shown. Figure 9 The more or fewer components shown, or having the same Figure 9 Different configurations are shown. For example, it may also have an internal communication bus for communication between the processor 901 and the memory 902; or it may have an external communication interface, such as a USB (Universal Serial Bus) interface, a CAN (Controller Area Network) bus interface, etc.; or it may have an information display component such as a display screen, but this is not a limitation.

[0305] In the embodiments of this application, the electronic device may be, but is not limited to, a server, a host, a smart terminal device, etc. Furthermore, the electronic device may also be a cluster of electronic devices consisting of multiple servers, multiple hosts, multiple smart terminal devices, servers and hosts, or servers and smart terminal devices.

[0306] Based on the same inventive concept, embodiments of this application also provide a computer-readable storage medium, such as a floppy disk, optical disk, hard disk, flash memory, USB flash drive, SD (Secure Digital Memory Card), MMC (Multimedia Card), etc. This computer-readable storage medium stores one or more programs that implement the various steps of the above-described fully automated digital circuit design method. These one or more programs can be executed by one or more processors to implement the above-described fully automated digital circuit design method. Alternatively, the computer-readable storage medium stores programs for each module of the above-described digital circuit design system. These programs can be executed by one or more processors to implement the functions of each module in the above-described digital circuit design system. Further details will not be elaborated here.

[0307] Based on the same inventive concept, this application also provides a computer program product, which includes computer program code. When the computer program code is run on a processor, it causes the processor to execute the above-described fully automatic digital circuit design method, or, when the computer program code is run on a processor, it implements the functions of each module in the above-described digital circuit design system.

[0308] In this embodiment of the application, the computer program product may be, but is not limited to, program installation packages, APPs, software packages, and other program products.

[0309] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0310] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0311] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0312] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0313] In this article, "multiple" refers to two or more.

[0314] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A digital circuit design system, characterized in that, include: The input parsing module is used for: Obtain the functional description of the target digital circuit, and derive a behavioral-level parameter model, a system-level parameter model, and an RTL-level parameter model based on the functional description; the behavioral-level parameter model includes behavioral-level parameters, the system-level parameter model includes system-level parameters, and the RTL-level parameter model includes RTL-level parameters. Dependencies are established for parameters in the behavior-level parameter model, the system-level parameter model, and the RTL-level parameter model to obtain a chip parameter set; The chip parameter set is optimized based on the dependency relationship to obtain a target chip parameter set that ensures the target digital circuit has no timing violations. Output a netlist file based on the target chip parameter set; The process abstraction interface module is used for: Obtain the process design kit (PDK) for the target process used in the target digital circuit; The metal layer rules are parsed from the PDK; The metal layer rules are converted into coefficients representing the minimum linewidth unit of the process to obtain a process parameter template; Based on the process parameter template, generate the physical design rules and rule check scripts corresponding to the target process.

2. The digital circuit design system as described in claim 1, characterized in that, The process abstraction interface module is specifically used to convert the PDK into a text file; The metal layer rules are extracted from the text file using regular expressions.

3. The digital circuit design system as described in claim 1, characterized in that, The digital circuit design system also includes: The intelligent constraint transfer module is used for: Receive the netlist file of the target digital circuit and convert it into a constraint map based on the netlist file; and extract the metal layer RC parameters corresponding to different process corners from the PDK. Based on the constraint map and the RC parameters of the metal layer, a constraint file corresponding to each process corner is generated.

4. The digital circuit design system as described in claim 3, characterized in that, The constraint graph is a directed acyclic graph, including: nodes representing design objects, and edges representing timing, power consumption, or physical constraints between the design objects, wherein the edges have attributes that define constraints; The design objects include the modules in the target digital circuits recorded in the netlist file.

5. The digital circuit design system as described in claim 3, characterized in that, The intelligent constraint transmission module is specifically used for: Receive the netlist file of the target digital circuit, convert it into a constraint graph based on the netlist file, and detect whether there are constraint conflicts in the constraint graph; In the event of a constraint conflict, the provider of the netlist file is informed of the constraint conflict to obtain a new netlist file for the target digital circuit. A new constraint graph is then generated based on the new netlist file, and the new constraint graph is checked for constraint conflicts. If there are no constraint conflicts in the new constraint map, constraint files corresponding to each process corner are generated based on the new constraint map and the RC parameters of the metal layer.

6. The digital circuit design system as described in claim 3, characterized in that, The digital circuit design system also includes: The EDA toolchain module includes multiple EDA tools that implement different functions of digital circuit design. It is used to sequentially call each EDA tool according to the preset EDA tool calling logic, the constraint file, the physical design rules and the rule checking script to implement the physical implementation of the target digital circuit and output the physical implementation result. A multi-objective optimization module is used to: optimize various design parameters to obtain optimized design parameters; the design parameters include chip parameters and process parameters in the physical implementation results, as well as EDA tool parameters of each EDA tool; provide the process parameters in the design parameters to the process abstraction interface module to update the process parameter template; output the chip parameters in the design parameters to the netlist file provider to update the netlist file; and output the EDA tool parameters in the design parameters to the EDA toolchain module to update each EDA tool.

7. The digital circuit design system as described in claim 6, characterized in that, The EDA tools include logic synthesis tools that use a line load model for logic synthesis; The intelligent constraint transfer module is also used to: transfer the line length in the physical implementation result to the logic synthesis tool to update the line load model.

8. The digital circuit design system as described in claim 6, characterized in that, The multi-objective optimization module uses a hybrid model of Gaussian process and deep kernel learning (GP-DKL) to optimize each design parameter.

9. The digital circuit design system as described in claim 8, characterized in that, The multi-objective optimization module is specifically used to optimize each design parameter using the GP-DKL multi-objective hybrid model in the following manner: Obtain the constraints of the target digital circuit; The search space of the GP-DKL multi-objective hybrid model is defined based on the design parameters and constraints. Multiple iterations are performed until a preset iteration stopping condition is reached; wherein, each iteration includes: searching the search space, reducing the dimensionality of the search space based on the search results, and updating the model parameters of the GP-DKL multi-objective hybrid model; wherein, in the first iteration, the search space is searched using the points in the search space mapped by the initial parameter values ​​of the design parameters as the initial points; When the iteration stopping condition is met, output the parameter values ​​of each design parameter corresponding to the optimal point searched by the GP-DKL multi-objective hybrid model; the optimized design parameters are the parameter values ​​of each design parameter corresponding to the optimal point.

10. The digital circuit design system as described in claim 9, characterized in that, The multi-objective optimization module is specifically used to reduce the dimensionality of the search space based on the search results in the following ways: The target model parameters in the model parameters of the GP-DKL multi-objective hybrid model are determined based on the search results; the target model parameters include model parameters whose change during the update process is less than a preset change threshold; The design parameters corresponding to the target model parameters are merged into one dimension.

11. The digital circuit design system as described in claim 10, characterized in that, The multi-objective optimization module is specifically used for: Determine the upper bound (UCB) of the confidence interval for each of the search results; When UCB is maximized, the design parameters corresponding to the target model parameters in the model parameters of the GP-DKL multi-objective hybrid model are merged into one dimension.

12. The digital circuit design system as described in claim 11, characterized in that, The multi-objective optimization module is further configured to reduce the dimensionality of the search space based on the search results in the following manner: Before determining the upper bound (UCB) of the confidence interval for each search result, the search space is reduced in dimensionality using a random projection matrix.

13. The digital circuit design system as described in claim 12, characterized in that, The input layer of the GP-DKL multi-objective hybrid model is embedded with an attention module; the random projection matrix is ​​updated according to the attention weight matrix output by the attention module.

14. The digital circuit design system as described in claim 12, characterized in that, When the multi-objective optimization module uses the random projection matrix to reduce the dimensionality of the search space, it outputs a Pareto front; the multi-objective optimization module is further used for: Based on the GP-DKL multi-objective hybrid model, the probability distribution of the joint prediction of multiple preset chip performance indicators is used to calculate the expected volumetric improvement EHVI index. Using the EHVI index as the acquisition function, candidate points are selected based on the acquisition function during the random projection dimensionality reduction process, and the Pareto front is updated based on the candidate points that maximize the EHVI index.

15. The digital circuit design system as described in claim 1, characterized in that, The input parsing module is specifically used for: The system-level parameters are obtained based on the functional description. The system-level parameters are transformed into intermediate representations (IRs) at the data flow graph level, nested loop level, and instruction operation level, according to their correspondence with data flow graphs, nested loops, and instruction operation levels. The parameters corresponding to the data flow graph level IR, the nested loop level IR, and the instruction operation level IR are orthogonalized to obtain the system-level parameter model.

16. The digital circuit design system according to any one of claims 6-14, characterized in that, The digital circuit design system also includes: The intelligent control module is connected to the process abstraction interface module, the multi-objective optimization module, the EDA toolchain module, and the intelligent constraint transmission module, respectively. It is used to manage the dependency relationship of tasks based on the directed acyclic graph and capture the return code of the EDA tool. If the return code indicates an error, it triggers the constraint rollback or parameter reset of the corresponding EDA tool. The process abstraction interface module, the multi-objective optimization module, the EDA toolchain module, and the intelligent constraint transfer module work together to output a physical implementation result as a task.

17. A fully automated digital circuit design method, characterized in that, include: Obtain the functional description of the target digital circuit and generate a netlist file based on the functional description; Obtain the process design package (PDK) of the target process used by the target digital circuit, and parse the metal layer rules from the PDK; The metal layer rules are converted into coefficients representing the minimum linewidth unit of the process to obtain a process parameter template; Generate physical design rules and rule check scripts corresponding to the target process based on the process parameter template; The constraint map is obtained by converting the netlist file, and the RC parameters of the metal layer corresponding to different process angles are parsed from the PDK. Based on the constraint map and the RC parameters of the metal layer, a constraint file corresponding to each process corner is generated; According to the preset EDA tool calling logic, the constraint file, the physical design rules, and the rule checking script, each EDA tool is called in sequence to realize the physical implementation of the target digital circuit and obtain the physical implementation result. Generate a netlist file based on the functional description, including: Based on the functional description, a behavioral-level parameter model, a system-level parameter model, and an RTL-level parameter model are obtained; the behavioral-level parameter model includes behavioral-level parameters, the system-level parameter model includes system-level parameters, and the RTL-level parameter model includes RTL-level parameters. Dependencies are established for parameters in the behavior-level parameter model, the system-level parameter model, and the RTL-level parameter model to obtain a chip parameter set; The chip parameter set is optimized based on the dependency relationship to obtain a target chip parameter set that ensures the target digital circuit has no timing violations. The netlist file is output based on the target chip parameter set.

18. The method as described in claim 17, characterized in that, After outputting the physical implementation results, the method further includes: Optimize each design parameter.

19. The method as described in claim 18, characterized in that, After optimizing each design parameter, the method further includes: Update the process parameter template according to the process parameters in the design parameters, update the netlist file according to the chip parameters in the design parameters, and update each EDA tool according to the EDA tool parameters in the design parameters; Regenerate the physical design rules and rule check scripts corresponding to the target process based on the process parameter template; The constraint map is reconstructed based on the netlist file, and the RC parameters of the metal layer corresponding to different process angles are parsed from the PDK. Based on the constraint map and the RC parameters of the metal layer, generate constraint files for each process corner. Following the preset EDA tool call logic, the constraint file, the physical design rules, and the rule check script, each EDA tool is called sequentially to implement the physical implementation of the target digital circuit and obtain the physical implementation result. Optimize each design parameter; Determine if the preset loop termination condition has been met; if not, repeat the above operation; if it has been met, output the physical implementation result after design parameter optimization.

20. The method as described in claim 19, characterized in that, The EDA tools include logic synthesis tools that use a line load model for logic synthesis; If the physical implementation result is obtained and the preset loop termination condition is not met, the method further includes: The line length in the physical implementation result is passed to the logic synthesis tool to update the line load model.

21. The method as described in claim 18, characterized in that, Optimize various design parameters, including: Obtain the constraints of the target digital circuit; The search space of the pre-defined Gaussian process and deep kernel learning GP-DKL multi-objective hybrid model is defined based on the design parameters and constraints. Multiple iterations are performed until a preset iteration stopping condition is reached; wherein, each iteration includes: searching the search space, reducing the dimensionality of the search space based on the search results, and updating the model parameters of the GP-DKL multi-objective hybrid model; wherein, in the first iteration, the search space is searched using the points in the search space mapped by the initial parameter values ​​of the design parameters as the initial points; When the iteration stopping condition is met, output the parameter values ​​of each design parameter corresponding to the optimal point searched by the GP-DKL multi-objective hybrid model; the optimized design parameters are the parameter values ​​of each design parameter corresponding to the optimal point.

22. The method as described in claim 21, characterized in that, Dimensionality reduction of the search space based on the search results includes: The target model parameters in the model parameters of the GP-DKL multi-objective hybrid model are determined based on the search results; the target model parameters include model parameters whose change during the update process is less than a preset change threshold; The design parameters corresponding to the target model parameters are merged into one dimension.

23. The method as described in claim 22, characterized in that, The target model parameters in the model parameters of the GP-DKL multi-objective hybrid model are determined based on the search results, including: Determine the upper bound (UCB) of the confidence interval for each of the search results; When UCB is maximized, the design parameters corresponding to the target model parameters in the model parameters of the GP-DKL multi-objective hybrid model are merged into one dimension.

24. The method as described in claim 23, characterized in that, Dimensionality reduction of the search space based on search results also includes: Before determining the upper bound (UCB) of the confidence interval for each search result, the search space is reduced in dimensionality using a random projection matrix.

25. The method as described in claim 24, characterized in that, The input layer of the GP-DKL multi-objective hybrid model is embedded with an attention module; the random projection matrix is ​​updated according to the attention weight matrix output by the attention module.

26. The method as described in claim 24, characterized in that, When using the random projection matrix to reduce the dimensionality of the search space, the output has a Pareto front; the method further includes: Based on the GP-DKL multi-objective hybrid model, the probability distribution of the joint prediction of multiple preset chip performance indicators is used to calculate the expected volumetric improvement EHVI index. Using the EHVI index as the acquisition function, candidate points are selected based on the acquisition function during the random projection dimensionality reduction process, and the Pareto front is updated based on the candidate points that maximize the EHVI index.

27. The method as described in claim 17, characterized in that, Based on the functional description, a system-level parameter model is obtained, including: The system-level parameters are obtained based on the functional description. The system-level parameters are transformed into intermediate representations (IRs) at the data flow graph level, nested loop level, and instruction operation level, according to their correspondence with data flow graphs, nested loops, and instruction operation levels. The parameters corresponding to the data flow graph level IR, the nested loop level IR, and the instruction operation level IR are orthogonalized to obtain the system-level parameter model.

28. The method according to any one of claims 17-27, characterized in that, The metal layer rules are parsed from the PDK, including: Convert the PDK into a text file; The metal layer rules are extracted from the text file using regular expressions.

29. The method as described in claim 28, characterized in that, The RC parameters of the metal layer corresponding to different process angles are extracted from the PDK, including: Extract the RC parameters of the metal layer corresponding to different process angles from the text file.

30. The method according to any one of claims 17-27, characterized in that, The method further includes: Before generating constraint files for each process corner based on the constraint map and the RC parameters of the metal layer, check whether there are constraint conflicts in the constraint map; In the event of a constraint conflict, a new netlist file is generated based on the functional description, and a constraint graph is obtained by converting the new netlist file. The constraint graph is then checked for constraint conflicts. In the absence of constraint conflicts, constraint files corresponding to each process corner are generated based on the constraint map and the RC parameters of the metal layer.

31. An electronic device, characterized in that, It includes a processor and a memory, the processor being configured to execute one or more program modules stored in the memory to implement the fully automated digital circuit design method as described in any one of claims 17-30.

32. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the fully automated digital circuit design method as described in any one of claims 17-30.

33. A computer program product, characterized in that, The computer program product includes computer program code, which, when run on a processor, implements the functions of each module in the digital circuit design system as described in any one of claims 1-16.

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