Dynamic load testing device for high-precision power management chip

Abstract

The invention discloses a high-precision dynamic load testing device for a power management chip, relates to the technical field of chip testing, and solves the problems that a traditional testing device is difficult to completely capture voltage change details in a full period of load jump and cannot provide accurate data support for chip design optimization. According to the invention, through a timeline integration strategy of ''a reference time period + a front and back extension time period'', a complete period of current jump and voltage response is completely covered; the time delay confirmation center locks the most accurate voltage valley value point through valley value traceability verification, and calculates the time delay in combination with the end moment of the reference time period, thereby breaking through the problem of fuzzy time node judgment in the traditional test, accurately screening out the chip with the delay exceeding the standard, and guaranteeing the response timeliness of the chip in a rapid load switching scene.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, specifically a high-precision dynamic load testing device for power management chips. Background Technology

[0002] With the rapid development of consumer electronics, industrial automation, and new energy storage, terminal devices are placing increasingly stringent demands on the stability, response speed, and energy efficiency of power supply systems.

[0003] As the core control component of the power supply system, the power management chip undertakes key functions such as voltage conversion, current distribution and load adaptation. Its performance directly determines the operational reliability of the terminal equipment. Especially in scenarios where core loads such as CPU, RF module and sensor frequently switch working states, the load current often needs to complete a rapid jump from hundreds of milliamps to amperes within milliseconds or even microseconds, which poses a severe challenge to the dynamic load response capability of the power management chip.

[0004] Currently, the industry's dynamic load testing of power management chips mostly adopts the traditional approach of simulating current changes with electronic loads and acquiring voltage waveforms with oscilloscopes. However, this approach has gradually revealed many limitations in practical applications: First, the test indicators are not focused enough. Existing solutions mainly focus on basic parameters such as output voltage ripple and static regulation, lacking precise quantitative judgment logic for the core dynamic indicator of "voltage response delay" during load transitions, making it difficult to identify the risk of insufficient instantaneous power supply to the device due to response lag. Second, the test judgment method is singular, generally adopting a binary judgment standard of "compliant / non-compliant", failing to consider that although some chips have slight delays, their voltage following ability under periodic dynamic loads can still meet the low-performance requirements. Directly judging them as unqualified can easily lead to a waste of chip resources. Meanwhile, as terminal devices develop towards miniaturization and integration, the internal circuit design of power management chips becomes increasingly complex. The influence of feedback loop characteristics and power device parameter differences on dynamic response becomes more and more significant. Traditional testing equipment is unable to fully capture the voltage change details throughout the entire load transition cycle, and cannot provide accurate data support for chip design optimization.

[0005] Therefore, developing a dynamic load testing device that can accurately capture dynamic response characteristics, achieve graded judgment, and has strong adaptability has become an urgent need to improve the testing efficiency and accuracy of power management chips and ensure the power supply stability of terminal equipment. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a high-precision dynamic load testing device for power management chips, which solves the problem that traditional testing devices are unable to fully capture the voltage change details throughout the entire load transition cycle, thus failing to provide accurate data support for chip design optimization.

[0007] To achieve the above objectives, the present invention provides the following technical solution: a high-precision power management chip dynamic load testing device, comprising: The step-by-step testing center performs step-by-step current transition processing on the power management chip, records the transition timeline, and locks the output voltage associated with the power management chip based on the transition timeline. The specific method is as follows: The power management chip is subjected to current step-by-step transition processing. Within a preset time period, the load current is rapidly transitioned from 100mA to 1A. The time period associated with the transition is recorded as the reference time period. The extended time period is confirmed before and after the reference time period. The extended time period is the preset time period. The two confirmed extended time periods and the reference time period are integrated to confirm the transition time line. Based on the confirmed transition timeline, the output voltage associated with the power management chip during the corresponding time period is confirmed, and output voltage change data associated with the corresponding transition timeline is generated according to the different output voltages associated at different times. The generated output voltage change data is then transmitted to the delay confirmation center. The delay confirmation center identifies the changes in output voltage associated with the transition timeline, and confirms whether the time delay associated with the output voltage meets the standard within the identified changes. The specific method is as follows: Based on the confirmed transition timeline and the different output voltages associated with different times, a voltage change curve associated with the output voltage is generated. The horizontal axis of the curve is the time line, and the vertical axis is the voltage parameter. From the confirmed voltage change curve, identify the voltage valley value and record the relevant time of the voltage valley value as the reference time. Then, using the reference time as the reference, trace back one time period, which is a preset period. Confirm the end time of the time period according to the tracing direction, and record the value point associated with the end time as the undetermined point. Identify the value change trend from the voltage valley value point to the undetermined point. If the value change trend is a continuous upward state, then record the current voltage valley value point as the confirmed valley value point. Otherwise, trace back and confirm another set of valley value points. The voltage change trends before and after the valley value point are opposite. The voltage change trend at the front end is downward, and the voltage change trend at the back end is upward. Verify and confirm the confirmed valley value point again to identify whether this valley value point is the confirmed valley value point. If it is, the confirmation process of the confirmed valley value point is completed. Otherwise, continue to trace back and confirm the valley value point until the confirmation process of the confirmed valley value point is completed. The time associated with the valley point is recorded as the determined time, and the end time of the reference period is recorded as the calibration time. The time delay between the determined time and the calibration time is determined, and the determined time delay is compared with the preset threshold Y1. If the time delay is ≤ Y1, it means that the time delay of this management chip meets the standard, and this management chip is marked as a qualified chip. If the time delay is greater than Y1, it means that the time delay of this management chip is not up to standard, and this management chip is marked as a non-compliant chip. The dynamic testing center performs dynamic testing on power management chips that fail to meet time delay standards. It simulates sinusoidal current during charging and identifies whether the power management chip can keep up with the standard based on the voltage parameter tracking characteristics.

[0008] Preferably, the dynamic testing center includes a load current characteristic confirmation terminal, a voltage waveform extraction terminal, and a characteristic parameter analysis terminal: The load current characteristic confirmation terminal confirms the analog frequency of the sinusoidal current based on the load current set during the current step transition processing, generates a sinusoidal current for secondary testing based on the analog frequency, and performs secondary testing processing on the non-compliant chip. The voltage waveform extraction end confirms the band of the voltage output waveform during the secondary test process, selects the characteristic analysis band from the continuously changing bands, and transmits the selected characteristic analysis band to the characteristic parameter analysis end. The feature parameter analysis terminal performs feature confirmation on the confirmed feature analysis band, identifies the associated time period, and confirms the maximum and minimum values ​​of the output voltage within the associated time period, thereby locking the voltage change value. Then, based on the voltage change value and the rated output voltage, feature verification is performed to identify whether the non-compliant chip follows the standard.

[0009] Preferably, the specific method for the load current characteristic confirmation terminal to perform secondary testing on substandard chips is as follows: Confirm the load current set during the current step-over process, confirm the sudden change value of the current 1A, and according to the set reference time period, use f=1÷reference time period to confirm its simulation frequency f, and generate a sinusoidal current for the secondary test according to the determined simulation frequency f. A set of test cycles is preset. During the test cycle, a sinusoidal current is used to perform a secondary test on the non-compliant chip. The voltage output waveform associated with the secondary test process is confirmed, and the associated voltage output waveform is transmitted to the voltage waveform extraction terminal.

[0010] Preferably, the voltage waveform extraction end selects the feature analysis band in the following specific way: The peak points in the voltage output waveform are identified. The waveform trends before and after the peak points are opposite, with the front waveform trending upward and the back waveform trending downward. The bands between adjacent peak points are recorded as single bands, and three groups of adjacent single bands are randomly selected from front to back for comparison and verification: the three groups of single bands are checked for overlap, the overlapping bands between the three groups of single bands are identified, and the overlap ratio of overlapping bands in each single band is confirmed. The three confirmed overlap ratios are averaged, the average ratio is confirmed, and the average ratio is used as the process feature of the current selection process. Several different selection processes are executed, and the process characteristics associated with each selection process are confirmed. The minimum value is selected from the confirmed process characteristics, and the three consecutive single bands associated with the minimum value are recorded as the feature analysis bands.

[0011] Preferably, the feature parameter analysis terminal identifies whether substandard chips follow suit and meet the standards: The maximum value of the output voltage within the associated time period is denoted as Vmax, and the minimum value is denoted as Vmin. The formula is: (Vmax-Vmin) = voltage change value. The rated output voltage of the power management chip is calibrated as Ve. The following formula is used: (voltage change value ÷ Ve) × 100% = GS. The following value GS associated with the non-compliant chip is confirmed. If GS ≤ 1%, it means that the non-compliant chip is compliant and a compliance signal is generated for display. If GS > 1%, it means that the non-compliant chip is non-compliant and a non-compliant signal is generated for display.

[0012] This invention provides a high-precision dynamic load testing device for power management chips. Compared with existing technologies, it has the following advantages: This invention employs a progressive architecture of "step-by-step testing center - delay confirmation center - dynamic testing center." First, it locks the output voltage change data by using a 100mA to 1A current step-by-step transition within 1ms. Then, it accurately identifies the voltage valley and time delay through a complete 7ms transition timeline. Finally, it performs a sinusoidal dynamic retest for chips that fail to meet the delay standard, forming a closed-loop testing logic of "initial screening - judgment - secondary verification." This effectively avoids misjudgments caused by a single testing dimension and significantly improves the reliability of the test results. By integrating the timeline strategy of "base period + extended periods before and after", the entire cycle of current jump and voltage response is fully covered; the delay confirmation center locks the most accurate voltage valley point through "valley source verification" and calculates the time delay by combining the end of the base period. This breaks through the problem of ambiguous time node determination in traditional testing, and can accurately screen out chips with excessive delay, ensuring the timely response of chips in rapid load switching scenarios. For chips that fail to meet latency standards, the Dynamic Testing Center generates a sinusoidal current based on the current parameters of jump tests. Through a process of "feature analysis band selection - voltage change value calculation - follow-up value verification," it determines the chip's voltage follow-up capability to periodic loads. This approach can both eliminate completely unusable defective products and identify chips with "slight latency but meeting follow-up standards," providing suitable options for scenarios with different performance requirements and improving the utilization efficiency of chip resources. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the principle framework of the present invention. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] First Embodiment Please see Figure 1 This application provides a high-precision power management chip dynamic load testing device, including a step-over test center, a delay confirmation center, and a dynamic test center. The step-over test center, the delay confirmation center, and the dynamic test center are electrically connected from the output node to the input node in sequence. The dynamic test center includes a load current characteristic confirmation terminal, a voltage waveform extraction terminal, and a characteristic parameter analysis terminal. The load current characteristic confirmation terminal, the voltage waveform extraction terminal, and the characteristic parameter analysis terminal are electrically connected from the output node to the input node in sequence. The step-by-step testing center performs step-by-step current transition processing on the power management chip, records the transition timeline, locks the output voltage associated with the power management chip based on the transition timeline, and transmits the generated output voltage change data to the delay confirmation center. Specifically, the step-by-step current transition processing means that the corresponding current needs to be changed from a smaller value to a larger value quickly, and the change time should be shortened to a very small range. The general operating standard is to make the load current jump from 100mA to 1A quickly, and the corresponding transition process is generally completed within 1ms. The specific method for confirming the output voltage change data is as follows: The power management chip performs current step-by-step transition processing, rapidly switching the load current from 100mA to 1A within a preset time period. The time period associated with the transition is recorded as the reference time period. An extended time period is confirmed before and after the reference time period, which is the preset time period, typically 3ms. The two confirmed extended time periods and the reference time period are integrated to confirm the transition timeline. The preset time period varies depending on the chip. Under normal circumstances, the preset time period is generally within ms and will not exceed 3ms. Here, we set it to 1ms. Then, if we confirm 3ms before and 3ms after, the overall transition timeline associated with the chip is 7ms. Based on the confirmed transition timeline, the output voltage associated with the power management chip during the corresponding time period is confirmed, and output voltage change data associated with the corresponding transition timeline is generated according to the different output voltages associated at different times. The generated output voltage change data is then transmitted to the delay confirmation center. Specifically, the output voltage change data refers to the different voltage data associated with different times. By following the change process of the time line, the change curve of the voltage change data associated with the corresponding time line is identified, which is the change curve of the voltage parameter associated with the corresponding output voltage.

[0016] The delay confirmation center identifies the changes in output voltage associated with the transition timeline, and then confirms whether the time delay associated with the output voltage meets the standard within the identified changes. Based on the confirmed transition timeline and the different output voltages associated with different times, a voltage change curve associated with the output voltage is generated. The horizontal axis of the curve is the time line, and the vertical axis is the voltage parameter. From the confirmed voltage change curve, identify the voltage valley (i.e., the lowest value) and record the relevant time of the voltage valley as the reference time. Then, using the reference time as the reference, trace back one time period, which is a preset period, generally 1ms. Confirm the end time of the time period (before the reference time) according to the tracing direction. Record the value point associated with the end time as the undetermined point and identify the value change trend from the voltage valley point to the undetermined point. If the value change trend is a continuous upward state, then record the current voltage valley point as the confirmed valley point. Otherwise, trace back and confirm another set of valley points. The voltage change trends before and after the valley point are opposite. The voltage change trend at the front end is downward and the voltage change trend at the back end is upward. Verify and confirm the confirmed valley point again to identify whether this valley point is a confirmed valley point. If it is, the confirmation process of the confirmed valley point is completed. Otherwise, continue to trace back to confirm the valley point until the confirmation process of the confirmed valley point is completed. The moment associated with the valley point is recorded as the determined moment, and the end of the reference time period is recorded as the calibration moment. The time delay between the determined moment and the calibration moment (i.e., the time difference between the two moments) is determined, and the determined time delay is compared with the preset threshold Y1. If the time delay is ≤ Y1, it means that the time delay of this management chip meets the standard, and this management chip is marked as a qualified chip. If the time delay is greater than Y1, it means that the time delay of this management chip is not up to standard, and this management chip is marked as a non-compliant chip. Specifically, in the process of confirming the time delay, it is necessary to confirm the time characteristics based on the sudden change process of the current and the corresponding change process of the voltage. During the confirmation process, the most accurate valley point of the characteristic is locked. Based on the specific locking process and the time confirmation process, it is possible to effectively confirm whether the chip has a time delay, and retest the chip that does not meet the time delay standard.

[0017] Second Embodiment In the specific implementation process of this embodiment, compared with the above embodiment, this embodiment mainly focuses on the secondary testing process of the qualified chip based on the specific change process of time characteristics, and is specifically executed by the dynamic testing center. Among them, the dynamic testing center performs dynamic testing on power management chips that fail to meet the time delay standard, simulates the sinusoidal current during the charging process, and identifies whether the power management chip can follow the standard based on the voltage parameter following characteristics. Its specific execution ends are the load current characteristic confirmation end, the voltage waveform extraction end, and the characteristic parameter analysis end; The load current characteristic verification terminal determines the analog frequency of the sinusoidal current based on the load current set during the current step transition processing, and generates a sinusoidal current for secondary testing based on the analog frequency. Substandard chips are then subjected to secondary testing. Confirm the load current set during the current step-over process, confirm the sudden change value of the current 1A, and according to the set reference time period, use: f=1÷reference time period (1ms) to confirm its simulation frequency f, and generate a sinusoidal current for the secondary test according to the determined simulation frequency f. A set of test cycles is preset (usually 5 seconds). During the test cycle, a sinusoidal current is used to perform a secondary test on the non-compliant chip, and the associated voltage output waveform during the secondary test is confirmed. The associated voltage output waveform is then transmitted to the voltage waveform extraction terminal.

[0018] The voltage waveform extraction end performs band confirmation on the voltage output waveform during the secondary test processing. From the continuously changing bands, it selects the characteristic analysis band and transmits the selected characteristic analysis band to the characteristic parameter analysis end. The selection process of the characteristic analysis band includes: The peak points in the voltage output waveform are identified. The waveform trends before and after the peak points are opposite, with the front waveform trending upward and the back waveform trending downward. The bands between adjacent peak points are recorded as single bands, and three groups of adjacent single bands are randomly selected from front to back for comparison and verification: the three groups of single bands are checked for overlap, and the overlapping bands between the three groups of single bands are identified (that is, the overlapping segments generated between the three consecutive bands). The overlap ratio of the overlapping bands in each single band is confirmed (the corresponding overlap ratio can be confirmed according to the specific line length ratio. If the line length of the overlapping band in a single band is L1 and the line length of the single band is L2, then the overlap ratio = L1 ÷ L2). The three confirmed overlap ratios are averaged to confirm the average ratio. The confirmed average ratio is used as the process feature of the current selected process. Several different selection processes are executed, and the process characteristics associated with each selection process are confirmed. The minimum value is selected from the confirmed process characteristics, and the three consecutive single bands associated with the minimum value are recorded as the feature analysis bands. Specifically, in the corresponding voltage output waveform, there are some bands with varying degrees of change, and there are also some bands with relatively small variations. In order to better confirm the proportion, it is necessary to identify overlapping bands and, based on the proportion of overlapping bands, comprehensively confirm the specific differences between each continuous band. In this way, the band with the greatest degree of difference can be selected in the corresponding voltage output waveform, which will facilitate the subsequent confirmation process of compliance.

[0019] The feature parameter analysis end confirms the characteristics of the identified feature analysis bands, identifies the associated time periods, and determines the maximum and minimum values ​​of the output voltage within these periods. This locks the voltage change value, and then performs feature verification based on the voltage change value and the rated output voltage to identify whether a non-compliant chip has been corrected to meet the standard. The maximum value of the output voltage within the associated time period is denoted as Vmax, and the minimum value is denoted as Vmin. The formula is: (Vmax-Vmin) = voltage change value. The rated output voltage of the power management chip is calibrated to Ve (a preset value). Using the formula: (voltage change ÷ Ve) × 100% = GS, the tracking value GS associated with the non-compliant chip is confirmed. If GS ≤ 1%, it means the non-compliant chip is compliant and a compliance signal is generated for display. (In subsequent practical applications, such non-compliant chips will not affect the actual use; there will only be a slight delay in performance. Compared to compliant chips, their performance is not optimal, but the tracking status is compliant, meaning the delay characteristic is not very obvious.) If GS > 1%, it means the non-compliant chip is non-compliant and a non-compliant signal is generated for display. Specifically, if the corresponding chip passes the test and meets the standard, it means that the chip will not lag behind in subsequent actual use, meaning the delay will not be very noticeable. Conversely, if the chip fails the test, it means that the corresponding chip cannot be used normally, is a defective product, and needs to be repaired or replaced.

[0020] Some of the data in the above formulas are numerical calculations with dimensions removed, and the contents not described in detail in this specification are all prior art known to those skilled in the art.

[0021] The above embodiments are only used to illustrate the technical methods of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical methods of the present invention without departing from the spirit and scope of the technical methods of the present invention.

Claims

1. A high-precision power management chip dynamic load testing device, characterized in that, include: The step-by-step testing center performs step-by-step current transition processing on the power management chip, records the transition timeline, and locks the output voltage associated with the power management chip based on the transition timeline. The delay confirmation center identifies the change value associated with the output voltage from the output voltage associated with the jump time line, and confirms whether the time delay associated with the output voltage meets the standard within the identified change value; The dynamic testing center performs dynamic testing on power management chips that fail to meet time delay standards. It simulates sinusoidal current during charging and identifies whether the power management chip can keep up with the standard based on the voltage parameter tracking characteristics.

2. The high-precision power management chip dynamic load testing device according to claim 1, characterized in that, The specific method by which the aforementioned step-by-step testing center confirms the output voltage change data is as follows: The power management chip is subjected to current step-by-step transition processing. Within a preset time period, the load current is rapidly transitioned from 100mA to 1A. The time period associated with the transition is recorded as the reference time period. The extended time period is confirmed before and after the reference time period. The extended time period is the preset time period. The two confirmed extended time periods and the reference time period are integrated to confirm the transition time line. Based on the confirmed transition timeline, the output voltage associated with the power management chip within the corresponding time period is confirmed. Based on the different output voltages associated with different times, the output voltage change data associated with the corresponding transition timeline is generated, and the generated output voltage change data is transmitted to the delay confirmation center.

3. The high-precision power management chip dynamic load testing device according to claim 1, characterized in that, The delay confirmation center confirms whether the time delay associated with its output voltage meets the standard in the following specific way: Based on the confirmed transition timeline and the different output voltages associated with different times, a voltage change curve associated with the output voltage is generated. The horizontal axis of the curve is the time line, and the vertical axis is the voltage parameter. From the confirmed voltage change curve, identify the voltage valley value and record the relevant time of the voltage valley value as the reference time. Then, using the reference time as the reference, trace back one time period, which is a preset period. Confirm the end time of the time period according to the tracing direction, and record the value point associated with the end time as the undetermined point. Identify the value change trend from the voltage valley value point to the undetermined point. If the value change trend is a continuous upward state, then record the current voltage valley value point as the confirmed valley value point. Otherwise, trace back and confirm another set of valley value points. The voltage change trends before and after the valley value point are opposite. The voltage change trend at the front end is downward, and the voltage change trend at the back end is upward. Verify and confirm the confirmed valley value point again to identify whether this valley value point is the confirmed valley value point. If it is, the confirmation process of the confirmed valley value point is completed. Otherwise, continue to trace back and confirm the valley value point until the confirmation process of the confirmed valley value point is completed. The time associated with the valley point is recorded as the determined time, and the end time of the reference period is recorded as the calibration time. The time delay between the determined time and the calibration time is determined, and the determined time delay is compared with the preset threshold Y1. If the time delay is less than or equal to Y1, it means that the time delay of this management chip meets the standard, and this management chip is marked as a compliant chip.

4. The high-precision power management chip dynamic load testing device according to claim 3, characterized in that, The delay confirmation center further includes the following specific methods for confirming whether the time delay associated with its output voltage meets the standard: If the time delay is greater than Y1, it means that the time delay of this management chip is not up to standard, and this management chip will be marked as a non-compliant chip.

5. The high-precision power management chip dynamic load testing device according to claim 4, characterized in that, The dynamic testing center includes a load current characteristic confirmation terminal, a voltage waveform extraction terminal, and a characteristic parameter analysis terminal. The load current characteristic confirmation terminal confirms the analog frequency of the sinusoidal current based on the load current set during the current step transition processing, generates a sinusoidal current for secondary testing based on the analog frequency, and performs secondary testing processing on the non-compliant chip. The voltage waveform extraction end confirms the band of the voltage output waveform during the secondary test process, selects the characteristic analysis band from the continuously changing bands, and transmits the selected characteristic analysis band to the characteristic parameter analysis end. The feature parameter analysis terminal performs feature confirmation on the confirmed feature analysis band, identifies the associated time period, and confirms the maximum and minimum values ​​of the output voltage within the associated time period, thereby locking the voltage change value. Then, based on the voltage change value and the rated output voltage, feature verification is performed to identify whether the non-compliant chip follows the standard.

6. The high-precision power management chip dynamic load testing device according to claim 5, characterized in that, The specific method for performing secondary testing on substandard chips at the load current characteristic confirmation terminal is as follows: Confirm the load current set during the current step-over process, confirm the sudden change value of the current 1A, and according to the set reference time period, use f=1÷reference time period to confirm its simulation frequency f, and generate a sinusoidal current for the secondary test according to the determined simulation frequency f. A set of test cycles is preset. During the test cycle, a sinusoidal current is used to perform a secondary test on the non-compliant chip. The voltage output waveform associated with the secondary test process is confirmed, and the associated voltage output waveform is transmitted to the voltage waveform extraction terminal.

7. The high-precision power management chip dynamic load testing device according to claim 6, characterized in that, The specific method for selecting the feature analysis band at the voltage waveform extraction end is as follows: The peak points in the voltage output waveform are identified. The waveform trends before and after the peak points are opposite, with the front waveform trending upward and the back waveform trending downward. The bands between adjacent peak points are recorded as single bands, and three groups of adjacent single bands are randomly selected from front to back for comparison and verification: the three groups of single bands are checked for overlap, the overlapping bands between the three groups of single bands are identified, and the overlap ratio of overlapping bands in each single band is confirmed. The three confirmed overlap ratios are averaged, the average ratio is confirmed, and the average ratio is used as the process feature of the current selection process. Several different selection processes are executed, and the process characteristics associated with each selection process are confirmed. The minimum value is selected from the confirmed process characteristics, and the three consecutive single bands associated with the minimum value are recorded as the feature analysis bands.

8. The high-precision power management chip dynamic load testing device according to claim 7, characterized in that, The feature parameter analysis terminal identifies whether substandard chips follow suit and meet the standards. The maximum value of the output voltage within the associated time period is denoted as Vmax, and the minimum value is denoted as Vmin. The formula is: (Vmax-Vmin) = voltage change value. The rated output voltage of the power management chip is calibrated as Ve. The following formula is used: (voltage change value ÷ Ve) × 100% = GS. The following value GS associated with the non-compliant chip is confirmed. If GS ≤ 1%, it means that the non-compliant chip is compliant and a compliance signal is generated for display. If GS > 1%, it means that the non-compliant chip is non-compliant and a non-compliant signal is generated for display.

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