A multi-parallel inverter current sharing control circuit

Abstract

The application discloses a kind of multi-path parallel inverter current sharing control circuit, including main control unit, the second pin of counter U1 in main control unit is connected with the one end of solid-state relay K1 coil, the eleventh pin is connected with the thirteenth pin, the fourteenth pin is connected with or gate U8 output end, and the output pin except third pin and twelfth pin is sequentially output start and EES series signal;Operational amplifier U2 same phase end is connected with the one end of resistance R5, the one end of resistance R9, opposite phase end is connected with the one end of resistance R2, the one end of resistance R8, output end is connected with the other end of resistance R8, operational amplifier U9 same phase end;Operational amplifier U3 same phase end is connected with the anode of diode D1, operational amplifier U9 opposite phase end, opposite phase end is connected with the one end of resistance R1, the one end of capacitor C2, the collector of triode Q2, operational amplifier U6 same phase end, output end is connected with the second input end of and gate U4;The first input end of and gate U4 is connected with the output end of operational amplifier U5, output end is connected with the base of triode Q1, the base of triode Q3.

Description

Technical Field

[0001] This invention relates to the field of power supply technology, and in particular to a current sharing control circuit for a multi-parallel inverter. Background Technology

[0002] With the rapid development of new energy power generation technology, inverters, as the core equipment for power conversion, directly affect the reliable operation of the entire power system due to their performance stability. In practical applications, due to inherent deviations in semiconductor device manufacturing processes, parameter mismatch is common among inverter modules of the same model. This is mainly reflected in the on-resistance of power switching transistors, switching characteristics, and drive circuit parameters. This mismatch can lead to control signal phase deviations in parallel-operated inverter systems. When the phase deviation accumulates to a certain extent, it will generate significant circulating currents between parallel inverters, and in severe cases, even cause current distortion. To address this issue, the mainstream solutions are centralized control and master-slave control. Centralized control uses a unified control module to generate synchronization signals and distribute power to achieve functional deployment, while master-slave control uses a distributed architecture to deploy control functions. Both solutions eliminate deviations by presetting parameters. However, due to their static configuration characteristics, when facing problems such as component mismatch and aging, parameters need to be readjusted periodically to maintain system stability. This requires a high level of professional expertise from operators, and there is uncertainty when parameters are not updated, which may also generate significant circulating currents. Summary of the Invention

[0003] To address the aforementioned technical problems, the present invention aims to provide a current sharing control circuit for a multi-parallel inverter, comprising a main control unit. In the main control unit, the second pin of counter U1 is connected to one end of the coil of solid-state relay K1, the eleventh pin is connected to the thirteenth pin, the fourteenth pin is connected to the output of OR gate U8, and the remaining output pins, except for the third and twelfth pins, output Start and EES series signals sequentially. The non-inverting input of operational amplifier U2 is connected to one end of resistor R5 and one end of resistor R9, the inverting input is connected to one end of resistor R2 and one end of resistor R8, and the output is connected to the other end of resistor R8 and the non-inverting input of operational amplifier U9. The non-inverting input of operational amplifier U3 is connected to the anode of diode D1 and the inverting input of operational amplifier U9. The inverting input is connected to one end of resistor R1, one end of capacitor C2, the collector of transistor Q2, and the non-inverting input of operational amplifier U6. The output is connected to the second input of AND gate U4. The first input of AND gate U4 is connected to the output of operational amplifier U5, and the output is connected to the base of transistor Q1 and the base of transistor Q3. The non-inverting input of operational amplifier U5 is connected to diode D1. 1. Cathode; Op-amp U6's inverting input is connected to one end of resistor R12, and its output is connected to one end of resistor R9 and the other end of resistor R12; Op-amp U7's non-inverting input is connected to one end of capacitor C1, the collector of transistor Q3, one end of resistor R3, and one end of resistor R13, and its output is connected to the first connection terminal of solid-state relay K1; OR gate U8's first input receives the IN1 start signal, and its second input is connected to the common terminal of solid-state relay K1; Op-amp U9's output is connected to the second connection terminal of solid-state relay K1; Transistor Q1's emitter is connected to the other end of resistor R1; Transistor Q2's base receives the MR reset signal; the other end of resistor R2 receives the compensation signal Vref; Counter U1's sixteenth pin, transistor Q1's collector, and the other end of resistor R3 are connected to the power supply; Counter U1's eighth pin, the other end of solid-state relay K1's coil, the other end of capacitor C1, the other end of capacitor C2, transistor Q2's emitter, transistor Q3's emitter, the other end of resistor R5, and the other end of resistor R13 are grounded.

[0004] Furthermore, the main control unit integrates a microprocessor. When the microprocessor receives the Start series signals input from the main control unit, it performs addition or subtraction counting on the internal clock signal and converts the count into voltage. When it receives the EES series signals, it controls the corresponding inverters 1_1 to 1_N to input the output voltage phase signal into IN1. When the inverters start in parallel, if the count voltage returns to zero, the internal pulse generator is activated to generate and start the signal when it returns to zero.

[0005] Furthermore, the main control unit integrates multiple sub-processing units. In each sub-processing unit, the third pin of digital potentiometer U10 is connected to the collector of transistor Q6 and one end of resistor R24; the fourth pin is connected to the fourth pin of digital potentiometer U12 and the Clk terminal; the fifth pin is connected to the output terminal of inverter U16 and one end of resistor R25; and the tenth pin is connected to the non-inverting input of operational amplifier U11, the inverting input of operational amplifier U15, and one end of resistor R17. The inverting input of operational amplifier U11 is connected to one end of resistor R16, and the output terminal is connected to the non-inverting input of operational amplifier U13. The inverting input and the other end of resistor R16; the third pin of digital potentiometer U12 is connected to the drain of MOSFET Q5 and one end of resistor R21, the fifth pin is connected to the drain of MOSFET Q4 and one end of resistor R19, the tenth pin is connected to the inverting input of op-amp U13 and one end of resistor R26; the output of op-amp U13 is connected to the Out terminal; the second pin of trigger U14 is connected to the sixth pin and the anode of diode D9, the third pin is connected to the gate of MOSFET Q4, the gate of MOSFET Q5, the cathode of diode D7, and diode D1. Pin 0 is the cathode; pin 4 is connected to the cathodes of diodes D8 and D9; pin 5 is connected to the source of MOSFET Q5; the output of op-amp U15 is connected to the emitter of transistor Q6; the base of transistor Q6 is connected to the cathode of diode D11 and one end of resistor R28; the input of inverter U16 is connected to the anode of diode D11 and IN2; the anodes of diodes D7 and D8 are connected to the MR terminal; the anode of diode D10 is connected to the Start_1 terminal; the source of MOSFET Q4, pins 1, 11, and 12 of digital potentiometer U10, pins 1, 11, and 12 of digital potentiometer U12, and pin 1 of trigger U14 are connected to the power supply; pins 2 and 14 of digital potentiometer U10, pins 2 and 14 of digital potentiometer U12, the other end of resistor R17, the other end of resistor R19, the other end of resistor R21, the other end of resistor R24, the other end of resistor R25, the other end of resistor R26, and the other end of resistor R28 are grounded.

[0006] Furthermore, the main control unit integrates a sub-switch unit. In the sub-switch unit, the anodes of diodes D2 to D5 respectively input Start0 to Start4 signals, and the cathodes are connected to one end of the coil of solid-state relay K2. The common terminal of solid-state relay K2 is input to the main control unit via IN0. The first connection terminal inputs the 1_1 signal, and the second connection terminal is connected to one end of solid-state relays K3, K5, and K6. The other end of solid-state relay K5 inputs the 1_2 signal, and one end of its coil inputs the EES_1 signal; the other end of solid-state relay K3 inputs the 1_3 signal, and one end of its coil inputs the EES-2 signal; the other end of solid-state relay K6 inputs the 1_4 signal, and one end of its coil inputs the EES_3 signal; one end of solid-state relay K4 inputs the 1_4 signal, and one end of its coil inputs the EES_4 signal; the other ends of the coils of solid-state relays K2 to K6 and the other end of solid-state relay K4 are grounded.

[0007] Furthermore, in the main control unit, one end of resistor R4 is connected to the thirteenth pin of counter U1, and one end of resistor R6 is connected to the fifteenth pin of counter U1; one end of resistor R7 is connected to the power supply, and the other end is connected to the inverting input of operational amplifier U5 and one end of resistor R11; one end of resistor R15 is connected to the second input of OR gate U8; the other ends of resistor R4, resistor R6, resistor R11, and resistor R15 are grounded.

[0008] Furthermore, in the sub-processing unit, one end of resistor R18 is connected to the power supply, and the other end is connected to the non-inverting input of operational amplifier U15 and one end of resistor R23; one end of resistor R20 is connected to the cathode of diode D10; one end of resistor R22 is connected to the anode of diode D9; one end of resistor R27 is connected to the IN2 terminal; and the other ends of resistors R20, R22, R23, and R27 are grounded.

[0009] Furthermore, one end of resistor R10 in the main control unit is connected to the power supply, and the other end is connected to the inverting input of operational amplifier U7 and one end of resistor R14; the other end of resistor R14 is grounded.

[0010] The advantages of this invention compared to the prior art are:

[0011] This invention can combine the number of inverters connected in parallel, and can correct the phase deviation caused by parameter mismatch or drive signal impedance deviation before operation to avoid circulating current failure. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 A schematic diagram of the main control unit circuit structure provided by the present invention.

[0014] Figure 2 This is a schematic diagram of the sub-processing unit circuit structure provided by the present invention.

[0015] Figure 3 A schematic diagram of the sub-switch unit circuit structure provided by the present invention. Detailed Implementation

[0016] To make the objectives and advantages of the present invention clearer, the present invention will be specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or more specific embodiments of the present invention and does not strictly limit the scope of protection specifically claimed by the present invention.

[0017] See Figure 1 , Figure 2 , Figure 3 In the circuit, IN1 is the start signal of the main control unit, 1_1 to 1_N are the voltage phase signals corresponding to the inverter output, and the 1_1 to 1_N signals are input to IN0 through the sub-switching unit. Start_0 to Start_N are dedicated control signals that control the sub-switching unit to input the voltage phase of the inverter corresponding to 1_1 to IN0. Start_1 to Start_N are also the static offset parameter start signals generated by the sub-processing units corresponding to 1_2 to 1_N based on the 1_1 main offset detection reference signal. EES_1 to EES_N are the control signals that control the voltage phase of the inverter corresponding to 1_2 to 1_N input to IN0. IN0 is a dedicated control signal; IN2 is the phase offset elimination control signal for inverters 1_2 to 1_N; Out is the pulse generation start signal for inverters 1_2 to 1_N after phase offset elimination; Vref is the compensation signal output after a phase lag when the phase reaches a specific angle during the generation of the main offset detection reference signal. During initial operation, initialization is performed. During initialization, the inverters connected in parallel are isolated to detect the phase offset of each inverter under the same pulse control. The entire initialization process is divided into T1 to TN times based on the number of parallel inverters. During T1, the main control unit first detects the 1_1 voltage and, upon reaching a specific... When the phase angle is adjusted, a corresponding main offset detection reference signal is generated, and hysteresis compensation is applied to this signal before proceeding to time T2. During time T2, the inverter voltage phase corresponding to 1_2 is input to IN0 for detection by the main control unit. When the voltage phase of 1_2 matches the main offset detection reference signal, the main control unit outputs Start_1 to start the sub-processing unit corresponding to 1_2, and simultaneously switches 1_1 to input to IN0, proceeding to time T3. During time T3, the sub-processing unit generates the corresponding main offset detection reference signal based on the Start_1 input state when the voltage phase of 1_2 matches the main offset detection reference signal, and the voltage phase of 1_1 reaches 90° again. The static offset parameter signal completes the detection of the phase offset relative to 1_1, and then enters time T4; during time T4, the input of 1_3 is switched to IN0, and the initialization detection of all inverters is completed through the above 1_2 loop operation. During the formal start-up, the sub-processing unit feeds back the corresponding Out signal to the inverter according to different static offset parameters to generate different pulses for startup. Initialization can also be generated and started simultaneously by discrete PWM generators at the same pulse period frequency. After initialization is completed, the sub-processing unit controls the corresponding PWM generator to generate different startups according to the Out signal. During startup, different pulse signals are input into the inverter circuit of the inverter.

[0018] See Figure 1The specific signal flow for initialization in the main control unit is as follows: During time T1, the main control unit inputs the IN1 signal to start. The IN1 signal is input to pin 14 of counter U1 via OR gate U8. Counter U1 changes from pin 3 to pin 2 and outputs to the coil of solid-state relay K1. The coil of solid-state relay K1 closes, and solid-state relay K1 changes from the contact state shown in the attached diagram to the other end being closed. At the same time, Start_0 is input to the sub-switch unit, which inputs 1_1 to IN0. The IN0 input signal is then input to operational amplifier U3 on one side and to operational amplifier U5 on the other side via diode D1. Operational amplifier U5 first filters out the phase signal with negative period from 180° to 360°, while operational amplifier U3 detects from 0° to 180°. Resistors R7 and R11 are used for setting... A zero-crossing reference signal is set. AND gate U4 is used for output detection of operational amplifiers U3 and U5. When IN0 is input from 0 to 90°, operational amplifiers U3 and U5 simultaneously output signals to AND gate U4. AND gate U4 outputs a high-level signal to the base of transistors Q1 and Q3, turning on transistors Q1 and Q3. Transistor Q1 conducts to input the IN0 phase voltage to capacitor C2. Resistor R1 is used for current limiting. Transistor Q3 is used for detection from 90° to 180°. When transistor Q1 is on, the power supply of transistor Q1's collector is fed back to capacitor C2 and the non-inverting input of operational amplifier U6 through resistor R1. When transistor Q3 is on, the power supply at the end of resistor R3 is looped through the collector, emitter, and ground of transistor Q3, and the voltage drop at the end of capacitor C1. When U7 does not output, the inverting input of op-amp U7 is set with a reference voltage. This reference voltage approaches the maximum voltage after voltage division by resistors R3 and R13 at the capacitor C1 terminal. Resistor R3 is a current-limiting resistor, and resistor R13 is used to discharge capacitor C1 during closed-loop operation. When the phase of the voltage output from inverter 1_1 corresponding to IN0 reaches 90°, the voltage at the capacitor C2 terminal is pulled up until op-amp U3 no longer responds to output. The voltage pulled up by the power supply at the capacitor C1 terminal via resistor R3 is fed back to op-amp U7, allowing the signal output by op-amp U7 to also be input to OR gate U8. OR gate U8 then outputs a signal to pin 14 of counter U1, forming the first closed loop. Pin 2 of counter U1 is switched to pin 4 for output input. Simultaneously, the auxiliary contact of solid-state relay K1 switches to the state shown in the attached diagram, and capacitor C... The voltage is pulled up to the 90° phase voltage of 1_1 to generate the main offset detection reference signal. The signal is also fed back to the non-inverting input of op-amp U6. Op-amp U6 and resistor R12 form a follower output, which is then input to the non-inverting input of op-amp U2 after passing through the circuit of resistors R9 and R5. The Vref compensation signal is input to the resistor R2 terminal. The signal amplitude is taken to be greater than and close to the value of the reference voltage parameter at the inverting input of op-amp U7, which is the integral curve of capacitor C1 and resistor R3. Vref is input to the inverting input of op-amp U2 through resistor R2. After negative feedback through resistor R8, op-amp U2 is differentially input to the non-inverting input of op-amp U9 for hysteresis compensation. The inverting input of op-amp U9 samples the IN0 signal for comparison. At the same time, the EES_1 signal output from pin 4 of counter U1 is input to the sub-switching unit.The sub-switch unit switches input 1_2 to the inverting input of operational amplifier U9, entering time T2. During time T2, the main control unit detects the phase voltage input of 1_2 and inputs it to operational amplifier U9. When the phase of 1_2 reaches 90°, the output of operational amplifier U9 goes through the auxiliary contact of solid-state relay K1 to OR gate U8. OR gate U8 outputs a signal to pin 14 of counter U1. Pin 7 of counter U1 outputs the Start_1 signal to the sub-processing unit and the sub-switch unit. The sub-switch unit switches input 1_1 again and inputs it to IN0 of the main control unit for detection. The sub-processing unit starts during the period when it receives the Start_1 signal and enters time T3. During time T3, the main control unit detects the voltage phase of 1_1 again. After the above control process in time T2, when it reaches 90° again, it makes U1 output the EES_2 signal to the sub-switch unit to enter time T4. At the same time, the sub-processing unit generates a signal based on the Start_1 signal status fed back by the main control unit during time T3. The corresponding static offset parameter signal; during time T4, the EES_2 signal inputs the inverter signal corresponding to 1_3 into IN0, and then cycles through the output signals of EES_1 and Start_1 until the initialization of T1 to TN is completed. In this embodiment, the control of the sub-processing unit and the sub-switching unit is completed by the microprocessor. In the sub-processing unit function, when the microprocessor receives the Start series signals from the main control unit, it performs addition counting on the internal clock signal and converts the count into voltage parameters to generate static offset parameters. When the inverter is started by inputting IN2, it performs subtraction counting. When returning to zero, it starts the internal pulse generator and inputs the generated pulse signal into the inverter circuit of the inverter. In the sub-switching unit function, the corresponding 1_1 to 1_N signals are controlled to be input to the main control unit according to the EES and Start series signals. The control flow is consistent with the above T1 to TN times.

[0019] See Figure 2In one embodiment, during initialization, the power signal first passes through the drain and source of the field-effect transistor Q4 to pin 5 of the digital potentiometer U12. Pin 3 of the digital potentiometer U12 passes through resistor R21, pin 3 of the digital potentiometer U10 passes through resistor R24, and the input of the inverter U16 passes through resistor R27 before being inverted and output to pin 5 of the digital potentiometer U10. During this period, both digital potentiometers U10 and U12 are reset to a high-impedance state with the CLK input. When the voltage at the connection point of the digital potentiometer U10 and resistor R17 is lower than the reference signal at the non-inverting input of the operational amplifier U15, the output signal of the operational amplifier U15 is turned on after passing through the emitter of transistor Q6, resistor R28, and ground. The signal of the operational amplifier U15 is then fed back to the digital potentiometer U10. Pin 3, digital potentiometer U10 is cut off, maintaining its pre-initialization state. After the Start_1 signal is input, the sub-processing unit outputs from pin 5 of trigger U14 on one side, and feeds back to the gates of MOSFETs Q4 and Q5 on the other. MOSFET Q5 blocks the output from pin 5 of trigger U14, and MOSFET Q4 is cut off. Digital potentiometer U12 gradually transitions from high impedance to low impedance. The voltage at the connection between resistor R26 and digital potentiometer U12 gradually increases, serving as a dynamic offset parameter signal fed back to operational amplifier U13. As the main control unit detects 1_1, when the phase of 1_1 reaches 90° again, pin 10 of counter U1 outputs, the corresponding Start_1 pin is pulled down, and the gate and source of MOSFET Q5... When the circuit is under negative voltage conduction, pin 5 of trigger U14 is fed back to pin 3 of digital potentiometer U12 via the source and drain of MOSFET Q5, converting the dynamic offset parameter signal of digital potentiometer U12 and resistor R26 into a static offset parameter signal. Simultaneously, pin 6 of trigger U14 is input to pin 4 of trigger U14 via diode D9, pulling down the signal and setting pin 5 of trigger U14 to 1 to shield it from subsequent write / erase inputs from the main control unit. Operational amplifier U11 and resistor R16 isolate the voltage at the connection point of digital potentiometer U10 and resistor R17, preventing a virtual short circuit at pin 3 of digital potentiometer U10 during direct comparison by operational amplifier U13, which could cause a pull-down failure. During normal startup, the IN2 input signal is inverted again after passing through the input of inverter U16 before being pulled down. Pin 5 of digital potentiometer U10 is connected to the base of transistor Q6 via diode D11. Since the base of transistor Q6 is higher than its emitter, it is cut off. Pin 3 of digital potentiometer U10 is connected to resistor R25. As CLK is input, the voltage of digital potentiometer U10 gradually increases and is then input to operational amplifier U13 via operational amplifier U11. Operational amplifier U13 compares the voltage at the connection point of digital potentiometer U12 and resistor R26. When the voltage at the connection point of digital potentiometer U10 and resistor R17 rises to the corresponding static offset parameter, operational amplifier U13 outputs an Out signal to the corresponding inverter's PWM generator. PWM then begins generating pulse signals based on the Out time and sends them to the corresponding inverter. If regeneration is needed, an MR reset signal is input to the sub-processing unit.The signal is input to pin 4 of flip-flop U14 via diodes D7 and D8, deactivating pin 5 of flip-flop U14 from its 1-1 state. Subsequent input at pin 3 causes pin 6 of flip-flop U14 to output again, resetting digital potentiometers U10 and U12. Diodes D7 and D8 are also used in series for Start series signal input. When IN2 is controlled by the reset switch, resistor R27 is required for pull-down. During the detection of multiple parallel inverter groups, the initialization reset of digital potentiometers U10 and U12 (excluding detection processes) can also be achieved via connector P1, allowing the microprocessor to serially input and control the tap positions corresponding to the high-impedance states of U10 and U12.

[0020] See 1 and Figure 3 In one embodiment, diodes D2 to D6 in the integrated switching circuit are used for signal reverse protection to prevent other sub-processing units from being activated when Start input is received. Solid-state relay K2 is used to switch 1_1 input to IN0. Solid-state relays K3 to K6 are used to receive EES signals and switch the corresponding 1_2 to 1_4. The 1_N series and EES_N series correspond to the number of output pins of counter U1 or the number of multiple counters U1 connected in series. In Start_N, except for Start_0 which does not correspond to a sub-processing unit, the number of the others is the same as the number of sub-processing units. The counters U1 are connected in series as follows: pin 11 of the first counter U1 is connected to pin 13 of the second counter U1 through an inverter and a jumper. Pins 14 and 15 of the two counters U1 are connected in parallel. An example of counter U1 series connection is not shown in the attached figure.

Claims

1. A current sharing control circuit for a multi-channel parallel inverter, characterized in that, The main control unit includes a counter U1 whose second pin is connected to one end of the solid-state relay K1 coil, its eleventh pin to its thirteenth pin, its fourteenth pin to the output of OR gate U8, and the remaining output pins (except for the third and twelfth pins) output Start and EES series signals in sequence. Operational amplifier U2's non-inverting input is connected to one end of resistor R5 and one end of resistor R9, its inverting input to one end of resistor R2 and one end of resistor R8, and its output to the other end of resistor R8 and the non-inverting input of operational amplifier U9. Operational amplifier U3's non-inverting input is connected to the anode of diode D1 and the inverting input of operational amplifier U9. The inverting input is connected to one end of resistor R1, one end of capacitor C2, the collector of transistor Q2, and the non-inverting input of operational amplifier U6. Its output is connected to the second input of AND gate U4. The first input of AND gate U4 is connected to the output of operational amplifier U5, and its output is connected to the base of transistors Q1 and Q3. The non-inverting input of operational amplifier U5 is connected to the cathode of diode D1. The inverting input of operational amplifier U6 is connected to resistor R1.

2. One end of the counter is connected to one end of resistor R9 and the other end of resistor R12; the non-inverting input of operational amplifier U7 is connected to one end of capacitor C1, the collector of transistor Q3, one end of resistor R3, and one end of resistor R13, and the output is connected to the first connection terminal of solid-state relay K1; the first input terminal of OR gate U8 receives the IN1 start signal, and the second input terminal of OR gate U8 is connected to the common terminal of solid-state relay K1; the output terminal of operational amplifier U9 is connected to the second connection terminal of solid-state relay K1; the emitter of transistor Q1 is connected to the other end of resistor R1; the base of transistor Q2 receives the MR reset signal; the other end of resistor R2 receives the compensation signal Vref; the sixteenth pin of counter U1, the collector of transistor Q1, and the other end of resistor R3 are connected to the power supply; the eighth pin of counter U1, the other end of the coil of solid-state relay K1, the other end of capacitor C1, the other end of capacitor C2, the emitters of transistors Q2 and Q3, the other end of resistor R5, and the other end of resistor R13 are grounded.

2. The current sharing control circuit for multi-parallel inverters according to claim 1, characterized in that, The main control unit integrates a microprocessor. When the microprocessor receives the Start series signals input by the main control unit, it performs addition or subtraction counting on the internal clock signal and converts the count into voltage. When it receives the EES series signals, it controls the corresponding inverters 1_1 to 1_N to input the output voltage phase signal into IN1. When the inverters are started in parallel, if the count voltage returns to zero, the internal pulse generator is started when the voltage returns to zero.

3. The current sharing control circuit for multi-channel parallel inverters according to claim 1, characterized in that, The main control unit integrates multiple sub-processing units. In each sub-processing unit, the third pin of digital potentiometer U10 is connected to the collector of transistor Q6 and one end of resistor R24; the fourth pin is connected to the fourth pin of digital potentiometer U12 and the Clk terminal; the fifth pin is connected to the output terminal of inverter U16 and one end of resistor R25; and the tenth pin is connected to the non-inverting input of operational amplifier U11, the inverting input of operational amplifier U15, and one end of resistor R17. The inverting input of operational amplifier U11 is connected to one end of resistor R16, and the output terminal is connected to the non-inverting input of operational amplifier U13. The inverting input and the other end of resistor R16; the third pin of digital potentiometer U12 is connected to the drain of MOSFET Q5 and one end of resistor R21, the fifth pin is connected to the drain of MOSFET Q4 and one end of resistor R19, the tenth pin is connected to the inverting input of op-amp U13 and one end of resistor R26; the output of op-amp U13 is connected to the Out terminal; the second pin of trigger U14 is connected to the sixth pin and the anode of diode D9, the third pin is connected to the gate of MOSFET Q4, the gate of MOSFET Q5, the cathode of diode D7, and diode D1. Pin 0 is the cathode; pin 4 is connected to the cathodes of diodes D8 and D9; pin 5 is connected to the source of MOSFET Q5; the output of op-amp U15 is connected to the emitter of transistor Q6; the base of transistor Q6 is connected to the cathode of diode D11 and one end of resistor R28; the input of inverter U16 is connected to the anode of diode D11 and IN2; the anodes of diodes D7 and D8 are connected to the MR terminal; the anode of diode D10 is connected to the Start_1 terminal; the source of MOSFET Q4, pins 1, 11, and 12 of digital potentiometer U10, pins 1, 11, and 12 of digital potentiometer U12, and pin 1 of trigger U14 are connected to the power supply; pins 2 and 14 of digital potentiometer U10, pins 2 and 14 of digital potentiometer U12, the other end of resistor R17, the other end of resistor R19, the other end of resistor R21, the other end of resistor R24, the other end of resistor R25, the other end of resistor R26, and the other end of resistor R28 are grounded.

4. The current sharing control circuit for multi-channel parallel inverters according to claim 1, characterized in that, The main control unit integrates a sub-switch unit. In this sub-switch unit, the anodes of diodes D2 to D5 receive Start0 to Start4 signals respectively, and their cathodes are connected to one end of the coil of solid-state relay K2. The common terminal of solid-state relay K2 is input to the main control unit via IN0. The first connection terminal receives a 1_1 signal, and the second connection terminal is connected to one end of solid-state relays K3, K5, and K6. The other end of solid-state relay K5 receives a 1_2 signal, and one end of its coil receives an EES_1 signal. The other end of solid-state relay K3 receives a 1_3 signal, and one end of its coil receives an EES-2 signal. The other end of solid-state relay K6 receives a 1_4 signal, and one end of its coil receives an EES_3 signal. One end of solid-state relay K4 receives a 1_4 signal, and one end of its coil receives an EES_4 signal. The other ends of the coils of solid-state relays K2 to K6 and the other end of solid-state relay K4 are grounded.

5. The current sharing control circuit for multi-parallel inverters according to claim 1, characterized in that, In the main control unit, one end of resistor R4 is connected to the thirteenth pin of counter U1, and one end of resistor R6 is connected to the fifteenth pin of counter U1; one end of resistor R7 is connected to the power supply, and the other end is connected to the inverting input of operational amplifier U5 and one end of resistor R11; one end of resistor R15 is connected to the second input of OR gate U8; the other ends of resistor R4, resistor R6, resistor R11, and resistor R15 are grounded.

6. The current sharing control circuit for multi-parallel inverters according to claim 3, characterized in that, In the sub-processing unit, one end of resistor R18 is connected to the power supply, and the other end is connected to the non-inverting input of operational amplifier U15 and one end of resistor R23; one end of resistor R20 is connected to the cathode of diode D10; one end of resistor R22 is connected to the anode of diode D9; one end of resistor R27 is connected to the IN2 terminal; and the other ends of resistors R20, R22, R23, and R27 are grounded.

7. The current sharing control circuit for multi-parallel inverters according to claim 1, characterized in that, In the main control unit, one end of resistor R10 is connected to the power supply, and the other end is connected to the inverting input of operational amplifier U7 and one end of resistor R14; the other end of resistor R14 is grounded.

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