Optoelectronic sensor in fan-out package of multi-chip integration and method of manufacturing the same

Abstract

The application discloses a kind of multi-chip integrated fan-out package photoelectric sensor and its manufacturing method, belong to integrated circuit technical field, the manufacturing method of the multi-chip integrated fan-out package photoelectric sensor, comprising the following steps: providing image sensor chip and light source chip, the photosensitive area of image sensor chip and the light-emitting area of light source chip are placed on the carrier board downward;Screen printing is used to print a plurality of metal columns for transmitting electrical signals;Epoxy plastic encapsulating material is arranged on the carrier board and is solidified;Thin the epoxy plastic encapsulating material to expose the metal column, and the remaining epoxy plastic encapsulating material constitutes the substrate;Back interconnect is screen printed on the back of substrate;Remove the carrier board, and front interconnect is screen printed on the front of substrate.The metal column and front interconnect, back interconnect that are screen printed realize the communication of front and back surface signals and the connection between image sensor chip and light source chip, reduce product size requirement.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a multi-chip integrated fan-out packaged photoelectric sensor and its manufacturing method. Background Technology

[0002] Multi-chip integrated optical sensors, in addition to a CIS (CMOS Image Sensor) image sensor, also integrate a light-emitting source chip. Typically, such multi-chip integrated optical sensors use a PCB substrate as the carrier board. Both the CIS chip and the light-emitting source chip are mounted on the substrate via die bonding, and the pads of the CIS chip and the light-emitting source chip are connected to the substrate pads using a wire bonding process. (See...) Figure 1 The limitations of the existing photoelectric sensor 100, with this packaging method, are:

[0003] Since the PCB substrate 102 is used as a carrier board with a certain thickness in the Z direction, and the carrier board requires metal plate making and protective layer, and the warpage of the carrier board needs to be considered to facilitate the high yield and stability of the packaging process mass production, the carrier board must have a certain thickness to support it.

[0004] The Y-direction is perpendicular to the paper plane. The PCB substrate 102 needs to consider the dimensions of the light source chip 108, the CIS chip 106, the wire bonding space 104, and the support of the optical packaging cover plate 103 in both the X and Y directions. Furthermore, the light source chip 108 and the CIS chip 106 are mostly standardized products, and can only be packaged and integrated using the PCB substrate 102 as a carrier, which makes further miniaturization impossible.

[0005] End customers are accelerating product iteration and upgrades, including mobile phones, smartwatches, smart bracelets, smart furniture, and IoT products. They are pursuing smaller product sizes, and the packaging process that uses PCB substrates as carriers can no longer meet the needs of products to be smaller in space.

[0006] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0007] The purpose of this invention is to provide a multi-chip integrated fan-out packaged photoelectric sensor and its manufacturing method, so as to solve the problem that the packaging process using PCB substrate as carrier can no longer meet the needs of products to be more miniaturized in space.

[0008] To address the aforementioned technical problems, this invention provides a method for manufacturing a multi-chip integrated fan-out packaged photoelectric sensor, comprising the following steps:

[0009] An image sensor chip and a light source chip are provided, with the photosensitive area of ​​the image sensor chip and the light-emitting area of ​​the light source chip placed downwards on a carrier board;

[0010] Based on the location of the RDL wiring layers and vias, multiple metal pillars for transmitting electrical signals are printed on the stencil.

[0011] An epoxy sealant is applied to the carrier plate and cured.

[0012] The epoxy molding compound is thinned to expose the metal pillar, and the remaining epoxy molding compound forms a substrate. The side of the substrate that is in contact with the carrier plate is the front side, and the other side is the back side.

[0013] Backside interconnects are printed on the back side of the substrate using a stencil to form electrical connection points connected to corresponding metal pillars;

[0014] Remove the carrier plate and print front interconnects on the front stencil of the substrate to connect the image sensor chip and the light source chip, and to transmit electrical signals to the corresponding metal pillars.

[0015] Preferably, the first side of the image sensor chip is further provided with two metal layer pads, which are respectively disposed on both sides of the photosensitive area, and the first side of the light source chip is further provided with two first pads, which are respectively disposed on both sides of the light-emitting area.

[0016] Preferably, the back-side interconnect includes back-side RDL traces and LGA pads.

[0017] Preferably, after fabricating the back interconnect, a back solder mask layer is also fabricated on the back side of the substrate, the back solder mask layer covering the back RDL traces and exposing the LGA pads.

[0018] Preferably, removing the carrier plate and printing front-side interconnects on the front-side stencil of the substrate for connecting the image sensor chip and the light source chip, and transmitting electrical signals to the corresponding metal pillars includes:

[0019] A first front-side RDL trace and a second front-side RDL trace are printed on the front side of the substrate using a stencil. The first front-side RDL trace is used to connect a metal layer pad and a first pad to a corresponding metal pillar, respectively. The second front-side RDL trace is used to connect another metal layer pad and another first pad.

[0020] Preferably, after the front interconnect is fabricated, a front solder mask layer of predetermined height is formed on the front side of the substrate, and the front solder mask layer exposes the photosensitive area and the light-emitting area.

[0021] A multi-chip integrated fan-out packaged photoelectric sensor, comprising:

[0022] A substrate, wherein an image sensor chip and a light source chip are disposed therein, and the upper edge of the photosensitive area of ​​the image sensor chip and the upper edge of the light-emitting area of ​​the light source chip are flush with the front side of the substrate, and the substrate is made of epoxy molding compound.

[0023] Multiple metal pillars are disposed in the substrate for transmitting electrical signals;

[0024] A back-side interconnect, located on the back side of the substrate, is used to form an electrical connection point connected to a corresponding metal pillar;

[0025] The front interconnect, located on the front side of the substrate, is used to connect the image sensor chip and the light source chip, and to transmit electrical signals to the corresponding metal pillars. The metal pillars, the front interconnect, and the back interconnect are all fabricated by stencil printing.

[0026] Preferably, the first side of the image sensor chip is further provided with two metal layer pads, which are respectively disposed on both sides of the photosensitive area, and the first side of the light source chip is further provided with two first pads, which are respectively disposed on both sides of the light-emitting area.

[0027] Preferably, the front interconnect includes a first front RDL trace and a second front RDL trace. The first front RDL trace is used to connect a metal layer pad and a first pad to a corresponding metal pillar, respectively. The second front RDL trace is used to connect another metal layer pad and another first pad.

[0028] Preferably, the back-side interconnect includes back-side RDL traces and LGA pads.

[0029] In the manufacturing method of the multi-chip integrated fan-out packaged photoelectric sensor provided by this invention, a method of first forming metal pillars and then encapsulating them, and finally forming front and back interconnects, is used to integrate the light source chip and image sensor chip in epoxy molding compound. The metal pillars and front and back interconnects printed by stencil printing achieve communication between the front and back signals, as well as the connection between the image sensor chip and the light source chip. This not only saves dimensions in the X and Y directions but also reduces the requirements for dimensions in the Z direction, contributing to a reduction in product size. Furthermore, this solution can be applied to different types of light source chip design structures.

[0030] The multi-chip integrated fan-out packaged photoelectric sensor provided by this invention and the manufacturing method of the multi-chip integrated fan-out packaged photoelectric sensor provided by this invention belong to the same inventive concept. Therefore, the multi-chip integrated fan-out packaged photoelectric sensor provided by this invention has at least all the advantages of the manufacturing method of the multi-chip integrated fan-out packaged photoelectric sensor provided by this invention, which will not be repeated here. Attached Figure Description

[0031] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0032] Figure 1 This is a schematic diagram of the structure of a photoelectric sensor in the prior art;

[0033] Figure 2 This is a schematic diagram of the structure in Embodiment 1 of the present invention, in which the image sensor chip and the light source chip are placed on a carrier board;

[0034] Figure 3 This is a schematic diagram of the structure for forming the first metal pillar according to Embodiment 1 of the present invention;

[0035] Figure 4 This is a schematic diagram of the structure after filling with epoxy molding compound and grinding according to Embodiment 1 of the present invention;

[0036] Figure 5 This is a schematic diagram of the structure after back-side encapsulation is completed according to Embodiment 1 of the present invention;

[0037] Figure 6 This is a structural schematic diagram of Embodiment 1 of the present invention;

[0038] Figure 7 This is an execution flowchart of Embodiment 1 of the present invention;

[0039] Figure 8 This is a schematic diagram of the structure of Embodiment 2 of the present invention;

[0040] Figure 9 This is a structural schematic diagram of Embodiment 3 of the present invention;

[0041] Figure 10 This is a schematic diagram of the structure of Embodiment 4 of the present invention;

[0042] Figure 11 This is a structural schematic diagram of Embodiment 5 of the present invention;

[0043] Figure 12 This is a schematic diagram of the structure of Embodiment Six of the present invention.

[0044] Figure 1 middle:

[0045] 100. Existing photoelectric sensor; 101. Back pad of PCB substrate; 102. PCB substrate; 103. Encapsulation cover plate; 104. Wire bond; 105. CIS chip pad; 106. CIS chip; 107. Front pad of PCB substrate; 108. Light source chip.

[0046] Figures 2 to 12 middle:

[0047] 1. Image sensor chip; 2. Light source chip; 3. First pad; 4. Light-emitting area; 5. Metal layer pad; 6. Photosensitive area; 7. First front RDL trace; 8. Front solder mask layer; 9. Substrate; 10. First metal pillar; 11. Second front RDL trace; 12. Back interconnect; 13. Back solder mask layer; 14. BGA solder ball; 15. Second metal pillar; 16. Third metal pillar; 17. Second pad; 18. Aperture; 19. Surface mount lens; 20. Fourth metal pillar; 21. Carrier board. Detailed Implementation

[0048] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0049] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; the term “at least two” is generally used to mean “two or more”; furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first," "second," and "third" may explicitly or implicitly include one or at least two of those features. The term "proximal" typically refers to the end closer to the operator, and the term "distal" typically refers to the end closer to the patient. "One end" and "the other end," as well as "proximal" and "distal," generally refer to two corresponding parts, including not only endpoints. The terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two elements or interactions between two elements. Furthermore, as used in this invention, the placement of one element on another element generally only indicates a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of another element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0050] Studies have found that, for example Figure 1 The existing photoelectric sensor 100 shown is an optical sensor packaged and integrated using a PCB substrate 102 as a carrier. It has certain requirements for the thickness of the carrier and also needs to take into account the structure of the wire bond 104, CIS chip 106, CIS chip pad 105, light source chip 108, and front pad 107 of the PCB substrate. An encapsulation cover plate 103 is set, and the back pad 101 of the PCB substrate further increases the overall thickness.

[0051] To meet the needs of end customers, a fan-out packaging method (wafer-level or board-level) is adopted to integrate the light source chip and image sensor chip into a single package. Metal pillars printed on a stencil and front and back interconnects enable communication between the front and back sides, as well as connections between the image sensor chip and the light source chip. Vias are formed in the epoxy molding compound (EMC). This solution not only saves dimensions in the X and Y directions but also reduces dimensions in the Z direction. Furthermore, this solution can be applied to different design structures of the light source chip, such as: the light-emitting area and positive and negative electrode pads are both on the upper surface of the chip; the light-emitting area and one electrode are on the upper surface, and the other electrode is on the lower surface; the light-emitting area is on the upper surface, and the positive and negative electrode pads are on the lower surface. In all cases, the light source chip and image sensor can be interconnected via the front interconnects, and the generated electrical signals can be connected to the corresponding metal pillars.

[0052] Example 1

[0053] For details, please refer to Figures 2-7 This is a schematic diagram of an embodiment of the present invention. Figure 7 As shown, a method for manufacturing a multi-chip integrated fan-out packaged photoelectric sensor includes the following steps:

[0054] Step 1: Provide an image sensor chip 1 and a light source chip 2, and place the photosensitive area 6 of the image sensor chip 1 and the light-emitting area 4 of the light source chip 2 downwards on the carrier plate 21.

[0055] In one embodiment, the first side of the image sensor chip 1 is further provided with two metal layer pads 5, which are respectively disposed on both sides of the photosensitive area 6. The first side of the light source chip 2 is further provided with two first pads 3, which are respectively disposed on both sides of the light-emitting area 4. The two first pads 3 of the light source chip 2 are positive and negative electrode pads, respectively, and the first pads 3 and the light-emitting area 4 are located on the same side of the light source chip 2.

[0056] First, the package design was finalized using the schematic diagram, determining the positions of the two chips and the required RDL (Redistribution Layer) and VIA via locations. The two chips were then placed upside down on the substrate 21 (not shown) with a film covering (die face down), meaning the light-emitting area 4 and photosensitive area 6 were placed downwards. Figure 2 As shown.

[0057] Step 2: Based on the location of the RDL wiring layer and vias, a number of metal pillars for transmitting electrical signals are printed on the stencil.

[0058] Understandably, since the metal layer pad 5 of the image sensor chip 1 and the first pad 3 of the light source chip 2 are on the same side, only two first metal pillars 10 penetrating the EMC are needed to transmit electrical signals, such as... Figure 3 As shown, the metal pillars here are the metal pillars inside the VIA vias. Using a pre-designed steel mesh, all the metal pillars are printed out. At this time, the height of the metal pillars should be higher than the design size to facilitate the subsequent grinding to expose the metal pillars and conduct the RDL or LGA (Land Grid Array) / BGA (Ball Grid Array) pads on the back.

[0059] Step 3: Apply epoxy molding compound to the carrier plate 21 and cure it. Preferably, the height of the epoxy molding compound is higher than the height of the metal column.

[0060] Step four: Thin the epoxy molding compound to expose the metal pillar. The remaining epoxy molding compound forms the substrate 9. The side of the substrate 9 that is in contact with the carrier plate 21 is the front side, and the other side is the back side.

[0061] like Figure 4 As shown, the first metal pillar 10 is exposed by back-side grinding.

[0062] Step 5: Print back interconnect 12 on the back of the substrate 9 using a stencil to form electrical connection points connected to the corresponding metal pillars.

[0063] The back-side interconnect 12 includes back-side RDL traces and LGA pads. The back-side RDL traces and LGA pads are also fabricated using stencil printing, allowing for the simultaneous formation of both. After fabricating the back-side interconnect 12, a back-side solder mask layer 13 is also fabricated on the back side of the substrate 9. The back-side solder mask layer 13 covers the back-side RDL traces and exposes the LGA pads.

[0064] For example, if necessary, a BGA package can be formed, creating BGA solder balls 14, such as... Figure 5 As shown. The formed LGA pads or BGA solder balls 14 serve as electrical connection points for transmitting electrical signals between the front and back sides via metal pillars.

[0065] Step six: Remove the carrier plate 21, and print front interconnects on the front stencil of the substrate 9 for connecting the image sensor chip 1 and the light source chip 2, and for transmitting electrical signals to the corresponding metal pillars.

[0066] Before removing the carrier 21, a UV film is first applied to the exposed LGA / BGA package, and then the carrier 21 on the surface is separated. Then, the residue on the surface of the substrate 9 is brushed away using a scrubber (a cleaning process mainly used to remove particles and contaminants from the surface to ensure the smooth progress of subsequent processes).

[0067] When the light-emitting area 4 and the first pad 3 are on the same side, the carrier plate 21 is removed, and front-side interconnects are printed on the front-side stencil of the substrate 9 for connecting the image sensor chip 1 and the light source chip 2, and for transmitting electrical signals to the corresponding metal pillars, including:

[0068] On the front side of the substrate 9, a first front-side RDL trace 7 and a second front-side RDL trace 11 are printed using a stencil. The first front-side RDL trace 7 is used to connect a metal layer pad and a first pad to corresponding metal pillars, respectively. The second front-side RDL trace 11 is used to connect another metal layer pad and another first pad. The second front-side RDL trace 11 enables the interconnection between the light source chip 2 and the image sensor chip 1, while the first front-side RDL trace 7 connects to the metal pillars. Together with the metal pillars and the back-side interconnect 12, the conduction of electrical signals on both sides is achieved.

[0069] like Figure 6 As shown, after fabricating the front interconnect, a front solder mask layer 8 of predetermined height is formed on the front side of the substrate 9, and the front solder mask layer 8 exposes the photosensitive area 6 and the light-emitting area 4. A front solder mask layer 8 of a certain height is formed on the surface of the substrate 9, exposing the light-emitting area 4 of the light source chip 2 and the photosensitive area 6 of the image sensor chip 1, forming two openings. The openings must have a certain size to ensure process windows. The UV film on the back side is peeled off by UV stripping to form the final product.

[0070] Understandably, the first front-side RDL trace 7, the second front-side RDL trace 11, the metal pillars, and the back-side RDL traces constitute the RDL reconfiguration wiring layer of this application. Unlike the traditional TSV process for forming VIA vias, this application prepares the entire package structure by pre-printing metal pillars and performing EMC curing and filling, thereby redistributing the chip's input / output (I / O) pad contact positions, shortening critical signal paths, significantly reducing the thickness requirements of the photoelectric sensor, optimizing the process flow, and enabling its application on various design types of light source chips 2.

[0071] Based on the same technical concept, this embodiment also provides a multi-chip integrated fan-out packaged photoelectric sensor, including:

[0072] The substrate 9 has an image sensor chip 1 and a light source chip 2 disposed therein. The upper edge of the photosensitive area 6 of the image sensor chip 1 and the upper edge of the light-emitting area 4 of the light source chip 2 are flush with the front side of the substrate 9. The substrate 9 is made of epoxy molding compound.

[0073] Multiple metal pillars are disposed in the substrate 9 for transmitting electrical signals;

[0074] The back-side interconnect 12 is located on the back side of the substrate 9 and is used to form an electrical connection point connected to the corresponding metal pillar;

[0075] The front interconnect is located on the front side of the substrate 9 and is used to connect the image sensor chip 1 and the light source chip 2, as well as to transmit electrical signals to the corresponding metal pillars. The metal pillars, the front interconnect, and the back interconnect 12 are all prepared by stencil printing.

[0076] Understandably, the front and back electrical signals of the photoelectric sensor are transmitted through the front interconnect, the back interconnect 12, and the metal pillars. The front interconnect can be used to connect the pads of the image sensor chip 1 and the light source chip 2 for front-side electrical signal transmission. The front interconnect can also be used to connect the metal pillars and the pads. The metal pillars are further connected to the back interconnect 12, which forms electrical connection points with the corresponding metal pillars. The two ends of the metal pillar can be the front interconnect and the back interconnect 12 respectively to achieve conduction between the front and back sides of the substrate 9. The two ends of the metal pillar can also be the pads of the light source chip 2 and the back interconnect 12 respectively. The positions of the front interconnect, the back interconnect 12, and the metal pillars are set according to the connection method required by the design layout.

[0077] In one embodiment, the first side of the image sensor chip 1 is further provided with two metal layer pads 5, which are respectively disposed on both sides of the photosensitive area 6. The first side of the light source chip 2 is further provided with two first pads 3, which are respectively disposed on both sides of the light-emitting area 4. The front interconnect includes a first front RDL trace 7 and a second front RDL trace 11. The first front RDL trace 7 is used to connect a metal layer pad and a first pad to corresponding metal pillars, respectively. The second front RDL trace 11 is used to connect another metal layer pad and another first pad. The back interconnect 12 includes a back RDL trace and an LGA pad.

[0078] To meet the needs of end customers, a fan-out packaging method (wafer-level or board-level) is adopted to integrate the light source chip and CIS chip into a single package. This involves reconstructing the routing layer (RDL) on both the surface and back of the package, and using an LGA (Land Grid Array) or BGA (Ball Grid Array) on the back of the package. Via vias are drilled within the EMC (Epoxy Molding Compound) to connect the surface RDL pads to the back RDL or LGA / BGA. This approach not only saves dimensions in the X and Y directions but also reduces dimensions in the Z direction. With this design, the light source chip 2 can be designed in three ways: the light-emitting region 4 and the positive and negative electrode pads are both on the upper surface of the chip; the light-emitting region 4 and one electrode are on the upper surface, while the other electrode is on the lower surface; and the light-emitting region 4 is on the upper surface, while the positive and negative electrode pads are on the lower surface. These three types of light-emitting chip designs determine the differences in structure. The specific structure and fabrication process will be further explained below according to the design type of light-emitting chip 2.

[0079]

Example 2

[0080] Please refer to Figure 8 The present invention also provides another embodiment of a multi-chip integrated fan-out packaged photoelectric sensor. The basic steps of this embodiment are the same as those of the first embodiment, but when fabricating the front solder mask layer 8, an aperture 18 is fabricated as needed, and a patch lens 19 is prepared on the surface of the photosensitive area 6.

[0081]

Example 3

[0082] Please refer to Figure 9 The present invention also provides another embodiment of a multi-chip integrated fan-out packaged photoelectric sensor. In this embodiment, the design type of the light source chip 2 is as follows: the light-emitting area 4 and one of the electrodes are on the upper surface (this electrode is mostly positive), and the other electrode is on the lower surface (this electrode is mostly negative). For example, the first pad 3 on the upper surface of the light source chip 2 is a positive pad, and the second pad 17 on the lower surface is a negative pad.

[0083] After placing the image sensor chip 1 and the light source chip 2 on the carrier board 21, when printing the metal pillars on the stencil, it is necessary to simultaneously print the first metal pillar 10, the second metal pillar 15, and the third metal pillar 16. The two first metal pillars 10 are connected to the front and back sides, the second metal pillar 15 is connected to the second pad 17 of the light source chip 2, and the third metal pillar 16 is connected to one of the metal layer pads 5 of the image sensor chip 1 through the second front RDL trace 11. One of the metal layer pads 5 is to be connected to the bottom second pad 17 electrode of the light source chip 2.

[0084] The back-side interconnect 12 is fabricated, and the back-side RDL traces are made using stencil printing to connect the second metal post 15 and the third metal post 16.

[0085] The front interconnect is fabricated by using stencil printing to create a second front RDL trace 11, which connects the third metal pillar 16 to one of the metal layer pads 5 of the image sensor chip 1. One of the metal layer pads 5 is to be connected to the bottom second pad 17 electrode of the light source chip 2 to achieve the connection between the two chips.

[0086] Understandably, the fabrication of the front interconnect, the back interconnect 12, and the metal pillars is based on the design type of the light source chip 2, as well as the design drawings of the RDL wiring layer and vias.

[0087]

Example 4

[0088] Please refer to Figure 10 The present invention also provides another embodiment of a multi-chip integrated fan-out packaged photoelectric sensor. The basic steps of this embodiment are the same as those of embodiment three, but when fabricating the front solder mask layer 8, an aperture 18 is fabricated as needed, and a patch lens 19 is prepared on the surface of the photosensitive area 6.

[0089] Example 5

[0090] Please refer to Figure 11 The present invention also provides another embodiment of a multi-chip integrated fan-out packaged photoelectric sensor. In this embodiment, the light source chip 2 is designed with the light-emitting area 4 on the upper surface and the positive and negative electrodes on the lower surface. Correspondingly, the two first pads 3 on the lower surface are the positive and negative electrode pads, respectively.

[0091] When making the stencil printed metal pillars, it is necessary to simultaneously make the first metal pillar 10, the second metal pillar 15, the third metal pillar 16, and the fourth metal pillar 20. One end of the second metal pillar 15 is connected to a first pad 3 at the bottom of the light source chip 2, and the other end is connected to the back interconnect 12. For example, the back interconnect 12 connects the second metal pillar 15 and the third metal pillar 16.

[0092] The other end of the third metal pillar 16 is connected to one of the metal layer pads 5 of the image sensor chip 1 through the second front RDL trace 11. One of the metal layer pads 5 is connected to a first pad 3 of the light source chip 2. The fourth metal pillar 20 is connected to another first pad 3 of the light source chip 2, and finally connected to a certain LGA pad or BGA solder ball 14 through the back RDL trace, so that the LGA / BGA pad can power the light source chip 2.

[0093] When creating the back RDL traces, stencil printing is used to create the back RDL traces to connect the second metal post 15 with the third metal post 16, and the fourth metal post 20 with the LGA pads or BGA solder balls 14.

[0094] When routing the front RDL, the third metal pillar 16 is connected to one of the metal layer pads 5 of the image sensor chip 1 by stencil printing. The metal layer pad 5 is required to be connected to one of the first pads 3 of the light source chip 2.

[0095] Example 6

[0096] Please refer to Figure 12 The present invention also provides another embodiment of a multi-chip integrated fan-out packaged photoelectric sensor. The basic steps of this embodiment are the same as those of embodiment five, but when fabricating the front solder mask layer 8, an aperture 18 is fabricated as needed, and a patch lens 19 is prepared on the surface of the photosensitive area 6.

[0097] This application employs wafer-level or board-level Fan-Out packaging technology to integrate the light source chip 2 and the CIS image sensor chip 1 onto the same package interface. The surface pads of the light source chip 2 and the CIS image sensor chip 1 are connected either through the aforementioned RDL reconstruction wiring (the light-emitting area 4 and the positive and negative electrode pads in the light source chip 2 are on one side), or through vias in the EMC (Epoxy Molding Compound), with RDL reconstruction wiring on the back side (the light-emitting area 4 and the positive and negative electrode pads are not on the same side, but the light-emitting area 4 and one of the pads are on the same side). The surface electrode pads are connected to the back side of the EMC through metal pillars in the vias of the EMC (Epoxy Molding Compound), and LGA / BGA package pads are formed on the back side of the EMC. This solution not only saves dimensions in the X and Y directions but also reduces the requirements for dimensions in the Z direction, contributing to a reduction in product size. Furthermore, this solution can be applied to different types of light source chip design structures.

[0098] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A method for manufacturing a multi-chip integrated fan-out packaged photoelectric sensor, characterized in that, Includes the following steps: An image sensor chip and a light source chip are provided, with the photosensitive area of ​​the image sensor chip and the light-emitting area of ​​the light source chip placed downwards on a carrier board; Based on the location of the RDL wiring layers and vias, multiple metal pillars for transmitting electrical signals are printed on the stencil. An epoxy sealant is applied to the carrier plate and cured. The epoxy molding compound is thinned to expose the metal pillar, and the remaining epoxy molding compound forms a substrate. The side of the substrate that is in contact with the carrier plate is the front side, and the other side is the back side. Backside interconnects are printed on the back side of the substrate using a stencil to form electrical connection points connected to corresponding metal pillars; Remove the carrier plate and print front interconnects on the front stencil of the substrate to connect the image sensor chip and the light source chip, and to transmit electrical signals to the corresponding metal pillars.

2. The method for manufacturing a multi-chip integrated fan-out packaged photoelectric sensor according to claim 1, characterized in that, The first side of the image sensor chip is also provided with two metal layer pads, which are respectively located on both sides of the photosensitive area. The first side of the light source chip is also provided with two first pads, which are respectively located on both sides of the light-emitting area.

3. The method for manufacturing a multi-chip integrated fan-out packaged photoelectric sensor according to claim 1, characterized in that, The back-side interconnect includes back-side RDL traces and LGA pads.

4. The method for manufacturing a multi-chip integrated fan-out packaged photoelectric sensor according to claim 3, characterized in that, After fabricating the back interconnect, a back solder mask layer is also fabricated on the back side of the substrate, which covers the back RDL traces and exposes the LGA pads.

5. The method for manufacturing a multi-chip integrated fan-out packaged photoelectric sensor according to claim 2, characterized in that, Removing the carrier plate and printing front-side interconnects on the front-side stencil of the substrate for connecting the image sensor chip and the light source chip, and transmitting electrical signals to the corresponding metal pillars, includes: A first front-side RDL trace and a second front-side RDL trace are printed on the front side of the substrate using a stencil. The first front-side RDL trace is used to connect a metal layer pad and a first pad to a corresponding metal pillar, respectively. The second front-side RDL trace is used to connect another metal layer pad and another first pad.

6. The method for manufacturing a multi-chip integrated fan-out packaged photoelectric sensor according to claim 1, characterized in that, After the front interconnect is fabricated, a front solder mask layer of predetermined height is formed on the front side of the substrate, and the front solder mask layer exposes the photosensitive area and the light-emitting area.

7. A multi-chip integrated fan-out packaged photoelectric sensor, characterized in that, include: A substrate, wherein an image sensor chip and a light source chip are disposed therein, and the upper edge of the photosensitive area of ​​the image sensor chip and the upper edge of the light-emitting area of ​​the light source chip are flush with the front side of the substrate, and the substrate is made of epoxy molding compound. Multiple metal pillars are disposed in the substrate for transmitting electrical signals; A back-side interconnect, located on the back side of the substrate, is used to form an electrical connection point connected to a corresponding metal pillar; The front interconnect, located on the front side of the substrate, is used to connect the image sensor chip and the light source chip, and to transmit electrical signals to the corresponding metal pillars. The metal pillars, the front interconnect, and the back interconnect are all fabricated by stencil printing.

8. The multi-chip integrated fan-out packaged photoelectric sensor according to claim 7, characterized in that, The first side of the image sensor chip is also provided with two metal layer pads, which are respectively located on both sides of the photosensitive area. The first side of the light source chip is also provided with two first pads, which are respectively located on both sides of the light-emitting area.

9. The multi-chip integrated fan-out packaged photoelectric sensor according to claim 8, characterized in that, The front interconnect includes a first front RDL trace and a second front RDL trace. The first front RDL trace is used to connect a metal layer pad and a first pad to a corresponding metal pillar, respectively. The second front RDL trace is used to connect another metal layer pad and another first pad.

10. The multi-chip integrated fan-out packaged photoelectric sensor according to claim 7, characterized in that, The back-side interconnect includes back-side RDL traces and LGA pads.

Images