A quantum circuit simulation method, device and equipment for distributed computing and a medium

Abstract

The present disclosure provides a quantum circuit simulation method, device, equipment and medium for distributed computing. The method comprises: obtaining a quantum circuit to be processed, the quantum circuit to be processed comprising a first number of bits; performing sub-circuit division on the quantum circuit to be processed to obtain at least two first-level sub-circuits each comprising a second number of quantum bits; performing sub-segment division on a state vector based on each first-level sub-circuit to obtain state vector sub-segment information corresponding to each first-level sub-circuit; distributing state vector sub-segment data corresponding to the state vector sub-segment information corresponding to each first-level sub-circuit to distributed quantum simulation nodes, so that each quantum simulation node performs simulation calculation of the at least two first-level sub-circuits based on the state vector sub-segment data corresponding to the state vector sub-segment information, until a simulation calculation result is obtained. The number of cross-node data transmissions in the circuit simulation process is reduced, and the overall processing efficiency of the circuit simulation process is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of quantum computing, and particularly relates to a quantum circuit simulation method and device based on distributed computing, equipment and a medium. BACKGROUND

[0002] As a new computing mode, quantum computing can exhibit stronger computing power than classical computing in specific computing tasks by using the superposition state and entanglement state principles of quantum mechanics. Quantum simulators can simulate the evolution process of quantum states on classical computers, making up for the deficiency of physical quantum computers in large-scale computing in the short term.

[0003] With the increase in the number of qubits, the complexity of quantum circuit simulation increases exponentially, and traditional quantum circuit simulation methods encounter bottlenecks in computing. Especially in the case of frequent quantum gate operations and a large number of qubits, the simulation speed is significantly reduced, and the demand for computing resources increases dramatically. To solve this problem, quantum circuit simulation is realized through a distributed computing simulation scheme. Specifically, quantum state data is distributed to multiple computing nodes to share the computing load and expand the simulation scale.

[0004] In the process of implementing the present disclosure, it is found that at least the following technical problems exist in the prior art: Distributed computing requires a large amount of communication and data synchronization, and frequent data exchange between different nodes significantly increases communication overhead and affects the efficiency of quantum circuit simulation. SUMMARY

[0005] The present disclosure provides a quantum circuit simulation method and device based on distributed computing to reduce the number of communications between nodes and improve the processing efficiency of the quantum circuit simulation process.

[0006] According to an aspect of the present disclosure, a quantum circuit simulation method based on distributed computing is provided, comprising:

[0007] obtaining a quantum circuit to be processed, the number of qubits of the quantum circuit to be processed being a first number;

[0008] dividing the quantum circuit to be processed into sub-circuits to obtain at least two first-level sub-circuits with a second number of qubits, the second number being less than the first number;

[0009] dividing the state vector based on each first-level sub-circuit into sub-segments to obtain state vector sub-segment information corresponding to each first-level sub-circuit;

[0010] distribute state vector subsegment data corresponding to the state vector subsegment information corresponding to each of the primary subcircuits to distributed quantum simulation nodes, so that each of the quantum simulation nodes sequentially performs simulation calculation of the at least two primary subcircuits based on the state vector subsegment data corresponding to the state vector subsegment information, until a simulation calculation result is obtained.

[0011] The quantum simulation nodes perform data communication based on the state vector subsegment information corresponding to the first primary subcircuit and the state vector subsegment information corresponding to the second primary subcircuit after the first primary subcircuit is executed, and continue to execute the second primary subcircuit.

[0012] According to another aspect of the present disclosure, a quantum circuit simulation device for distributed computing is provided, comprising:

[0013] A quantum circuit acquisition module is configured to acquire a to-be-processed quantum circuit, wherein the number of quantum bits of the to-be-processed quantum circuit is a first number.

[0014] A subcircuit division module is configured to divide the to-be-processed quantum circuit into at least two primary subcircuits, wherein the number of quantum bits of each of the primary subcircuits is a second number, and the second number is less than the first number.

[0015] A state vector division module is configured to divide a state vector based on each of the primary subcircuits to obtain state vector subsegment information corresponding to each of the primary subcircuits.

[0016] A simulation calculation module is configured to distribute state vector subsegment data corresponding to the state vector subsegment information corresponding to each of the primary subcircuits to distributed quantum simulation nodes, so that each of the quantum simulation nodes sequentially performs simulation calculation of the at least two primary subcircuits based on the state vector subsegment data corresponding to the state vector subsegment information, until a simulation calculation result is obtained.

[0017] The quantum simulation nodes perform data communication based on the state vector subsegment information corresponding to the first primary subcircuit and the state vector subsegment information corresponding to the second primary subcircuit after the first primary subcircuit is executed, and continue to execute the second primary subcircuit.

[0018] According to another aspect of the present disclosure, an electronic device is provided, comprising:

[0019] at least one processor; and

[0020] a memory in communication with the at least one processor; wherein

[0021] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to perform the distributed quantum circuit simulation method according to any one of the embodiments of the present disclosure.

[0022] According to another aspect of the present disclosure, a computer readable storage medium is provided, which stores computer instructions for enabling a processor to implement the distributed quantum circuit simulation method according to any one of the embodiments of the present disclosure when executed by the processor.

[0023] According to another aspect of the present disclosure, a computer program product is provided, which comprises a computer program for implementing the distributed quantum circuit simulation method according to any one of the embodiments of the present disclosure when executed by a processor.

[0024] The technical solution of the embodiments of the present disclosure divides the processing quantum circuit into at least two first-order sub-circuits, so that the distributed quantum simulation nodes do not need to perform cross-node data transmission in the process of executing each first-order sub-circuit, thereby reducing the number of cross-node data transmissions in the circuit simulation process, reducing the communication delay and bandwidth consumption caused by cross-node communication, and improving the overall processing efficiency of the circuit simulation process. Further, by segmenting the state vector in the process of processing each first-order sub-circuit, the distributed quantum simulation nodes can execute each first-order sub-circuit in parallel for different state vector segments, realize parallel processing in the circuit simulation process, fully utilize the resource advantages of the distributed quantum simulation nodes, and improve the calculation efficiency of the circuit simulation.

[0025] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art without creative labor.

[0027] Figure 1 is a schematic diagram of a quantum circuit provided by an embodiment of the present disclosure;

[0028] Figure 2 is a flowchart of a distributed quantum circuit simulation method provided by an embodiment of the present disclosure;

[0029] Figure 3 is a schematic diagram of a hierarchical adjusted quantum circuit provided by an embodiment of the present disclosure;

[0030] Figure 4 is a schematic diagram of a quantum circuit after quantum merging processing provided by an embodiment of the present disclosure;

[0031] Figure 5 is a schematic diagram of a sub-circuit division provided by an embodiment of the present disclosure;

[0032] Figure 6 is a directed acyclic graph of a quantum circuit provided by an embodiment of the present disclosure;

[0033] Figure 7 is another schematic diagram of a sub-circuit division provided by an embodiment of the present disclosure;

[0034] Figure 8 is a schematic diagram of index information of state vector quantum blocks provided by an embodiment of the present disclosure;

[0035] Figure 9 is a schematic diagram of bit rearrangement provided by an embodiment of the present disclosure;

[0036] Figure 10 is a schematic diagram of data exchange between distributed quantum simulation nodes in a circuit simulation process provided by an embodiment of the present disclosure;

[0037] Figure 11 is a flowchart of a distributed quantum circuit simulation method provided by an embodiment of the present disclosure;

[0038] Figure 12 is a schematic diagram of two-level division of a quantum circuit provided by an embodiment of the present disclosure;

[0039] Figure 13 is a schematic diagram of index information of state vector quantum blocks corresponding to a first-level sub-circuit and a second-level sub-circuit respectively provided by an embodiment of the present disclosure;

[0040] Figure 14 is a schematic diagram of a distributed quantum circuit simulation method provided by an embodiment of the present disclosure;

[0041] Figure 15 is a structural schematic diagram of a distributed quantum circuit simulation device provided by an embodiment of the present disclosure;

[0042] Figure 16 is a structural schematic diagram of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] In order for those skilled in the art to better understand the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, not all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative labor should fall within the scope of protection of the present disclosure.

[0044] It should be noted that the terms "first", "second", and the like in the specification and claims of the present disclosure and the above-described drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to only those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0045] Referring to Figure 1 , Figure 1 is a schematic diagram of a quantum circuit provided by an embodiment of the present disclosure. According to Figure 1 It can be known that the quantum circuit to be processed includes 6 bits (Q0, Q1, Q2, Q3, Q4, Q5), and quantum gates are respectively arranged on the circuits corresponding to each bit.

[0046] In the distributed quantum circuit simulation, the amplitude data of the state vector is usually distributed on multiple quantum simulation nodes, and in order to perform quantum gate operations, data needs to be frequently exchanged between quantum simulation nodes. Specifically, if each quantum simulation node stores 2 m amplitudes, the entire state vector is distributed in 2 n-m quantum simulation nodes. For single-bit gate operations of low m-bit quantum bits, the calculation can be performed within the same quantum simulation node without data exchange; but for high n-m-bit quantum bit operations, the amplitude data is distributed on different quantum simulation nodes, which requires frequent cross-node data transmission to synchronize data between different quantum simulation nodes by transmitting state information through the network. For example, Figure 1 In the case of m=3, the quantum gates on the bit positions Q0, Q1, Q2 can be performed within the same quantum simulation node, and data communication between quantum simulation nodes is required for each quantum gate on the bit positions Q3, Q4, Q5. Frequent quantum simulation node communication greatly consumes bandwidth resources, increases communication overhead, and reduces overall simulation speed.

[0047] It can be understood that the quantum simulation node described above can be a software computing node, such as a virtual machine, and can also be a hardware computing node, such as a classical computer or a server, etc.

[0048] To solve the above technical problems, the present disclosure provides a quantum circuit simulation method for distributed computing, Figure 2 is a flowchart of a quantum circuit simulation method for distributed computing provided by an embodiment of the present disclosure. The embodiment can be applicable to dividing a quantum circuit into a plurality of first sub-circuits in the process of performing quantum circuit simulation by a classical computer, so that the distributed quantum simulation nodes do not communicate data in the process of performing quantum simulation calculation on each first sub-circuit, and only communicate data when switching between first sub-circuits, thereby reducing the number of communications between quantum simulation nodes in the quantum circuit simulation process. The method can be performed by a quantum circuit simulation device for distributed computing. The quantum circuit simulation device for distributed computing can be realized in the form of hardware and / or software, and can be configured in an electronic device capable of classical computing, such as a classical computer, a server, or a terminal device, etc. As shown in the figure, Figure 2 The method comprises the following steps:

[0049] S110, obtaining a to-be-processed quantum circuit, the number of qubits of the to-be-processed quantum circuit being a first number.

[0050] S120, performing sub-circuit division on the to-be-processed quantum circuit to obtain at least two first sub-circuits with a second number of qubits, the second number being less than the first number.

[0051] S130, performing sub-segment division on the state vector based on each first sub-circuit to obtain state vector sub-segment information corresponding to each first sub-circuit.

[0052] S140, distributing state vector sub-segment data corresponding to the state vector sub-segment information corresponding to each first sub-circuit to distributed quantum simulation nodes, so that each quantum simulation node performs simulation calculation of the at least two first sub-circuits based on the state vector sub-segment data corresponding to the state vector sub-segment information in turn, until the simulation calculation result is obtained.

[0053] The to-be-processed quantum circuit can have a first number of bit positions, and the first number is marked as n. At least one quantum gate can be arranged on the circuit corresponding to each bit position. Here, the quantum gate can be at least one of a single-bit gate and a multi-bit gate.

[0054] In the embodiment, the to-be-processed quantum circuit is divided into at least two sub-circuits, so that the distributed quantum simulation nodes do not need to perform cross-node data communication in the process of simulating each sub-circuit, only cross-node data communication is generated when the sub-circuits are switched, the number of data communication is reduced, the communication overhead is reduced, and the overall simulation efficiency is improved.

[0055] According to Figure 1 It can be known that the to-be-processed quantum circuit includes a large number of quantum gates and has a large circuit depth, and there is a problem of large calculation amount and long time consumption in the sub-circuit division process. In some embodiments of the present disclosure, before the to-be-processed quantum circuit is divided into sub-circuits, the to-be-processed quantum circuit is also subjected to circuit depth adjustment, so as to reduce the circuit depth and / or reduce the number of quantum gates. Through the circuit depth adjustment, the to-be-processed quantum circuit is simplified, the processing complexity of the sub-circuit division process is reduced, and the sub-circuit division efficiency is improved.

[0056] Optionally, the circuit depth adjustment includes removing a redundant quantum gate combination acting on the same bit. The redundant quantum gate combination can be understood as an invalid gate operation acting on the bit, that is, the redundant quantum gate combination acting after the bit has the same effect as the redundant quantum gate combination acting before the bit. For example, the redundant quantum gate combination can include two consecutive X gates, two consecutive H gates, and a quantum gate and an inverse operation gate of the quantum gate arranged in series. The redundant quantum gate combination includes at least two quantum gates, and there is no other quantum gate depending on the intermediate state of the redundant quantum gate combination.

[0057] Optionally, the circuit depth adjustment includes adjusting the level of the quantum gate acting on each bit without changing the dependency relationship, so that the quantum gates acting on different bits and not having the dependency relationship are arranged in parallel. According to Figure 1 It can be known that the quantum gates acting on different bits can be on different levels, and there can be idle levels between the quantum gates acting on the same bit, resulting in a large number of levels in the to-be-processed quantum circuit, and further increasing the circuit depth. In the embodiment, the level of the quantum gate acting on each bit is adjusted, so as to reduce the circuit depth, that is, for any quantum gate, the quantum gate is adjusted to a lower level without changing the dependency relationship, so that the quantum gates acting on different bits and not having the dependency relationship are arranged in parallel. For example, by adjusting the level of each quantum gate in Figure 1 , a quantum circuit after level adjustment is obtained. Referring to Figure 3 , Figure 3 is a schematic diagram of the quantum circuit after level adjustment provided by the embodiment of the present disclosure. It can be understood that Figure 1 and Figure 3 the numbers arranged in the quantum gates in the above two figures are used to represent the types of the quantum gates.

[0058] Optionally, the circuit depth adjustment comprises: merging the continuous single-bit gates acting on the same bit to obtain a composite gate. For the continuous single-bit gates U1 and U2 acting on the same bit, the quantum state is changed to obtain , according to the matrix multiplication association law, the can be a new quantum gate , the is a composite gate. Similarly, for at least two continuous single-bit gates acting on the same bit, a composite gate can be obtained by merging the at least two continuous single-bit gates, and the at least two continuous single-bit gates are replaced by the composite gate to reduce the number of quantum gates and the circuit depth.

[0059] Optionally, the circuit depth adjustment comprises: adjusting the level of the quantum gates acting on each bit without changing the dependency relationship, and merging the continuous single-bit gates acting on the same bit to obtain a composite gate. In the case of adjusting the level of the quantum gates in the quantum circuit to be processed, the continuous single-bit gates acting on each bit are determined, and the continuous single-bit gates acting on each bit are merged to obtain corresponding composite gates, respectively. For example, for the bit Q1 in Figure 3 , the quantum gates 7, 8, 11 and 14 are continuous single-bit gates acting on the same bit, which can be merged into a composite gate G. Similarly, the quantum gates 3, 5, 6, 10 and 13 acting on the bit Q2 are continuous single-bit gates acting on the same bit, which can be merged into a composite gate G. It can be understood that “G” only represents that the quantum gate is a composite gate, which is different from a non-composite gate, and cannot represent the specific type of the composite gate obtained by merging multiple quantum gates. The specific type of the composite gate is determined according to the type of the single-bit gate being merged. For example, see Figure 4 , Figure 4 is a schematic diagram of the quantum circuit after quantum merging processing, Figure 4 is a quantum circuit obtained by merging the quantum gates in the quantum circuit in Figure 3 . Figure 4 The quantum circuit in Figure 1 has fewer quantum gates and smaller circuit depth compared with the quantum circuit in Figure 1 , which provides a basis for improving processing efficiency in subsequent quantum simulation.

[0060] On the basis of the above-mentioned embodiments, the to-be-processed quantum circuit or the quantum circuit after the depth adjustment is divided into sub-circuits to obtain at least two first-level sub-circuits, wherein each quantum simulation node does not need to perform data communication between nodes in the process of processing each first-level sub-circuit, so as to reduce the number of data communication between nodes. Each first-level sub-circuit includes a second number of bit positions, and the number of quantum gates included in different first-level sub-circuits can be different, and the bit positions provided with quantum gates are different. Optionally, each first-level sub-circuit includes the lowest k bit positions in a plurality of bit positions, for example, when k = 2, each first-level sub-circuit must include Q0 and Q1 two bit positions. Exemplarily, the second number can be m, and it can be understood that the second number m and k can be preset, and can be set according to the processing capacity of the quantum simulation node.

[0061] In some optional embodiments, a plurality of sub-circuits can be sequentially determined by traversing quantum gates in the to-be-processed quantum circuit or the quantum circuit after the depth adjustment. According to the dependence relationship between quantum gates, different traversal sequences can be generated, and thus different sub-circuit division modes are generated. Optionally, the quantum gates can be sorted according to the order from low layer to high layer and from low bit position to high bit position according to the hierarchy and bit position sequence of the quantum circuit, and the first-level sub-circuit satisfying that the number of bit positions corresponding to the quantum gate is less than or equal to the second number is sequentially determined. Specifically, a bit set Q is constructed to record the quantum bits included in the current sub-circuit. Since the sub-circuit must include the lowest k bits (0 to k-1), Q is initialized as {0, 1,..., k-1}. Then, each quantum gate in the circuit is sequentially traversed according to the sorting, and the set q composed of all quantum bits acted on by the gate is recorded. The size of the union of q and Q is judged: if it does not exceed the maximum allowed number of bits m (i.e., |q∪Q|≤m), the quantum gate is added to the current sub-circuit, and the bits in q are merged into the set Q (updated as Q=Q∪q); if it exceeds m (i.e., |q∪Q|>m), it indicates that the current sub-circuit division is completed. At this time, a new sub-circuit needs to be created, and the set Q is reinitialized as {0, 1,..., k-1}, and the current quantum gate is divided into this new sub-circuit. The traversal and judgment process is repeated until all quantum gates in the circuit are divided into corresponding sub-circuits. Exemplarily, for the quantum circuit shown in FIG. 2, the traversal and judgment process is as follows: Figure 3The shown quantum circuit, k = 2, m = 4, each first sub-circuit includes two bit positions Q0 and Q1, on this basis, for the first layer Q2 without setting quantum gate, in the case of adding sub-circuit 1 to Q3 without setting quantum gate, the number of bit positions with quantum gate in sub-circuit 1 is less than m; in the case of adding sub-circuit 1 to Q4 quantum gate G, the number of bit positions with quantum gate in sub-circuit 1 is equal to m; in the case of adding sub-circuit 1 to Q5 quantum gate G, the number of bit positions with quantum gate in sub-circuit 1 is greater than m, canceling the Q5 quantum gate G added to sub-circuit 1, and sub-circuit 1 is determined to be completed, and the Q5 quantum gate G belongs to sub-circuit 2, and sub-circuit 2 is determined, and the multi-bit gate 2 in the second layer is added to sub-circuit 2, the number of bit positions with quantum gate in sub-circuit 2 is less than m, the multi-bit gate 4 in the third layer is added to sub-circuit 2, the number of bit positions with quantum gate in sub-circuit 2 is greater than m, canceling the multi-bit gate 4 added to sub-circuit 2, sub-circuit 2 is determined to be completed, and the multi-bit gate 4 belongs to sub-circuit 3, and so on, until all quantum gates on the quantum circuit are divided. For example, see Figure 5 , Figure 5 is a schematic diagram of sub-circuit division provided by the embodiment of the present disclosure. According to Figure 5 It can be known that by performing sub-circuit division on the quantum circuit after adjusting the depth of the quantum circuit, six sub-circuits are obtained, and correspondingly, in the process of simulating the quantum circuit, the distributed quantum simulation nodes can complete the simulation of the quantum circuit by performing data communication for only five times, the number of cross-node communication is small, the bandwidth resource is saved, and the processing efficiency is improved.

[0062] It can be understood that by directly performing sub-circuit division on the to-be-processed quantum circuit, a plurality of sub-circuits can also be obtained, and compared with the processing process of the to-be-processed quantum circuit without sub-circuit division, the number of cross-node communication is also small, the bandwidth resource is saved, and the processing efficiency is improved.

[0063] In some optional embodiments, the to-be-processed quantum circuit is divided into at least two first sub-circuits, including: constructing a topological order corresponding to the to-be-processed quantum circuit, the topological order including sequentially ordered quantum gate identifiers; based on the second quantity and the topological order, the to-be-processed quantum circuit is divided into at least two first sub-circuits.

[0064] The topological order can be understood as representing the order of quantum gate execution in a quantum circuit (a quantum circuit to be processed or a quantum circuit after depth adjustment of the quantum circuit), and includes sequentially ordered quantum gate identifiers in the topological order. Each quantum gate identifier is used to uniquely identify a quantum gate. The quantum gate identifier can include, but is not limited to, a numerical identifier and a character identifier, and the like, without limitation. The topological order can be determined based on the dependency relationship of the quantum gates in the quantum circuit.

[0065] Optionally, the topological order is constructed in multiple ways. The time consumption of constructing the topological order based on different construction methods of the topological order is different, and the number of sub-circuits obtained by division is different. For example, the construction method of the topological order includes at least one of the following: overall division, overall optimal division, local optimal division, overall greedy division, and local greedy division. Different construction methods are suitable for different sub-circuit division requirements according to their respective characteristics. For example, see Table 1 for an example table of the characteristics and application scope of different construction methods of the topological order.

[0066] Table 1

[0067]

[0068] It can be understood that the time complexity described above can be understood as time consumption. The greater the time consumption, the higher the time complexity. The time complexity, the number of sub-circuits, the circuit size, and the node transmission rate each correspond to a plurality of classifications. The classification of each of the above indicators can be obtained based on a respective classification threshold, for example, a plurality of threshold ranges of node transmission rates are pre-set, each threshold range corresponds to a node transmission rate type, which can include high, higher, lower, and low types. Through the above table, the classification labels of each construction method of the topological order for multiple indicators such as time complexity, sub-circuit number, circuit size, and node transmission rate are pre-set.

[0069] Optionally, at least one of the transmission rate and time consumption requirement information between the distributed quantum simulation nodes is obtained, and the target construction method of the topological order is determined based on at least one of the transmission rate and time consumption requirement information between the distributed quantum simulation nodes. The transmission rate between the distributed quantum simulation nodes can be determined based on the historical transmission rate or the average transmission rate between the distributed quantum simulation nodes. The time consumption requirement information can be determined according to the selection operation of the time consumption duration or the time consumption level.

[0070] The at least one of the transmission rate and time consumption requirement information between the distributed quantum simulation nodes is matched with the classification label of multiple indicators corresponding to the construction method of the topological order, and the target construction method of the topological order is determined.

[0071] Optionally, the number of qubits and the number of quantum gates of the quantum circuit can also be acquired, the circuit scale is determined according to the number of qubits and the number of quantum gates, and correspondingly, the target construction mode of the topological sorting is determined based on at least one of the transmission rate between the distributed quantum simulation nodes, the time consumption requirement information and the circuit scale. Different circuit scales correspond to a range of the number of qubits and / or a range of the number of quantum gates, the number of qubits is matched with the number of qubits corresponding to each circuit scale and the number of quantum gates, and / or the number of quantum gates is matched with the range of the number of quantum gates corresponding to each circuit scale, so as to determine the circuit scale. Correspondingly, at least one of the transmission rate between the distributed quantum simulation nodes, the time consumption requirement information and the circuit scale is matched with the classification label of a plurality of indexes corresponding to the construction mode of the topological sorting, so as to determine the target construction mode of the topological sorting.

[0072] Optionally, determining the topological sorting based on the overall division mode comprises: constructing a directed acyclic graph corresponding to the quantum circuit to be processed, and generating a target topological sorting based on the dependency relationship between the graph nodes in the directed acyclic graph. The directed acyclic graph includes a graph node corresponding to each quantum gate in the quantum circuit, and a directed edge representing the dependency relationship between quantum gates. The construction mode of the directed acyclic graph comprises: generating a graph node based on the quantum gate identifier of each quantum gate in the quantum circuit, the graph node can carry the quantum gate identifier of the quantum gate, and for quantum gates with a dependency relationship, a directed edge representing the dependency relationship is set between the graph nodes, forming a directed acyclic graph. For example, see Figure 6 , Figure 6 is a directed acyclic graph of a quantum circuit provided by an embodiment of the present disclosure, wherein, Figure 6 the left graph of is a quantum circuit, and the numbers on the quantum gates in the quantum circuit are quantum gate identifiers, Figure 6 the right graph of is a directed acyclic graph corresponding to the quantum circuit.

[0073] According to the overall directed acyclic graph of the quantum circuit, multiple topological sequences can be generated. For quantum gate identifiers with a dependency relationship in the directed acyclic graph, for example, A depends on B, where B is a dependent quantum gate identifier and A is a dependent quantum gate identifier, the dependent quantum gate identifier in the topological sequence is located before the dependent quantum gate identifier, and the quantum gate identifiers without a dependency relationship are randomly ordered. According to the directed acyclic graph of the quantum circuit, multiple topological sequences can be generated. In this embodiment, a topological sequence can be randomly generated according to the directed acyclic graph of the quantum circuit as the target topological sequence. Alternatively, a topological sequence can be generated according to the directed acyclic graph of the quantum circuit, the level and the bit position of the quantum gate, that is, the dependent quantum gate identifier in the topological sequence is located before the dependent quantum gate identifier, and the quantum gate identifiers without a dependency relationship are ordered according to the bit position and the level, the quantum gate identifier with a lower bit position is located before the quantum gate identifier with a higher bit position, and the quantum gate identifier with a lower level is located before the quantum gate identifier with a higher level.

[0074] For example, the first quantum gate identifier in the topological sequence can be a random quantum gate identifier of the independent graph node in the directed acyclic graph, so that Figure 6 For example, the first quantum gate identifier in the topological sequence can be a random quantum gate identifier of the independent graph node in the directed acyclic graph, so that

[0075] Alternatively, the topological sequence can be determined based on the overall optimal partitioning manner, including: constructing a directed acyclic graph corresponding to the to-be-processed quantum circuit, and obtaining a target topological sequence based on the directed acyclic graph by using a backtracking method, that is, a topological sequence capable of partitioning the least sub-circuits. The construction process of the directed acyclic graph is not repeated. The backtracking method is a preferred search method that searches forward according to a selection priority condition to achieve a target. However, when it is found that the original selection is not optimal or cannot achieve the target at a certain step, the method reselects by returning one step. This technique of returning to walk again when it cannot be walked is the backtracking method, and a point of a state that meets the backtracking condition is called a backtracking point. The priority condition is that the least sub-circuits can be partitioned.

[0076] Optionally, determining the topological order based on the local optimal partition manner comprises: performing segmentation processing on the to-be-processed quantum circuit to obtain a plurality of quantum gate groups, constructing a directed acyclic graph corresponding to each quantum gate group, obtaining a sub-topological order corresponding to each quantum gate group based on the directed acyclic graph corresponding to each quantum gate group through backtracking, and obtaining the target topological order based on the sub-topological orders corresponding to the plurality of quantum gate groups.

[0077] It can be understood that in the process of generating the target topological order by the overall optimal partition manner, the amount of processing data is large and the time consumption is long. In the embodiment, the quantum circuit is divided into a plurality of quantum gate groups. For each quantum gate group, a directed acyclic graph corresponding to each quantum gate group is constructed, and a sub-topological order corresponding to each quantum gate group is obtained based on the directed acyclic graph corresponding to each quantum gate group through backtracking. The generation process of the sub-topological order corresponding to each quantum gate group is similar to the overall optimal partition manner, which will not be described here again. The target topological order is obtained by combining the sub-topological orders corresponding to the plurality of quantum gate groups. For example, the quantum circuit can be segmented according to the number of levels of the quantum circuit. For example, the number of quantum gate groups and the number of levels of the quantum circuit determine the number of levels corresponding to each quantum gate group, so as to realize the segmentation processing of the quantum circuit. For example, the number of quantum gate groups can be 2, and the quantum circuit is divided into two quantum gate groups according to the number of levels of the quantum circuit / 2. It can be explained that the number of quantum gate groups is not limited, and the quantum circuit can be divided into different numbers of quantum gate groups according to the size of the quantum circuit.

[0078] Optionally, determining the topological order based on the overall greedy partition manner comprises: constructing a directed acyclic graph corresponding to the to-be-processed quantum circuit, and sequentially determining quantum gate identifiers from the directed acyclic graph to add to the topological order, wherein for any quantum gate identifier in the topological order, the bit multiplexing rate of the quantum gate identifier and the added quantum gate identifiers in the topological order is determined based on a specific bit.

[0079] The first quantum gate identifier in the topological order can be a quantum gate identifier of an independent graph node in the directed acyclic graph, so as to Figure 6The left graph in FIG. 1 is taken as an example. The quantum gate identifiers of the independent graph nodes include 1, 2, 3, and 4. Alternatively, the first quantum gate identifier in the topological sorting can be any one of the quantum gate identifiers of the independent graph nodes. Alternatively, the bit multiplexing rate of the independent graph node in the directed acyclic graph can be determined. The bit multiplexing rate can be determined in the following manner. The bit multiplexing rate of the quantum gate identifier of the independent graph node relative to a specific bit position. Each primary sub-circuit includes a third number of low bit positions in the to-be-processed quantum circuit. The third number of low bit positions can be a specific bit position. If the independent graph node is located on the third number of low bit positions, the bit multiplexing rate is 1. If the independent graph node is not located on the third number of low bit positions, the bit multiplexing rate is 0. Take Figure 6 For example, the third number of low bit positions can be Q0 and Q1. The independent graph node 1 is located on the bit position Q1. The corresponding bit multiplexing rate is 1. The corresponding bit multiplexing rates of the independent graph nodes 2, 3, and 4 are 0. Accordingly, the first quantum gate identifier in the topological sorting can be the quantum gate identifier 1.

[0080] For example, when the quantum gate identifier 1 is taken as the first quantum gate identifier in the topological sorting, the dependence of the successor gate of the quantum gate identifier added in the topological sorting is removed, that is, the dependence of the successor gate 5 of the quantum gate identifier 1 is removed. Accordingly, the other quantum gate identifiers that can be added to the topological sorting include 2, 3, 4, and 5, that is, the independent gates in the current state. According to the bit multiplexing rates of the other quantum gate identifiers and the quantum gate identifiers added in the topological sorting, the other quantum gate identifier corresponding to the maximum bit multiplexing rate is added to the topological sorting as the second quantum gate identifier in the topological sorting. The process is repeated until the topological sorting is obtained.

[0081] The determination manner of the bit multiplexing rate can include the following steps. The number of multiplexed bit positions corresponding to the other quantum gate identifier and the quantum gate identifier added in the topological sorting is obtained. The total number of bit positions corresponding to the quantum gate identifier added in the topological sorting is obtained. The bit multiplexing rate is determined based on the ratio of the number of multiplexed bit positions to the total number of bit positions. For example, the bit multiplexing rate can be represented by the following formula: wherein, The quantum gate identifier The bit position set used by the quantum gate identifier Figure 6 The bit position set corresponding to the quantum gate identifier 1 in the left graph in FIG. 1 is {Q1}. The bit position set corresponding to the quantum gate identifier 5 is {Q1, Q2}. Q represents the bit position set used by the quantum gate identifier added in the topological sorting. It can be understood that each primary sub-circuit includes the lowest k bit positions. Therefore, the lowest k bit positions are in the bit position set used by the quantum gate identifier added in the topological sorting. The number of multiplexed bit positions is represented by The total number of bits is used to represent the added quantum gate identifier pair in the topological sorting.

[0082] Optionally, the topological sorting is determined based on the local greedy partition manner, including: performing segmentation processing on the to-be-processed quantum circuit to obtain a plurality of quantum gate groups, and constructing a directed acyclic graph corresponding to each quantum gate group; for the directed acyclic graph corresponding to each quantum gate group, based on the bit multiplexing rate, quantum gate identifiers are sequentially determined from the directed acyclic graph and added to the topological sorting to obtain a sub-topological sorting corresponding to the quantum gate group, and the target topological sorting is obtained based on the sub-topological sorting corresponding to the plurality of quantum gate groups.

[0083] In the case of performing segmentation processing on the quantum circuit to obtain a plurality of quantum gate groups, for the directed acyclic graph corresponding to each quantum gate group, the bit multiplexing rate is used to determine the sub-topological sorting corresponding to each quantum gate group, and the determination manner of the sub-topological sorting is similar to the overall greedy partition manner, which will not be repeated here. The target topological sorting is obtained based on the sub-topological sorting corresponding to the plurality of quantum gate groups.

[0084] Based on the above embodiment, the to-be-processed quantum circuit is divided into at least two first-order sub-circuits based on the topological sorting. The number of first-order sub-circuits obtained by different topological sortings and the quantum gates included in the first-order sub-circuits are different.

[0085] Optionally, based on the second number and the topological sorting, the to-be-processed quantum circuit is divided into at least two first-order sub-circuits, including: traversing the quantum gate identifiers in the topological sorting, and sequentially adding the quantum gate identifiers in the topological sorting to a first-order sub-circuit set; determining the number of bit positions corresponding to the quantum gate identifiers in the first-order sub-circuit set when any quantum gate identifier is added to the first-order sub-circuit set; if the number of bit positions is less than or equal to the second number, it is determined that the quantum gate identifier is added to the first-order sub-circuit set, the first-order sub-circuit set is updated, and it is continued to determine whether the quantum gate identifier in the topological sorting can be added to the first-order sub-circuit set; if the number of bit positions is greater than the second number, the quantum gate identifier is cancelled from the first-order sub-circuit set, the first-order sub-circuit set is closed, and a new first-order sub-circuit set is set; and a first-order sub-circuit is formed based on the quantum gate identifiers in each first-order sub-circuit set.

[0086] In the case of performing segmentation processing on the quantum circuit to obtain a plurality of quantum gate groups, for the directed acyclic graph corresponding to each quantum gate group, the bit multiplexing rate is used to determine the sub-topological sorting corresponding to each quantum gate group, and the determination manner of the sub-topological sorting is similar to the overall greedy partition manner, which will not be repeated here. The target topological sorting is obtained based on the sub-topological sorting corresponding to the plurality of quantum gate groups. Figure 7Taking the quantum circuits in the example, the topological order can be 1, 2, 3, 4, 5, 12, 6, 9, 7, 8, 11, 10, 13. The first set of first-level sub-circuits in the above topological order is sequentially processed. For example, the first set of first-level sub-circuits may include {1}. For quantum gate identifier 2, if the number of bits corresponding to the quantum gate identifier in the first set of first-level sub-circuits is determined to be 3 (each first-level sub-circuit includes low-order bits of k=2), which is less than the second quantity m, then the first set of first-level sub-circuits is updated to {1, 2}. For quantum gate identifier 3, if the number of bits corresponding to the quantum gate identifier in the first set of first-level sub-circuits is determined to be 4, which is equal to the second quantity m, then the first set of first-level sub-circuits is updated to {1, 2, 3}. For quantum gate identifier 4, if the number of bits corresponding to the quantum gate identifier in the first-level sub-circuit set is 5 when quantum gate identifier 4 is added to the first-level sub-circuit set, which is greater than the second number m, then the addition of the quantum gate identifier to the first-level sub-circuit set is cancelled, and the first-level sub-circuit set is determined to be {1, 2, 3}. The second-level sub-circuit set is set, and quantum gate identifier 4 is added to the second-level sub-circuit set, which is {4}. This process continues until each quantum gate identifier in the topological sort is assigned to a different first-level sub-circuit set, resulting in multiple first-level sub-circuit sets. The quantum gates in each first-level sub-circuit set constitute a first-level sub-circuit.

[0087] For example, see Figure 7 , Figure 7 This is another schematic diagram of sub-circuit division provided in this embodiment of the disclosure. Figure 8 The quantum circuit is divided into two sub-circuits. Accordingly, in the process of quantum circuit simulation, the quantum circuit simulation can be completed through only one cross-node data communication, which reduces the time consumption and bandwidth occupation caused by cross-node data communication and improves the efficiency of quantum circuit simulation.

[0088] Based on the sub-circuit partitioning, the state vector data is further divided into sub-segments to obtain state vector sub-segments. This allows distributed quantum simulation nodes to process each pair of different state vector sub-segments in parallel, leveraging the computational advantages of distributed quantum simulation nodes, improving the efficiency of quantum circuit simulation, and enabling large-scale circuit simulation, thus avoiding the limitation of quantum simulation nodes on circuit size.

[0089] In this embodiment, by dividing the sub-circuits, each first-level sub-circuit is executed in turn, and therefore, the state vector is divided into sub-sections for each first-level sub-circuit, and state vector sub-section information corresponding to each first-level sub-circuit is obtained. Optionally, the state vector is divided into sub-sections for each first-level sub-circuit to obtain state vector sub-section information corresponding to each first-level sub-circuit, including: determining idle bit positions in the first-level sub-circuit that are not provided with quantum gates, and dividing the state vector into a plurality of state vector sub-sections based on state values of the idle bit positions; performing block processing on each state vector sub-section corresponding to each first-level sub-circuit to obtain a plurality of state vector sub-blocks for each first-level sub-circuit, and setting index information of the state vector sub-blocks, and taking the index information of the state vector sub-blocks in each state vector sub-section as the state vector sub-section information.

[0090] The third quantity of low bit positions are included in each first-level sub-circuit in the quantum circuit to be processed; the third quantity can be k. Correspondingly, the third quantity of low bit positions are not included in the idle bit positions in the first-level sub-circuit that are not provided with quantum gates, that is, the idle bit positions are determined in bit positions other than the third quantity of low bit positions in the first-level sub-circuit. For example, bit position j is an idle bit position, and the state vector is divided into two state vector sub-sections, i.e., sub-section a (……0 j ……) and sub-section b (……1 j ……), based on the state value of the idle bit position. There is no dependency between different state vector sub-sections, and therefore, the above state vector sub-sections can be distributed to different quantum simulation nodes for parallel calculation. For example, bit position i and bit position j are idle bit positions, and the state vector is divided into four state vector sub-sections, i.e., sub-section a (…0 i …0 j …), sub-section b (…0 i …1 j …), sub-section c (…1 i …0 j …), and sub-section d (…1 i …1 j …) based on the state values of the idle bit positions. In the quantum circuit, there are n bit positions, each sub-circuit includes m bit positions, and the number of state vector sub-sections is 2 n -m It can be understood that “…” in each sub-section represents a state value of a non-idle bit position, and the state value of any bit position can be 0 or 1. Optionally, the state vector sub-section information can include a state vector sub-section identifier to mark each state vector sub-section.

[0091] Since each primary sub-circuit involves different bit positions, each time the divided state vector sub-segment also has differences. To facilitate the calculation of the position of each state vector sub-segment in the original state vector, the state vector sub-segment can be further divided into smaller state vector sub-blocks. Each primary sub-circuit includes a third number of low bit positions in the quantum circuit to be processed, and the state vector data can be divided into state vector sub-blocks with a size of 2 k . Each state vector sub-segment can include a plurality of state vector sub-blocks, and the state vector sub-block is the smallest data unit and cannot be further split. Correspondingly, the state vector sub-segment information can include index information of a plurality of state vector sub-blocks in the state vector sub-segment.

[0092] Each state vector sub-block includes 2 k continuous amplitudes, and the index information of the state vector sub-block is determined based on the high n-k bits of the quantum state. Taking n=5 and k=2 as an example, the index information of each state vector sub-block is determined based on the state values of the 3-5 bits of the quantum state.

[0093] Optionally, the index information of each state vector sub-block is set by: obtaining state combination values corresponding to other bit positions in the primary sub-circuit except the third number of low bit positions, and forming the index information of a state vector sub-block based on each state combination value. Among the other bit positions in the primary sub-circuit except the third number of low bit positions, there can be idle bit positions and non-idle bit positions. The state value of the idle bit position is fixed in each state vector sub-segment, and the state value of the non-idle bit position can be 0 or 1. A plurality of state combination values are formed according to the state value of the idle bit position and the state value of the non-idle bit position, each state combination value corresponds to a state vector sub-block, and the index information of the corresponding state vector sub-block is determined based on each state combination value.

[0094] For example, referring to Figure 8 , Figure 8 is a schematic diagram of the index information of the state vector sub-block provided by the embodiment of the present disclosure. Figure 8In the sub-circuit, bit positions Q0, Q1, Q2 and Q4 are non-idle bit positions, and bit position Q3 is an idle bit position. The state vector can be divided into two state vector sub-segments, i.e., sub-segment 0 and sub-segment 1. Each bit position in the sub-circuit can be represented by (· × ···). The '×' represents an idle bit position, and the '·' represents a non-idle bit position. Different state vector sub-segments correspond to different state values of the idle bit positions. For example, the state value of the idle bit position in sub-segment 0 is 0, and the state value of the idle bit position in sub-segment 1 is 1. The combined state value of the high n-k bits is taken as a binary value and converted into a decimal value as the index information of the state vector sub-block. For example, for the high n-k bits (·0·) of sub-segment 0, the combined state value can be (000), (001), (100), (101) when the state values of the non-idle bit positions are 0 or 1, respectively. The combined state value is converted into a decimal value as a binary value: 1, 2, 4, 5. That is, sub-segment 0 corresponds to four state vector sub-blocks, and the index information of the state vector sub-blocks is 0, 1, 4, 5, respectively. Similarly, the index information of the four state vector sub-blocks corresponding to sub-segment 1 is 2, 3, 6, 7, respectively. The index information and the data of the state vector sub-blocks are shown in Figure 8 Figure 9 The state vector sub-block corresponding to field 0 in the above table is a blue block, and the four state vector sub-blocks corresponding to sub-segment 1 are white blocks.

[0095] Optionally, the index information of each state vector sub-block is set by: in the case that the bit positions in the primary sub-circuit are discontinuous, rearranging the bit positions in the primary sub-circuit to make the non-idle bit positions in the primary sub-circuit continuous; and based on the state combination values corresponding to the bit positions other than the third number of low bit positions in the primary sub-circuit after the rearrangement, forming the index information of a state vector sub-block based on each state combination value.

[0096] In this embodiment, the bit positions in the primary sub-circuit are rearranged to map the non-idle bit positions that are discontinuous in the primary sub-circuit to continuous states. That is, the rearrangement is not needed when the non-idle bit positions in the primary sub-circuit are continuous. Specifically, the non-idle bit positions of high bits can be sequentially mapped to the idle bit positions of low bits. For example, bit position i is an idle bit position, and bit positions i+1 and i+2 are non-idle bit positions. Bit position i+1 is mapped to bit position i. At this time, bit position i+1 can be regarded as an idle bit position, and bit position i+2 is mapped to bit position i+1, and so on.

[0097] For example, Figure 9 , Figure 9 The bit rearrangement diagram provided by the embodiment of the present disclosure is shown in the figure. In the figure, the bit positions filled with gray are non-idle bit positions, Figure 8 ​The non-idle bits in the middle left figure are discontinuous, and the non-idle bits in the quantum circuit are continuous after rearrangement. The index information of the state vector sub-blocks is determined based on the state combination values corresponding to the bits in the first-level sub-circuit after rearrangement except for the third number of low bits. The determination method of the index information of the state vector sub-blocks is similar to the above-mentioned embodiments, and will not be described here.

[0098] During the bit rearrangement process, the continuous amplitudes in each state vector sub-block do not change, and the bit rearrangement is only used to set the index information of each state vector sub-block. For example, Figure 8 After rearrangement of the sub-circuit in Figure 10 , the index information of the four state vector sub-blocks in sub-section 0 is 0, 1, 2, and 3, respectively, and the index information of the four state vector sub-blocks in sub-section 1 is 4, 5, 6, and 7, respectively, and the state vector sub-block data in each field does not change.

[0099] It can be understood that according to the above-mentioned method, at least two state vector sub-sections corresponding to each first-level sub-circuit and a plurality of state vector sub-blocks included in each state vector sub-section can be determined, and state vector sub-section information corresponding to each first-level sub-circuit is obtained. The distributed quantum simulation nodes are controlled to perform parallel line simulation processes through the state vector sub-section information corresponding to each first-level sub-circuit. The control process can be realized through pre-set code data. After bit rearrangement of the non-continuous sub-circuit, it can be regarded as a continuous line containing a second number of bits, and the code data of the existing conventional continuous quantum line can be reused for line simulation calculation, without the need to repeatedly write new code data. In the present embodiment, the bit rearrangement method is used to make the state vector sub-section information of at least two state vector sub-sections of different first-level sub-circuits consistent, so as to realize the reuse of code data.

[0100] On the basis of the above-mentioned embodiments, the distributed quantum simulation nodes sequentially execute each first-level sub-circuit, wherein each first-level sub-circuit has an execution time sequence. For each first-level sub-circuit, each quantum simulation node processes the state vector sub-section data corresponding to the state vector sub-section corresponding to the first-level sub-circuit, and the distributed multiple quantum simulation nodes process the state vector sub-section data corresponding to the multiple state vector sub-sections in parallel.

[0101] The state vector subsegment data corresponding to different primary subcircuits are different, and after each quantum simulation node completes execution of a first primary subcircuit, the quantum simulation node performs data communication based on state vector subsegment information corresponding to the first primary subcircuit and state vector subsegment information corresponding to a second primary subcircuit, and continues to execute the second primary subcircuit. The first primary subcircuit is any primary subcircuit except the last primary subcircuit in the plurality of primary subcircuits, and the second primary subcircuit is an adjacent primary subcircuit after the first primary subcircuit. Through data communication between the quantum simulation nodes, the state vector subsegment data in the memory of each quantum simulation node is exchanged, and after the data exchange, the state vector subsegment data in the memory of each quantum simulation node matches the state vector subsegment information corresponding to the second primary subcircuit, so as to meet the data condition for executing the second primary subcircuit.

[0102] Optionally, based on at least two state vector subsegment information corresponding to a first primary subcircuit, initial state vector subsegment data is distributed to the distributed quantum simulation nodes, so that each quantum simulation node stores the initial state vector subsegment data in the memory and sequentially executes simulation calculation of each primary subcircuit; wherein the initial state vector subsegment data can be understood as unprocessed state vector subsegment data, and the state vector subsegment data includes a plurality of state vector block data in the state vector subsegment.

[0103] At least two state vector subsegment information corresponding to a first primary subcircuit, i.e. index information of each state vector block in each state vector subsegment, is obtained, and state vector block data corresponding to the index information of each state vector block in different state vector subsegments is distributed to different quantum simulation nodes, so that each quantum simulation node can execute simulation calculation of the first primary subcircuit on state vector block data in one state vector subsegment.

[0104] For example, referring to Figure 10 , Figure 10 is a schematic diagram of data exchange between distributed quantum simulation nodes in a circuit simulation process. Wherein, subcircuit 1 is the first primary subcircuit, and through four state vector subsegment information corresponding to subcircuit 1, a plurality of state vector block data in the state vector subsegment are respectively distributed to node 0-node 3, so that the four quantum simulation nodes perform parallel processing on subcircuit 1. Specifically, state vector block data with index information 0, 1, 4 and 5 can be distributed to node 0, state vector block data with index information 2, 3, 6 and 7 can be distributed to node 1, state vector block data with index information 8, 9, 12 and 13 can be distributed to node 2, and state vector block data with index information 10, 11, 14 and 15 can be distributed to node 3.

[0105] In the simulation process, the data communication is performed between the quantum simulation nodes in the case of switching between different levels of sub-lines. Specifically, the data communication is performed based on the state vector sub-segment information corresponding to the first level sub-line and the state vector sub-segment information corresponding to the second level sub-line, including: for any quantum simulation node, determining updated state vector sub-segment information based on the state vector sub-segment information corresponding to the first level sub-line and the state vector sub-segment information corresponding to the second level sub-line, and performing communication transmission of local state vector sub-segment data corresponding to the updated state vector sub-segment information between the quantum simulation nodes.

[0106] For example, sub-line 1 is the first level sub-line, and sub-line 2 is the second level sub-line. The updated state vector sub-segment information is determined based on the state vector sub-segment information corresponding to sub-line 1 and the state vector sub-segment information corresponding to sub-line 2. The updated state vector sub-segment information can be the index information of the local or all state vector sub-blocks in each quantum simulation node. The updated state vector sub-segment information can include the index information of the state vector sub-blocks that change in the state vector sub-segment information corresponding to sub-line 1 and the state vector sub-segment information corresponding to sub-line 2. For example, the updated state vector sub-segment information in node 0 is 4 and 5, and the updated state vector sub-segment information in node 1 is 2 and 3. That is, data exchange is performed between node 0 and node 1, and data exchange is performed between node 2 and node 3. After the data exchange, the index information of the state vector sub-block data in each quantum simulation node satisfies the state vector sub-segment information corresponding to sub-line 2, and can satisfy the continued execution of sub-line 2.

[0107] Similarly, after the execution of sub-line 2 is completed, sub-line 2 is taken as the first level sub-line, and sub-line 3 is taken as the second level sub-line. The updated state vector sub-segment information is determined based on the state vector sub-segment information corresponding to sub-line 2 and the state vector sub-segment information corresponding to sub-line 3. The data exchange is performed between the quantum simulation nodes, so that the index information of the state vector sub-block data in each quantum simulation node satisfies the state vector sub-segment information corresponding to sub-line 3 after the data exchange, and the continued execution of sub-line 3 can be satisfied, until the simulation calculation of all level sub-lines is completed. Among them, Figure 10 In each sub-line, the non-idle bit is represented by yellow, Figure 11 In each node, the index information in the red block represents the updated state vector sub-segment information.

[0108] In the case of completing the simulation calculation of all level sub-lines, the state vector sub-block data in the distributed quantum simulation nodes is integrated to obtain the simulation calculation result.

[0109] The technical scheme of the embodiment is that the processing quantum circuit is divided into at least two first-order sub-circuits, so that the distributed quantum simulation node does not need to perform cross-node data transmission in the process of executing each first-order sub-circuit, the number of cross-node data transmission in the circuit simulation process is reduced, the communication delay and bandwidth consumption caused by cross-node communication are reduced, and the overall processing efficiency of the circuit simulation process is improved. Further, the state vector in the process of each first-order sub-circuit is segmented and processed, so that the distributed quantum simulation node can execute each first-order sub-circuit in parallel for different state vector segments, realize parallel processing in the circuit simulation process, fully exert the resource advantage of the distributed quantum simulation node, and improve the calculation efficiency of the circuit simulation.

[0110] Figure 11 is a flowchart of a distributed computing quantum circuit simulation method provided by the embodiment of the disclosure. On the basis of the above embodiment, the memory resources of the distributed quantum simulation node are determined. When the memory resources of the distributed quantum simulation node do not meet the demand resource amount of the quantum circuit to be processed, the external storage resources of the distributed quantum simulation node are started, and large-scale circuit simulation calculation is realized by the auxiliary calculation mode of combination of the internal storage and the external storage. As shown in Figure 12 , the method comprises:

[0111] S210, obtaining a quantum circuit to be processed, the number of quantum bits of the quantum circuit to be processed being a first number.

[0112] S220, determining a demand resource amount according to the number of bits of the quantum circuit to be processed; determining the total internal storage resource amount and the total external storage resource amount of the distributed quantum simulation node based on the number of nodes of the distributed quantum simulation node, the internal storage resource amount and the external storage resource amount of each quantum simulation node.

[0113] S230, in the case where the demand resource amount is less than the total internal storage resource amount of the distributed quantum simulation node, performing sub-circuit division on the quantum circuit to be processed to obtain at least two first-order sub-circuits with a second number of quantum bits, the second number being less than the first number;

[0114] S240, performing sub-segment division on the state vector based on each first-order sub-circuit to obtain state vector sub-segment information corresponding to each first-order sub-circuit; distributing state vector sub-segment data corresponding to the state vector sub-segment information of each first-order sub-circuit to the distributed quantum simulation node, so that each quantum simulation node performs simulation calculation of the at least two first-order sub-circuits based on the state vector sub-segment data corresponding to the state vector sub-segment information in turn, until the simulation calculation result is obtained.

[0115] S250, in the case that the required resource amount is greater than the total memory resource amount of the distributed quantum simulation nodes and less than or equal to the total external storage resource amount of the distributed quantum simulation nodes, performing secondary sub-circuit division on the to-be-processed quantum circuit to obtain at least two primary sub-circuits and at least two secondary sub-circuits in each primary sub-circuit, and sequentially executing the at least two secondary sub-circuits in each primary sub-circuit by the distributed quantum simulation nodes.

[0116] S260, performing sub-segment division on the state vector based on each primary sub-circuit to obtain state vector sub-segment information corresponding to each primary sub-circuit; distributing state vector sub-segment data corresponding to the state vector sub-segment information corresponding to each primary sub-circuit to the distributed quantum simulation nodes, so that each quantum simulation node sequentially performs simulation calculation of the at least two primary sub-circuits based on the state vector sub-segment data corresponding to the state vector sub-segment information, until a simulation calculation result is obtained.

[0117] It can be understood that for complex quantum circuit simulation, the required memory increases exponentially with the increase of the number of qubits, and even in a distributed computing environment, the memory requirement is very large. When the dimension of the state vector is too large, the required storage space exceeds the total memory resource amount of the distributed quantum simulation nodes, and the memory of the distributed quantum simulation nodes cannot meet the requirement of circuit simulation. In order to solve the above technical problems, in the embodiment, an auxiliary calculation mode combining memory and external storage is used to meet the storage resource requirement of complex quantum circuit simulation. The external storage resource of the quantum simulation node can be provided by the external storage component carried by the quantum simulation node.

[0118] In the case that the to-be-processed quantum circuit includes a first number n of bits, the required resource amount corresponding to the to-be-processed quantum circuit can be 2n nThe memory resource amount of each quantum simulation node and the external storage resource amount of each quantum simulation node are obtained. The quantum simulation node can be an available quantum simulation node, for example, a quantum simulation node in an idle state. The total memory resource amount of the distributed quantum simulation nodes is determined by the product of the memory resource amount of each quantum simulation node and the number of the distributed quantum simulation nodes. The total external storage resource amount of the distributed quantum simulation nodes is determined by the product of the external storage resource amount of each quantum simulation node and the number of the distributed quantum simulation nodes. The required resource amount corresponding to the to-be-processed quantum circuit is compared with the total memory resource amount of the distributed quantum simulation nodes. If the required resource amount corresponding to the to-be-processed quantum circuit is less than the total memory resource amount of the distributed quantum simulation nodes, it indicates that the memory resource of the distributed quantum simulation nodes can support the simulation calculation process on the to-be-processed quantum circuit. If the required resource amount corresponding to the to-be-processed quantum circuit is greater than the total memory resource amount of the distributed quantum simulation nodes and less than or equal to the total memory resource amount of the distributed quantum simulation nodes, it indicates that the memory resource of the distributed quantum simulation nodes cannot support the simulation calculation on the to-be-processed quantum circuit, and the simulation calculation on the to-be-processed quantum circuit needs to be implemented by the auxiliary calculation mode combining the memory and the external storage. If the required resource amount corresponding to the to-be-processed quantum circuit is greater than the total memory resource amount of the distributed quantum simulation nodes, it indicates that the external storage resource needs to be expanded.

[0119] In the case that the required resource amount corresponding to the to-be-processed quantum circuit is less than the total memory resource amount of the distributed quantum simulation nodes, the simulation calculation on the to-be-processed quantum circuit is performed through steps S230 and S240 to obtain the simulation calculation result. In the case that the required resource amount corresponding to the to-be-processed quantum circuit is greater than the total memory resource amount of the distributed quantum simulation nodes and less than or equal to the total memory resource amount of the distributed quantum simulation nodes, steps S250 and S260 are performed to divide the to-be-processed quantum circuit into secondary sub-circuits, so as to perform the simulation calculation on the to-be-processed quantum circuit to obtain the simulation calculation result.

[0120] In this embodiment, the quantum circuit (to-be-processed quantum circuit or quantum circuit after circuit depth adjustment) is divided into one-level sub-circuits to obtain at least two one-level sub-circuits with a second number of quantum bits. Each one-level sub-circuit is further divided into two-level sub-circuits to obtain at least two two-level sub-circuits in each one-level sub-circuit. The two-level sub-circuit contains a fourth number of bits, and the fourth number is less than the second number. The demand resource amount corresponding to the two-level sub-circuit is less than or equal to the memory resource amount of each quantum simulation node. The fourth number can be determined according to the memory resource amount of each quantum simulation node. The division method of the two-level sub-circuit is similar to that of the one-level sub-circuit, for example, it can include: constructing a topological order corresponding to the one-level sub-circuit, dividing the one-level sub-circuit based on the fourth number and the topological order corresponding to the one-level sub-circuit to obtain at least two two-level sub-circuits, which will not be repeated here.

[0121] Similarly, the state vector is divided into sub-segments for each one-level sub-circuit to obtain state vector sub-segment information corresponding to each one-level sub-circuit, and index information of state vector sub-blocks in each state vector sub-segment corresponding to the one-level sub-circuit. Further, the index information of the state vector sub-block corresponding to the two-level sub-circuit included in the one-level sub-circuit is determined, wherein the index information of the state vector sub-block corresponding to the two-level sub-circuit can include at least two local sub-block index information. For example, see Figure 12 , Figure 13 is a schematic diagram of two-level division of a quantum circuit provided by an embodiment of the present disclosure. See Figure 13 , Figure 12 is a schematic diagram of index information of state vector sub-blocks corresponding to one-level sub-circuits and two-level sub-circuits, respectively. According to Figure 12 It can be known that the one-level sub-circuit is divided into two two-level sub-circuits S1 and S2, the one-level sub-circuit corresponds to four state vector sub-segments, and the index information of the state vector sub-blocks corresponding to the two two-level sub-circuits is independent of each other and does not overlap, wherein the non-idle bits in the one-level sub-circuit are set as pink background, the non-idle bits in the two-level sub-circuit S1 are set as green background, and the non-idle bits in the two-level sub-circuit S2 are set as blue background for partition display.

[0122] For example, Figure 13For example, the first number is 6, the second number is 4, the third number is 2, and the fourth number is 3. Taking node 0 as an example, bit Q3 and Q5 are free bits, and their state values can be 0, and the state values of padding bits Q2 and Q4 are 0, 1, 4, and 5. For sub-line S1, sub-segment 0 sequence number (0)2, filling Q2 bit can be represented as (0x00), and filling other bits can obtain (0000), (0100), that is, 0 and 4; sub-segment 1 sequence number (1)2, filling Q2 bit can be represented as (0x01), and filling other bits can obtain (0001), (0101), that is, 1 and 5. For sub-line S2, sub-segment 0 sequence number (0)2, filling Q4 bit can be represented as (000x), and filling other bits can obtain (0000), (0001), that is, 0 and 1; sub-segment 1 sequence number (1)2, filling Q4 bit can be represented as (010x), and filling other bits can obtain (0100) and (0101), that is, 4 and 5.

[0123] The state vector sub-segment data corresponding to the state vector sub-segment information corresponding to each of the primary sub-lines is distributed to the distributed quantum simulation nodes for storage in the external storage of each quantum simulation node. Specifically, the initial state vector sub-segment data can be distributed to the distributed quantum simulation nodes based on at least two state vector sub-segment information corresponding to the first primary sub-line, so that the quantum simulation nodes store the initial state vector sub-segment data in the external storage, and sequentially simulate and calculate the secondary sub-lines in each primary sub-line. Figure 12 For example, specifically, the state vector sub-block data with index information 0, 1, 4, and 5 can be distributed to node 0, the state vector sub-block data with index information 2, 3, 6, and 7 can be distributed to node 1, the state vector sub-block data with index information 8, 9, 12, and 13 can be distributed to node 2, and the state vector sub-block data with index information 10, 11, 14, and 15 can be distributed to node 3. The above-mentioned state vector sub-block data is respectively stored in the external storage of each quantum simulation node.

[0124] In the simulation and calculation process of any primary sub-line in the quantum simulation node, at least two secondary sub-lines in the primary sub-line are sequentially executed, and specifically: based on the index information of the state vector sub-block corresponding to the first secondary sub-line, the first state vector sub-block data is read from the external storage, the first secondary sub-line is executed, and the executed first state vector sub-block data is written into the external storage; based on the index information of the state vector sub-block corresponding to the second secondary sub-line, the second state vector sub-block data is read from the external storage, the second secondary sub-line is executed, and the executed second state vector sub-block data is written into the external storage, until each secondary sub-line in the primary sub-line is executed.

[0125] The first and second level sub-circuits can be any two consecutive second level sub-circuits from the first level sub-circuit. Each second level sub-circuit can correspond to at least one local segment, and each local segment includes at least one state vector sub-block. When executing any second level sub-circuit for any quantum simulation node, the corresponding state vector sub-block data is read from the external memory of the quantum simulation node based on the index information of at least one state vector sub-block in each local segment. After executing the second level sub-circuit, the obtained state vector sub-block data is written back to the external memory of the quantum simulation node, and at least one state vector sub-block data in the next local segment is read, until the second level sub-circuit has completed processing all at least one local segment corresponding to the second level sub-circuit, and then the next second level sub-circuit is executed.

[0126] by Figure 14 For example, for the first-level sub-circuit, the first-level sub-circuit can be the second-level sub-circuit S1, and the second-level sub-circuit can be the second-level sub-circuit S2. The distributed quantum simulation nodes execute each second-level sub-circuit in parallel. For any quantum simulation node, taking node 0 as an example, the first-level sub-circuit S1 corresponds to two local segments, namely local segment 0 and local segment 1. Based on the index information 0 and 4 of the state vector sub-block of local segment 0 corresponding to the first and second-level sub-line S1, the first state vector sub-block data corresponding to index information 0 and 4 is read from the external memory of node 0. Node 0 executes the first and second-level sub-line S1 based on the first state vector sub-block data to obtain the executed first state vector sub-block data, and writes the executed first state vector sub-block data back to the external memory. Based on the index information 1 and 5 of the state vector sub-block of local segment 1 corresponding to the first and second-level sub-line S1, the first state vector sub-block data corresponding to index information 1 and 5 is read from the external memory of node 0. Node 0 executes the first and second-level sub-line S1 based on the first state vector sub-block data to obtain the executed first state vector sub-block data, and writes the executed first state vector sub-block data back to the external memory.

[0127] The first and second-level sub-line S2 corresponds to two local sub-segments, namely local sub-segment 0 and local sub-segment 1. Based on the index information 0 and 1 of the state vector sub-block corresponding to the second-level sub-line S2, the second state vector sub-block data corresponding to index information 0 and 1 is read from the external memory of node 0. Node 0 executes the second and second-level sub-line S2 based on the second state vector sub-block data to obtain the executed second state vector sub-block data, and writes the executed second state vector sub-block data back to the external memory. Based on the index information 4 and 5 of the state vector sub-block corresponding to the second-level sub-line, the second state vector sub-block data corresponding to index information 4 and 5 is read from the external memory of node 0. Node 0 executes the second and second-level sub-line S2 based on the second state vector sub-block data to obtain the executed second state vector sub-block data, and writes the executed second state vector sub-block data back to the external memory.

[0128] When the first primary sub-circuit does not include other secondary sub-circuits, it is determined that the first primary sub-circuit is executed and completed.

[0129] Based on the state vector sub-segment information corresponding to the first primary sub-circuit and the state vector sub-segment information corresponding to the second primary sub-circuit, updated state vector sub-segment information is determined, and local state vector sub-segment data corresponding to the updated state vector sub-segment information is communicated and transmitted between the quantum simulation nodes, so as to update the vector sub-segment data in the external storage of each quantum simulation node. The vector sub-segment data in the external storage of each quantum simulation node after the update matches the state vector sub-segment information corresponding to the second primary sub-circuit. At least two secondary sub-circuits in the second primary sub-circuit are sequentially executed until the simulation calculation on all primary sub-circuits is completed, and a simulation calculation result is obtained.

[0130] The technical scheme of the embodiment compares the required resource amount and the total internal memory resource amount and the total external storage resource amount of the distributed quantum simulation nodes respectively, determines whether the auxiliary simulation calculation of the internal memory and the external storage needs to be performed, performs secondary sub-circuit division on the to-be-processed quantum circuit in the case that the total internal memory resource amount of the distributed quantum simulation nodes is insufficient to support the simulation calculation of the to-be-processed quantum circuit, and realizes the parallel simulation calculation of the to-be-processed quantum circuit by means of the external storage resource of each quantum simulation node, realizes the block loading of the state vector data, avoids being limited by the internal memory resource, and can support the simulation of a complex large-scale quantum circuit.

[0131] The embodiment of the present disclosure provides an example of a quantum circuit simulation method for distributed computing. Figure 14 , Figure 15 is a schematic diagram of a quantum circuit simulation method for distributed computing provided by the embodiment of the present disclosure. In the embodiment, the bit number of the to-be-processed quantum circuit is n, k=2, the node number of the distributed quantum simulation node is r, the available external storage resource amount of each quantum simulation node is 2 l+4 bytes, the available internal memory resource amount of each quantum simulation node is 2 m+4 bytes, and the required resource amount corresponding to the to-be-processed quantum circuit can be 2 n . If 2 n ≤r×2 m , distributed computing (as method 1) is performed, that is, the to-be-processed quantum circuit is divided into primary sub-circuits and the circuit simulation is performed. m n ≤r×2 l , the simulation calculation process of the external storage assistance+distributed computing (as method 2) is performed, that is, the to-be-processed quantum circuit is divided into secondary sub-circuits and the circuit simulation is performed.

[0132] For method 1:

[0133] ​Step (1): divide the original quantum circuit into several primary sub-circuits, each containing m qubits, calculate and construct a block index table to record the block index of each sub-segment in each primary sub-circuit, so as to allocate data blocks to each node;

[0134] Step (2): block the initial state vector;

[0135] Step (3): process each primary sub-circuit in turn:

[0136] Step (3.1): rearrange the quantum gates: if the bit positions in the primary sub-circuit are not continuous, move the high-bit quantum gate operation to the low bit to remap it to continuous bit index to form a continuous primary sub-circuit, if the bit positions are already continuous, no rearrangement is needed.

[0137] Step (3.2): simulate the primary sub-circuit (this process can directly call the simulator operation without circuit segmentation, that is, it can simulate the conventional continuous quantum circuit with m qubits, so it can be compatible with existing quantum computing simulator framework): allocate sub-blocks to each node according to the index table, in each node, construct a state vector simulator with m bits, aggregate the sub-blocks into a sub-segment and set it as the initial state of the simulator, then execute the quantum gate operations in the primary sub-circuit in turn. Inside the sub-node, use thread-level parallelism to accelerate the execution speed of the gate operation. If there are other primary sub-circuits, go back to step (3), otherwise go to step (4);

[0138] Step (4): aggregate the calculation results from all nodes to obtain the complete state vector.

[0139] For method 2:

[0140] Step (1): divide the original circuit into two levels, construct a block index table containing external and internal memory allocation information: primary sub-circuit determines external memory allocation sub-block; secondary sub-circuit determines the sub-block read into the internal memory each time;

[0141] Step (2): block the initial state vector;

[0142] Step (3): simulate each primary sub-circuit in turn:

[0143] Step (3.1): allocate sub-blocks to external memory according to the index table for each node;

[0144] Step (3.2): Simulate each secondary sub-circuit (i.e. m-sub-circuit) in turn: (1) index rearrangement of quantum gate operations; (2) construct a state vector simulator with m bits (still compatible with other simulator frameworks); (3) process each sub-section in turn: read in the corresponding sub-blocks to form a sub-section and set as the initial state of the simulator, then execute the rearranged quantum gate operations, and then re-block the results according to the original index and write back to the external memory. Due to the slow read-write speed of internal and external memory, the read-write operations of each sub-block can be performed in parallel. Repeat this process until all sub-sections are calculated;

[0145] Step (4): Obtain the complete state vector from all nodes and complete the calculation.

[0146] Figure 15 is a structural schematic diagram of a distributed computing quantum circuit simulation device provided by an embodiment of the present disclosure. As shown in Figure 16 , the device comprises:

[0147] A quantum circuit acquisition module 310 is configured to acquire a quantum circuit to be processed, wherein the number of quantum bits of the quantum circuit to be processed is a first number.

[0148] A sub-circuit division module 320 is configured to divide the quantum circuit to be processed into at least two first-level sub-circuits, each of which has a second number of quantum bits, wherein the second number is less than the first number.

[0149] A state vector division module 330 is configured to divide a state vector into sub-sections based on each of the first-level sub-circuits, to obtain state vector sub-section information corresponding to each of the first-level sub-circuits.

[0150] An analog computing module 340 is configured to distribute state vector sub-section data corresponding to the state vector sub-section information of each of the first-level sub-circuits to distributed quantum simulation nodes, so that each of the quantum simulation nodes performs analog computation of the at least two first-level sub-circuits based on the state vector sub-section data corresponding to the state vector sub-section information, until an analog computation result is obtained.

[0151] In the present embodiment, after each of the quantum simulation nodes completes the first first-level sub-circuit, the quantum simulation nodes perform data communication based on the state vector sub-section information corresponding to the first first-level sub-circuit and the state vector sub-section information corresponding to the second first-level sub-circuit, and continue to execute the second first-level sub-circuit.

[0152] The technical scheme of the embodiment divides the processing quantum circuit into at least two first-order sub-circuits, so that the distributed quantum simulation nodes do not need to perform cross-node data transmission in the process of executing each first-order sub-circuit, the number of cross-node data transmission in the circuit simulation process is reduced, the communication delay and bandwidth consumption caused by cross-node communication are reduced, and the overall processing efficiency of the circuit simulation process is improved. Further, the state vector in the process of each first-order sub-circuit is processed in segments, so that the distributed quantum simulation nodes can execute each first-order sub-circuit in parallel for different state vector segments, realize parallel processing in the circuit simulation process, fully exert the resource advantage of the distributed quantum simulation nodes, and improve the calculation efficiency of the circuit simulation.

[0153] On the basis of the above-mentioned embodiment, the device further comprises a circuit depth adjusting module for adjusting the circuit depth of the to-be-processed quantum circuit before the to-be-processed quantum circuit is divided into sub-circuits.

[0154] The circuit depth adjusting module is specifically configured to perform at least one of the following: removing redundant quantum gate combinations acting on the same bit; merging continuous single-bit gates acting on the same bit to obtain a composite gate; adjusting the levels of quantum gates acting on different bits without changing the dependency relationship, so that quantum gates acting on different bits and not having a dependency relationship are arranged in parallel.

[0155] On the basis of the above-mentioned embodiment, the sub-circuit division module 320 is configured to: construct a topological order corresponding to the to-be-processed quantum circuit, wherein the topological order comprises quantum gate identifiers in sequence.

[0156] The to-be-processed quantum circuit is divided into sub-circuits based on the second number and the topological order, and at least two first-order sub-circuits are obtained.

[0157] Optionally, the topological order is constructed in multiple ways, and the time consumption for constructing the topological order is different based on different construction ways of the topological order, and the number of sub-circuits obtained by division is different.

[0158] The sub-circuit division module 320 is further configured to: acquire at least one of the transmission rate and the time consumption requirement information between the distributed quantum simulation nodes, and determine the target construction way of the topological order based on at least one of the transmission rate and the time consumption requirement information between the distributed quantum simulation nodes.

[0159] Optionally, the sub-circuit division module 320 is further configured to perform at least one of the following:

[0160] constructing a directed acyclic graph corresponding to the to-be-processed quantum circuit, and randomly generating a topological order based on a dependency relationship between nodes in the directed acyclic graph;

[0161] constructing a directed acyclic graph corresponding to the to-be-processed quantum circuit, and obtaining a target topological order based on the directed acyclic graph by using a backtracking method;

[0162] segmenting the to-be-processed quantum circuit to obtain a plurality of quantum gate groups, constructing a directed acyclic graph corresponding to each quantum gate group, and obtaining a sub-topological order corresponding to each quantum gate group based on the directed acyclic graph corresponding to each quantum gate group by using a backtracking method, and obtaining a target topological order based on the sub-topological orders corresponding to the plurality of quantum gate groups.

[0163] constructing a directed acyclic graph corresponding to the to-be-processed quantum circuit, and sequentially determining quantum gate identifiers in the directed acyclic graph to be added to a topological order, wherein for any quantum gate identifier in the topological order, a bit multiplexing rate is determined based on the quantum gate identifier and the quantum gate identifiers already added to the topological order / specific bit positions.

[0164] segmenting the to-be-processed quantum circuit to obtain a plurality of quantum gate groups, constructing a directed acyclic graph corresponding to each quantum gate group, and for the directed acyclic graph corresponding to each quantum gate group, sequentially determining quantum gate identifiers in the directed acyclic graph to be added to a topological order to obtain a sub-topological order corresponding to the quantum gate group based on a bit multiplexing rate, and obtaining a target topological order based on the sub-topological orders corresponding to the plurality of quantum gate groups.

[0165] Optionally, the sub-circuit division module 320 is further configured to traverse the quantum gate identifiers in the topological order and sequentially add the quantum gate identifiers in the topological order to a first-level sub-circuit set.

[0166] determining the number of bit positions corresponding to the quantum gate identifiers in the first-level sub-circuit set in the case where any quantum gate identifier in the first-level sub-circuit set is added to the first-level sub-circuit set, and if the number of bit positions is less than or equal to the second number, determining that the quantum gate identifier is added to the first-level sub-circuit set, updating the first-level sub-circuit set, and continuing to determine whether the quantum gate identifiers in the topological order can be added to the first-level sub-circuit set; if the number of bit positions is greater than the second number, canceling the addition of the quantum gate identifier to the first-level sub-circuit set, closing the first-level sub-circuit set, and setting a new first-level sub-circuit set; and forming a first-level sub-circuit based on the quantum gate identifiers in each first-level sub-circuit set.

[0167] On the basis of the above-mentioned embodiment, optionally, the state vector division module 330: determines idle bits in the first-level sub-circuit which are not provided with quantum gates, divides the state vector into a plurality of state vector segments based on state values of the idle bits; performs block processing on each state vector segment corresponding to each first-level sub-circuit to obtain a plurality of state vector blocks of the first-level sub-circuit, sets index information of each state vector block, and takes the index information of the state vector block in each state vector segment as the state vector segment information.

[0168] Optionally, each of the first-level sub-circuits includes a third number of low bits in the to-be-processed quantum circuit;

[0169] The state vector division module 330 is further configured to: obtain state combination values corresponding to other bits in the first-level sub-circuit except for the third number of low bits, and form index information of a state vector block based on each state combination value.

[0170] Optionally, the state vector division module 330 is further configured to: in the case that non-idle bits in the first-level sub-circuit are discontinuous, rearrange the bits in the first-level sub-circuit to make the non-idle bits in the first-level sub-circuit continuous; form index information of a state vector block based on each state combination value based on state combination values corresponding to other bits in the first-level sub-circuit except for the third number of low bits.

[0171] Optionally, the simulation calculation module 340 is further configured to:

[0172] based on the at least two state vector segment information corresponding to the first first-level sub-circuit, distribute initial state vector segment data to the distributed quantum simulation nodes, so that each quantum simulation node stores the initial state vector segment data in the memory and sequentially performs simulation calculation of each first-level sub-circuit;

[0173] and for any quantum simulation node, based on the state vector segment information corresponding to the first first-level sub-circuit and the state vector segment information corresponding to the second first-level sub-circuit, determine updated state vector segment information, and perform communication transmission of local state vector segment data corresponding to the updated state vector segment information between each quantum simulation node.

[0174] On the basis of the above-mentioned embodiment, optionally, the sub-circuit division module 320 is further configured to:

[0175] determining a required resource amount according to a bit number of the to-be-processed quantum circuit; determining a total memory resource amount and a total external storage resource amount of the distributed quantum simulation nodes based on a node number of the distributed quantum simulation nodes, a memory resource amount and an external storage resource amount of each quantum simulation node; in a case where the required resource amount is less than the total memory resource amount of the distributed quantum simulation nodes, performing sub-circuit division on the to-be-processed quantum circuit to obtain at least two primary sub-circuits; in a case where the required resource amount is greater than the total memory resource amount of the distributed quantum simulation nodes and less than or equal to the total external storage resource amount of the distributed quantum simulation nodes, performing secondary sub-circuit division on the to-be-processed quantum circuit to obtain at least two primary sub-circuits and at least two secondary sub-circuits in each primary sub-circuit, and sequentially executing at least two secondary sub-circuits in each primary sub-circuit by the distributed quantum simulation nodes.

[0176] Optionally, the secondary sub-circuit includes a fourth number of quantum bits, and the fourth number is less than the second number.

[0177] The required resource amount corresponding to the secondary sub-circuit is less than or equal to the memory resource amount of each quantum simulation node.

[0178] Optionally, the state vector sub-segment information corresponding to each primary sub-circuit includes index information of a state vector sub-block in each state vector sub-segment corresponding to the primary sub-circuit, and index information of a state vector block corresponding to each secondary sub-circuit.

[0179] Optionally, the simulation calculation module 340 is further configured to: based on the at least two state vector sub-segment information corresponding to the first primary sub-circuit, distribute initial state vector sub-segment data to the distributed quantum simulation nodes, so that the quantum simulation nodes store the initial state vector sub-segment data in the external storage, and sequentially perform simulation calculation on the secondary sub-circuits in each primary sub-circuit.

[0180] In the simulation calculation process of the quantum simulation node on any primary sub-circuit: based on index information of a state vector block corresponding to a first secondary sub-circuit, reading first state vector block data from the external storage, executing the first secondary sub-circuit, and writing executed first state vector block data into the external storage; based on index information of a state vector block corresponding to a second secondary sub-circuit, reading second state vector block data from the external storage, executing the second secondary sub-circuit, and writing executed second state vector block data into the external storage, until each secondary sub-circuit in the primary sub-circuit is executed.

[0181] The quantum circuit simulation device for distributed computing provided by the embodiments of the present disclosure can execute the quantum circuit simulation method for distributed computing provided by any of the embodiments of the present disclosure, and has the corresponding function modules and beneficial effects of the execution method.

[0182] Figure 16 is a structural schematic diagram of an electronic device provided by the embodiments of the present disclosure. The electronic device 10 is intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular telephones, smart phones, wearable devices (such as headsets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be examples only, and are not intended to limit the implementations of the present disclosure described and / or claimed in this document.

[0183] As shown in ​ The electronic device 10 includes at least one processor 11, and a memory, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., which is communicatively connected to the at least one processor 11, wherein the memory stores a computer program executable by the at least one processor. The processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 into the random access memory (RAM) 13. In the random access memory (RAM) 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the read-only memory (ROM) 12, and the random access memory (RAM) 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0184] A plurality of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network, such as the Internet, and / or various telecommunications networks.

[0185] The processor 11 can be various general and / or special purpose processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, and the like. The processor 11 performs various methods and processes described above, such as the distributed computing quantum circuit simulation method.

[0186] In some embodiments, the distributed computing quantum circuit simulation method can be implemented as a computer program tangibly embodied in a computer readable storage medium, such as the storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed onto the electronic device 10 via the read-only memory (ROM) 12 and / or the communication unit 19. When the computer program is loaded onto the random access memory (RAM) 13 and executed by the processor 11, one or more steps of the distributed computing quantum circuit simulation method described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to perform the distributed computing quantum circuit simulation method by any other suitable means, such as by means of firmware.

[0187] Various implementations of the systems and techniques described above can be realized in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a programmable logic device (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0188] A computer program for implementing the quantum circuit simulation method of distributed computing of the present disclosure can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general-purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the computer program, when executed by the processor, implements the functions / operations specified in the flowcharts and / or block diagrams. The computer program can be executed entirely on a machine, partially on a machine, partially on a machine as a standalone software package and partially on a remote machine, or entirely on a remote machine or server.

[0189] The embodiments of the present disclosure also provide a computer readable storage medium, which stores computer instructions for causing a processor to execute a quantum circuit simulation method of distributed computing, the method comprising:

[0190] obtaining a to-be-processed quantum circuit, the number of qubits of the to-be-processed quantum circuit being a first number; performing sub-circuit division on the to-be-processed quantum circuit to obtain at least two first-level sub-circuits each having a second number of qubits, the second number being less than the first number; performing sub-segment division on a state vector based on each of the first-level sub-circuits to obtain state vector sub-segment information corresponding to each of the first-level sub-circuits; distributing state vector sub-segment data corresponding to the state vector sub-segment information of each of the first-level sub-circuits to distributed quantum simulation nodes, so that each of the quantum simulation nodes performs simulation calculation of the at least two first-level sub-circuits based on the state vector sub-segment data corresponding to the state vector sub-segment information in sequence until a simulation calculation result is obtained; wherein, after each of the quantum simulation nodes completes execution of a first first-level sub-circuit, data communication is performed based on the state vector sub-segment information corresponding to the first first-level sub-circuit and the state vector sub-segment information corresponding to a second first-level sub-circuit, and the second first-level sub-circuit is continuously executed.

[0191] In the context of the present disclosure, the computer readable storage medium can be a tangible medium that can contain or store the computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the above. Alternatively, the computer readable storage medium can be a machine readable signal medium. More specific examples of the machine readable storage medium will include one or more wires, portable computer disks, hard disk drives, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disc read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above.

[0192] To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the electronic device. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0193] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), blockchain network, and the Internet.

[0194] The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. A server can be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system, to solve the defects of large management difficulty and weak business scalability in traditional physical host and VPS service.

[0195] The embodiments of the present disclosure further provide a computer program product, comprising a computer program, which, when executed by a processor, implements the quantum circuit simulation method for distributed computing according to any of the embodiments of the present disclosure.

[0196] Computer program products can be written in any one of a number of programming languages, including object oriented languages such as Java, Smalltalk, C++, or conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0197] It should be understood that the various forms of flow shown above can be re-ordered, added to, or have steps deleted. For example, the steps recited in the present disclosure can be performed in parallel, in series, or in a different order, as long as the desired results of the present disclosure are achieved, and are not limited herein.

[0198] The specific embodiments discussed above have been presented by way of example only and not limitation. It will be apparent to persons skilled in the art that various modifications, combinations, sub-combinations, and alternatives can be made to the specific embodiments without departing from the spirit and principles of the disclosure. Any such modifications, equivalents, and alternatives are intended to fall within the scope of the disclosure.

Claims

1. A method for simulating quantum circuits in distributed computing, characterized in that, include: Obtain the quantum circuit to be processed, wherein the number of qubits in the quantum circuit to be processed is a first quantity; The quantum circuit to be processed is divided into sub-circuits to obtain at least two first-level sub-circuits with a second number of qubits, where the second number is less than the first number. Based on each of the first-level sub-lines, the state vector is divided into segments to obtain the state vector segment information corresponding to each of the first-level sub-lines; The state vector segment data corresponding to the state vector segment information of each first-level sub-circuit is distributed to distributed quantum simulation nodes, so that each quantum simulation node sequentially performs simulation calculations of at least two first-level sub-circuits based on the state vector segment data corresponding to the state vector segment information until the simulation calculation result is obtained; After completing the execution of the first-level sub-circuit, each quantum simulation node performs data communication based on the state vector sub-segment information corresponding to the first-level sub-circuit and the state vector sub-segment information corresponding to the second-level sub-circuit, and continues to execute the second-level sub-circuit.

2. The method according to claim 1, characterized in that, Before dividing the quantum circuit to be processed into sub-circuits, the method also includes adjusting the circuit depth of the quantum circuit to be processed. The line depth adjustment includes at least one of the following: Remove redundant quantum gate combinations that act on the same bit; By merging consecutive single-bit gates that operate on the same bit, a composite gate is obtained. Without changing the dependencies, the quantum gates acting on each bit are hierarchically adjusted so that independent quantum gates acting on different bits can be set up in parallel.

3. The method according to claim 1 or 2, characterized in that, The quantum circuit to be processed is divided into sub-circuits to obtain at least two first-order sub-circuits, including: Construct a topological sort for the quantum circuit to be processed, wherein the topological sort includes sequentially ordered quantum gate identifiers; Based on the second quantity and the topological sorting, the quantum circuit to be processed is divided into sub-circuits to obtain at least two first-level sub-circuits.

4. The method according to claim 3, characterized in that, There are multiple ways to construct the topology sorting. The time required to construct the topology sorting based on different topology sorting methods is different, as are the number of sub-lines obtained. The method further includes: Obtain at least one of the transmission rate and time consumption requirements between the distributed quantum simulation nodes, and determine the target construction method of the topology sorting based on at least one of the transmission rate and time consumption requirements between the distributed quantum simulation nodes.

5. The method according to claim 3, characterized in that, Constructing the topological ordering corresponding to the quantum circuit to be processed includes at least one of the following: Construct a directed acyclic graph corresponding to the quantum circuit to be processed, and randomly generate a topological sort based on the dependency relationship between the nodes in the directed acyclic graph. Construct a directed acyclic graph corresponding to the quantum circuit to be processed, and obtain the target topological sort based on the directed acyclic graph using a backtracking method; The quantum circuit to be processed is segmented to obtain multiple quantum gate groups. A directed acyclic graph corresponding to each quantum gate group is constructed. By backtracking, a sub-topological sort corresponding to each quantum gate group is obtained based on the directed acyclic graph corresponding to each quantum gate group. A target topological sort is obtained based on the sub-topological sorts corresponding to multiple quantum gate groups. Construct a directed acyclic graph corresponding to the quantum circuit to be processed, and sequentially determine quantum gate identifiers from the directed acyclic graph and add them to the topological sort. For any quantum gate identifier in the topological sort, the determination is based on the bit reuse rate of the quantum gate identifier and the quantum gate identifiers / specific bits already added in the topological sort. The quantum circuit to be processed is segmented to obtain multiple quantum gate groups, and a directed acyclic graph corresponding to each quantum gate group is constructed. For each directed acyclic graph corresponding to a quantum gate group, the quantum gate identifiers are determined sequentially from the directed acyclic graph based on the bit reuse rate and added to the topological sorting to obtain the sub-topological sorting corresponding to the quantum gate group. The target topological sorting is obtained based on the sub-topological sortings corresponding to multiple quantum gate groups.

6. The method according to claim 3, characterized in that, Based on the second quantity and the topological sorting, the quantum circuit to be processed is divided into sub-circuits to obtain at least two first-level sub-circuits, including: Traverse the quantum gate identifiers in the topological sort and add them sequentially to the first-level sub-circuit set: Determine the number of bits corresponding to any of the quantum gate identifiers in the first-level sub-circuit set when any of the quantum gate identifiers is added to the first-level sub-circuit set; If the number of bits is less than or equal to the second number, then the quantum gate identifier is determined to be added to the first-level sub-circuit set, the first-level sub-circuit set is updated, and it is further determined whether the quantum gate identifier in the topological sorting can be added to the first-level sub-circuit set. If the number of bits is greater than the second number, then cancel adding the quantum gate identifier to the first-level sub-circuit set, close the first-level sub-circuit set, and set a new first-level sub-circuit set; A first-level sub-circuit is formed based on the quantum gate identifiers in each set of first-level sub-circuit sets.

7. The method according to claim 1, characterized in that, Based on each of the first-level sub-lines, the state vector is segmented to obtain the state vector segment information corresponding to each of the first-level sub-lines, including: Identify the unused bits in the first-level sub-circuit that do not have quantum gates, and divide the state vector into multiple state vector sub-segments based on the state values ​​of the unused bits; Each state vector sub-segment corresponding to each first-level sub-line is divided into blocks to obtain multiple state vector sub-blocks for each first-level sub-line. Index information of each state vector sub-block is set, and the index information of the state vector sub-block in each state vector sub-segment is used as the state vector sub-segment information.

8. The method according to claim 7, characterized in that, Each of the first-level sub-circuits includes a third number of low-order bits in the quantum circuit to be processed; The setting of index information for each state vector sub-block includes: Obtain the state combination values ​​corresponding to the other bits in the first-level sub-line, excluding the third number of low-order bits, and form the index information of a state vector sub-block based on each state combination value.

9. The method according to claim 7, characterized in that, Configure the index information for each state vector sub-block, including: In the case where non-idle bits in the first-level sub-line are not consecutive, the bits in the first-level sub-line are rearranged to make the non-idle bits in the first-level sub-line consecutive. Based on the state combination values ​​corresponding to the other bits in the rearranged first-level sub-line except for the third number of low-order bits, index information of a state vector sub-block is formed based on each of the state combination values.

10. The method according to claim 1, characterized in that, The method further includes: Based on at least two state vector segments corresponding to the first-level sub-circuit, the initial state vector segment data is distributed to the distributed quantum simulation nodes, so that each quantum simulation node stores the initial state vector segment data in memory and executes the simulation calculation of each first-level sub-circuit in sequence; Furthermore, during the simulation calculation process, data communication is performed based on the state vector segment information corresponding to the first-level sub-line and the state vector segment information corresponding to the second-level sub-line, including: For any of the quantum simulation nodes, updated state vector segment information is determined based on the state vector segment information corresponding to the first-level sub-circuit and the state vector segment information corresponding to the second-level sub-circuit, and communication transmission of the local state vector segment data corresponding to the updated state vector segment information is performed between the quantum simulation nodes.

11. The method according to claim 1, characterized in that, The method further includes: The required resource quantity is determined based on the number of bits in the quantum circuit to be processed; The total memory resources and total external storage resources of the distributed quantum simulation nodes are determined based on the number of nodes, the memory resources of each quantum simulation node, and the external storage resources. If the required resources are less than the total memory resources of the distributed quantum simulation nodes, the quantum circuit to be processed is divided into sub-circuits to obtain at least two first-level sub-circuits. When the required resource amount is greater than the total memory resource amount of the distributed quantum simulation node and less than or equal to the total external memory resource amount of the distributed quantum simulation node, the quantum circuit to be processed is divided into secondary sub-circuits to obtain at least two primary sub-circuits and at least two secondary sub-circuits in each primary sub-circuit. At least two secondary sub-circuits in each primary sub-circuit are executed sequentially by the distributed quantum simulation node.

12. The method according to claim 11, characterized in that, The secondary sub-line contains a fourth number of bits, which is less than the second number; The resource requirements corresponding to the secondary sub-circuit are less than or equal to the memory resource requirements of each quantum simulation node.

13. The method according to claim 11, characterized in that, The state vector sub-segment information corresponding to each of the first-level sub-lines includes: the index information of the state vector sub-blocks in each state vector sub-segment corresponding to the first-level sub-line, and the index information of the state vector sub-blocks corresponding to each of the second-level sub-lines; The method further includes: Based on at least two state vector segments corresponding to the first-level sub-circuit, the initial state vector segment data is distributed to the distributed quantum simulation nodes, so that the quantum simulation nodes store the initial state vector segment data in external memory and perform simulation calculations on the second-level sub-circuits in each first-level sub-circuit in sequence. During the simulation calculation of any first-level sub-circuit at the quantum simulation node: based on the index information of the state vector sub-block corresponding to the first-level sub-circuit, the first state vector sub-block data is read from the external memory, the first-level sub-circuit is executed, and the executed first state vector sub-block data is written to the external memory; based on the index information of the state vector sub-block corresponding to the second-level sub-circuit, the second state vector sub-block data is read from the external memory, the second-level sub-circuit is executed, and the executed second state vector sub-block data is written to the external memory, until all second-level sub-circuits in the first-level sub-circuit are executed.

14. A quantum circuit simulation device for distributed computing, characterized in that, include: A quantum circuit acquisition module is used to acquire a quantum circuit to be processed, wherein the number of qubits in the quantum circuit to be processed is a first quantity; The sub-circuit partitioning module is used to partition the quantum circuit to be processed into sub-circuit segments to obtain at least two first-level sub-circuit segments with a second number of qubits, where the second number is less than the first number. The state vector partitioning module is used to divide the state vector into segments based on each of the first-level sub-lines to obtain the state vector segment information corresponding to each of the first-level sub-lines. The simulation calculation module is used to distribute the state vector sub-segment data corresponding to the state vector sub-segment information of each of the first-level sub-circuits to distributed quantum simulation nodes, so that each of the quantum simulation nodes sequentially performs simulation calculations of at least two first-level sub-circuits based on the state vector sub-segment data corresponding to the state vector sub-segment information until the simulation calculation result is obtained; After completing the execution of the first-level sub-circuit, each quantum simulation node performs data communication based on the state vector sub-segment information corresponding to the first-level sub-circuit and the state vector sub-segment information corresponding to the second-level sub-circuit, and continues to execute the second-level sub-circuit.

15. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the quantum circuit simulation method for distributed computing as described in any one of claims 1-13.

16. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed by a processor, implement the quantum circuit simulation method for distributed computing as described in any one of claims 1-13.

17. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the quantum circuit simulation method for distributed computing according to any one of claims 1-13.

Images