Computing node, method and device for detecting computing node

Abstract

The disclosure provides a kind of computing node, the detection method and equipment of computing node, it is related to computer technical field, by powering on computing node, BMC detects the type of central processing unit according to the configuration pin of mainboard, configures communication link;According to the deployment environment of rack in situ pin determination computing node, and load the out-of-band monitoring strategy corresponding to deployment environment;According to power supply configuration detection whether there is voltage conversion module, adjust I2C rate;The configuration information of graphics processor node connected with computing node is detected, and the switch and central processing unit are configured;According to the interconnection mode of switch downstream in situ state determination switch, and carry out global address space mapping;Control complex programmable logic device to central processing unit power on.In this way, the adaptability, stability, reliability and performance of computing node can be improved, signal attenuation and jitter in transmission process are reduced, and data transmission efficiency and quality are improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of computer, and particularly relates to a computing node, a detection method and equipment of the computing node. BACKGROUND

[0002] In the related art, with the rapid development of artificial intelligence technology, large models have been widely applied in various fields, and inference calculation has become the most important demand for computing power at present. With the acceleration of the landing application of super-large scale models, new servers and cabinet architectures are also increasingly inclined to GPUs (Graphics Processing Unit), and the computing nodes still use general servers. Since the interconnection bandwidth of the general server is usually low, this not only affects the transmission speed, but also may cause signal attenuation and jitter for long-distance transmission. SUMMARY

[0003] The present disclosure provides a computing node, a detection method and equipment of the computing node. The main purpose is to solve the technical problem that long-distance transmission may cause signal attenuation and jitter.

[0004] According to a first aspect of the present disclosure, a computing node is provided, comprising a mainboard, a power adapter board, and a front window input / output module; wherein:

[0005] The mainboard comprises a central processing unit, a dual in-line memory module connected with the central processing unit, a voltage regulation module, a multi-channel input / output connector, a baseboard management controller module, and a complex programmable logic device;

[0006] The power adapter board comprises a power module, a power blind plug connector, and a signal blind plug connector, and the power adapter board is connected with the mainboard;

[0007] The front window input / output module comprises a hard disk, an input / output panel, and a network card, and is connected with the multi-channel input / output connector of the mainboard through the network card.

[0008] According to a second aspect of the present disclosure, a detection method of a computing node is provided, applied to a computing node, and the detection method of the computing node comprises:

[0009] After the computing node is powered on, the type of the central processing unit is detected according to the configuration pin of the mainboard through the baseboard management controller module, and a communication link is configured according to the type of the central processing unit;

[0010] The deployment environment of the computing node is determined according to the cabinet in-place pin, and an out-of-band monitoring strategy corresponding to the deployment environment is loaded;

[0011] According to the power supply configuration, it is detected whether there is a voltage conversion module, and the I2C rate is adjusted according to the detection result.

[0012] Configuration information of a graphics processor node connected with the computing node is detected, and the switch and the central processor are configured according to the configuration information.

[0013] According to the downlink in-place state of the switch, the interconnection mode of the switch is determined, and global address space mapping is performed according to the interconnection mode.

[0014] The complex programmable logic device is controlled to power on the central processor.

[0015] According to a third aspect of the present disclosure, a detection device of a computing node is provided, comprising:

[0016] A link configuration module is configured to detect the type of the central processor according to the configuration pin of the mainboard through the baseboard management controller module after the computing node is powered on, and configure the communication link according to the type of the central processor.

[0017] A loading module is configured to determine the deployment environment of the computing node according to the cabinet in-place pin, and load the out-of-band monitoring strategy corresponding to the deployment environment.

[0018] An adjustment module is configured to detect whether there is a voltage conversion module according to the power supply configuration, and adjust the I2C rate according to the detection result.

[0019] A configuration module is configured to detect the configuration information of a graphics processor node connected with the computing node, and configure the switch and the central processor according to the configuration information.

[0020] A mapping module is configured to determine the interconnection mode of the switch according to the downlink in-place state of the switch, and perform global address space mapping according to the interconnection mode.

[0021] A power-on module is configured to control the complex programmable logic device to power on the central processor.

[0022] According to a fourth aspect of the present disclosure, an electronic device is provided, comprising:

[0023] At least one processor; and

[0024] A memory in communication connection with the at least one processor; wherein,

[0025] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method of the second aspect.

[0026] According to a fifth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause the computer to perform the method of the preceding second aspect.

[0027] According to a sixth aspect of the present disclosure, a computer program product is provided, comprising a computer program which, when executed by a processor, implements the method of the preceding second aspect.

[0028] In summary, the method provided by the embodiments of the present disclosure can detect the type of the central processor according to the configuration pin of the mainboard through the baseboard management controller module after the computing node is powered on, and configure the communication link according to the type of the central processor; determine the deployment environment of the computing node according to the in-place pin of the cabinet, and load the out-of-band monitoring strategy corresponding to the deployment environment; detect whether there is a voltage conversion module according to the power supply configuration, and adjust the I2C rate according to the detection result; detect the configuration information of the graphics processor node connected with the computing node, and configure the switch and the central processor according to the configuration information; determine the interconnection mode of the switch according to the downlink in-place state of the switch, and perform global address space mapping according to the interconnection mode; and control the complex programmable logic device to power on the central processor. In this way, not only can the automatic detection and configuration of the computing node be realized, the labor cost and errors are reduced, and the configuration error risk and cost are reduced; but also different monitoring strategies can be loaded according to different deployment environments, the I2C rate can be adjusted according to the power supply configuration, the SW and the CPU can be configured according to the configuration of the GPU node, and the address mapping can be performed according to the interconnection mode of the SW, so that the adaptability, stability, reliability and performance of the computing node can be effectively improved, the signal attenuation and jitter in the transmission process can be reduced, and the data transmission efficiency and quality can be improved.

[0029] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0030] The accompanying drawings are used to better understand the present scheme and do not limit the present disclosure. Among them:

[0031] Figure 1 A flowchart of a computing node provided by an embodiment of the present disclosure is shown;

[0032] Figure 2a A structural schematic diagram of a computing node under a platform provided by an embodiment of the present disclosure is shown;

[0033] Figure 2b A structural schematic diagram of a computing node under another platform provided by an embodiment of the present disclosure is shown;

[0034] Figure 3a A structural schematic diagram of a liquid cooling cold plate of a GPU node provided by an embodiment of the present disclosure is shown in FIG. 7.

[0035] Figure 3b A structural schematic diagram of a liquid cooling cold plate of a computing node provided by an embodiment of the present disclosure is shown in FIG. 8.

[0036] Figure 4a A signal logic design schematic diagram of a mainboard provided by an embodiment of the present disclosure is shown in FIG. 9.

[0037] Figure 4b Another signal logic design schematic diagram of a mainboard provided by an embodiment of the present disclosure is shown in FIG. 10.

[0038] Figure 5a A liquid leakage detection schematic diagram of a single machine provided by an embodiment of the present disclosure is shown in FIG. 11.

[0039] Figure 5b A liquid leakage detection schematic diagram of an entire cabinet provided by an embodiment of the present disclosure is shown in FIG. 12.

[0040] Figure 6 A flow schematic diagram of a detection method of a computing node provided by an embodiment of the present disclosure is shown in FIG. 13.

[0041] Figure 7 A power-on detection flow schematic diagram provided by an embodiment of the present disclosure is shown in FIG. 14.

[0042] Figure 8a A single machine design schematic diagram of a computing node provided by an embodiment of the present disclosure is shown in FIG. 15.

[0043] Figure 8b An entire cabinet design schematic diagram of a computing node provided by an embodiment of the present disclosure is shown in FIG. 16.

[0044] Figure 9 A structural schematic diagram of a detection device of a computing node provided by an embodiment of the present disclosure is shown in FIG. 17. DETAILED DESCRIPTION

[0045] Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, which include various details of the embodiments of the present disclosure to assist in understanding, and should be considered as merely exemplary. Thus, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Also, in order to be clear and concise, descriptions of well-known functions and structures are omitted in the following description.

[0046] The computing node, the detection method and the device of the computing node of the embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0047] Figure 1This is a schematic diagram of a computing node provided in an embodiment of this disclosure. Figure 1 As shown, the computing node includes a motherboard, a power adapter board, and a front window input / output module, wherein:

[0048] The motherboard includes a central processing unit (CPU), a dual in-line memory module, a voltage regulator module, a multi-channel input / output connector, a baseboard management controller module, and complex programmable logic devices connected to the CPU.

[0049] The power adapter board includes a power module, a power blind-mating connector, and a signal blind-mating connector. The power adapter board is connected to the motherboard.

[0050] The front window input / output module includes a hard drive, an input / output panel, and a network card, and is connected to the motherboard's multi-channel input / output connector via the network card.

[0051] The compute nodes can be designed with an IU (Inter-Unit) height. For example... Figure 1 As shown, the computing node can consist of three parts: a motherboard, a power adapter board, and a front-window I / O module. The entire computing node can adopt a two-level blind-mating structure (power blind-mating and signal blind-mating), connecting to the server or rack power supply backplane and cable backplane via a rear-window power blind-mating connector. For example, by using a two-level signal blind-mating and power blind-mating structure with a power adapter board, compatibility with two or more different voltage power supplies can be achieved, such as 54V or 12V power supply compatibility; moreover, based on the blind-mating structure, compatibility between single-machine and rack-wide systems can also be achieved, the specific implementation of which will be described in subsequent embodiments.

[0052] The number of CPUs (Central Processing Units) can be one, two, or more, and the CPUs can be from different series and models; the number of DIMMs (Dual-Inline-Memory-Modules) can also be customized, such as 24 or 32; the number of CPU VRs (Central Processing Unit Voltage Regulators) can also be customized; and the MCIO connectors (Multi-Channel I / O) can be high-speed signal connectors.

[0053] Furthermore, the power adapter board also reserves space for liquid cooling pipes to accommodate liquid cooling modules; the network cards include at least a PCIe network card and an Open Compute Project network card, and the front window input / output module is connected to the motherboard's multi-channel input / output connector via the PCIe network card.

[0054] The power adapter plate can also reserve a liquid cooling pipe space to support the design of a liquid cooling cold plate, and is used to set a liquid cooling module to dissipate heat for the node and improve the stability and performance of the computing node. The network card in the front window IO module can include a PCIE network card and an OPC network card (open computing project network card), and the front window IO module can be connected to the multi-channel input and output connector of the mainboard through the PCIE network card. In this way, the PCIE network card has lower delay and higher reliability, which can ensure the stable operation of the node under high load; the combination of the PCIE network card and the OCP network card can adapt to different network requirements and also realize high-speed transmission of data.

[0055] As an example, refer to Figure 2a the structural diagram of a computing node under another platform shown in Figure 2b It can be seen that the front window IO module of the computing node can include an SSD (Solid State Disk), a PCIE network card, an OCP network card, and an IO panel, or in some platforms, the front window IO module of the computing node can also include an M.2, which can refer to an expansion card or connector of the M.2 interface, and the M.2 is a computer internal expansion card and connector specification. The mainboard can include a CPU, an MCIO connector, a CPU VR, a DIMM, and a BMC (Baseboard Management Controller) module. The power adapter plate can include a 54V to 12V power line, a power blind connector, and a high-density signal blind connector. As a specific example, the mainboard can include 2 CPUs, 24 / 32 DIMMs, a CPU VR, a high-speed signal MCIO connector, a BMC module, a CPLD (Complex Programmable Logic Device), etc., the CPU can support multiple series and models, all PCIE network card resources are connected to the MCIO connector on the mainboard, two x16 PCIE resources of the rear window can be used for interconnection of the CPU and the PCIE SW (switch), and the remaining PCIE resources are used to connect to the hard disk, PCIE network card, OCP network card, etc. IO module in the front window of the host node.

[0056] As an example, the power adapter plate can also reserve a liquid cooling pipe space to support the design of a liquid cooling cold plate, and is used to set a liquid cooling module. It can be understood that the liquid cooling module can include a liquid cooling cold plate. As a specific example, refer to Figure 3a the GPU node liquid cooling cold plate design shown in Figure 3bThe liquid cooling cold plate design of the illustrated compute node, the cold plate design of the GPU node can include: a GPU cold plate that can be in direct contact with the GPU chip, responsible for absorbing the heat generated by the GPU; a manifold that can be a pipe connecting the GPU cold plate and the external cooling system, used to transport the cooling liquid; a volume damper instead of a blind plug, which can be a pipe for connecting the inflow and outflow of the cooling liquid, and can contain a quick connector for easy installation and maintenance; a volume damper instead of a quick connector, which can be used to implement an inlet and outlet design, allowing quick connection and disconnection of the flow of cooling liquid, facilitating maintenance and upgrading. The liquid cooling cold plate design structure of the compute node can include: a CPU cold plate that can be in direct contact with the CPU, used to absorb the heat generated by the CPU; a DIMM cold plate that can be in direct contact with the DIMM, used to cool the DIMM; a volume damper instead of a quick connector, similar to the GPU cold plate, which can be used to connect the inflow and outflow of the cooling liquid, and can contain a quick connector for easy installation and maintenance; an inlet and outlet for allowing the cooling liquid to flow into and out of the cold plate for heat exchange.

[0057] In the compute node provided in the embodiments of the present disclosure, the BMC module can be used for out-of-band management and control of the entire AI (Artificial Intelligence, artificial intelligence) server system, and the BMC module can be placed with a BMC chip, an EMMC (embedded MultiMediaCard, embedded multimedia card), a BMC Boot Flash (substrate management controller startup flash), etc. The BMC module is interconnected with the mainboard through a 4C+ connector. The signal logic design of the mainboard can be as shown in Figure 4a and Figure 4b as shown, see Figure 4a and Figure 4bThe BMC module can output some signals to the front window IO panel, such as a UART (Universal Asynchronous Receiver / Transmitter Signal) signal, a VGA (Video Graphics Array Signal) signal, and an RGMII (Reduced Gigabit Media Independent Interface Signal) signal. Meanwhile, the BMC module is connected with a CPU through ESPI (Enhanced Serial Peripheral Interface Signal), PECI (Platform Environment Control Interface Signal), and SPI (Serial Peripheral Interface Signal) signals. In order to shorten the wiring distance, the BMC module can be placed close to the CPU and the IO panel. In order to save space, the BMC module can be designed in a vertical card form and has a height less than 1U cabinet height. Different from the conventional server design, the BMC module also needs to be managed across nodes. The I2C (Inter-Integrated Circuit) signal of the BMC can be connected to an AI acceleration node through a high-speed signal connector, and is used for the BMC to read and monitor some states of the AI acceleration node, such as temperature, voltage, and alarm information.

[0058] Further, the computing node further comprises a board card; the board card is provided with a liquid leakage detection module; the liquid leakage detection module comprises a liquid leakage detection line, a liquid leakage detection connector connected through the liquid leakage detection line, a switch arranged in the liquid leakage detection line, an amplifier connected with the liquid leakage detection line, a complex programmable logic device connected with the amplifier, and an analog-to-digital converter.

[0059] In the case where the node is provided with a liquid cooling module, a liquid leakage detection module can also be provided for detecting liquid leakage of the liquid cooling module. As an example, the liquid leakage detection module can be provided on a board card of the node, and the liquid leakage detection module includes a liquid leakage detection line. As an example, each liquid leakage detection line can include two connection terminals and a terminal resistor, and the terminal resistor is infinite by default, indicating an open circuit state. A liquid leakage detection connector connected by the liquid leakage detection line can also be included, and the number of the liquid leakage detection connector can be customized, for example, set to 2. Each liquid leakage detection connector can have three signal lines, including leakage_B, leakage_R, and Leakage_Prsnt. Under normal circumstances, after the liquid leakage detection line is plugged in, leakage_B and Leakage_Prsnt are turned on and pulled down to ground, and the CPLD can determine that the liquid leakage detection module is in place. In addition, a switch provided in the liquid leakage detection line can be used to control whether the liquid leakage detection line is connected to the liquid leakage detection circuit; an amplifier connected to the liquid leakage detection line can be used to amplify the signal transmitted through the liquid leakage detection line; and a complex programmable logic device (CPLD) and an analog-to-digital converter (ADC) connected to the amplifier can be used. The CPLD can be used to process the amplified signal and determine whether the liquid leakage detection line is in place, and the ADC can convert the analog signal to a digital signal for processing by the CPLD.

[0060] As an example, Figure 5a and Figure 5b respectively show a structure diagram of a single-machine liquid leakage detection link and a whole-cabinet liquid leakage detection link. Referring to Figure 5a , the single-machine liquid leakage detection link can include a BMC for monitoring and managing the hardware state of the server, including receiving and processing liquid leakage detection signals; a CPLD for processing signals from the amplifier module, determining whether liquid leakage occurs, and controlling subsequent actions; an amplifier for amplifying weak signals from the liquid leakage detection line so that the CPLD can clearly detect them; a liquid leakage detection line including two connection terminals and a terminal resistor (default open circuit, infinite resistance) for detecting whether the cooling liquid leaks; a gating switch for controlling whether the liquid leakage detection line is connected to the circuit for detection or maintenance; a connector for connecting the liquid leakage detection line and the amplifier module, and feeding back signals to the BMC; a signal line including leakage_B, leakage_R, and Leakage_Prsnt for transmitting detection signals; an ADC for converting analog signals to digital signals for processing by the CPLD; and a resistor divider for fixing the voltage of the reference end of the amplifier.

[0061] Similarly, referring to Figure 5bThe whole cabinet liquid leakage detection link can include: a power shelf for providing power for the whole system; a REC (Remote Environment Controller) for monitoring and managing the rack environment; a TOR (top-of-rack switch) for connecting all servers on the rack and providing uplink connection to a higher layer network structure; a BMC for monitoring and managing the server hardware state, including receiving and processing the liquid leakage detection signal; an ADC for converting an analog signal into a digital signal for CPLD processing; a resistor voltage divider for fixing the voltage at the reference end of the amplifier; a CPLD for processing signals from the amplifier module, determining whether liquid leakage occurs, and controlling subsequent actions; an amplifier for amplifying the weak signal from the liquid leakage detection line so that the CPLD can clearly detect it; signal lines conn including leakage_B, leakage_R, Leakage_Prsnt for transmitting detection signals; Simulate_B, Simulate_R for simulating liquid leakage detection signals; and a gating switch switch for controlling whether the liquid leakage detection line is connected to the circuit for detection or maintenance.

[0062] Figure 6 A flowchart of a detection method of a computing node provided by an embodiment of the present disclosure can be applied to the computing node described above, as shown in Figure 6 The method includes the following steps:

[0063] In step 601, after the computing node is powered on, the baseboard management controller module detects the type of the central processing unit according to the configuration pin of the mainboard, and configures the communication link according to the type of the central processing unit.

[0064] In the above embodiment, after the computing node is powered on, the BMC can automatically initiate the power-on detection process, first detect the type of the central processing unit, that is, determine the CPU type, for example, determine the CPU series, model, etc. Then, the communication link can be configured differently according to different CPU types.

[0065] Further, the type of the central processing unit is detected according to the configuration pin of the mainboard, and the communication link is configured according to the type of the central processing unit, including:

[0066] In the case where the type of the central processing unit is detected by the baseboard management controller module according to the configuration pin of the mainboard as a first mainboard type, the communication link of the baseboard management controller module is configured as an enhanced serial peripheral interface;

[0067] In a case where the type of the central processing unit is determined as the second mainboard type according to the configuration pin of the mainboard by the baseboard management controller module, the communication link of the baseboard management controller module is configured as a low pin count.

[0068] The BMC can determine the CPU type according to the configuration pin pin on the mainboard. If the CPU type is the first mainboard type, the communication link of the BMC can be configured as ESPI (Enhanced Serial Peripheral Interface). For example, when the CPU is powered on, the communication with the CPU can be established through the ESPI to transmit the initialization data of devices such as ACPI (Advanced Configuration and Power Interface), Port80, UART (Universal Asynchronous Receiver / Transmitter), support I / O space and memory mapping access, replace the related data transmission of the traditional LPC (Low Pin Count) interface, and ensure the normal power-on of the CPU. If the CPU type is the second mainboard type, the communication link of the BMC can be configured as LPC. For example, the initialization information of the BIOS Flash (Basic Input / Output System Flash) and the configuration data of the Super I / O (Super Input / Output Device) device are transmitted to cooperate with the normal power-on of the CPU. The specific types of the first mainboard type and the second mainboard type can be set according to actual needs.

[0069] In step 602, the deployment environment of the computing node is determined according to the cabinet in-place pin, and the out-of-band monitoring strategy corresponding to the deployment environment is loaded.

[0070] The BMC can check the cabinet in-place pin by the checking machine to determine the deployment environment of the computing node, for example, whether it is in the cabinet or in the single machine. Then, the BMC can determine the out-of-band monitoring strategy corresponding to different deployment environments and load the out-of-band monitoring strategy corresponding to the deployment environment to adapt to different monitoring requirements. It can be understood that the out-of-band monitoring strategy can include specific monitoring content.

[0071] Further, the deployment environment of the computing node is determined according to the cabinet in-place pin, and the out-of-band monitoring strategy corresponding to the deployment environment is loaded, including:

[0072] The baseboard management controller module checks the cabinet in-place pin.

[0073] In the case that the cabinet-in-place pin indicates that the computing node is in the cabinet, a first out-of-band monitoring strategy suitable for the whole cabinet is loaded; wherein the first out-of-band monitoring strategy is used to monitor the computing node;

[0074] In the case that the cabinet-in-place pin indicates that the computing node is in the single machine, a second out-of-band monitoring strategy is loaded; wherein the second out-of-band monitoring strategy is used to monitor the computing node and the upper GPU node.

[0075] Wherein, after the BMC checks the cabinet-in-place pin through the inspection machine, it can determine the high and low of the in-place pin, for example, whether the level of the in-place pin is a logic low level (such as 0) or a logic high level (such as 1) state. If the in-place pin is pulled low, it indicates that the computing node is in the cabinet. At this time, the out-of-band monitoring strategy suitable for the whole cabinet can be loaded, that is, the first out-of-band monitoring strategy, for example, the management test suitable for the whole cabinet can be loaded, which is responsible for the out-of-band monitoring of the computing node, including the monitoring and control of voltage, temperature, power consumption, fan, etc. On the contrary, if the in-place pin is high, it can be determined that the computing node is in the single machine, and more out-of-band monitoring strategies, that is, the second out-of-band monitoring strategy, are loaded, for example, in addition to monitoring the temperature, voltage, fan, etc. of itself, it also needs to monitor the temperature, voltage, power consumption, heat dissipation control, etc. of the upper GPU node through the I2C link.

[0076] Step 603, detecting whether there is a voltage conversion module according to the power configuration, and adjusting the I2C rate according to the detection result.

[0077] Wherein, the BMC can also detect the power configuration, determine whether there is a voltage conversion module by detecting the power configuration. Then, according to the detection result of whether there is a voltage conversion module, the I2C rate is adjusted to adapt to the existence of the power module and ensure stability.

[0078] Further, according to the power configuration, it is detected whether there is a voltage conversion module, and the I2C rate is adjusted according to the detection result, including:

[0079] The power configuration is detected by the baseboard management controller module; wherein the power configuration is used to indicate whether the power adapter board is in place;

[0080] In the case that the power configuration indicates that the power adapter board is in place, it is determined that there is a voltage conversion module, and the I2C rate is adjusted to a preset rate.

[0081] The BMC checks the power supply configuration, for example, whether there is a voltage conversion module, for example, whether there is a 54V to 12V voltage conversion module, by detecting whether the power adapter is in place. Considering that the presence of the voltage conversion module will greatly affect the rise time of I2C, and in turn will affect the I2C link identification of the whole machine, therefore, after detecting that the conversion module is in place, the I2C rate can be adjusted to a preset rate, and the specific range of the preset rate can be customized, for example, it can be in the range of 1K-10KHZ. In this way, the adjustment of the I2C rate can ensure the stability of the I2C communication.

[0082] In step 604, the configuration information of the graphics processor node connected to the computing node is detected, and the switch and the central processor are configured according to the configuration information.

[0083] The configuration information of the GPU node connected to the computing node by the BMC can include, for example, the number of uplink ports and the number of downlink ports of the switch SW. Then, the BMC can configure the SW and the CPU according to the configuration information of the GPU node.

[0084] Further, the configuration information of the graphics processor node connected to the computing node is detected, and the switch and the central processor are configured according to the configuration information, including:

[0085] The configuration information of the graphics processor node connected to the computing node is detected by the baseboard management controller module; wherein the configuration information at least includes uplink port in place pin of the graphics processor node, downlink port in place pin of the graphics processor node;

[0086] The number of ports of the computing node connected to the switch is detected according to the uplink port in place pin;

[0087] In the case where the number of ports belongs to the first port number range, the central processor is notified to adapt the PCIe fork channel configuration;

[0088] In the case where the number of ports belongs to the second port number range, the central processor and the switch are notified to adapt the double uplink bandwidth test.

[0089] The BMC detects configuration information of the GPU node connected to the computing node, which can include the number of uplink ports and the number of downlink ports of the SW, to configure the SW and the CPU. For example, the number of uplink ports can be determined by detecting the number of bit pins of the uplink port of the GPU node, and the number of downlink ports can be determined by detecting the number of bit pins of the downlink port of the GPU node. Then, the number range of the port number can be determined to configure the SW and the CPU. For example, if the port number belongs to a first port number range, for example, when one SW has only one x16 or x8 connected to the CPU (i.e., the first port number range is less than or equal to 1, or can also be set to 1), the BMC can configure the PCIe bifurcation channel (PCIe, bifurcation) through the CPU. On the contrary, if the port number belongs to a second port number range (for example, greater than or equal to 2), for example, when it is detected that the SW has two X16 or two X8, which are different ports port connected to the SW, the BMC can notify the CPU and the SW to adapt the double uplink bandwidth test. It can be understood that after the configuration of the switch and the central processing unit according to the configuration information, the address space allocation of the CPU can also be performed.

[0090] In step 605, the interconnection mode of the switch is determined according to the downlink bit state of the switch, and the global address space mapping is performed according to the interconnection mode.

[0091] The BMC can also determine the interconnection mode of the switch according to the downlink bit state of the switch, for example, full interconnection or ring interconnection. Then, the BMC can perform global address space mapping (for example, mapping the logical address to the physical address) according to different interconnection modes to realize effective data transmission.

[0092] Further, the interconnection mode of the switch is determined according to the downlink bit state of the switch, and the global address space mapping is performed according to the interconnection mode, including:

[0093] Detecting the number of downlink network cards of the switch;

[0094] In the case where the number of downlink network cards belongs to a first network card number range, the interconnection mode of the switch is determined to be full interconnection, and the first mapping mode is used for global address space mapping;

[0095] In the case where the number of downlink network cards belongs to a second network card number range, the interconnection mode of the switch is determined to be ring interconnection, and the second mapping mode is used for global address space mapping.

[0096] The BMC can determine the interconnection mode of the switch by detecting the number of downlink network cards of the switch. For example, if the number of downlink network cards of the switch belongs to a first network card number range, for example, less than or equal to 4, or other values, the specific values can be set as needed, it can be determined that the interconnection mode of the switch is full interconnection, at this time, the first mapping mode can be used for global address space mapping, for example, the first mapping mode can be flat address space mapping, hierarchical address space mapping, load balancing address mapping, multicast address mapping, virtualization address mapping, policy-based address mapping, dynamic address mapping and the like. Conversely, if the number of downlink network cards belongs to a second network card number range, for example, greater than 4 and less than or equal to 8, or can also be set according to actual needs, it can be determined that the interconnection mode of the switch is ring interconnection, at this time, the second mapping mode can be used for global address space mapping, for example, the second mapping mode can be sequential address mapping, ring address mapping, distributed address mapping, fixed address mapping, dynamic address mapping, multicast address mapping, virtual ring address mapping, failover address mapping and the like.

[0097] In step 606, the complex programmable logic device is controlled to power on the central processor.

[0098] After the above power-on detection process is performed, the BMC can control the complex programmable logic device CPLD to power on the CPU, and complete the power-on startup process of the computing node. It can be understood that the above steps can also be executed in other orders.

[0099] In summary, the method provided by the embodiments of the present disclosure can detect the type of central processor according to the configuration pin of the mainboard after the computing node is powered on through the baseboard management controller module, and configure the communication link according to the type of central processor; determine the deployment environment of the computing node according to the cabinet in-place pin, and load the out-of-band monitoring strategy corresponding to the deployment environment; detect whether there is a voltage conversion module according to the power supply configuration, and adjust the I2C rate according to the detection result; detect the configuration information of the graphics processor node connected to the computing node, and configure the switch and the central processor according to the configuration information; determine the interconnection mode of the switch according to the downlink in-place state of the switch, and perform global address space mapping according to the interconnection mode; and control the complex programmable logic device to power on the central processor. In this way, not only can the automatic detection and configuration of the computing node be realized, the labor cost and errors can be reduced, and the configuration error risk and cost can be reduced; different monitoring strategies can be loaded according to different deployment environments, the I2C rate can be adjusted according to the power supply configuration, the SW and CPU can be configured according to the configuration of the GPU node, and address mapping can be performed according to the interconnection mode of the SW, so that the adaptability, stability, reliability and performance of the computing node can be effectively improved, the signal attenuation and jitter in the transmission process can be reduced, and the data transmission efficiency and quality can be improved.

[0100] Further, it also includes:

[0101] detecting the liquid leakage detection line;

[0102] determining whether the liquid cooling module is in place according to the liquid leakage detection line;

[0103] in the case that the liquid cooling module is in place, loading the liquid cooling heat dissipation control strategy and the liquid leakage detection function;

[0104] in the case that the liquid cooling module is not in place, loading the fan control strategy for air cooling control.

[0105] Wherein, the BMC can also detect whether the liquid cooling module is in place by detecting the in-place condition of the liquid leakage detection line. If the liquid cooling module is in place, the BMC can adapt the liquid cooling heat dissipation control strategy, and load and activate the liquid leakage detection function to respond in time when liquid leakage occurs, and can also report the monitoring result to the RMC in real time for real-time cooling liquid control by the RMC. Conversely, if the liquid cooling module is not in place, the fan control strategy can be loaded to switch to the air cooling control mode for air cooling control, ensuring that the system will not overheat due to lack of cooling. In this way, through intelligent cooling control and automatic liquid leakage detection, not only the performance and reliability of the computing node can be improved, but also the maintenance cost can be reduced and the energy efficiency can be improved.

[0106] To make the above power-on process (i.e. configuration identification process) provided by the embodiments of the present disclosure clearer, the following will be described in conjunction with the power-on process schematic diagram shown in Figure 7 As an example, since the computing node design needs to be compatible with various configurations, the BMC needs to distinguish different configurations, and needs to load different out-of-band management parameters according to different configurations, so a set of configuration identification logic can be set on the BMC to distinguish single machine / whole cabinet, air cooling / liquid cooling, 54V power supply / 12V power supply. As shown in Figure 7 The configuration identification process includes:

[0107] After the computing node is powered on, the BMC will automatically initiate the detection process, first detects the mainboard type, judges the CPU type according to the configuration pin on the mainboard, when detecting as Intel mainboard, configures the communication link of the BMC as ESPI, when the CPU is powered on, establishes communication with the CPU through ESPI, transmits initialization data of devices such as ACPI, Port80, UART, supports I / O space and memory mapping access, replaces related data transmission of traditional LPC interface, ensures normal CPU startup. When detecting as HG mainboard, configures the communication link of the BMC as LPC, transmits initialization information of BIOS Flash, configuration data of SuperI / O device, cooperates with HG CPU to start normally.

[0108] Next, the BMC will check the cabinet in place pin through the PCA9555, when the in place pin is pulled low, it will be interpreted that the computing node is in the cabinet, the BMC will load the management test suitable for the whole cabinet, only responsible for the out-of-band monitoring of the computing node, including voltage, temperature, power consumption, fan control, etc. When the pin is high, it will be determined that the computing node is in a single machine, and more out-of-band monitoring strategies will be loaded. In addition to the temperature, voltage, fan, etc. of itself, the temperature, voltage, power consumption, and heat dissipation control of the upper GPU node need to be monitored through the I2C link.

[0109] After that, the BMC will check the power supply configuration, mainly to detect whether the power adapter board is in place to determine whether there is a 54V to 12V voltage conversion module. Because the presence of the power module will greatly affect the I2C rise time, and in turn affect the I2C link identification of the whole machine, after detecting that there is a power conversion module in place, the BMC will automatically reduce the I2C rate to the 1K-10KHZ range, so as not to affect the I2C communication.

[0110] After that, the BMC will detect whether the liquid cooling module is in place, and will interpret that the liquid cooling module is in place by detecting the presence of the liquid leakage detection line. When the liquid cooling module is in place, the BMC will adapt the liquid cooling heat dissipation control strategy and load the liquid leakage detection function, and will report the monitoring structure to the RMC in real time, and the RMC will make real-time control of the cooling liquid. When it is detected that the liquid cooling module is not in place, the fan control strategy will be loaded for air cooling control.

[0111] After that, the BMC will detect the configuration of the GPU node connected to the computing node, including the number of SW uplink and downlink, and then configure the SW and CPU. By detecting the detection of the GPU node uplink port in place pin, it is determined that the computing node has several ports connected to the SW. When a SW has only one x16 or x8 connected to the CPU, the BMC will notify the CPU to adapt to this PCIe bifurcation. When it is detected that the SW has two X16 or two X8, respectively, different ports are connected to the SW, the BMC will notify the CPU and SW to adapt to the bandwidth test of the double uplink, and perform address space allocation of the CPU.

[0112] And the BMC will determine whether the SW is full interconnection or ring interconnection by detecting the in-place state of the downlink, so as to perform different global address space mapping. After completing these state recognition, the BMC will give the CPLD a command to power on the CPU, and then complete the whole machine or cabinet power-on.

[0113] Further, in the case of the liquid cooling module in place, after loading the liquid cooling heat dissipation control strategy and the liquid leakage detection function, it also includes:

[0114] In the case of liquid leakage determined by the complex programmable logic device, the power-off process is triggered.

[0115] The complex programmable logic device can monitor the state of the liquid leakage detection line. Once the CPLD determines that liquid leakage occurs (for example, the resistance of the detection line changes from high impedance to low impedance), the preset power-off process is triggered to safely shut down the system and prevent further damage or accidents that may be caused by liquid leakage.

[0116] Further, it also includes:

[0117] In the case of liquid leakage detection function simulation or liquid leakage detection function precision adjustment, the baseboard management controller module sends a function simulation notification or a liquid leakage detection function precision adjustment notification to the complex programmable logic device;

[0118] The complex programmable logic device responds to the function simulation notification or the liquid leakage detection function precision adjustment notification to simulate the liquid leakage detection function through the amplifier or adjust the liquid leakage detection function precision through the digital-to-analog converter.

[0119] When liquid leakage detection function simulation is required, the BMC can notify the CPLD to simulate the liquid leakage detection function through I2C. For example, the CPLD can control the pin state to set the gate switch to Z=Y0, Simulate_B and Simulate_R are connected, because Simulate_B and Leakage_B are conductive, Simulate_R and leakage_R are connected, and because leakage_B is grounded, leakage_R is grounded, and then through the amplifier, the CPLD can detect the simulated liquid leakage. It can be understood that in order to adjust the sensitivity of the liquid leakage detection and to be compatible with the quick response to the liquid leakage detection function, an ADC module can be added, which is directly controlled by the CPLD. Normally, the CPLD directly controls the ADC not to work through the EN pin, and the reference end of the amplifier is fixed by a hardware resistance divider. When liquid leakage detection function precision adjustment is required, the BMC can notify the CPLD through I2C. After the CPLD receives the data, it sends it to the ADC through I2C to adjust the output voltage of the ADC, and then adjusts the reference end voltage of the amplifier and the voltage of Simulate_B, providing data to adjust the two voltages, and then simulating the sensitivity of liquid leakage detection under different precision, and also adjusting the sensitivity of the liquid leakage detection line under normal detection.

[0120] Further, it also includes:

[0121] In the case that the computing nodes are in a single machine, the leakage detection signals of all the computing nodes of the whole machine are sent to the baseboard management controller module through the complex programmable logic device, and in the case that leakage is detected, all the computing nodes of the whole machine are powered off under the control of the complex programmable logic device.

[0122] The leakage notification is sent to the baseboard management controller module.

[0123] In the case that the computing nodes are in a single machine, the leakage detection signals of all the computing nodes of the whole machine are sent to the baseboard management controller module through the complex programmable logic device, and in the case that leakage is detected, all the computing nodes of the whole machine are powered off under the control of the complex programmable logic device.

[0124] Further, it further comprises:

[0125] In the case that the computing nodes are in a single machine, the leakage detection signals of all the computing nodes of the whole machine are sent to the baseboard management controller module through the complex programmable logic device, and in the case that leakage is detected, all the computing nodes of the whole machine are powered off under the control of the complex programmable logic device.

[0126] The leakage notification is sent to the baseboard management controller module of the computing node where the complex programmable logic device is located.

[0127] In the case that the computing nodes are in a single machine, the leakage detection signals of all the computing nodes of the whole machine are sent to the baseboard management controller module through the complex programmable logic device, and in the case that leakage is detected, all the computing nodes of the whole machine are powered off under the control of the complex programmable logic device.

[0128] Based on the above computing node and the detection method of the computing node, the disclosure can be based on the topology of the above computing node, the power-on detection process, and the leakage detection process. The computing node design can be compatible with single machines or whole cabinets, air cooling or liquid cooling, and multiple voltages (such as 54V or 12V). In the 1U height, the extreme computing power density is realized, and the simple interconnection and convenient maintenance of the computing node and other nodes are realized. Such a computing node can realize the requirements of high density and high performance, provide more space and higher performance for GPU scale up, and realize the pluggability of the computing node and the isolation from the GPU node, thereby increasing the maintainability and availability of the system.

[0129] To make the design of the computing node provided by the disclosure clearer, the following describes the single machine design and the whole cabinet design shown in Figure 8a and 8b As an example, the computing node can be applied in an AI server and an AI whole cabinet.

[0130] In the AI server (artificial intelligence server), the computing node can be built with a 2*2 full interconnection topology with the PCIe Switch chip, as shown in Figure 8a A single PCIe Switch chip supports 144 PCIe GEN5 lanes (PCI Express fifth generation channel) (i.e. 9 groups of x16 PCIe lanes), 3 groups of x16 lanes in each PCIe Switch chip are set to Fabric mode (structure mode) for full interconnection between 4 PCIe Switch chips, forming a PCIe Fabric network; 1 group of x16 lanes is set to HOST mode (host mode) for connecting the CPU; 5 groups of x16 lanes are set to Device mode (device mode), 4 groups of x16 lanes are connected to the GPU, and 1 group of x16 lanes is used to connect the network card.

[0131] In the AI whole cabinet, the computing node is built with an 8 PCIe Switch full interconnection topology with the PCIe Switch chip, each group of 4 GPUs is connected to a downstream switch, and each two groups are assembled into a GPU node. There are 4 GPU nodes in a single Zone. The GPUs are interconnected through an internal fabric bus. Each GPU node outputs 12 downstream PCIE x8. Each group of switches is interconnected with the HOST CPU (host central processing unit) through 1 upstream PCIE X8, and is equipped with a 400G network card to support GPU networking expansion. Each GPU node outputs 2 upstream PCIE x8. The single Zone in the whole cabinet can support up to 32 PCIE5.0 GPUs (PCI Express 5.0 graphics processing units).

[0132] Based on the above topology scheme, the embodiment of the present disclosure provides a computing node design compatible with single machine or whole cabinet, air cooling or liquid cooling, 54V or 12V, which realizes the ultimate computing power density in 1U height, and can realize simple interconnection and convenient maintenance of the computing node and other nodes. Compared with the computing node of the traditional AI server, this computing node realizes the requirements of high density and high performance, can provide more space and higher performance for GPU Scale up (GPU expansion upgrade), and can realize the pluggability of the computing node and the isolation from the GPU node, thereby increasing the maintainability and availability of the system.

[0133] It should be noted that the embodiments of the present disclosure can include a plurality of steps, which are numbered for the convenience of description, but these numbers are not a limitation on the execution time slot and execution order between the steps; these steps can be implemented in any order, and the embodiments of the present disclosure do not limit this.

[0134] According to the embodiments of the present disclosure, the present disclosure also provides a detection device of a computing node. Exemplarily, Figure 9 A structural schematic diagram of a detection device of a computing node provided by the embodiments of the present disclosure. The detection device 900 of the computing node comprises:

[0135] A link configuration module 910 is configured to, after the computing node is powered on, detect the type of the central processing unit according to the configuration pin of the mainboard through the baseboard management controller module, and configure the communication link according to the type of the central processing unit.

[0136] A loading module 920 is configured to determine the deployment environment of the computing node according to the rack in-place pin, and load the out-of-band monitoring strategy corresponding to the deployment environment.

[0137] An adjustment module 930 is configured to detect whether there is a voltage conversion module according to the power supply configuration, and adjust the I2C rate according to the detection result.

[0138] A configuration module 940 is configured to detect the configuration information of the graphics processor node connected with the computing node, and configure the switch and the central processing unit according to the configuration information.

[0139] A mapping module 950 is configured to determine the interconnection mode of the switch according to the downlink in-place state of the switch, and perform global address space mapping according to the interconnection mode.

[0140] A power-on module 960 is configured to control the complex programmable logic device to power on the central processing unit.

[0141] Further, the link configuration module 910 is configured to:

[0142] In a case where the type of the central processing unit detected by the baseboard management controller module according to the configuration pin of the mainboard is a first mainboard type, the communication link of the baseboard management controller module is configured as an enhanced serial peripheral interface;

[0143] In a case where the type of the central processing unit detected by the baseboard management controller module according to the configuration pin of the mainboard is a second mainboard type, the communication link of the baseboard management controller module is configured as a low pin count.

[0144] Further, the loading module 920 is configured to:

[0145] Check the in-place pin of the cabinet through the baseboard management controller module;

[0146] Load a first out-of-band monitoring strategy suitable for the whole cabinet in the case that the cabinet in-place pin indicates that the computing node is in the cabinet; wherein, the first out-of-band monitoring strategy is used to monitor the computing node;

[0147] Load a second out-of-band monitoring strategy in the case that the cabinet in-place pin indicates that the computing node is in a single machine; wherein, the second out-of-band monitoring strategy is used to monitor the computing node and the upper layer graphics processor node.

[0148] Further, the adjusting module 930 is configured to:

[0149] Detect the power supply configuration through the baseboard management controller module; wherein, the power supply configuration is used to indicate whether the power adapter board is in place;

[0150] In the case that the power supply configuration indicates that the power adapter board is in place, determine that there is a voltage conversion module, and adjust the I2C rate to a preset rate.

[0151] Further, the configuration module 940 is configured to:

[0152] Detect the configuration information of the graphics processor node connected to the computing node through the baseboard management controller module; wherein, the configuration information at least includes the uplink port in-place pin of the graphics processor node and the downlink port in-place pin of the graphics processor node;

[0153] Detect the number of ports of the computing node connected to the switch according to the uplink port in-place pin;

[0154] In the case that the number of ports belongs to a first port number range, notify the central processor to adapt the PCIe bifurcated channel configuration;

[0155] In the case that the number of ports belongs to a second port number range, notify the central processor and the switch to adapt the double uplink bandwidth test.

[0156] Further, the mapping module 950 is configured to:

[0157] Detect the number of downlink network cards of the switch;

[0158] In the case that the number of downlink network cards belongs to a first network card number range, determine that the interconnection mode of the switch is full interconnection, and use a first mapping mode for global address space mapping;

[0159] In the case that the number of downlink network cards belongs to a second network card number range, determine that the interconnection mode of the switch is ring interconnection, and use a second mapping mode for global address space mapping.

[0160] Further, it further includes a liquid leakage detection module, which is configured to:

[0161] detecting a leakage detection line;

[0162] determining whether the liquid cooling module is in place according to the leakage detection line;

[0163] in a case where the liquid cooling module is in place, loading a liquid cooling heat dissipation control strategy and a leakage detection function;

[0164] in a case where the liquid cooling module is not in place, loading a fan control strategy for air cooling control.

[0165] Further, a leakage simulation module is further included, and is configured to:

[0166] in a case where the leakage is determined to occur by the complex programmable logic device, triggering a power-off process.

[0167] Further, a leakage simulation module is further included, and is configured to:

[0168] in a case where the leakage detection function simulation or the leakage detection function precision adjustment is needed, the baseboard management controller module sends a function simulation notification or a leakage detection function precision adjustment notification to the complex programmable logic device;

[0169] the complex programmable logic device responds to the function simulation notification or the leakage detection function precision adjustment notification, and simulates the leakage detection function through an amplifier or adjusts the leakage detection function precision through a digital-to-analog converter.

[0170] Further, a first leakage power-off module is further included, and is configured to:

[0171] in a case where the computing node is in a single machine, the complex programmable logic device of each computing node sends a leakage detection signal of all computing nodes of the whole machine to the baseboard management controller module, and controls all computing nodes of the whole machine to be powered off in a case where the leakage is detected to occur;

[0172] sends a leakage notification to the baseboard management controller module.

[0173] Further, a second leakage power-off module is further included, and is configured to:

[0174] in a case where the computing node is in a cabinet, the complex programmable logic device of each computing node controls the computing node to be powered off;

[0175] the complex programmable logic device of each computing node sends a leakage notification to the baseboard management controller module of the computing node.

[0176] It should be noted that the description of the features in the embodiments corresponding to the detection device of the computing node can refer to the related description of the embodiments corresponding to the detection method of the computing node, which will not be repeated here.

[0177] Embodiments of the present disclosure further provide an electronic device, comprising a memory and a processor, the memory storing a computer program, and the processor being configured to execute the computer program to perform the steps in any of the above method embodiments.

[0178] Embodiments of the present disclosure further provide a computer readable storage medium storing a computer program, wherein the computer program is configured to perform the steps in any of the above method embodiments when executed.

[0179] In one example embodiment, the above computer readable storage medium can include, but is not limited to, a U disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media capable of storing computer programs.

[0180] Embodiments of the present disclosure further provide a computer program product comprising a computer program, wherein the computer program is executed by a processor to implement the steps in any of the above method embodiments.

[0181] Embodiments of the present disclosure further provide another computer program product comprising a non-volatile computer readable storage medium storing a computer program, wherein the computer program is executed by a processor to implement the steps in any of the above method embodiments.

[0182] Those skilled in the art will further appreciate that the units and algorithm steps of the examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the above description has generally been stated in terms of examples without limiting the scope of the disclosure. The described features can be implemented in hardware or software, or a combination of both, depending on the particular application and design constraints. Those skilled in the art can use different methods to implement the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present disclosure.

[0183] The above describes in detail a method provided by the present disclosure. The principles and implementation manners of the present disclosure are described by applying specific examples. The above description of the examples is only to help understand the method of the present disclosure and its core idea. It should be noted that, for those skilled in the art, without departing from the principles of the present disclosure, the present disclosure can be improved and modified in several ways. These improvements and modifications also fall within the scope of protection of the claims of the present disclosure.

Claims

1. A method of detecting a computing node, the method comprising: The method for detecting computing nodes includes: After the computing node is powered on, the baseboard management controller module detects the type of the central processing unit (CPU) based on the configuration pins of the motherboard and configures the communication link according to the type of the CPU. The deployment environment of the compute node is determined based on the in-situ pins in the rack, and the out-of-band monitoring policy corresponding to the deployment environment is loaded. The system detects the presence of a voltage conversion module based on the power supply configuration and adjusts the I2C rate accordingly. The configuration information of the graphics processing unit node connected to the computing node is detected, and the switch and central processing unit configuration are configured according to the configuration information; The interconnection method of the switches is determined based on the downlink presence status of the switches, and global address space mapping is performed based on the interconnection method; The complex programmable logic device is controlled to power on the central processing unit. The step of detecting the type of central processing unit (CPU) based on the configuration pins of the motherboard and configuring the communication link according to the CPU type includes: When the type of the central processing unit is detected as the first motherboard type by the baseboard management controller module according to the configuration pins of the motherboard, the communication link of the baseboard management controller module is configured as an enhanced serial peripheral interface. When the type of the central processing unit is detected as the second motherboard type by the baseboard management controller module according to the configuration pins of the motherboard, the communication link of the baseboard management controller module is configured to a low pin count. The step of determining the deployment environment of the compute node based on the in-place pins in the rack and loading the out-of-band monitoring policy corresponding to the deployment environment includes: The cabinet presence pins are checked using the baseboard management controller module. When the rack-in-place pin indicates that the compute node is in the rack, a first out-of-band monitoring strategy adapted to the entire rack is loaded; wherein, the first out-of-band monitoring strategy is used to monitor the compute node; When the rack-in-place pin indicates that the compute node is in standalone mode, a second out-of-band monitoring strategy is loaded; wherein the second out-of-band monitoring strategy is used to monitor the compute node and the upper-layer graphics processor node; The process of detecting the configuration information of the graphics processing unit (GPU) node connected to the computing node and configuring the switch and CPU configuration based on the configuration information includes: The configuration information of the graphics processing unit (GPU) node connected to the computing node is detected by the baseboard management controller module; wherein the configuration information includes at least the uplink port presence pin and the downlink port presence pin of the GPU node. The number of ports connected to the switch by the computing node is detected based on the uplink port in-situ pin. If the number of ports is within the range of the first number of ports, notify the central processing unit to adapt to the PCIe fork channel configuration; If the number of ports falls within the range of the second number of ports, notify the central processing unit and the switch to perform dual uplink bandwidth testing.

2. The method of claim 1, wherein, The step of detecting the presence of a voltage conversion module based on the power supply configuration and adjusting the I2C rate based on the detection result includes: The power configuration is detected by the baseboard management controller module; wherein the power configuration is used to indicate whether the power adapter board is in place; When the power configuration indicates that the power adapter board is in place, the presence of a voltage conversion module is confirmed, and the I2C rate is adjusted to a preset rate.

3. The method of claim 1, wherein, The step of determining the interconnection mode of the switches based on their downlink presence status and performing global address space mapping based on the interconnection mode includes: Detect the number of downlink network interface cards (NICs) on the switch; If the number of downlink network cards is within the range of the first number of network cards, the interconnection mode of the switch is determined to be full interconnection, and the first mapping method is used for global address space mapping; If the number of downlink network cards falls within the range of the second number of network cards, the interconnection method of the switches is determined to be ring interconnection, and the second mapping method is used for global address space mapping.

4. The method of claim 1, wherein, Also includes: Leak detection line; Determine whether the liquid cooling module is in place based on the aforementioned leakage detection line; With the liquid cooling module in place, a liquid cooling heat dissipation control strategy and a leakage detection function are implemented. When the liquid cooling module is not in place, a fan control strategy is applied to control air cooling.

5. The method of claim 4, wherein, After loading the liquid cooling heat dissipation control strategy and leakage detection function when the liquid cooling module is in place, the method further includes: If leakage is detected by the complex programmable logic device, a power-down process is triggered.

6. The method of claim 4, wherein, Also includes: When it is necessary to simulate or adjust the accuracy of the leakage detection function, the substrate management controller module sends a function simulation notification or a leakage detection function accuracy adjustment notification to the complex programmable logic device. In response to the function simulation notification or the leak detection function accuracy adjustment notification, the complex programmable logic device simulates the leak detection function through an amplifier or adjusts the leak detection function accuracy through a digital-to-analog converter.

7. The method of claim 5, wherein, Also includes: When the computing node is in a standalone state, the complex programmable logic device sends the liquid leakage detection signals of all computing nodes of the whole machine to the substrate management controller module, and controls all computing nodes of the whole machine to power down when liquid leakage is detected. Send a leakage notification to the substrate management controller module.

8. The method of claim 7, wherein, Also includes: When the computing node is in a rack, the complex programmable logic device of each computing node controls the computing node to power down; Each computing node's complex programmable logic device sends a leakage notification to the substrate management controller module of its respective computing node.

9. A computing node, characterized in that, The computing node employs the detection method for any of claims 1-8, comprising a motherboard, a power adapter board, and a front window input / output module; wherein: The motherboard includes a central processing unit, a dual in-line memory module, a voltage regulation module, a multi-channel input / output connector, a baseboard management controller module, and a complex programmable logic device connected to the central processing unit; The power adapter board includes a power module, a power blind-mating connector, and a signal blind-mating connector, and the power adapter board is connected to the motherboard; The front window input / output module includes a hard drive, an input / output panel, and a network card, and is connected to the multi-channel input / output connector of the motherboard through the network card.

10. The computing node according to claim 9, characterized in that, The power adapter board has reserved space for liquid cooling pipes for setting up a liquid cooling module; the network card includes at least a PCIe network card and an Open Compute Project network card, and the front window input / output module is connected to the multi-channel input / output connector of the motherboard through the PCIe network card.

11. The computing node according to claim 10, characterized in that, It also includes a circuit board; the circuit board is equipped with a leakage detection module, the leakage detection module includes a leakage detection line, a leakage detection connector connected through the leakage detection line, a switch disposed in the leakage detection line, an amplifier connected to the leakage detection line, a complex programmable logic device and an analog-to-digital converter connected to the amplifier.

12. An electronic device, characterized in that, include: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 8.

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