Array substrate, preparation method thereof and display device

Abstract

The invention provides an array substrate and a preparation method thereof and a display device.The array substrate comprises a substrate, a driving layer, a first protective layer, a second protective layer and a third protective layer which are arranged in a stacked mode, the first protective layer comprises a first sub-protective layer located in a first non-display area and a second sub-protective layer located in a second non-display area, and the third protective layer comprises a second sub-protective layer located in a third non-display area; the first sub-protection layer covers the first scanning line in a stacked mode, the second sub-protection layer covers the second scanning line in a stacked mode, wiring protection of the non-display area is achieved, meanwhile, the second protection layer covers the first protection layer, side edge blocking of the first protection layer can be achieved, water vapor invasion is effectively reduced, and the display effect is improved. And the third protective layer is laminated on the second protective layer and covers the display area, so that the display area is protected, water vapor invasion and chipping damage are prevented, and the display effect of the display panel is improved.

Description

Technical Field

[0001] This invention belongs to the field of display panel technology, and particularly relates to an array substrate, its preparation method, and a display device. Background Technology

[0002] Currently, electronic paper display panels typically include a counter substrate, an array substrate, and an electronic ink film layer located between the counter substrate and the array substrate. The electronic ink is composed of millions of microcapsules, each containing negatively charged and positively charged electrophoretic particles suspended in a transparent liquid. The array substrate and the counter substrate provide positive and negative electrodes. Electrophoretic particles with different charges move up and down between the array substrate and the counter substrate according to the electric field applied to them until the electrophoretic particles reach a designated position. When ambient light shines on the electrophoretic particles, the electrophoretic particles can refract the ambient light of the corresponding color, causing the microcapsules to display the corresponding color.

[0003] An array substrate typically includes a display chip IC, which is attached to the motherboard via adhesive. During the manufacturing process, the module manufacturer may perform further processing, which can cause the PFA layer to peel off. The peeling off of the PFA layer can cause the ITO film on top to peel off. Therefore, PFA cutouts are made near the IC area. Glass fragments may be generated when cutting the array substrate. If these fragments fly near the display chip, especially if they fall onto the traces, they may damage the traces and cause display panel abnormalities.

[0004] To avoid damage to the traces, the conventional method is to cover the entire surface of the array substrate with a protective layer. However, because of the entire surface coverage, moisture can easily invade from the interface of the protective layer after cutting, causing the protective layer to peel off or the vias to corrode, thus affecting the display effect. Summary of the Invention

[0005] The purpose of this invention is to provide an array substrate that solves the problem of moisture intrusion in traditional array substrates, which leads to abnormal display of the display panel.

[0006] A first aspect of the present invention provides an array substrate, comprising:

[0007] A substrate, wherein the substrate is sequentially divided into a first non-display area, a display area and a second non-display area along a first direction;

[0008] A driving layer is stacked on the substrate. The driving layer includes a first scan line located in the first non-display area, a thin film transistor located in the display area, and a second scan line located in the second non-display area. The first scan line, the thin film transistor, and the second scan line are arranged side by side and extend along a second direction. The first direction and the second direction intersect.

[0009] The first protective layer includes a first sub-protective layer located in the first non-display area and a second sub-protective layer located in the second non-display area. The first sub-protective layer is stacked and covers the first scan line, and the second sub-protective layer is stacked and covers the second scan line.

[0010] A second protective layer is stacked and covers the first protective layer and the thin-film transistor;

[0011] A third protective layer is layered on top of the second protective layer and covers the display area;

[0012] The pixel electrode is located on the third protective layer and connected to the thin-film transistor through a via.

[0013] Optionally, the thin-film transistor includes:

[0014] A gate electrode, which is stacked on the substrate of the display area;

[0015] A gate insulating layer, wherein the gate insulating layer is stacked on the substrate and covers the gate;

[0016] A semiconductor layer is stacked on the gate insulating layer;

[0017] A source / drain metal layer is stacked on the gate insulating layer and makes contact with both ends of the semiconductor layer. The source / drain metal layer is also connected to the pixel electrode through the via.

[0018] Optionally, the first scan line and the second scan line are stacked on the gate insulating layer.

[0019] Optionally, the second protective layer forms a groove in the display area, and the third protective layer fills the groove.

[0020] Optionally, the array substrate further includes:

[0021] The third scan line is stacked on the array substrate of the first non-display area, and the third scan line and the first scan line are arranged in an alternating pattern along the first direction;

[0022] The fourth scan line is stacked on the array substrate of the second non-display area, and the fourth scan line and the second scan line are arranged in an alternating pattern along the first direction.

[0023] A second aspect of this invention provides a method for fabricating an array substrate, comprising:

[0024] A driving layer is stacked on a substrate. The array substrate is sequentially divided into a first non-display area, a display area, and a second non-display area along a first direction. The driving layer includes a first scan line located in the first non-display area, a thin film transistor located in the display area, and a second scan line located in the second non-display area. The first scan line, the thin film transistor, and the second scan line are arranged side by side and extend along a second direction. The first direction and the second direction intersect.

[0025] A first protective layer is stacked on the driving layer. The first protective layer includes a first sub-protective layer located in the first non-display area and a second sub-protective layer located in the second non-display area. The first sub-protective layer is stacked and covers the first scan line, and the second sub-protective layer is stacked and covers the second scan line.

[0026] A second protective layer is formed on top of the first protective layer and the thin-film transistor;

[0027] A third protective layer is formed on the second protective layer, the third protective layer covering the display area;

[0028] A hole is drilled in the third protective layer to the thin-film transistor, and a pixel electrode is disposed in the third protective layer. The pixel electrode is connected to the thin-film transistor through a via.

[0029] Optionally, the first protective layer being formed on the driving layer includes:

[0030] A first protective layer is deposited on the driving layer to cover the first scan line, the thin-film transistor, and the second scan line;

[0031] The first protective layer is etched in the display area along the stacking direction, and a groove is formed in the display area to expose the thin film transistor. A first sub-protective layer covering the first scan line is formed in the first non-display area, and a second sub-protective layer covering the second scan line is formed in the second non-display area.

[0032] Optionally, forming a third protective layer on the second protective layer, the third protective layer covering the display area, includes:

[0033] A third protective layer is deposited on the second protective layer;

[0034] The third protective layer is etched in the first non-display area and the second non-display area, and then formed on the display area.

[0035] Optionally, the thin-film transistor includes:

[0036] A gate electrode, which is stacked on the substrate of the display area;

[0037] A gate insulating layer, wherein the gate insulating layer is stacked on the substrate and covers the gate;

[0038] A semiconductor layer is stacked on the gate insulating layer;

[0039] A source / drain metal layer is stacked on the gate insulating layer and contacts both ends of the semiconductor layer. The source / drain metal layer is also connected to the pixel electrode through the via.

[0040] Prior to the step of stacking and forming the driving layer on the substrate, the method further includes:

[0041] A third scan line is stacked on the substrate of the first non-display area, and the third scan line and the first scan line are arranged in an alternating pattern along the first direction.

[0042] A fourth scan line is formed by stacking the substrate in the second non-display area, and the fourth scan line and the second scan line are arranged in an alternating pattern along a first direction.

[0043] A third aspect of the present invention provides a display panel comprising an opposing substrate and an array substrate disposed opposite to each other, wherein the array substrate is an array substrate as described above or an array substrate prepared based on the array substrate preparation method described above.

[0044] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: The array substrate mentioned above includes a substrate, a driving layer, a first protective layer, a second protective layer and a third protective layer stacked together. The first protective layer includes a first sub-protective layer located in a first non-display area and a second sub-protective layer located in a second non-display area. The first sub-protective layer is stacked and covers the first scan line, and the second sub-protective layer is stacked and covers the second scan line, thereby protecting the traces in the non-display area. At the same time, the second protective layer covers the first protective layer, thereby blocking the side of the first protective layer and effectively reducing moisture intrusion. The third protective layer is stacked on the second protective layer and covers the display area, thereby protecting the display area, preventing moisture intrusion and debris damage, and improving the display effect of the display panel. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of the first structure of the array substrate provided in Embodiments 1 and 2 of the present invention;

[0046] Figure 2 This is a schematic diagram of a second structure of the array substrate provided in Embodiments 1 and 2 of the present invention;

[0047] Figure 3This is a schematic diagram of the first process of the array substrate fabrication method provided in Embodiment 2 of the present invention;

[0048] Figure 4 This is a schematic diagram of a third structure of the array substrate provided in Embodiment 2 of the present invention;

[0049] Figure 5 This is a schematic diagram of the fourth structure of the array substrate provided in Embodiment 2 of the present invention;

[0050] Figure 6 This is a schematic diagram of the fifth structure of the array substrate provided in Embodiment 2 of the present invention;

[0051] Figure 7 This is a schematic diagram of the sixth structure of the array substrate provided in Embodiment 2 of the present invention;

[0052] Figure 8 for Figure 3 A schematic diagram of the process of S20 in the substrate preparation method shown;

[0053] Figure 9 for Figure 3 A schematic diagram of the process of S40 in the substrate preparation method shown;

[0054] Figure 10 This is a schematic diagram of the second process of the array substrate fabrication method provided in Embodiment 2 of the present invention;

[0055] Figure 11 This is a schematic diagram of the structure of the display panel provided in Embodiment 3 of the present invention.

[0056] The figures in the diagram are labeled as follows:

[0057] 100, Array substrate; 200, Opposing substrate; 300, Electronic ink thin film layer; 101, Driving circuit; 102, Pin port; 11, Substrate; 12, First scan line; 131, Gate; 132, Gate insulating layer; 133, Source / drain metal layer; 134, Semiconductor layer; 14, Second scan line; 151, First sub-protective layer; 152, Second sub-protective layer; 153, Groove; 16, Second protective layer; 17, Third protective layer; 171, Via; 18, Pixel electrode; 19, Third scan line; 20, Fourth scan line;

[0058] F1, First Non-Display Area; F2, Second Non-Display Area; AA, Display Area;

[0059] x, first direction; z, second direction; y, stacking direction. Detailed Implementation

[0060] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0061] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0062] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0063] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0064] Example 1

[0065] A first aspect of the present invention provides an array substrate 100, such as... Figure 1 and Figure 2 As shown, the array substrate 100 includes:

[0066] The substrate 11 is divided along the first direction x into a first non-display area F1, a display area AA, and a second non-display area F2.

[0067] A driving layer is stacked on the substrate 11. The driving layer includes a first scan line 12 located in the first non-display area F1, a thin film transistor located in the display area AA, and a second scan line 14 located in the second non-display area F2. The first scan line 12, the thin film transistor and the second scan line 14 are arranged side by side and extend along the second direction z. The first direction x and the second direction z intersect.

[0068] The first protective layer includes a first sub-protective layer 151 located in the first non-display area F1 and a second sub-protective layer 152 located in the second non-display area F2. The first sub-protective layer 151 is stacked and covers the first scan line 12, and the second sub-protective layer 152 is stacked and covers the second scan line 14.

[0069] The second protective layer 16 is stacked and covers the first protective layer and the thin-film transistor;

[0070] The third protective layer 17 is stacked on top of the second protective layer 16 and covers the display area AA;

[0071] The pixel electrode 18 is located on the third protective layer 17 and connected to the thin-film transistor through the via 171.

[0072] In this embodiment, the substrate 11 can be a transparent substrate, such as a glass substrate. The substrate 11 can be divided into a first non-display area F1, a display area AA, and a second non-display area F2 along the first direction x. The first non-display area F1 and the second non-display area F2 are disposed on both sides of the display area AA. In an optional embodiment, the first non-display area F1 and the second non-display area F2 are symmetrically disposed on both sides of the display area AA. The first non-display area F1 and the second non-display area F2 are used to set up traces, such as scan lines. The scan lines are used to input line scan signals.

[0073] The display area AA is used to set pixel units. The pixel units may include corresponding data lines, thin film transistors, pixel electrodes 18, etc. The thin film transistors are connected to the corresponding scan lines and data lines and input the line scan signals and data signals, and transmit the data signals to the pixel electrodes 18. The pixel electrodes 18 and the common electrode layer on the opposing substrate 200 form a driving voltage and control the electrophoretic particles located in the middle to move up and down.

[0074] The array substrate also has a bonding area, which is used to bond the driving circuit 101 and the pin port 102. The driving circuit 101 can be composed of multiple flip-chip films. The driving circuit 101 is connected to the data line and the scan line through the pin port 102 respectively, and transmits the row scan signal and the data signal.

[0075] To form pixel units and transmit signals, a driving layer is stacked on the substrate 11. The driving layer may include a first scan line 12 disposed in the first non-display area F1, a second scan line 14 disposed in the second non-display area F2, and a thin-film transistor and a pixel electrode 18 disposed in the display area AA. The thin-film transistor is connected to the pixel electrode 18 through a via 171 to form a pixel unit. When the thin-film transistor receives a row scan signal and an input data signal, the thin-film transistor is turned on and transmits the data signal to the pixel electrode 18. The pixel electrode 18 forms a driving voltage with the common electrode layer on the opposing substrate 200 and controls the electrophoretic particles located in the middle to move up and down until the electrophoretic particles reach the designated position, so that when ambient light shines on the electrophoretic particles, the electrophoretic particles can refract ambient light of the corresponding color, so that the electronic ink displays the corresponding color.

[0076] The thin-film transistor can employ a top-gate structure or a bottom-gate structure. In one optional embodiment, such as... Figure 2 As shown, the thin-film transistor includes:

[0077] Gate 131 is stacked on the substrate 11 of the display area;

[0078] A gate insulating layer 132 is stacked on the substrate and covers the gate 131.

[0079] Semiconductor layer 134 is stacked on gate insulating layer 132;

[0080] The source / drain metal layer 133 is stacked on the gate insulating layer 132 and is in contact with both ends of the semiconductor layer 134. The source / drain metal layer 133 is also connected to the pixel electrode 18 through the via 171.

[0081] In this embodiment, the thin-film transistor adopts a bottom-gate structure, that is, the gate 131 is located below the semiconductor layer 134. The gate 131 is disposed opposite to the semiconductor layer 134 and is spaced apart by the gate insulating layer 132. The gate 131 is connected to the first scan line 12 of the first non-display area F1 and / or the second scan line 14 of the second non-display area F2 and inputs the line scan signal. The source drain metal layer 133 includes a source electrode and a drain electrode. The source electrode and the drain electrode are respectively connected to the two ends of the semiconductor layer 134. The drain electrode is used to connect the data line. The source electrode is connected to the pixel electrode 18 through the via 171. The gate 131, the source drain metal layer 133, the semiconductor layer 134 and the pixel electrode 18 constitute a pixel unit. When the gate 131 receives the line scan signal, the semiconductor layer 134 forms a path and transmits the data signal received by the drain electrode to the source electrode and the pixel electrode 18. The pixel electrode 18 forms a driving voltage with the common electrode layer on the opposing substrate 200 and controls the electrophoretic particles located in the middle to move up and down.

[0082] Corresponding to the thin-film transistor structure, the first scan line 12 and the second scan line 14 can be arranged in a corresponding position relative to the gate 131. In an optional embodiment, the first scan line 12 and the second scan line 14 are stacked on the gate insulating layer 132 and are connected to the gate 131 at the edge of the array substrate.

[0083] To prevent debris from the substrate 11 from falling onto the scan lines of the non-display area AA, causing damage to the traces and display abnormalities, a first protective layer is provided at the first non-display area F1 and the second non-display area F2. The first protective layer covers the first scan line 12 and the second scan line 14, respectively. That is, the first protective layer includes a first sub-protective layer 151 provided in the first non-display area F1 and a second sub-protective layer 152 provided in the second non-display area F2. The first sub-protective layer 151 covers the first scan line 12 and wraps the first scan line 12 with the gate insulating layer 132. The second sub-protective layer 152 covers the second scan line 14 and wraps the second scan line 14 with the gate insulating layer 132. The first protective layer can effectively reduce debris splashing onto the traces, avoid trace damage, and improve the display reliability of the display panel.

[0084] Meanwhile, to prevent moisture intrusion that could cause the first protective layer to peel off or the via 171 to corrode, a second protective layer 16 is stacked on top of the first protective layer. The second protective layer 16 covers the first sub-protective layer 151 and the second sub-protective layer 152. The second protective layer 16 and the grid insulating layer 132 surround the first sub-protective layer 151 and the second sub-protective layer 152, thereby encapsulating the first sub-protective layer 151 and the second sub-protective layer 152. With the side blocking of the second protective layer 16, the first sub-protective layer 151 and the second sub-protective layer 152 can reduce the risk of moisture intrusion from the cross-section, thereby avoiding the problem of the first protective layer peeling off or the via 171 corroding, and effectively ensuring the stability of the display effect.

[0085] Meanwhile, the second protective layer 16 protects the source / drain metal layer 133 and the semiconductor layer 134, preventing debris from falling onto the source / drain metal layer 133 and the semiconductor layer 134, effectively ensuring the display reliability of the display area AA.

[0086] In this embodiment, since the first non-display area F1 and the second non-display area F2 have a dual structure of a first protective layer and a second protective layer 16, the layer height of the first non-display area F1 and the second non-display area F2 is greater than the layer height of the display area AA. In an optional embodiment, the second protective layer 16 forms a groove 153 in the display area AA, and the protective effect of the non-display area AA is greater than the protective effect of the display area AA. In order to achieve consistency in layer height and protection effect, a third protective layer 17 is also stacked on the second protective layer 16 located in the display area AA. The third protective layer 17 fills the groove 153. The third protective layer 17 and the second protective layer 16 of the display area AA provide dual protection for the thin film transistors of the display area AA, and achieve consistency in layer height and protection effect.

[0087] Furthermore, in order to form a pixel unit, a pixel electrode 18 is disposed on a third protective layer 17 on the display area AA, and a via 171 is formed on the second protective layer 16 and the third protective layer 17. The bottom of the pixel electrode 18 is connected to the source electrode of the source / drain metal layer 133. The pixel electrode 18 and the common electrode layer on the opposing substrate 200 form a driving voltage and control the electrophoretic particles located in the middle to move up and down until the electrophoretic particles reach the designated position, so that when ambient light shines on the electrophoretic particles, the electrophoretic particles can refract ambient light of the corresponding color, so that the electronic ink displays the corresponding color.

[0088] The via 171 can be of a corresponding shape. In an optional embodiment, in order to facilitate drilling and mounting of the pixel electrode 18, the via 171 is V-shaped. Correspondingly, the pixel electrode 18 is V-shaped and is mounted on the inner wall of the via 171.

[0089] Furthermore, since the width of the metal trace is limited when the scan line uses a single-layer trace, in an optional embodiment, to increase the width of the metal trace, such as... Figure 2 As shown, the array substrate 100 also includes:

[0090] The third scan line 19 is stacked on the substrate 11 of the first non-display area F1, and the third scan line 19 and the first scan line 12 are arranged in an alternating pattern along the first direction x.

[0091] The fourth scan line 20 is stacked on the substrate 11 of the second non-display area F2, and the fourth scan line 20 and the second scan line 14 are arranged in an alternating pattern along the first direction x.

[0092] In this embodiment, the first scan line 12 and the second scan line 14 are located on the upper part of the gate insulating layer 132, and the third scan line 19 and the fourth scan line 20 are located on the lower part of the gate insulating layer 132. The first scan line 12 and the third scan line 19 are alternately routed, and the second scan line 14 and the fourth scan line 20 are alternately routed. By increasing the width of the metal traces, a greater number of scan lines can be set.

[0093] The gate insulating layer 132 is also used to achieve insulation between the double scan lines.

[0094] The first protective layer, the second protective layer 16, and the third protective layer 17 can be made of different materials. In an optional embodiment, the first protective layer and the third protective layer 17 are made of PFA material, also known as soluble polytetrafluoroethylene. The first protective layer and the second protective layer 16 serve as both planarization layers and protective layers.

[0095] In an optional embodiment, the second protective layer 16 is made of gallium nitride material. As a protective layer, the second protective layer 16 has good insulation effect and stability, which can reduce the damage of external ions to the channel and prevent moisture intrusion.

[0096] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: The array substrate 100 mentioned above includes a substrate 11, a driving layer, a first protective layer, a second protective layer 16, and a third protective layer 17 stacked together. The first protective layer includes a first sub-protective layer 151 located in the first non-display area F1 and a second sub-protective layer 152 located in the second non-display area F2. The first sub-protective layer 151 is stacked and covers the first scan line 12, and the second sub-protective layer 152 is stacked and covers the second scan line 14, thereby protecting the traces in the non-display area AA. At the same time, the second protective layer 16 covers the first protective layer, thereby blocking the side of the first protective layer and effectively reducing moisture intrusion. The third protective layer 17 is stacked on the second protective layer 16 and covers the display area AA, thereby protecting the display area AA, preventing moisture intrusion and debris damage, and improving the display effect of the display panel.

[0097] Example 2

[0098] Based on the structure of the array substrate 100 described above, a second aspect of the present invention provides a method for fabricating the array substrate 100, such as... Figure 3 As shown, the preparation method includes:

[0099] S10. A driving layer is stacked on the substrate 11. The array substrate 100 is divided into a first non-display area F1, a display area AA and a second non-display area F2 along the first direction x. The driving layer includes a first scan line 12 located in the first non-display area F1, a thin film transistor located in the display area AA and a second scan line 14 located in the second non-display area F2. The first scan line 12, the thin film transistor and the second scan line 14 are arranged side by side and extend along the second direction z. The first direction x and the second direction z intersect.

[0100] In this embodiment, refer to Figure 4As shown, the substrate 11 can be a transparent substrate, such as a glass substrate. The substrate 11 can be divided into a first non-display area F1, a display area AA, and a second non-display area F2 along the first direction x. The first non-display area F1 and the second non-display area F2 are disposed on both sides of the display area AA. In an optional embodiment, the first non-display area F1 and the second non-display area F2 are symmetrically disposed on both sides of the display area AA. The first non-display area F1 and the second non-display area F2 are used to set traces, such as scan lines, which are used to input line scan signals.

[0101] The display area AA is used to set pixel units. The pixel units may include corresponding data lines, thin film transistors, pixel electrodes 18, etc. The thin film transistors are connected to the corresponding scan lines and data lines and input the line scan signals and data signals, and transmit the data signals to the pixel electrodes 18. The pixel electrodes 18 and the common electrode layer on the opposing substrate 200 form a driving voltage and control the electrophoretic particles located in the middle to move up and down.

[0102] The array substrate also has a bonding area, which is used to bond the driving circuit 101 and the pin port 102. The driving circuit 101 can be composed of multiple flip-chip films. The driving circuit 101 is connected to the data line and the scan line through the pin port 102 respectively, and transmits the row scan signal and the data signal.

[0103] To form pixel units and transmit signals, a driving layer is stacked on the substrate 11. The driving layer includes a first scan line 12 disposed in the first non-display area F1, a second scan line 14 disposed in the second non-display area F2, and a thin-film transistor disposed in the display area AA. The thin-film transistor is connected to the pixel electrode 18 through a via 171 to form a pixel unit. When the thin-film transistor receives a row scan signal and a data signal, the semiconductor layer 134 is turned on and transmits the data signal to the pixel electrode 18. The pixel electrode 18 and the common electrode layer on the opposing substrate 200 form a driving voltage and control the electrophoretic particles located in the middle to move up and down until the electrophoretic particles reach the designated position. When ambient light shines on the electrophoretic particles, the electrophoretic particles can refract ambient light of the corresponding color, so that the electronic ink displays the corresponding color.

[0104] The thin-film transistor can employ a top-gate structure or a bottom-gate structure. In one optional embodiment, such as... Figure 2 As shown, the thin-film transistor includes:

[0105] Gate 131 is stacked on the substrate of the display area;

[0106] A gate insulating layer 132 is stacked on the substrate and covers the gate 131.

[0107] Semiconductor layer 134 is stacked on gate insulating layer 132;

[0108] The source / drain metal layer 133 is stacked on the gate insulating layer 132 and is in contact with both ends of the semiconductor layer 134. The source / drain metal layer 133 is also connected to the pixel electrode 18 through the via 171.

[0109] In this embodiment, the thin-film transistor adopts a bottom-gate structure, that is, the gate 131 is located below the semiconductor layer 134. The gate 131 is disposed opposite to the semiconductor layer 134 and is spaced apart by the gate insulating layer 132. The gate 131 is connected to the first scan line 12 of the first non-display area and / or the second scan line 14 of the second non-display area and inputs the line scan signal. The source drain metal layer 133 includes a source electrode and a drain electrode. The source electrode and the drain electrode are respectively connected to the two ends of the semiconductor layer 134. The drain electrode is used to connect the data line. The source electrode is connected to the pixel electrode 18 through the via 171. The gate 131, the source drain metal layer 133, the semiconductor layer 134 and the pixel electrode 18 constitute a pixel unit. When the gate 131 receives the line scan signal, the semiconductor layer 134 forms a path and transmits the data signal received by the drain electrode to the source electrode and the pixel electrode 18. The pixel electrode 18 forms a driving voltage with the common electrode layer on the opposing substrate 200 and controls the electrophoretic particles located in the middle to move up and down.

[0110] Corresponding to the thin-film transistor structure, the first scan line 12 and the second scan line 14 can be arranged in a corresponding position relative to the gate 131. In an optional embodiment, the first scan line 12 and the second scan line 14 are stacked on the gate insulating layer 132 and are connected to the gate 131 at the edge of the array substrate.

[0111] The first scan line 12, the source / drain metal layer 133, the semiconductor layer 134, and the second scan line 14 can be formed by corresponding deposition, development / exposure, etching, and other methods.

[0112] S20. A first protective layer is formed on the driving layer. The first protective layer includes a first sub-protective layer 151 located in the first non-display area F1 and a second sub-protective layer 152 located in the second non-display area F2. The first sub-protective layer 151 is stacked and covers the first scan line 12, and the second sub-protective layer 152 is stacked and covers the second scan line 14.

[0113] Reference Figure 4As shown, to prevent debris from falling onto the gate 131 layer of the non-display area AA during substrate 11 cutting, which could cause trace damage and display abnormalities, a first protective layer is stacked at the first non-display area F1 and the second non-display area F2. The first protective layer covers the first scan line 12 and the second scan line 14, respectively. That is, the first protective layer includes a first sub-protective layer 151 disposed in the first non-display area F1 and a second sub-protective layer 152 disposed in the second non-display area F2. The first sub-protective layer 151 covers the first scan line 12 and wraps the first scan line 12 with the substrate 11, and the second sub-protective layer 152 covers the second scan line 14 and wraps the second scan line 14 with the substrate 11. The first protective layer can effectively reduce debris splashing onto the traces, avoid trace damage, and improve the display reliability of the display panel.

[0114] The first sub-protective layer 151 and the second sub-protective layer 152 can be formed by deposition, etching, or other methods, respectively. In an optional embodiment, such as... Figure 8 As shown, step S20 includes:

[0115] S21. Deposit a first protective layer on the driving layer and cover the first scan line 12, the source / drain metal layer 133, the semiconductor layer 134, and the second scan line 14.

[0116] S22. The first protective layer is etched in the display area AA along the stacking direction y, and a groove 153 is formed in the display area AA to expose the source / drain metal layer 133 and the semiconductor layer 134. A first sub-protective layer 151 covering the first scan line 12 is formed in the first non-display area F1, and a second sub-protective layer 152 covering the second scan line 14 is formed in the second non-display area F2.

[0117] In the fabrication of the first sub-protective layer 151 and the second sub-protective layer 152, the first protective layer is first deposited on the entire surface of the driving layer, covering the driving layer. Then, along the stacking direction y, etching and exposure development are performed at the position of the display area AA, so that there is no first protective layer in the display area AA, and no protective layer covering the source / drain metal layer 133 and the semiconductor layer 134. The first sub-protective layer 151 and the second sub-protective layer 152 are formed in the first non-display area F1 and the second non-display area F2, respectively. The first sub-protective layer 151 covers the first scan line 12 and wraps the first scan line 12 with the gate insulating layer 132. The second sub-protective layer 152 covers the second scan line 14 and wraps the second scan line 14 with the gate insulating layer 132. The first protective layer can effectively reduce debris splashing onto the traces, avoid trace damage, and improve the display reliability of the display panel.

[0118] Meanwhile, the first sub-protective layer 151, the substrate 11, and the second sub-protective layer 152 form a groove 153 in the display area AA, and the thin film transistor is disposed in the groove 153.

[0119] S30. A second protective layer 16 is formed on the first protective layer and the thin-film transistor.

[0120] To prevent moisture intrusion, which could lead to the peeling of the first protective layer or corrosion of the through-hole 171, such as... Figure 5 As shown, a second protective layer 16 is stacked on top of the first protective layer. The second protective layer 16 covers the first sub-protective layer 151 and the second sub-protective layer 152. The second protective layer 16 and the grid insulating layer 132 surround the first sub-protective layer 151 and the second sub-protective layer 152, thereby encapsulating the first sub-protective layer 151 and the second sub-protective layer 152. With the side blocking of the second protective layer 16, the first sub-protective layer 151 and the second sub-protective layer 152 can reduce the risk of moisture intrusion from the cross section, thereby avoiding the problem of peeling of the first protective layer or corrosion of the via 171, and effectively ensuring the stability of the display effect.

[0121] The second protective layer 16 has a uniform width along the first direction x. The second protective layer 16 can be formed on the inner wall of the groove 153 by etching, exposure and development after being deposited in the groove 153 of the display area AA.

[0122] S40, A third protective layer 17 is formed on the second protective layer 16, and the third protective layer 17 covers the display area AA.

[0123] like Figure 6 and Figure 7 As shown, since the first non-display area F1 and the second non-display area F2 have a dual structure of first protective layer and second protective layer 16, the layer height of the first non-display area F1 and the second non-display area F2 is greater than the layer height of the display area AA, and the protection effect of the non-display area AA is greater than the protection effect of the display area AA. In order to achieve consistency in layer height and protection effect, a third protective layer 17 is also stacked on the second protective layer 16 located in the display area AA. The third protective layer 17 fills the groove 153. The third protective layer 17 and the second protective layer 16 of the display area AA provide dual protection for the thin film transistor of the display area AA, and achieve consistency in layer height and protection effect.

[0124] The third protective layer 17 can be formed within the groove 153 by means of deposition, etching, exposure and development, etc. In an optional embodiment, such as... Figure 9 As shown, step S40 includes:

[0125] S41. Deposit a third protective layer 17 on the second protective layer 16;

[0126] S42, the third protective layer 17 is etched in the first non-display area F1 and the second non-display area F2, and the third protective layer 17 is formed on the display area AA.

[0127] When preparing the third protective layer 17, such as Figure 6 As shown, a third protective layer 17 is first deposited over the entire surface of the second protective layer 16, covering the second protective layer 16. Then, as... Figure 7 As shown, etching, exposure and development are performed at the positions of the first non-display area F1 and the second non-display area F2 along the stacking direction y, so that there is no third protective layer 17 in the non-display area AA, but a third protective layer 17 is formed on the display area AA. The source drain metal layer 133 and the semiconductor layer 134 are covered by the third protective layer 17. The third protective layer 17 and the second protective layer 16 of the display area AA provide dual protection for the source drain metal layer 133 and the semiconductor layer 134 of the display area AA, and achieve consistent layer height and consistent protection effect.

[0128] S50. A hole is drilled in the third protective layer 17 to the thin film transistor, and a pixel electrode 18 is provided in the third protective layer 17. The pixel electrode 18 is connected to the thin film transistor through a via 171, specifically, to the source and drain metal layer 133 of the thin film transistor.

[0129] In order to form pixel units, such as Figure 7 and Figure 2 As shown, the pixel electrode 18 is disposed on the third protective layer 17 on the display area AA, and vias 171 are formed on the second protective layer 16 and the third protective layer 17, and the pixel electrode 18 is deposited thereon. The bottom of the pixel electrode 18 is connected to the source electrode of the source-drain metal layer 133. The source electrode, drain electrode, semiconductor layer 134 and pixel electrode 18 constitute a pixel unit. The pixel electrode 18 forms a driving voltage with the common electrode layer on the opposing substrate 200 and controls the electrophoretic particles located in the middle to move up and down until the electrophoretic particles reach the designated position, so that when the ambient light shines on the electrophoretic particles, the electrophoretic particles can refract the ambient light of the corresponding color, so that the electronic ink displays the corresponding color.

[0130] Furthermore, since the width of the metal trace is limited when the scan line uses a single-layer trace, in an optional embodiment, to increase the width of the metal trace, such as... Figure 10 As shown, before step S10, the procedure further includes:

[0131] S60. A third scan line 19 is formed on the substrate 11 of the first non-display area F1. The third scan line 19 and the first scan line 12 are arranged in an alternating pattern along the first direction x.

[0132] S70, a fourth scan line 20 is formed by stacking the substrate 11 in the second non-display area F2, and the fourth scan line 20 and the second scan line 14 are arranged in an alternating pattern along the first direction x.

[0133] In this embodiment, the first scan line 12 and the second scan line 14 are located on the upper part of the gate insulating layer 132, and the third scan line 19 and the fourth scan line 20 are located on the lower part of the gate insulating layer 132. The first scan line 12 and the third scan line 19 are alternately routed, and the second scan line 14 and the fourth scan line 20 are alternately routed. By increasing the width of the metal traces, a greater number of scan lines can be set.

[0134] The gate insulating layer 132 is also used to achieve insulation between the double scan lines.

[0135] The first protective layer, the second protective layer 16, and the third protective layer 17 can be made of different materials. In an optional embodiment, the first protective layer and the third protective layer 17 are made of PFA material, also known as soluble polytetrafluoroethylene. The first protective layer and the second protective layer 16 serve as both planarization layers and protective layers.

[0136] In an optional embodiment, the second protective layer 16 is made of gallium nitride material. As a protective layer, the second protective layer 16 has good insulation effect and stability, which can reduce the damage of external ions to the channel and prevent moisture intrusion.

[0137] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0138] like Figure 11 As shown, a third aspect of the present invention provides a display panel, which includes an opposing substrate 200 and an array substrate 100 disposed opposite to each other. The array substrate 100 is the array substrate 100 described above or an array substrate 100 prepared based on the preparation method of the array substrate 100 described above. The specific structure of the array substrate 100 is as described in the above embodiments. Since this display panel adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0139] The display panel also includes an electronic ink film layer 300 located between the opposing substrate 200 and the array substrate 100. The electronic ink is composed of millions of microcapsules, each containing negatively charged and positively charged electrophoretic particles suspended in a transparent liquid. The array substrate 100 and the opposing substrate 200 provide positive and negative electrodes. Electrophoretic particles with different charges move up and down between the array substrate 100 and the opposing substrate 200 according to the electric field applied to them until the electrophoretic particles reach a designated position. When ambient light shines on the electrophoretic particles, the electrophoretic particles can refract ambient light of the corresponding color, so that the microcapsules display the corresponding color.

[0140] The opposing substrate 200 also includes a substrate 11 and a common electrode layer. The common electrode layer is located on the side of the substrate 11 close to the array substrate 100. The common electrode layer and the pixel electrode 18 form positive and negative electrodes and drive the electrophoretic particles of the electronic ink.

[0141] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. An array substrate, characterized by, The array substrate comprises: a substrate substrate sequentially divided into a first non-display area, a display area and a second non-display area along a first direction; a driving layer stacked on the substrate substrate, the driving layer comprising a first scan line in the first non-display area, a thin film transistor in the display area, and a second scan line in the second non-display area, the first scan line, the thin film transistor and the second scan line being arranged side by side and extending along a second direction, the first direction and the second direction intersecting; a first protection layer comprising a first sub-protection layer in the first non-display area and a second sub-protection layer in the second non-display area, the first sub-protection layer being stacked on the first scan line, and the second sub-protection layer being stacked on the second scan line; a second protection layer stacked on the first protection layer and the thin film transistor; a third protection layer stacked on the second protection layer and covering the display area; a pixel electrode on the third protection layer and connected to the thin film transistor through a via hole.

2. The array substrate of claim 1, wherein, The thin film transistor comprises: a gate electrode stacked on the substrate substrate of the display area; a gate insulating layer stacked on the substrate substrate and covering the gate electrode; a semiconductor layer stacked on the gate insulating layer; a source-drain metal layer stacked on the gate insulating layer and in contact with both ends of the semiconductor layer, the source-drain metal layer also connected to the pixel electrode through the via hole.

3. The array substrate of claim 2, wherein, The first scan line and the second scan line are stacked on the gate insulating layer.

4. The array substrate of claim 1, wherein, The second protection layer forms a groove in the display area, and the third protection layer is filled in the groove.

5. The array substrate of claim 3, wherein, The array substrate further comprises: a third scan line stacked on the array substrate of the first non-display area, the third scan line and the first scan line being staggered along the first direction; a fourth scan line stacked on the array substrate of the second non-display area, the fourth scan line and the second scan line being staggered along the first direction.

6. A method for fabricating an array substrate, characterized in that, The array substrate comprises: a driving layer stacked on the substrate substrate, the array substrate sequentially divided into a first non-display area, a display area and a second non-display area along a first direction, the driving layer comprising a first scan line in the first non-display area, a thin film transistor in the display area, and a second scan line in the second non-display area, the first scan line, the thin film transistor and the second scan line being arranged side by side and extending along a second direction, the first direction and the second direction intersecting; a first protection layer stacked on the driving layer, the first protection layer comprising a first sub-protection layer in the first non-display area and a second sub-protection layer in the second non-display area, the first sub-protection layer being stacked on the first scan line, and the second sub-protection layer being stacked on the second scan line; a second protection layer stacked on the first protection layer and the thin film transistor; a third protection layer formed on the second protection layer, the third protection layer covering the display area; Punching holes to the thin film transistor on the third protective layer, and setting a pixel electrode on the third protective layer, the pixel electrode being connected to the thin film transistor through the via hole.

7. The manufacturing method of an array substrate according to claim 6, wherein The first protective layer is formed on the driving layer, comprising: Depositing a first protective layer on the driving layer and covering the first scan line, the thin film transistor and the second scan line; Etching the first protective layer along the stacking direction in the display area, forming a groove in the display area and exposing the thin film transistor, and forming a first sub-protective layer covering the first scan line in the first non-display area and a second sub-protective layer covering the second scan line in the second non-display area.

8. The method for manufacturing an array substrate according to claim 6, wherein The third protective layer is formed on the second protective layer, and the third protective layer covers the display area, comprising: Depositing a third protective layer on the second protective layer; Etching the third protective layer in the first non-display area and the second non-display area, and forming the third protective layer on the display area.

9. The method for manufacturing an array substrate according to claim 6, wherein The thin film transistor comprises: A gate electrode is stacked on the substrate of the display area; A gate insulating layer is stacked on the substrate and covers the gate electrode; A semiconductor layer is stacked on the gate insulating layer; A source-drain metal layer is stacked on the gate insulating layer and contacts both ends of the semiconductor layer, and the source-drain metal layer is also connected to the pixel electrode through the via hole; Before the step of stacking a driving layer on the substrate, it further comprises: A third scan line is formed on the substrate in the first non-display area, and the third scan line and the first scan line are staggered along the first direction; A fourth scan line is formed on the substrate in the second non-display area, and the fourth scan line and the second scan line are staggered along the first direction.

10. A display panel, characterized by, It comprises oppositely arranged opposing substrate and array substrate, the array substrate is the array substrate as claimed in any one of claims 1-5 or prepared based on the preparation method of array substrate as claimed in any one of claims 6-9.

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