Edge fault diagnosis design method for electromagnetic valve fault data acquisition and diagnosis

Abstract

The invention discloses an edge fault diagnosis design method for solenoid valve fault data acquisition and diagnosis, and the method comprises the steps: designing a data collection module which is responsible for collecting driving current and driving voltage physical analog quantity signals in the operation process of a solenoid valve; designing a data transmission module, and transmitting the acquired voltage and current data to an upper computer; designing a top layer module of the fault data acquisition equipment, and integrating a data acquisition module and a data transmission module; the method comprises the following steps of: designing a dual-time-frequency attention network model, deploying the model on edge computing equipment, constructing a fault diagnosis terminal system, cooperatively operating electromagnetic valve fault data acquisition equipment based on an FPGA (Field Programmable Gate Array) and a Jetson AGX Xavier edge computing platform, and testing. According to the invention, real-time monitoring, fault identification and local data processing of the operation state of the solenoid valve can be realized, the advantages of low delay and high efficiency of edge calculation are fully played, the accuracy of fault diagnosis and the response speed of the system are improved, and the operation requirements in a complex industrial field are met.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electromagnetic valve fault diagnosis, and particularly relates to an edge fault diagnosis design method for electromagnetic valve fault data acquisition and diagnosis. BACKGROUND

[0002] Pneumatic electromagnetic valves are common actuators in industrial automation systems, widely used in process control, pneumatic assembly, automated production lines and other scenarios. It controls the on-off of gas by receiving electrical signals, achieving precise control of mechanical action. With the high-frequency operation of industrial equipment and the improvement of system complexity, the reliability of electromagnetic valves is increasingly prominent. Common faults such as slow response, sticking, leakage, coil burning, etc. If not discovered and handled in time, it may cause system malfunction, shutdown and even equipment damage, seriously affecting the safety and continuity of the industrial site.

[0003] With the continuous development of sensing technology, embedded systems and artificial intelligence, electromagnetic valve fault diagnosis has gradually shifted from traditional manual detection to intelligent and real-time development. Especially with the support of edge computing and deep learning, building a high-precision, low-latency, deployable electromagnetic valve fault diagnosis system has become a hot spot in current research and engineering applications. However, existing electromagnetic valve fault diagnosis methods still have many shortcomings in practical application, which can be divided into the following three categories: 1) Fault diagnosis method based on electrical signal analysis This method mainly collects current, voltage and other electrical parameters during the operation of the electromagnetic valve, and combines with the set threshold to make judgments. For example, according to the coil current change trend to judge the abnormality of on-off state, according to the response time to judge whether there is mechanical sticking, etc. This method has the advantages of simple implementation and low cost. However, this method is highly dependent on threshold setting and expert experience, and it is difficult to guarantee the generalization ability and robustness of the diagnosis under different electromagnetic valve models, working loads and external interference conditions. At the same time, this method is difficult to perceive small changes such as non-linear and early faults, and the misjudgment and omission phenomenon is more prominent, which is difficult to meet the requirements of accuracy and sensitivity in complex industrial environments.

[0004] 2) Fault diagnosis method based on time-frequency features and traditional machine learning Such methods usually utilize time-frequency analysis tools such as Short-Time Fourier Transform (STFT), Wavelet Transform, etc. to perform multi-scale transformation on electrical signals, extract representative features such as frequency band energy, frequency drift, time variation rate, etc. from them, and then use traditional machine learning algorithms such as Support Vector Machine (SVM), Random Forest, K-Nearest Neighbor, etc. for classification and recognition. Compared with pure signal analysis methods, this type of method improves the pattern recognition ability of fault diagnosis and is suitable for the discrimination of various typical faults. However, there are two core problems: first, feature engineering relies on manual design and is difficult to automatically adapt to different fault scenarios; second, this type of method mostly operates in offline state, with large computational overhead and poor real-time performance, making it unsuitable for deployment on edge terminals for online diagnosis.

[0005] 3) Intelligent diagnosis method based on deep neural network This type of method can automatically extract complex time-frequency features from a large amount of electromagnetic valve fault data, achieve accurate recognition of fault patterns, has strong feature learning ability and high diagnostic accuracy, can adapt to various fault types and working condition changes, and significantly improves the generality and robustness of the system. However, this type of method usually has complex model structure, numerous parameters, and high computational resource demand, making it difficult to be directly deployed on resource-constrained edge devices. Complex models face real-time challenges when deployed on edge platforms, affecting the timely response of fault diagnosis.

[0006] In summary, the current fault diagnosis methods for electromagnetic valves mainly have the following problems: First, methods based on electrical signal analysis are highly dependent on expert experience and threshold setting, lack self-adaptability to diversified faults under complex working conditions, are difficult to accurately capture early or minor fault signals, and have a high risk of misdiagnosis and missed diagnosis; second, methods based on time-frequency features and traditional machine learning have improved fault recognition ability, but their feature extraction relies on manual design and is difficult to achieve automation and generalization, and most are offline analysis, lacking real-time performance and online deployment capability, making it difficult to meet the demand for fast response in industrial sites; intelligent diagnosis methods based on deep neural networks have strong feature learning and recognition ability, but their complex model structure and high computational resource consumption limit their application on resource-constrained edge devices, and the model has poor interpretability, affecting the analysis and judgment of fault causes, in addition, it relies on a large amount of labeled data, with high data acquisition cost, and still faces great challenges in real-time performance. In view of the above problems, the existing technology is difficult to achieve efficient, accurate, real-time and deployable intelligent diagnosis of electromagnetic valve faults, and there is an urgent need for a fault diagnosis terminal system that combines high precision, real-time performance and edge computing adaptability to meet the strict requirements of modern industrial automation for equipment condition monitoring and maintenance. SUMMARY

[0007] The edge fault diagnosis design method for electromagnetic valve fault data acquisition and diagnosis provided by the application can acquire and diagnose the voltage and current signals of the electromagnetic valve, and can solve at least one of the technical problems in the background art.

[0008] To achieve the above-mentioned object, the application adopts the following technical solutions: An edge fault diagnosis design method for electromagnetic valve fault data acquisition and diagnosis comprises the following steps, Step 1: design a data acquisition module, which is responsible for acquiring the driving current and driving voltage physical analog quantity signals in the operation process of the electromagnetic valve and converting them into digital signals; Step 2: design a data transmission module to transmit the voltage and current data acquired in step 1 to the upper computer; Step 3: design a top module of the fault data acquisition equipment, integrate the main data acquisition module and the data transmission module to complete the overall design of the fault data acquisition equipment; Step 4: design a dual-time-frequency attention network model and deploy the model on the edge computing device, in order to ensure the real-time performance of the model, use the ONNX Runtime inference engine and the TensorRT framework to accelerate the inference of the model respectively, and compare the inference time and model accuracy to determine whether to use the ONNX Runtime inference engine for acceleration inference. Finally, build a fault diagnosis terminal system, and make the FPGA-based electromagnetic valve data acquisition equipment and the edge computing platform run cooperatively; Step 5: test the complete fault diagnosis terminal system composed of the designed FPGA-based fault data acquisition equipment and the Jetson AGX Xavier edge computing platform.

[0009] Further, step 1 comprises, In the design, the data acquisition module is mainly responsible for acquiring the driving current and driving voltage physical analog quantity signals in the operation process of the electromagnetic valve and converting them into digital signals. The application designs a voltage acquisition and current acquisition module based on FPGA to convert analog signals into digital signals, which facilitates the acquisition of fault data of the faulty electromagnetic valve.

[0010] In the design, the electromagnetic valve rated driving voltage is the industry standard 24V, and the voltage input range of the selected data acquisition AD board card is-5V to 5V. Because the driving voltage exceeds the input range of the AD board card, the AD board card cannot be directly connected with the test circuit when collecting the voltage signal. Therefore, the electromagnetic valve driving voltage signal needs to be reduced. The input voltage signal range is converted to the output signal range 0-5V by using the voltage transmitter, the amplitude matching of the signal is realized, so as to ensure that the voltage signal is safely input to the AD board card without distortion, and meet the requirements of subsequent data acquisition and analysis. In order to improve the accuracy of the collected voltage results, the measurement method of defining the median value is used.

[0011] In the design, for current acquisition, a current-to-voltage module is designed to convert the current in the range of 4-20mA to the voltage in the range of 0-5V. The main function of the circuit design is to detect and convert the current of the input module into voltage and amplify it. When the current-to-voltage module is input with 4mA current, it outputs 0V voltage, and when it is input with 20mA current, it outputs 5V voltage. Therefore, the conversion proportionality coefficient is According to formula (5), the collected voltage data can be restored to current data.

[0012] ; In formula (5), is the restored current data, is the conversion proportionality coefficient, is the collected voltage data.

[0013] Further, step 2 includes, A data transmission module is constructed for transmitting fault data from the data acquisition module to the host computer. In the design, Ethernet technology is used to realize high reliability and high real-time transmission. The data transmission module is constructed based on the TCP / IP five-layer protocol model, and UDP protocol is preferably used to reduce resource consumption and improve transmission rate. The functions of each layer in the five-layer protocol structure are as follows: Physical layer: composed of LAN8720A PHY chip, connected with Ethernet MAC layer through RMII interface, realizes physical transmission of signal and electrical interface, data is transmitted through RJ45 interface for wired Ethernet communication; Data link layer (MAC layer): assembles the UDP data packet encapsulated by the upper layer with MAC frame header, frame start delimiter, preamble, etc., to ensure the integrity of the frame structure and the ordered transmission of data. The frame header contains source / destination MAC address and frame type; Network layer: responsible for encapsulating data packets into IP packets, adding IP headers, including source / destination IP addresses, etc., for logical addressing and routing functions, ensuring that data is correctly addressed in the network; Transport layer: encapsulates collected data using the UDP protocol, adds an 8-byte UDP header containing source / destination port numbers and data length information; Application layer: using UDP packets as carriers, the collected solenoid valve fault data is received and displayed in real time through the software interface of the host computer, realizing the actual monitoring function of the system.

[0014] Further, step 2 further comprises, In the designed data transmission module, FIFO module, eth_udp_rmii module and PLL module are designed respectively. The FIFO module uses registers to cache the data transmitted by the data acquisition module before transmitting it to the eth_udp_rmii module, avoiding data loss or overflow; the PLL module is a phase-locked loop module that converts the system clock signal input into the PLL module into different frequency clock signals required by each module inside the FPGA; the eth_udp_rmii module is the core part of the data transmission module, mainly responsible for encapsulating the received data into MAC layer packet format, and sending the data to the host computer using the RMII interface after verification. Among them, the eth_udp_rmii module is mainly divided into ip_receive module, ip_send module and crc_32 module. The ip_receive module receives the rx_data information from the host computer using the RMII interface protocol, and sends an rx_end end signal after a single data reception is completed; the ip_send module encapsulates the data (send_data) received from the FIFO module into a UDP packet according to the preset packet format, and transmits the encapsulated data to the host computer through the RMII interface, and then sends the transmitted data to the crc_32 module; the crc_32 module receives the data sent by the ip_send module and calculates the check value using the CRC32 algorithm, and then sends the CRC check value to the ip_send module.

[0015] Further, step 3 comprises, The top module of the fault data acquisition device designed by the application mainly integrates the data acquisition module and the data transmission module to complete the overall design of the fault data acquisition device.

[0016] The top module of the fault data acquisition device accesses the data acquisition module designed in step 1 and the data transmission module designed in step 2, wherein the data acquisition module is controlled by the ad_top module, is responsible for acquiring the driving current or voltage signal of the electromagnetic valve, and performs conversion processing on the data. In order to realize the data sending control of the data acquisition module to the data transmission module, control logic is added to the original FIFO module used for data caching to form the ad_send_ctrl module, which is used to complete the data caching and sending scheduling functions at the same time. The design further adds the eth_receive_ctrl module and the eth_send_ctrl module, the former controls the eth_udp_rmii module to receive the data sent by the upper computer through the RMII interface, and the latter controls the eth_udp_rmii module to send data to the upper computer through the RMII interface. The top module of the fault data acquisition device first acquires the driving current (or voltage) signal of the electromagnetic valve through the data acquisition module, converts the data and sends it to the ad_send_ctrl module. The ad_send_ctrl module mainly includes an asynchronous FIFO module for buffering the driving signal data sent by the ad_top module to the eth_udp_rmii module. The eth_receive_ctrl module and the eth_send_ctrl module use the RMII interface protocol to control the eth_udp_rmii module to receive and send data to the upper computer, respectively.

[0017] Further, step 4 comprises, The edge fault diagnosis terminal system design mainly includes the design and deployment of the dual time-frequency attention network model and the design of the fault terminal system. In order to improve the extraction ability of the model to the time-frequency characteristics of the signal, a dual time-frequency attention network model is designed. First, the short-time Fourier transform (STFT) is discretized and constructed into a convolution kernel function that can be embedded in a neural network, and then a preprocessing layer for time-frequency analysis is introduced. Subsequently, based on the preprocessing layer, the structure of the traditional channel attention mechanism and spatial attention mechanism is improved, and a dual time-frequency attention module that integrates time-frequency information is constructed by referring to the architecture design of the CBAM module. Finally, the dual time-frequency attention module is combined with a one-dimensional convolutional neural network basic backbone model to build a dual time-frequency attention network with stronger time-frequency feature modeling capability. The designed dual time-frequency attention network model is deployed on the Jetson AGX Xavier of Nvidia Company to diagnose the electromagnetic valve fault data. The deep learning framework used to build and train the model is the PyTorch framework, and after the training is completed, the pth model of the PyTorch framework can be exported. In order to ensure the real-time and stability of the fault diagnosis model in the Jetson AGX Xavier edge computing platform, after the model is trained and exported, the ONNX Runtime engine and the TensorRT framework are used to realize the efficient deployment and accelerated inference of the PyTorch model. Considering the inference time and model accuracy after deploying the model in these two ways, the ONNX Runtime engine is finally used to accelerate the model inference.

[0018] The fault diagnosis terminal system is the core of the design to realize real-time detection and diagnosis of solenoid valve faults. Through the collaborative work of the designed fault data acquisition device and the edge computing device Jetson AGX Xavier deployed with the dual-time-frequency attention network model, the fault data of the solenoid valve can be quickly and accurately collected, transmitted, inferred, and diagnosed. In the fault diagnosis terminal system, the FPGA-based fault data acquisition device is mainly responsible for real-time acquisition and preprocessing of solenoid valve fault signals. After collecting the current and voltage data generated during the operation of the solenoid valve, the data is encapsulated and transmitted to Jetson AGX Xavier using the UDP protocol. After receiving the UDP data packet, Jetson AGX Xavier first performs CRC check analysis on the transmission data, restores the original signal waveform, and performs data normalization to convert it into the input format required by the model. When there are 1024 data in the cache, it is packaged and sent to the inference model as input data. Then, the dual-time-frequency attention network model optimized by the ONNX Runtime engine is called to classify and infer the input model data. By adding a Softmax layer, a fault probability distribution is generated to determine which fault type the current solenoid valve state belongs to. The solenoid valve fault diagnosis result is directly output by the program.

[0019] Finally, the designed FPGA-based fault data acquisition device and Jetson AGX Xavier edge computing platform were tested together to form a complete fault diagnosis terminal system. The final test results show that the fault diagnosis terminal system designed in this design can accurately diagnose solenoid valve faults while ensuring real-time performance, effectively demonstrating the feasibility of the fault diagnosis terminal system designed in this design for practical engineering applications.

[0020] From the above technical solutions, since the existing methods can be divided into fault diagnosis methods based on electrical signal analysis, fault diagnosis methods based on time-frequency characteristics and traditional machine learning, and intelligent diagnosis methods based on deep neural networks. Electromagnetic valve fault diagnosis generally relies on sensors, including voltage, current and other characteristic quantities. These methods have different degrees of limitations when dealing with electromagnetic valve fault diagnosis; the edge fault diagnosis design method for electromagnetic valve fault data acquisition and diagnosis in the embodiment of the application mainly includes two parts: an electromagnetic valve fault data acquisition device based on FPGA design and a JetsonAGX Xavier edge computing platform. First, the FPGA hardware design and architecture of the electromagnetic valve fault data acquisition device are designed; a data transmission module is designed to transmit the collected voltage and current data to the host computer; the top module of the fault data acquisition device is designed to integrate the data acquisition module and the data transmission module to complete the overall design of the fault data acquisition device; a dual-time-frequency attention network model is designed, and the model is deployed on the edge computing device. In order to ensure the real-time performance of the model, the ONNX Runtime inference engine and the TensorRT framework are used to accelerate the inference of the model, and the inference time and model accuracy are compared to determine the use of the ONNX Runtime inference engine for acceleration inference; a fault diagnosis terminal system is constructed, and the electromagnetic valve data acquisition device based on FPGA and the edge computing platform are cooperatively operated. Finally, the complete fault diagnosis terminal system composed of the designed FPGA-based fault data acquisition device and the Jetson AGX Xavier edge computing platform is tested.

[0021] The technical solutions proposed in the present application can solve or improve the following technical defects: 1) The traditional electrical signal analysis method relies on manual experience and fixed threshold, and it is difficult to accurately identify early and small faults. The present application designs a high-precision fault data acquisition module to collect the driving voltage and current signals in real time during the operation of the electromagnetic valve, avoiding the dependence on manual threshold setting. The acquisition module realizes high-speed sampling, preprocessing and packaging of signals based on FPGA, and uses UDP protocol to transmit the original fault data to the edge computing platform in real time. Compared with the traditional method, this method can retain more dynamic detail features in the electrical signal, providing high-quality raw data support for subsequent intelligent diagnosis, and effectively improving the perception ability of weak abnormal signals under complex and nonlinear working conditions.

[0022] 2) The traditional time-frequency analysis and machine learning method rely on manual feature extraction, have poor generalization ability and cannot run in real time. The application constructs a double time-frequency attention neural network model, introduces a discretized short-time Fourier transform (STFT) convolution kernel as a time-frequency feature extraction module at the front end to realize the automation and learnability of the feature extraction process. The model combines improved spatial attention and channel attention mechanisms to enhance the focusing ability of the model on key feature areas. This structure has stronger feature adaptability and discrimination ability, significantly improves the robustness and generalization of the model under complex fault modes, and avoids the limitations brought by the dependence of traditional methods on manual feature selection and rule design.

[0023] 3) The existing deep learning model is complex to calculate and difficult to deploy efficiently on edge devices. After the model training is completed, the ONNX Runtime inference engine and the TensorRT framework are used to accelerate the deployment evaluation of the model, and finally the ONNX Runtime mode with the best calculation efficiency and accuracy performance is selected for edge deployment. The entire neural network model can run in real time on the Jetson AGX Xavier edge computing platform after compression optimization. This deployment strategy fully considers the actual situation of limited resources of edge computing platforms, ensures the inference efficiency of the model without sacrificing the diagnostic accuracy, and effectively improves the online running ability and response speed of the edge system. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 The flowchart of the embodiment of the application is shown in the figure. Figure 2 The voltage acquisition schematic diagram of the embodiment of the application is shown in the figure. Figure 3 The current acquisition schematic diagram of the embodiment of the application is shown in the figure. Figure 4 The circuit principle diagram of the current-to-voltage module of the embodiment of the application is shown in the figure. Figure 5 The overall design framework diagram of the data transmission module of the embodiment of the application is shown in the figure. Figure 6 The double time-frequency attention network model schematic diagram of the embodiment of the application is shown in the figure. Figure 7 The deployment and inference flowchart of the embodiment of the application using the ONNX Runtime engine is shown in the figure. Figure 8 The deployment and inference flowchart of the embodiment of the application using the TensorRT framework is shown in the figure. Figure 9 The fault diagnosis terminal system work flowchart of the embodiment of the application is shown in the figure. DETAILED DESCRIPTION

[0025] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application.

[0026] As shown in Figure 1 The edge fault diagnosis design method for electromagnetic valve fault data acquisition and diagnosis of the embodiments of the present application mainly includes two parts: an electromagnetic valve fault data acquisition device based on FPGA design and a Jetson AGX Xavier edge computing platform.

[0027] First, the FPGA hardware design and architecture of the electromagnetic valve fault data acquisition device are designed; a data transmission module is designed to transmit the collected voltage and current data to the host computer; a top module of the fault data acquisition device is designed to integrate the data acquisition module and the data transmission module to complete the overall design of the fault data acquisition device; a dual-time-frequency attention network model is designed, and the model is deployed on the edge computing device; in order to ensure the real-time performance of the model, the ONNXRuntime inference engine and the TensorRT framework are used to accelerate the inference of the model, and the inference time and model accuracy of the two are compared to determine the use of the ONNX Runtime inference engine for acceleration; a fault diagnosis terminal system is constructed to cooperatively operate the FPGA-based electromagnetic valve data acquisition device and the edge computing platform. Finally, the FPGA-based fault data acquisition device and the Jetson AGX Xavier edge computing platform cooperatively constitute a complete fault diagnosis terminal system, which is tested.

[0028] The specific steps of the method are as follows: Step 1, design a data acquisition module. The data acquisition module is mainly responsible for collecting the driving current and driving voltage physical analog quantity signals in the operation process of the electromagnetic valve, and converting them into digital signals. The data acquisition module uses an external AD board card to collect and convert the physical analog quantity signals, and the board card is driven by FPGA. The AD chip AD9280 of ANALOG Company is used to realize data acquisition and conversion. The data acquisition module of the present design needs to collect voltage data and current data respectively, and the FPGA digital logic design is based on the voltage acquisition design when designing the module. The current-to-voltage circuit is added based on the voltage acquisition, so as to realize current acquisition.

[0029] The voltage acquisition schematic diagram is as Figure 2As shown, the principle is to connect the acquisition module with the electromagnetic valve in parallel, and the module acquires the driving voltage of the electromagnetic valve at this time. The rated driving voltage of the electromagnetic valve targeted by the design is 24V, but the voltage input range of the AD board card is-5V~5V, so the board card cannot be directly connected to the test circuit when acquiring the driving voltage of the electromagnetic valve. In order to not damage the AD board card, the acquisition voltage needs to be reduced, and the voltage transmitter is used in the design to convert the input signal of 0-30V into the output signal of 0-5V, and the output signal is connected to the AD board card. The voltage acquisition range of the design is 0~5V, and the bit width of the AD9280 chip is 8 bits, so the ADC sampling resolution of the data acquisition module of the design can be calculated according to formula (1) .

[0030] ; In formula (1), FSR represents the full-scale voltage, LSB represents the sampling resolution, and n is the bit width of the AD9280 chip.

[0031] Since the bit width of the AD9280 chip is 8 bits, the voltage value collected by the chip is between 0-255, indicating that the collected voltage is in the range of 0~5V. However, this value cannot be directly used and needs to be converted to a voltage value in the AD operation module. The voltage conversion formula is as follows: ; In formula (2), V is the converted voltage, LSB is the ADC sampling resolution of the data acquisition module of the design, and A is the voltage value collected by the AD9280 chip.

[0032] However, the voltage value obtained by directly converting is not accurate enough. In order to improve the accuracy of the collected voltage result, the measurement method of defining the median value is used. Before the data acquisition module is connected to the test circuit, a standard current source is used for power-on calibration, and the average of several voltage values collected by the AD9280 chip at the beginning is taken to obtain the measurement median M corresponding to the actual collected voltage 2.5V. When the voltage value A collected by the AD9280 chip is between 0~M, the voltage conversion is performed using the following formula: ; In formula (3), , is the sampling resolution when the voltage value A is between 0~ M , FSR is the full-scale voltage 5V of the design.

[0033] When the voltage value A collected by the AD9280 chip is between M~255, the voltage conversion is performed using the following formula: ; In formula (4), A is the voltage value, FSR is the full-scale voltage 5V, and M is the maximum value of the voltage value A. , The sampling resolution is the sampling resolution when the voltage value A is between M and 255, and FSR is the full-scale voltage 5V.

[0034] The FPGA development board used in the application has a crystal frequency of 50 MHz, and the driving clock signal of the AD board card is 12.5 MHz, so the clock signal of the development board needs to be divided by four to obtain the clock signal of the AD board card. The sampling frequency of the data acquisition module refers to the number of data samples that the acquisition module can collect per second. The higher the sampling frequency of the data acquisition module, the richer the signal characteristics that the acquisition module can collect, and the more realistic the analog signal that can be restored. The sampling frequency of the designed data acquisition module is 5KHz. Since the clock signal of the AD board card is 12.5MHz, and the AD9280 chip of the board card samples the voltage data at the rising edge of the clock signal, the theoretical upper limit of the sampling frequency of the data acquisition module can reach 12.5MHz. In order to achieve the design requirement of 5KHz sampling frequency, in the above calculation, the voltage data transmitted by the AD9280 chip every 2500 times is taken as a group, which is accumulated and averaged, and according to the size of the voltage value A and M at this time, the calculated data is taken as the median and substituted into formula (3) or formula (4) voltage conversion formula to calculate the converted voltage V1 or V2.

[0035] The current acquisition schematic diagram is shown in Figure 3 , and its principle is to connect the current-to-voltage module with the measured electromagnetic valve in series, and the current-to-voltage module converts the series current at this time into voltage, and then the voltage at this time is collected through the voltage acquisition design mentioned above, and finally the driving current data of the electromagnetic valve at this time is obtained through conversion. The driving current signal of the measured electromagnetic valve is a standard signal, and its current range is 4-20mA. The circuit design principle diagram of the current-to-voltage module is shown in Figure 4 . The main function of this circuit design is to detect and convert the current of the input module into voltage and amplify it. When the current-to-voltage module is input with 4mA current, it outputs 0V voltage, and when it is input with 20mA current, it outputs 5V voltage. When current acquisition is to be performed, the current-to-voltage module is connected in series with the measured object, and the measured current is converted into voltage, and then the converted voltage is collected using the designed voltage acquisition module. When current acquisition is performed, the data collected by the data acquisition module is the voltage data converted from the current data, which needs to be restored to the collected current data through the conversion ratio relationship between current and voltage. As known from the above, the current-to-voltage module converts 4-20ma current into 0-5V voltage, so the conversion ratio coefficient can be determined as . The collected voltage data can be restored to current data according to the following formula (5).

[0036] ; In formula (5), is reduced current data, is a conversion coefficient, is collected voltage data.

[0037] Step 2, design a data transmission module. In order to transmit the fault data collected by the data acquisition module to the host computer at high speed and reliably, the application proposes a data transmission module design scheme based on the UDP protocol in the fault diagnosis terminal system. The scheme can effectively improve the data transmission rate and resource utilization efficiency of the system under the premise of ensuring communication reliability, and is particularly suitable for FPGA platforms. The present embodiment adopts the hierarchical packaging idea, combines the TCP / IP five-layer network communication model, and transmits the current and voltage signal data collected by the electromagnetic valve through the UDP protocol for fast packaging and transmission. The UDP protocol is a transport layer protocol, which has the advantages of simple protocol structure, small overhead, and fast transmission speed compared with the TCP protocol, and is particularly suitable for scenarios with strong real-time performance and tolerating a small amount of data loss. According to the transmission characteristics of the fault signal in the application, the use of the UDP protocol can significantly reduce the system burden and improve the data processing efficiency of the edge device.

[0038] The data transmission module is based on the TCP / IP five-layer protocol model and uses the UDP protocol to reduce resource consumption and improve transmission rate. The functions of each layer in the five-layer protocol structure are as follows: Physical layer: composed of LAN8720A PHY chip, connected with Ethernet MAC layer through RMII interface, realizes physical transmission and electrical interface of signals, and data is communicated through RJ45 interface for wired Ethernet communication; Data link layer, i.e. MAC layer: assembles the UDP data packet packaged by the upper layer with MAC frame header, frame start delimiter, and preamble to ensure the integrity of the frame structure and the ordered transmission of data; the frame header contains source / destination MAC address and frame type; Network layer: responsible for encapsulating data packets into IP packets, adding IP header, including source / destination IP address, for logical addressing and routing functions to ensure correct addressing of data in the network; Transport layer: encapsulates collected data using the UDP protocol and adds an 8-byte UDP header containing source / destination port number and data length information; Application layer: takes the UDP packet as a carrier and receives and displays the collected electromagnetic valve fault data through the software interface of the host computer in real time to realize the actual monitoring function of the system.

[0039] In the actual system architecture, the collected signal data is first buffered by the FIFO module in the FPGA, and then transmitted to the eth_udp_rmii module for data encapsulation and sending. The data encapsulation process of the UDP protocol is carried out according to the following flow: first, the collected data is spliced with the 8-byte UDP header, including the source port, the destination port, the data length and the check information; then the IP header is added, which undertakes the network addressing function; finally, the encapsulation result is combined with the MAC layer header information, including the preamble, the frame start delimiter, the destination and source MAC address, the data type, etc., to form a complete data packet structure. The data packet is then transmitted to the Ethernet PHY chip through the RMII interface, and then sent to the host computer or edge server through the RJ45 interface using standard Ethernet cable for subsequent processing.

[0040] To realize efficient encapsulation and transceiver process, the system uses an Ethernet PHY chip with model LAN8720A, which is connected with the MAC layer of the FPGA through the RMII interface. RMII (Reduced Media Independent Interface) has the characteristics of few pins and stable speed, and is suitable for Ethernet communication of resource-limited platforms. The PHY chip and the host computer are connected through the Ethernet physical layer to ensure high-speed and stable connection. The system block diagram of the whole data transmission module is as follows Figure 5As shown, mainly includes FIFO cache module, PLL clock module and core eth_udp_rmii module. Among them, FIFO module realizes asynchronous FIFO design through Quartus IP core, which is used to solve the clock difference problem between data acquisition module and data sending module. The write clock is provided by the acquisition module, and the read clock is driven by the working clock of the data sending module, which realizes the safe cache of data between clock domains. In order to prevent data overflow or loss, the maximum cache capacity of FIFO module is set to 2048 bytes. PLL module is responsible for converting system main clock into various frequency clock signals suitable for different modules inside FPGA. Its design also uses Quartus self PLL IP core to generate, which ensures the stable operation of each sub module of the system. PLL module realizes the synchronous timing control of different modules such as data transceiver and FIFO access by configuring multiple output frequencies. In eth_udp_rmii module, it is further subdivided into ip_receive module, ip_send module and crc_32 check module. Ip_receive module is responsible for receiving data returned from host computer and parsing MAC layer data structure, checking preamble, frame delimiter, Ethernet frame header and valid data area layer by layer according to protocol, and generating rx_end end signal after receiving. Ip_send module encapsulates the data read from FIFO according to the specified encapsulation order according to MAC layer format, and completes the data sending process through RMII interface. Crc_32 module is responsible for CRC32 redundancy check of sending data packet, so as to verify the integrity of data at the receiving end. This module receives the encapsulated data frame, generates the check value according to the CRC32 algorithm, and guarantees that the data will not be damaged in the physical transmission process. The principle of CRC32 check algorithm is shown in formula (6).

[0041] ; G(x) is the generating polynomial of CRC32, which is the core of CRC check, used to calculate the check value of data. Each term appearing in the formula represents that the coefficient of the term is 1, and the non appearing represents that the coefficient of the term is 0. X is a formal variable, which is used to represent the position weight of each bit in the polynomial.

[0042] Step 3, design the top module. This design proposes a top module system of fault data acquisition equipment, which integrates data acquisition module and data transmission module organically to form a complete fault signal acquisition and sending link.

[0043] The top module of the fault data acquisition device accesses the data acquisition module designed in step 1 and the data transmission module designed in step 2, wherein the data acquisition module is controlled by the ad_top module, is responsible for acquiring the driving current or voltage signal of the electromagnetic valve, and performs conversion processing on the data. In order to realize the data sending control of the data acquisition module to the data transmission module, control logic is added to the original FIFO module used for data caching to form the ad_send_ctrl module, which is used to complete the data caching and sending scheduling functions at the same time. The design further adds the eth_receive_ctrl module and the eth_send_ctrl module, the former controls the eth_udp_rmii module to receive the data sent by the upper computer through the RMII interface, and the latter controls the eth_udp_rmii module to send data to the upper computer through the RMII interface. The top module of the fault data acquisition device first acquires the driving current (or voltage) signal of the electromagnetic valve through the data acquisition module, sends the converted data to the ad_send_ctrl module. The ad_send_ctrl module mainly includes an asynchronous FIFO module for buffering the driving signal data sent by the ad_top module to the eth_udp_rmii module. The eth_receive_ctrl module and the eth_send_ctrl module use the RMII interface protocol to control the eth_udp_rmii module to receive and send data to the upper computer, respectively.

[0044] Step 4, design an edge fault diagnosis terminal system.

[0045] 1) Dual Time-Frequency Attention Network Model Building. The short-time Fourier transform (STFT) is combined with a one-dimensional convolution kernel to derive its complex-valued convolution kernel function, thereby constructing a time-frequency analysis preprocessing layer based on the STFT transform. Then, the time-frequency analysis preprocessing layer is used to improve the channel attention mechanism and the spatial attention mechanism, respectively, and the dual time-frequency attention module is built by referring to the CBAM module architecture. Finally, the dual time-frequency attention module is combined with a one-dimensional convolutional neural network to build a dual time-frequency attention network. Among them, referring to the architecture of the CBAM model, the time-frequency analysis channel attention module (TFC) and the time-frequency analysis spatial attention module (TFS) are used to build the dual time-frequency attention module (DTFA). The dual time-frequency attention module improved by using the time-frequency analysis preprocessing layer is combined with the one-dimensional convolutional neural network basic backbone model, and the network obtained is named dual time-frequency attention network (DTFAN). The schematic diagram of the dual time-frequency attention network model is shown in FIG. 6.

[0046] 2) Fault Diagnosis Model Deployment. The deep learning framework used for model building and training is the PyTorch framework. After training is completed, the pth model of the PyTorch framework can be exported. In order to ensure that the fault diagnosis model in this paper can realize the real-time and stability of fault diagnosis on the JetsonAGX Xavier edge computing platform, after the model is trained and exported, the ONNX Runtime engine and the TensorRT framework are used to realize the efficient deployment and accelerated inference of the PyTorch model. Considering the inference time and model accuracy after deploying the model in these two ways, it is decided which way to use to accelerate the model inference. The process of deploying the fault diagnosis model using the ONNX Runtime engine mainly includes model export, format conversion, model loading, and deployment verification, as shown in FIG. 7. Figure 7

[0047] ​First, the trained PyTorch model is converted into an ONNX (Open Neural Network Exchange) format model using the model conversion interface torch.onnx.export interface provided by the PyTorch framework. The structure of the ONNX model is checked online through the Netron website to ensure that the structure and parameters of the converted model are consistent with the original PyTorch model. Second, the ONNX model is loaded and verified using the ONNX Runtime engine to ensure that the model maintains functional consistency and correctness in the ONNX environment.

[0048] The process of deploying the fault diagnosis model using the TensorRT framework is similar to the process of using the ONNX Runtime engine. The difference lies in the need to use the NVIDIA TensorRT tool chain to parse and convert the ONNX model into the NVIDIA TensorRT inference engine. This inference engine provides deep optimization for GPU in model parsing, layer fusion, and precision quantization, significantly improving inference speed and reducing resource occupation. The flow of deploying inference using the TensorRT framework is shown in Figure 8

[0049] ​In order to evaluate the effect of model deployment, this paper conducts practical tests on the Jetson AGX Xavier platform, and compares the inference performance of the original PyTorch model, the ONNX Runtime engine accelerated model and the TensorRT engine. At the same time, in order to ensure the fairness of the test, the evaluation test code only changes the model loading part, and the rest of the calculation part remains unchanged, so as to avoid the test result fluctuation caused by the error of the code. While ensuring the real-time performance of model inference, the inference accuracy of the model is also very important. The test environment is Ubuntu 20.06, CUDA is 11.4 version, cuDNN is 8.6 version. PyTorch framework uses 2.1.0 version, ONNX Runtime engine uses onnxruntime-gpu 1.11.0 version, and TensorRT framework uses 8.5.2.2 version. The electromagnetic valve dataset is collected by using the acquisition card designed in this paper. Seventy percent of the dataset is used as the training dataset of the PyTorch model, and the other three percent is used as the evaluation dataset for this test. The experimental results show that the average single inference delay of the original PyTorch model is 116.67ms, the total test time is 5.6s, and the inference accuracy is 98.67%, which is used as the baseline performance. Such inference efficiency is obviously difficult to meet the real-time requirement of this study. When the model is converted to ONNX format and inferred by ONNX Runtime engine, the average single inference delay is greatly reduced to 3.13ms, the total test time is shortened to 0.15s, and the speedup ratio is 37.33x. At the same time, the inference accuracy of ONNX Runtime remains at 98.00%, which is only 0.67% lower than that of the original PyTorch model, which can be ignored. This shows that the ONNX Runtime engine can provide efficient inference while retaining the predictive ability of the model. Therefore, the ONNX Runtime engine is finally selected for model deployment in this paper.

[0050] Step 5, design fault diagnosis terminal system. The fault diagnosis terminal system is the core of this study to realize real-time detection and diagnosis of electromagnetic valve faults. The fault data acquisition device designed in the previous section and the edge computing device Jetson AGX Xavier deployed with the dual time-frequency attention network model work together to quickly and accurately realize the collection, transmission, inference and diagnosis of electromagnetic valve fault data.

[0051] In the fault diagnosis terminal system, the fault data acquisition device of the base FPGA is mainly responsible for the real-time acquisition and preprocessing of the solenoid valve fault signal. After the current and voltage data generated during the operation of the solenoid valve are acquired, the data are packaged, and the packaged data are transmitted to the Jetson AGX Xavier using the UDP protocol. After receiving the UDP data packet, the Jetson AGX Xavier first performs CRC check analysis on the transmission data, restores the original signal waveform, and performs data normalization operation to convert it into the input format required by the model. When 1024 data are buffered, they are packaged and sent to the inference model as input data. Then, the double time-frequency attention network model optimized by the ONNX Runtime engine is called to classify and infer the input model data, generate a fault probability distribution by adding a Softmax layer, determine which fault type the current solenoid valve state belongs to, and output the solenoid valve fault diagnosis result directly through the program. The working process of the above fault diagnosis terminal system is as shown in Figure 9 .

[0052] For the above embodiments, the relevant alternatives are as follows: 1) The hardware platform of the data acquisition device is replaced. The data acquisition described in the embodiments of the application is based on the FPGA hardware acquisition platform. In addition, domestic embedded chips such as RK3588 and RK3568 can also be used.

[0053] 2) In terms of communication interface design, the RMII interface is used to connect with the Ethernet PHY chip and realize data transmission through the UDP protocol. In addition, Pcie3.0 protocol, Pcie4.0 protocol, etc. can also be used to connect with the Ethernet PHY chip.

[0054] From the above, the core technical key points of the present application are as follows: 1) A multi-channel synchronous acquisition and preprocessing logic based on FPGA is built In the FPGA, logical modules including sampling control, data buffering, and data frame packaging are designed to support the synchronous acquisition and packaging processing of multi-channel solenoid valve data. The module uses a double-buffering mechanism and a finite state machine control to ensure that data flow processing is still realized without packet loss and low delay under high sampling rate conditions, providing high-quality original data for subsequent model inference.

[0055] 2) Efficient data transmission mechanism of UDP communication protocol The data collected by the FPGA is sent to an Ethernet PHY chip through an RMII interface to form a standard Ethernet frame, and the data is transmitted to an edge computing platform in real time based on a UDP protocol. The communication mechanism reduces transmission overhead while ensuring real-time performance, and guarantees data integrity and sequence through fixed-length data frames and a fast confirmation mechanism.

[0056] 3) Jetson AGX Xavier-based edge inference platform deployment A trained deep learning fault diagnosis model is deployed on the Jetson AGX Xavier platform. The model combines multi-scale time series feature extraction and time-frequency attention mechanisms, and can accurately identify different electromagnetic valve action states and potential fault types. The model is trained using PyTorch and exported in ONNX format, and is deployed and run using ONNX Runtime, achieving cross-platform portability and efficient inference capabilities.

[0057] In another aspect, the application also discloses a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to make the processor execute steps of the method.

[0058] In another aspect, the application also discloses a computer device, which comprises a memory and a processor, and the memory stores a computer program, and the computer program is executed by the processor to make the processor execute steps of the method.

[0059] In another embodiment provided in the application, a computer program product containing instructions is also provided, which makes a computer execute any method in the above embodiments when the computer program product is run on the computer.

[0060] It can be understood that the system, device and storage medium provided by the embodiments of the application correspond to the method provided by the embodiments of the application, and the explanation, examples and beneficial effects of the related content can refer to the corresponding part in the above method.

[0061] In the embodiments described above, all or some of the steps can be implemented by hardware, software, firmware or any combination thereof. When implemented by software, all or some of the steps can be implemented in the form of one or more computer programs or program elements. The computer programs reside (at least temporarily) in a memory of a computer during execution. The memory can be a RAM memory, a flash memory, a ROM memory, an EPROM memory, or any other suitable memory. The memory can be integral to or separate from the computer. The computer programs can be written in any suitable programming language, such as C, C++, Java, Visual Basic, etc. The computer programs can be written in assembly or machine language, if desired. The computer programs can be distributed over network coupled file servers, or can be distributed by any other suitable means.

[0062] It is to be understood that the terminology "first", "second", etc. used herein merely for the purpose of distinguishing one entity or action from another, and does not necessarily imply these entities or actions are mutually exclusive or are either temporal or spatial priorities of one another. Moreover, the terms "comprising", "including", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that processes, methods, articles, or apparatuses that comprise a list of elements are not necessarily limited to those elements, but can include other elements not expressly listed or inherent to such processes, methods, articles, or apparatuses. Without more specificity, no element is implied to be essential, unless explicitly required.

[0063] Each of the embodiments described in the specification adopt a relevant manner, and the same or similar parts between each of the embodiments can be referred to each other. Each of the embodiments focuses on the difference from other embodiments. In particular, for the system embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiments.

[0064] The above examples are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that the technical solutions recorded in the foregoing examples can be modified, or some technical features can be replaced by equivalent features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for edge fault diagnostic design for solenoid valve failure data acquisition and diagnosis, characterized by, Comprising the following steps, Step 1, design the data acquisition module, responsible for collecting the driving current and driving voltage physical analog quantity signals in the operation process of the electromagnetic valve, and converting them into digital signals; Step 2, design the data transmission module to transmit the voltage and current data collected in step 1 to the host computer; Step 3, design the top module of the fault data acquisition device, and integrate the data acquisition module and the data transmission module to complete the overall design of the fault data acquisition device; Step 4, design a dual-time-frequency attention network model and deploy it on an edge computing device, use the ONNXRuntime inference engine to speed up inference, and finally build a fault diagnosis terminal system, which cooperates the electromagnetic valve fault data acquisition device based on FPGA with the Jetson AGX Xavier edge computing platform; Step 5, test the complete fault diagnosis terminal system composed of the designed electromagnetic valve fault data acquisition device based on FPGA and the Jetson AGX Xavier edge computing platform.

2. The edge fault diagnostic design method for solenoid valve failure data acquisition and diagnosis according to claim 1, characterized in that: Step 1 includes, The rated driving voltage of the electromagnetic valve is the industrial standard of 24V, and the voltage input range of the selected data acquisition AD board card is-5V to 5V; The input voltage signal range is converted to the output signal range 0-5V by using the voltage transmitter, realizing the amplitude matching of the signal, so as to ensure that the voltage signal is safely input to the AD board card without distortion, meeting the requirements of subsequent data acquisition and analysis; In order to improve the accuracy of the collected voltage results, the measurement method of defining the median value is used.

3. The edge fault diagnostic design method for solenoid valve failure data acquisition and diagnosis according to claim 2, characterized in that: Step 1 also includes, For current acquisition, a current-to-voltage module is designed to convert the current in the range of 4-20mA to voltage in the range of 0-5V. This circuit design detects and converts the current of the input module to voltage and amplifies it. When the current-to-voltage module is input with 4mA current, it outputs 0V voltage, and when it is input with 20mA current, it outputs 5V voltage. Thus, the conversion proportion coefficient of the current is determined as According to formula (5), the collected voltage data is restored to current data. ； In formula (5), is the reduced current data, is the conversion ratio coefficient, is the collected voltage data.

4. The edge fault diagnostic design method for solenoid valve failure data acquisition and diagnosis according to claim 1, characterized in that: Step 2 includes, The data transmission module is based on the TCP / IP five-layer protocol model and uses the UDP protocol to reduce resource consumption and improve transmission rate. The functions of each layer in the five-layer protocol structure are as follows: Physical layer: composed of LAN8720A PHY chip, connected with Ethernet MAC layer through RMII interface, realizing physical transmission of signal and electrical interface, data is communicated through RJ45 interface for wired Ethernet; Data link layer, i.e. MAC layer: assembles the UDP data packet encapsulated by the upper layer with MAC frame header, frame start delimiter, and preamble to ensure the integrity of the frame structure and the ordered transmission of data; the frame header contains source / destination MAC address and frame type; Network layer: responsible for encapsulating data packets into IP packets, adding IP header, including source / destination IP address, used for logical addressing and routing function, ensuring correct addressing of data in the network; Transport layer: uses UDP protocol to encapsulate collected data, adds 8-byte UDP header, including source / destination port number and data length information; Application layer: with UDP packet as carrier, the collected electromagnetic valve fault data is received and displayed in real time through the software interface of the host computer, realizing the actual monitoring function of the system.

5. The edge fault diagnostic design method for solenoid valve failure data acquisition and diagnosis according to claim 4, characterized in that: Step 2 further comprises, The collected signal data is first buffered by the FIFO module in the FPGA, and then transmitted to the eth_udp_rmii module for data encapsulation and sending. The data encapsulation process of the UDP protocol is as follows: First, the collected data is spliced with the 8-byte UDP header, including the source port, destination port, data length and check information; then the IP header is added, which undertakes the network addressing function; finally, the encapsulation result is combined with the MAC layer header information, including the preamble, frame start delimiter, destination and source MAC address, data type, to form a complete data packet structure. The data packet is then transmitted to the Ethernet PHY chip through the RMII interface, and then sent to the host computer or edge server through the RJ45 interface using standard Ethernet cable for subsequent processing.

6. The edge fault diagnostic design method for solenoid valve failure data acquisition and diagnosis according to claim 5, characterized in that: Step 2 further comprises, In the designed data transmission module, FIFO module, eth_udp_rmii module and PLL module are designed respectively; the FIFO module uses registers to buffer the data transmitted by the data acquisition module and then transmits it to the eth_udp_rmii module, avoiding data loss or overflow during transmission; The PLL module is a phase-locked loop module that converts the system clock signal input into the PLL module into different frequency clock signals required by each module inside the FPGA; The eth_udp_rmii module is the core part of the data transmission module, responsible for encapsulating the received data into MAC layer data packet format and sending the data to the host computer after verification using the RMII interface; among them, the eth_udp_rmii module is divided into ip_receive module, ip_send module and crc_32 verification module; The ip_receive module uses the RMII interface protocol to receive the rx_data information returned from the host computer, and sends a rx_end end signal after a single data reception is completed; The ip_send module encapsulates the data received from the FIFO module into a UDP data packet according to the preset data packet format, and transmits the encapsulated data to the host computer through the RMII interface, and then sends the transmitted data to the crc_32 module; the crc_32 module receives the data sent by the ip_send module and calculates the check value using the CRC32 algorithm, and then sends the CRC check value to the ip_send module.

7. The edge fault diagnostic design method for solenoid valve failure data acquisition and diagnosis according to claim 1, characterized in that: Step 3 comprises, The fault data acquisition device top module accesses the data acquisition module designed in step 1 and the data transmission module designed in step 2, wherein the data acquisition module is controlled by the ad_top module, responsible for collecting the driving current or voltage signal of the electromagnetic valve and performing data conversion processing; In order to realize the data sending control of the data acquisition module to the data transmission module, the control logic is added to the original FIFO module for data buffering to form the ad_send_ctrl module, which is used to complete the data buffering and sending scheduling functions at the same time. The eth_receive_ctrl module and the eth_send_ctrl module are added, the eth_receive_ctrl module controls the eth_udp_rmii module to receive the data sent by the upper computer through the RMII interface, and the eth_send_ctrl module controls the data sent to the upper computer through the RMII interface. The top module of the fault data acquisition device first acquires the driving current or voltage signal of the electromagnetic valve through the data acquisition module, and sends it to the ad_send_ctrl module after conversion. The ad_send_ctrl module includes an asynchronous FIFO module for buffering the driving signal data sent by the ad_top module to the eth_udp_rmii module. The eth_receive_ctrl module and the eth_send_ctrl module use the RMII interface protocol to control the eth_udp_rmii module to receive the data of the upper computer and send the data of the upper computer respectively.

8. The edge fault diagnostic design method for solenoid valve failure data acquisition and diagnosis according to claim 1, characterized in that: Step 4 includes, The edge fault diagnosis terminal system design includes a dual time-frequency attention network model design and deployment and a fault terminal system design. The design of the dual time-frequency attention network model includes first, the discrete processing of the short-time Fourier transform STFT, and the construction of the convolution kernel function which can be embedded into the neural network, and then the introduction of the preprocessing layer of time-frequency analysis. Subsequently, based on the preprocessing layer, the structure of the traditional channel attention mechanism and the spatial attention mechanism is improved, the architecture of the CBAM module is referred to, and the dual time-frequency attention module integrating time-frequency information is constructed. The designed dual time-frequency attention network model is deployed on the Jetson AGX Xavier of Nvidia Company to diagnose the electromagnetic valve fault data.

9. The edge fault diagnostic design method for solenoid valve failure data acquisition and diagnosis according to claim 8, characterized in that: Step 4 also includes, The deep learning framework used for building and training the dual time-frequency attention network model is the PyTorch framework, and the pth model of the PyTorch framework is exported after training. After completing the model training and exporting the model, the ONNX Runtime engine and the TensorRT framework are used to realize the efficient deployment and accelerated inference of the PyTorch model, and the inference time and model accuracy of the two model deployment methods are considered, and finally the ONNX Runtime engine is used to accelerate the model inference.

10. The edge fault diagnostic design method for solenoid valve failure data acquisition and diagnosis according to claim 7, characterized in that: Step 4 also includes, In the fault diagnosis terminal system, the FPGA-based fault data acquisition device is responsible for real-time acquisition and preprocessing of solenoid valve fault signals. After collecting the current and voltage data generated during the operation of the solenoid valve, the data is encapsulated and transmitted to the Jetson AGX Xavier using the UDP protocol. After receiving the UDP data packet, the Jetson AGX Xavier first performs CRC check analysis on the transmission data, restores the original signal waveform, and performs data normalization to convert it to the input format required by the model. When there are 1024 data in the cache, it is packaged and sent to the inference model as input data. Then, the dual-time-frequency attention network model optimized by the ONNX Runtime engine is called to classify and infer the input model data. By adding a Softmax layer, a fault probability distribution is generated to determine which fault type the current solenoid valve state belongs to. The solenoid valve fault diagnosis result is directly output by the program.

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