PCB intelligent paneling based on parameterized driving and process compensation method and system

Abstract

The application discloses a kind of based on parameterization drive's PCB intelligent board and process compensation method and system, comprising the following steps: S1.determine board structure, input board parameter by graphical interface, finally real-time calculation board size;S2.based on input board parameter, process edge compensation is carried out, and the coordinate positioning of tool hole and optical point is calculated;S3.parse original PCB contour data, calculate the specific position of not milling to place of comparison calculation of pre-preparation mill belt and theoretical contour;S4.addition position as corner hole cleaning position.The application can provide intuitive graphical parameter input interface, support real-time preview, and realize the intelligentization of process edge compensation and mill empty position generation, parameterization.

Description

Technical Field

[0001] This invention relates to the field of printed circuit board (PCB) design technology, and in particular to a parametrically driven intelligent PCB panelization and process compensation method and system. Background Technology

[0002] PCB manufacturing plants typically produce small boards in units of pcs (pieces), while PCB manufacturers themselves produce larger panels. This is simply a way for PCB manufacturers to improve efficiency. After PCB production, there are many processes, such as surface mount technology (SMT) and component insertion. Producing SMT and component insertion in units of pcs is extremely inefficient, leading to the production of small, continuous PCB sets. Downstream manufacturers, such as SMT manufacturers, often impose requirements on the shipped boards, such as adding positioning holes and mark points to assist in downstream production. Therefore, PCB manufacturers need to consider and add corresponding tooling points during production.

[0003] like Figures 1-2 As shown, there is a single board image and a set image. From the images, you can see that I need to add a process edge. In order to ensure the position of the irregular shape, we need to recess it a bit towards the process edge to control the shape. The following actions are required: traverse the largest point in the four positions of top, bottom, left and right, calculate the size, and place the panel; add positioning holes and make points (optical points) for the process edge; add milling gaps at the process edge; add corner clearances to make the shape more complete.

[0004] However, traditional methods require manual dimension calculation (consuming 40% of the time), and complex shapes require piece-by-piece adjustments (common rework rate of 15-20%). Fixed process edge widths cannot adapt to different production needs; tool hole positioning relies on experience (common positional deviation ±0.2mm); manual identification of shape boundaries is required, and automatic processing of irregularly shaped plates is not possible (efficiency reduced by more than 30%); manual identification of sharp corners less than 90 degrees is required (for forming areas with sharp corners less than 90 degrees, milling to such positions using a 1.6mm milling tool will not be able to reach the desired position; adding corner clearing holes aims to use smaller drilling tools to assist forming and make the sharp corner position closer to the customer's design value, such as...). Figure 3 As shown, the area surrounded by green lines is the molding area required by the customer, the white area is the cutting path of the milling cutter, the included angle not covered by the white area is the specific position where the milling is not in place, and the red area is the added corner clearing hole. However, through manual identification and manual addition of corner clearing holes, there are serious omissions in the identification and addition process. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a PCB intelligent panelization and process compensation method and system based on parameter-driven design. It can provide an intuitive graphical parameter input interface, support real-time preview, and realize intelligent and parameterized process edge compensation and router space generation.

[0006] The objective of this invention is achieved through the following technical solution: a parameter-driven intelligent PCB panelization and process compensation method, comprising the following steps:

[0007] S1. Determine the panel structure, input panel parameters through the graphical interface, and finally calculate the panel size in real time;

[0008] S2. Perform process edge compensation based on input panel parameters, and calculate the coordinate positioning of tool holes and optical points;

[0009] S3. Analyze the original PCB outline data and calculate the machining positions of the router slots;

[0010] S4. Compare and calculate the specific position of the pre-made gong strip and the theoretical shape to determine the position of the gong not in place, which will be used as the position for adding corner holes.

[0011] A parameter-driven intelligent PCB panelization and process compensation system includes:

[0012] The graphical parameter input module allows users to input panel parameters through a graphical interface.

[0013] The real-time calculation module is used to calculate the panel size in real time based on the input panel parameters;

[0014] The process edge compensation module performs process edge compensation based on the input panel parameters, and calculates the coordinate positioning of the tool hole and optical point;

[0015] The router clearance location calculation module is used to parse the original PCB outline data and calculate the router clearance locations.

[0016] The corner hole addition position calculation module is used to calculate the specific position of the pre-made gong strip and the theoretical shape, and use it as the corner hole addition position.

[0017] The beneficial effects of this invention are: it can provide an intuitive graphical parameter input interface, support real-time preview, and realize intelligent and parameterized process edge compensation and milling space generation. It can also calculate the specific position of the milling not in place by comparing the pre-made milling strip with the theoretical shape, and use it as the position for adding corner holes, which can automatically reduce manual intervention and improve the panelization efficiency to within 1 hour / project. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a single-board image;

[0019] Figure 2 This is a diagram illustrating the setting of an image;

[0020] Figure 3 A schematic diagram of a forming area with a sharp angle of less than 90 degrees;

[0021] Figure 4 This is a schematic diagram illustrating the principle of the present invention. Detailed Implementation

[0022] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings, but the scope of protection of the present invention is not limited to the following description.

[0023] like Figure 4 As shown, a parameter-driven intelligent PCB panelization and process compensation method includes the following steps:

[0024] S1. Determine the panel structure, input panel parameters through the graphical interface, and finally calculate the panel size in real time;

[0025] In step S1, the panel structure is composed of multiple single panels;

[0026] Each board consists of multiple core boards arranged from top to bottom. Each core board includes a substrate layer and copper foil on both sides of the substrate layer. Each copper foil is a circuit layer. In order to achieve the connection between the circuit layers, multiple drill holes are set perpendicular to the circuit layers. Positioning holes need to be added in the drilled layers.

[0027] Each board needs to have a solder mask layer added to both the top and bottom sides to protect the copper foil of the top and bottom layers of the board and prevent leakage. There are component solder joints on the circuit layers on the top and bottom sides of the board. Open windows are made for these solder joints to expose the copper foil so that it can be soldered.

[0028] In a panel composed of multiple single boards, positioning holes need to be added to facilitate panel positioning; and optical points need to be added as references; windows need to be opened at the positioning holes and optical points to prevent ink from covering the optical points or positioning holes.

[0029] Since single boards have different shapes, in order to prevent the single board outline from being lost, the lines of the single board outline are saved in the single board shape data.

[0030] Based on the shape data, when processing each single board with a cutting tool, due to the limitation of the tool size, not all contours can be processed. To prevent the cutting tool from damaging the board during processing, a corresponding routing layer is generated based on the shape data and the size of the cutting tool. The routing layer refers to the processing path using the cutting tool. Since the drilling tool is smaller than the cutting tool, corner holes are added to the contours that cannot be processed in the routing layer.

[0031] The panel parameters include:

[0032] The size of the single board in the x-direction, the number of single boards, and the spacing between single boards;

[0033] The dimensions of the single-board in the y-direction, the number of single-boards, and the spacing between single-boards;

[0034] Whether there are process edges in the x and y directions, and the size of the process edges, where the process edges in the x direction are the left and right process edges, and the process edges in the y direction are the top and bottom process edges.

[0035] The real-time calculation of panel dimensions includes:

[0036] X = (sizex × quantityx) + (spacingx × (quantityx-1)) + edge_left +edge_right

[0037] Where X represents the panel size in the x-direction, sizex represents the single board size in the x-direction, quantityx represents the number of single boards in the x-direction, spacingx represents the spacing between single boards in the x-direction, edge_lift represents the size of the left process edge, and edge_right represents the size of the right process edge.

[0038] Y = (sizey × quantityy) + (spacingy × (quantityy-1)) + edge_top +edge_bottom

[0039] Where Y represents the panel size in the y direction, sizey represents the single panel size in the y direction, quantityy represents the number of single panels in the y direction, spacingy represents the spacing between single panels in the y direction, edge_top represents the size of the top process edge, and edge_bottom represents the size of the bottom process edge.

[0040] Assume the panels are located in a known coordinate system.

[0041] The minimum and maximum coordinates of the puzzle pieces in the x and y directions are named set_x_min, set_y_min, set_x_max, and set_y_max, respectively.

[0042] The maximum and minimum coordinates of the board dimensions excluding the process edge are named SRxmin, SRymin, SRxmax, and SRymax, respectively.

[0043] S2. Perform process edge compensation based on input panel parameters, and calculate the coordinate positioning of tool holes and optical points;

[0044] Step S2 includes:

[0045] S201. Tool Hole Coordinate Calculation:

[0046] Based on the dimensions of the process edge input in the four directions (up, down, left, and right) on the GUI window, calculate the positioning holes that need to be added to the process edge. If it is a left or right process edge, the positions of the four positioning holes are as follows:

[0047] hole_x1 = set_x_min + left process edge size / 2, hole_y1 = set_y_min + 10mm

[0048] hole_x2 = set_x_min + left process edge size / 2, hole_y2 = set_y_max - 5mm

[0049] hole_x3 = set_x_max - right process edge size / 2, hole_y3 = set_y_min + 5mm

[0050] hole_x4 = set_x_max - right edge size / 2, hole_y4 = set_y_max - 5mm

[0051] The positions of the positioning holes on the upper and lower process edges are as follows:

[0052] hole_x5 = set_x_min + 10, hole_y5 = set_y_min + bottom edge size / 2

[0053] hole_x6=set_x_max-5, hole_y6=set_y_min+bottom process edge size / 2

[0054] hole_x7 = set_x_min + 5, hole_y7 = set_y_min + size of the top edge / 2

[0055] hole_x8 = set_x_max - 5, hole_y8 = set_y_min + size of the top edge / 2

[0056] Where hole_x1~hole_x8 represent the coordinates of the positioning hole in the x direction, and hole_y1~hole_y8 represent the coordinates of the positioning hole in the y direction;

[0057] Each positioning hole is a 2mm positioning hole centered on the calculated coordinates;

[0058] Solder resist needs to prevent ink from entering the hole. Therefore, an opening 0.3mm larger than the positioning hole needs to be added to the solder resist layer on both the top and bottom surfaces.

[0059] S202. Optical point positioning:

[0060] The coordinates of the optical point are as follows:

[0061] The optical point positions on the left and right sides of the process edge are as follows:

[0062] make_x1 = set_x_min + left process edge size / 2, make_y1 = set_y_min + 15mm

[0063] make_x2 = set_x_min + left process edge size / 2, make_y2 = set_y_max -10mm

[0064] make_x3 = set_x_max - right process edge size / 2, make_y3 = set_y_min + 10mm

[0065] make_x4 = set_x_max - right process edge size / 2, make_y4 = set_y_max - 10mm

[0066] The positions of the optical dots along the vertical process edge are as follows:

[0067] make_x5 = set_x_min + 15, make_y5 = set_y_min + bottom process edge size / 2

[0068] make_x6 = set_x_max - 10, make_y6 = set_y_min + bottom process edge size / 2

[0069] make_x7 = set_x_min + 10, make_y7 = set_y_min + size of top edge process edge / 2

[0070] make_x8 = set_x_max - 10, make_y8 = set_y_min + size of the top edge / 2;

[0071] Where make_x1~make_x8 represent the coordinates of the optical point in the x-direction, and make_y1~make_y8 represent the coordinates of the optical point in the y-direction;

[0072] The optical dot includes adding a 1.0mm copper dot centered on the optical dot coordinates on the outer circuit layer and making a 2.0mm opening in the solder mask layer. The purpose of adding the opening is to make the optical dot visible in the finished product.

[0073] S3. Analyze the original PCB outline data and calculate the machining positions of the router slots;

[0074] Step S3 includes:

[0075] S301. Extract all the outline lines from the puzzle pieces.

[0076] Each outline line includes: the coordinates of the line's start point, the coordinates of its end point, and its width;

[0077] Extract lines from all lines whose start or end x-coordinate is SRxmin; remove set_y_min and set_y_max; save the y-coordinates of lines that are not connected.

[0078] Extract lines from all lines whose start or end x-coordinate is SRxmax; remove set_y_min and set_y_max; save the y-coordinates of lines that are not connected.

[0079] Extract the lines with a start or end y-coordinate of SRymin from all lines; remove set_x_min and set_x_max; save the x-coordinates of lines that are not connected.

[0080] Extract lines from all lines whose start or end y-coordinate is SRymax; remove set_x_min and set_x_max; save the x-coordinates of lines that are not connected.

[0081] S302. A safe zone is generated through coordinate offset, using the following formula:

[0082] Calculate the offset position that needs to be calculated for each process edge:

[0083] For the left process edge: xx1 = SRxmin - min_rou_var;

[0084] For the right-hand process edge: xx1 = SRxmax + min_rou_var;

[0085] For the upper process edge: yy1 = SRymax + min_rou_var;

[0086] For the following process edge: yy1 = SRymin + min_rou_var;

[0087] Where xx1 represents the milling cutter compensation position in the x direction, SRxmin represents the minimum effective board position x value, and min_rou_var represents the minimum milling cutter compensation value;

[0088] S303. Automatically identify the process edge and panel spacing to generate closed polygonal slots:

[0089] (1) For the left process edge:

[0090] A1. First, extract two adjacent y-coordinates from the coordinates in step S301, and denote them as y1 and y2. Then, obtain four coordinates (SRxmin, y1), (xx1, y1), (SRxmin, y2), and (xx1, y2).

[0091] A2. Iterate through any two adjacent y-coordinates and repeat step A1.

[0092] (2) For the right-hand process edge:

[0093] B1. First, extract two adjacent y coordinates from the coordinates in step S301, and denote them as y10 and y20. Then, obtain four coordinates (SRxmax, y10), (xx1, y10), (SRxmax, y20), and (xx1, y20).

[0094] B2. Iterate through any two adjacent y-coordinates and repeat step B1.

[0095] (3) For the upper process edge:

[0096] C1. First, extract two adjacent x-coordinates from the coordinates in step S301, and denote them as x1 and x2. Then, obtain four coordinates (x1, SRymax), (x1, yy1), (x2, SRymax), (x2, yy1).

[0097] C2. Iterate through any two adjacent x-coordinates and repeat step C1.

[0098] (4) For the lower process edge:

[0099] D1. First, extract two adjacent x-coordinates from the coordinates in step S301, and denote them as x10 and x20. Then, obtain four coordinates (x10, SRymin), (x10, yy1), (x20, SRymin), (x20, yy1).

[0100] D2. Iterate through any two adjacent x-coordinates and repeat step D1.

[0101] The calculated offset position is used as the machining position for the gong.

[0102] S4. Compare and calculate the specific position of the pre-made gong strip and the theoretical shape to determine the position of the gong not in place, which will be used as the position for adding corner holes.

[0103] Step S4 includes:

[0104] S401. Based on the generated outline lines and the calculated gong space, pre-fabricate the gong strip;

[0105] S402. Calculate the specific position of each gong based on the comparison between the pre-made gong strip and the theoretical shape; where the theoretical shape is the outline and the calculated gong space is...

[0106] The location of the un-soldered area is used as the location for adding the corner clearing hole; in order to prevent ink from entering the corner clearing hole, an opening 0.3mm larger than the corner clearing hole is added to the solder mask layer.

[0107] Based on the information obtained from steps S1 to S4 above, the panel can be processed to achieve compensation for process edges and processing of milling gaps and corner holes.

[0108] A parameter-driven intelligent PCB panelization and process compensation system includes:

[0109] The graphical parameter input module allows users to input panel parameters through a graphical interface.

[0110] The real-time calculation module is used to calculate the panel size in real time based on the input panel parameters;

[0111] The process edge compensation module performs process edge compensation based on the input panel parameters, and calculates the coordinate positioning of the tool hole and optical point;

[0112] The router clearance location calculation module is used to parse the original PCB outline data and calculate the router clearance locations.

[0113] The corner hole addition position calculation module is used to calculate the specific position of the pre-made gong strip and the theoretical shape, and use it as the corner hole addition position.

[0114] The above description represents preferred embodiments of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technical or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A PCB intelligent panelization and process compensation method based on parameter-driven design, characterized in that: Includes the following steps: S1. Determine the panel structure, input panel parameters through the graphical interface, and finally calculate the panel size in real time; S2. Perform process edge compensation based on input panel parameters, and calculate the coordinate positioning of tool holes and optical points; Step S2 includes: S201. Tool Hole Coordinate Calculation: Based on the dimensions of the process edge input in the four directions (up, down, left, and right) on the GUI window, calculate the positioning holes that need to be added to the process edge. If it is a left or right process edge, the positions of the four positioning holes are as follows: hole_x1 = set_x_min + left process edge size / 2, hole_y1 = set_y_min + 10mm hole_x2 = set_x_min + left process edge size / 2, hole_y2 = set_y_max - 5mm hole_x3 = set_x_max - right process edge size / 2, hole_y3 = set_y_min + 5mm hole_x4 = set_x_max - right edge size / 2, hole_y4 = set_y_max - 5mm The positions of the positioning holes on the upper and lower process edges are as follows: hole_x5 = set_x_min + 10, hole_y5 = set_y_min + bottom edge size / 2 hole_x6=set_x_max-5, hole_y6=set_y_min+bottom process edge size / 2 hole_x7 = set_x_min + 5, hole_y7 = set_y_min + size of the top edge / 2 hole_x8 = set_x_max - 5, hole_y8 = set_y_min + size of the top edge / 2 Where hole_x1~hole_x8 represent the coordinates of the positioning hole in the x direction, and hole_y1~hole_y8 represent the coordinates of the positioning hole in the y direction; Each positioning hole is a 2mm positioning hole centered on the calculated coordinates; Solder resist needs to prevent ink from entering the hole. Therefore, an opening 0.3mm larger than the positioning hole needs to be added to the solder resist layer on both the top and bottom surfaces. S202. Optical point positioning: The coordinates of the optical point are as follows: The optical point positions on the left and right sides of the process edge are as follows: make_x1 = set_x_min + left process edge size / 2, make_y1 = set_y_min + 15mm make_x2 = set_x_min + left process edge size / 2, make_y2 = set_y_max - 10mm make_x3 = set_x_max - right process edge size / 2, make_y3 = set_y_min + 10mm make_x4 = set_x_max - right process edge size / 2, make_y4 = set_y_max - 10mm The positions of the optical dots along the vertical process edge are as follows: make_x5 = set_x_min + 15, make_y5 = set_y_min + bottom process edge size / 2 make_x6 = set_x_max - 10, make_y6 = set_y_min + bottom process edge size / 2 make_x7 = set_x_min + 10, make_y7 = set_y_min + size of top edge process edge / 2 make_x8 = set_x_max - 10, make_y8 = set_y_min + size of the top edge / 2; Where make_x1~make_x8 represent the coordinates of the optical point in the x-direction, and make_y1~make_y8 represent the coordinates of the optical point in the y-direction; Centered on the optical point coordinates, a 1.0mm copper point is added as a solder joint on the outer circuit layer, and a 2.0mm window is made in the solder mask layer. The purpose of adding the window is to make the optical point visible in the finished product. S3. Analyze the original PCB outline data and calculate the machining positions of the router slots; S4. Compare and calculate the specific position of the pre-made gong strip and the theoretical shape to determine the position of the gong not in place, which will be used as the position for adding corner holes.

2. The PCB intelligent panelization and process compensation method based on parameter-driven design according to claim 1, characterized in that: In step S1, the panel structure is composed of multiple single panels; Each board consists of multiple core boards arranged from top to bottom. Each core board includes a substrate layer and copper foil on both sides of the substrate layer. Each copper foil is a circuit layer. In order to achieve the connection between the circuit layers, multiple drill holes are set perpendicular to the circuit layers. Each board needs to have a solder mask layer added to both the top and bottom sides to protect the copper foil of the top and bottom layers of the board and prevent leakage. There are component solder joints on the circuit layers on the top and bottom sides of the board. Open windows are made for these solder joints to expose the copper foil so that it can be soldered. In a panel composed of multiple single boards, positioning holes need to be added to facilitate panel positioning; and optical points need to be added as references for solder joints; windows need to be opened at the positioning holes and optical points to prevent ink from covering the optical points or positioning holes. Since single boards have different shapes, in order to prevent the loss of single board outline, the lines of the single board outline are saved in the PCB outline data of the single board. Based on the shape data, when processing each single board with a cutting tool, due to the limitation of the tool size, not all contours can be processed. To prevent the cutting tool from damaging the board during processing, a corresponding routing layer is generated based on the shape data and the size of the cutting tool. The routing layer refers to the processing path using the cutting tool. Since the drilling tool is smaller than the cutting tool, corner holes are added to the contours that cannot be processed in the routing layer. The panel parameters include: The size of the single board in the x-direction, the number of single boards, and the spacing between single boards; The dimensions of the single-board in the y-direction, the number of single-boards, and the spacing between single-boards; Whether there are process edges in the x and y directions, and the size of the process edges, where the process edges in the x direction are the left and right process edges, and the process edges in the y direction are the top and bottom process edges.

3. The PCB intelligent panelization and process compensation method based on parameter-driven design according to claim 1, characterized in that: The real-time calculation of panel dimensions includes: ； Where X represents the panel size in the x-direction, sizex represents the single panel size in the x-direction, quantityx represents the number of single panels in the x-direction, spacingx represents the spacing between single panels in the x-direction, edge_left represents the size of the left process edge, and edge_right represents the size of the right process edge. ； Where Y represents the panel size in the y direction, sizey represents the single panel size in the y direction, quantityy represents the number of single panels in the y direction, spacingy represents the spacing between single panels in the y direction, edge_top represents the size of the top process edge, and edge_bottom represents the size of the bottom process edge. Assume the panels are located in a known coordinate system. The minimum and maximum coordinates of the puzzle pieces in the x and y directions are named set_x_min, set_y_min, set_x_max, and set_y_max, respectively. The maximum and minimum coordinates of the board dimensions excluding the process edge are named SRxmin, SRymin, SRxmax, and SRymax, respectively.

4. The PCB intelligent panelization and process compensation method based on parameter-driven design according to claim 1, characterized in that: Step S3 includes: S301. Extract all the outline lines from the puzzle pieces. Each outline line includes: the coordinates of the line's start point, the coordinates of its end point, and its width; Extract lines from all lines whose start or end x-coordinate is SRxmin; remove set_y_min and set_y_max; save the y-coordinates of lines that are not connected. Extract lines from all lines whose start or end x-coordinate is SRxmax; remove set_y_min and set_y_max; save the y-coordinates of lines that are not connected. Extract the lines with a start or end y-coordinate of SRymin from all lines; remove set_x_min and set_x_max; save the x-coordinates of lines that are not connected. Extract lines from all lines whose start or end y-coordinate is SRymax; remove set_x_min and set_x_max; save the x-coordinates of lines that are not connected. S302. A safe zone is generated through coordinate offset, using the following formula: Calculate the offset position that needs to be calculated for each process edge: For the left-hand process edge: ; For the right-hand process edge: xx1 = SRxmax + min_rou_var; For the upper process edge: yy1 = SRymax + min_rou_var; For the following process edge: yy1 = SRymin + min_rou_var; Where xx1 represents the milling cutter compensation position in the x direction, SRxmin represents the minimum effective board position x value, and min_rou_var represents the minimum milling cutter compensation value; S303. Automatically identify the process edge and panel spacing to generate closed polygonal slots: (1) For the left process edge: A1. First, extract two adjacent y-coordinates from the coordinates in step S301, and denote them as y1 and y2. Then, obtain four coordinates (SRxmin, y1), (xx1, y1), (SRxmin, y2), and (xx1, y2). A2. Iterate through any two adjacent y-coordinates and repeat step A1. (2) For the right-hand process edge: B1. First, extract two adjacent y coordinates from the coordinates in step S301, and denote them as y10 and y20. Then, obtain four coordinates (SRxmax, y10), (xx1, y10), (SRxmax, y20), and (xx1, y20). B2. Iterate through any two adjacent y-coordinates and repeat step B1. (3) For the upper process edge: C1. First, extract two adjacent x-coordinates from the coordinates in step S301, and denote them as x1 and x2. Then, obtain four coordinates (x1, SRymax), (x1, yy1), (x2, SRymax), (x2, yy1). C2. Iterate through any two adjacent x-coordinates and repeat step C1. (4) For the lower process edge: D1. First, extract two adjacent x-coordinates from the coordinates in step S301, and denote them as x10 and x20. Then, obtain four coordinates (x10, SRymin), (x10, yy1), (x20, SRymin), (x20, yy1). D2. Iterate through any two adjacent x-coordinates and repeat step D1. The calculated offset position is used as the machining position for the gong.

5. The PCB intelligent panelization and process compensation method based on parameter-driven design according to claim 1, characterized in that: Step S4 includes: S401. Based on the generated outline lines and the calculated gong space, pre-fabricate the gong strip; S402. Calculate the specific position of each gong based on the comparison between the pre-made gong strip and the theoretical shape; where the theoretical shape is the outline and the calculated gong empty space is used. S403. The location of the un-soldered corner hole is used as the location for adding the corner hole; in order to prevent ink from entering the corner hole, an opening 0.3mm larger than the corner hole is added to the solder mask layer.

6. A PCB intelligent panelization and process compensation system based on parameter-driven design, employing the method described in any one of claims 1 to 5, characterized in that: include: The graphical parameter input module allows users to input panel parameters through a graphical interface. The real-time calculation module is used to calculate the panel size in real time based on the input panel parameters; The process edge compensation module performs process edge compensation based on the input panel parameters, and calculates the coordinate positioning of the tool hole and optical point; The router clearance location calculation module is used to parse the original PCB outline data and calculate the router clearance locations. The corner hole addition position calculation module is used to calculate the specific position of the pre-made gong strip and the theoretical shape, and use it as the corner hole addition position.

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