An address mapping method of a memory chip and a memory chip

Abstract

The application provides an address mapping method of a storage chip and the storage chip. The method comprises the following steps: obtaining original addresses of a plurality of storage units; determining target distances from each storage unit to a driver; dividing the original addresses into a plurality of address regions according to the target distances, each address region having region information; sorting the plurality of address regions according to the region information, and reassigning the original addresses in each sorted address region to obtain first target addresses and an address mapping relationship, the address mapping relationship representing a mapping relationship between the first target addresses and the original addresses, the first target addresses in each address region being continuous, and the first target addresses in two adjacent address regions being continuous. Based on the above technical scheme, the address test can be more conveniently completed; the first target addresses in the same address region are continuous, no additional mapping logic needs to be developed for a storage controller, and the use complexity of a user is reduced.

Description

Technical Field

[0001] This application relates to the field of phase-change memory technology, and in particular to an address mapping method for a memory chip and a memory chip. Background Technology

[0002] The memory chip internally calculates the address of the memory cell sent by the memory controller, determines the target distance from the driver, and dynamically adjusts the voltage or current based on the target distance. As the memory cell addresses increase sequentially, adjacent addresses are grouped into the same "location," thus obtaining a location distribution map within the memory chip.

[0003] When the address sent by the storage controller is fixed, different physical stacking methods will result in different distances from the target to the driver, and thus different location distribution maps of the entire storage chip. When there are many location divisions, the location distribution map will be irregular and the addresses of two adjacent "locations" will be discontinuous, which is not conducive to testers quickly carrying out address testing. Summary of the Invention

[0004] This application proposes an address mapping method and a memory chip to solve the technical problem of non-contiguous addresses between two adjacent locations within a memory chip.

[0005] To achieve the above objective, according to a first aspect of this application, an address mapping method for a memory chip is provided. The memory chip includes multiple stacked memory arrays and a driver electrically connected to the memory arrays. Each memory array includes multiple memory cells. The method includes:

[0006] Obtain the original addresses of the multiple storage units;

[0007] Determine the target distance from each of the storage cells to the drive;

[0008] Based on the target distance, the original address is divided into multiple address regions, and each address region has region information;

[0009] Based on the region information, the multiple address regions are sorted, and the original addresses in each sorted address region are reassigned to obtain a first target address and an address mapping relationship. The address mapping relationship represents the mapping relationship between the first target address and the original address. The first target addresses in each address region are continuous, and the first target addresses in two adjacent address regions are continuous.

[0010] In some embodiments, after obtaining the first target address and the address mapping relationship, the method further includes:

[0011] Receive the first address to be processed, the first instruction, and the second instruction;

[0012] When the second instruction is a mapping instruction, the second address to be processed corresponding to the first address to be processed is determined according to the first address to be processed and the address mapping relationship;

[0013] Execute the first instruction to process the storage unit corresponding to the second address to be processed.

[0014] In some embodiments, the first instruction includes any one of a set operation, a reset operation, and a read operation.

[0015] In some embodiments, after determining the second address to be processed corresponding to the first address to be processed based on the first address to be processed and the address mapping relationship, the method further includes:

[0016] Perform location compensation on the second address to be processed;

[0017] Execute the first instruction to process the storage unit corresponding to the second address to be processed after position compensation.

[0018] In some embodiments, the method further includes: if the second instruction is a rejection mapping instruction, executing the first instruction to process the storage unit corresponding to the first address to be processed.

[0019] In some embodiments, the driver includes a word line driver and a bit line driver;

[0020] Determining the target distance from the plurality of said storage cells to the drive includes:

[0021] Determine a first distance from each of the memory cells to the word line driver;

[0022] Determine a second distance from each of the memory cells to the bit line driver;

[0023] The target distance is determined based on the first distance and the second distance.

[0024] In some embodiments, the original address is divided into multiple address regions based on the target distance, including:

[0025] Determine the range of values ​​for the target distance;

[0026] The range of values ​​is divided into multiple sub-intervals, and the original address included in each sub-interval is determined.

[0027] Multiple original addresses belonging to the same sub-interval are divided into an address region; and the region information of the address region is obtained based on the interval attribute value of the sub-interval.

[0028] According to a second aspect of this application, a memory chip is provided, comprising:

[0029] Multiple stacked storage arrays, each storage array comprising multiple storage cells;

[0030] A driver is configured to drive the storage array;

[0031] The address mapping module is configured as follows:

[0032] Obtain the original addresses of the multiple storage units;

[0033] Determine the target distance from each of the storage cells to the drive;

[0034] Based on the target distance, the original address is divided into multiple address regions, and each address region has region information;

[0035] Based on the region information, the multiple address regions are sorted, and the original addresses in each sorted address region are reassigned to obtain a first target address and an address mapping relationship. The address mapping relationship represents the mapping relationship between the first target address and the original address. The first target addresses in each address region are continuous, and the first target addresses in two adjacent address regions are continuous.

[0036] In some embodiments, the memory chip further includes:

[0037] The storage controller, electrically connected to the address mapping module, is configured to receive a first address to be processed and a first instruction.

[0038] The judgment module is electrically connected to the address mapping module, the processing module, and the storage controller, and is configured to receive a second instruction.

[0039] The address mapping module is further configured to: when the second instruction is a mapping instruction, determine the second address to be processed corresponding to the first address to be processed based on the first address to be processed and the address mapping relationship;

[0040] The memory chip also includes a processing module, which is electrically connected to the address mapping module and the memory array, and is configured to execute the first instruction to process the memory cell corresponding to the second address to be processed.

[0041] In some embodiments, the processing module is further configured to execute the first instruction and process the storage unit corresponding to the first address to be processed when the second instruction is a rejection mapping instruction.

[0042] The technical solution of this application can achieve the following beneficial effects: The embodiments of this application provide an address mapping method for a memory chip, which can obtain continuously distributed address regions. The first target address in each address region is continuous, and the first target addresses in two adjacent address regions are continuous, thereby making it easier to complete address testing. For the memory controller, the first target addresses in the same address region are continuous, so the memory controller does not need to develop additional mapping logic, reducing the logic complexity of the memory controller and the complexity of user operation.

[0043] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0046] Figure 1 A schematic diagram of the structure of a storage array provided in one embodiment;

[0047] Figure 2 A flowchart illustrating an address mapping method for a memory chip provided in an embodiment of this application;

[0048] Figure 3 A flowchart illustrating an address mapping method for a memory chip provided in an embodiment of this application;

[0049] Figure 4 A flowchart illustrating an address mapping method for a memory chip provided in an embodiment of this application;

[0050] Figure 5 This is a schematic diagram of the structure of a memory chip provided in an embodiment of this application;

[0051] Figure 6 This application provides a schematic diagram of an address region before mapping.

[0052] Figure 7This is a schematic diagram of a mapped address region provided in an embodiment of this application. Detailed Implementation

[0053] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0054] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0055] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0056] The use of "applies to" or "configured to" in this application implies open and inclusive language, which does not exclude the applicability to or configuration to devices performing additional tasks or steps. Additionally, the use of "based on" implies openness and inclusivity, because processes, steps, calculations, or other actions "based on" one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0057] In this application, the term "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use this application. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be made without using these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0058] See Figure 1 As shown, the memory array consists of multiple memory cells arranged in an array. The memory array and the driver are electrically connected. The driver includes word line driver and bit line driver.

[0059] Multiple array-arranged memory cells are electrically connected to bit line drivers via multiple bit lines (first bit line BL1, second bit line BL2, third bit line BL3, and fourth bit line BL4). These memory cells are also electrically connected to word line drivers via multiple word lines (first word line WL1, second word line WL2, third word line WL3, and fourth word line WL4). The drivers provide voltage and current to the memory cells. The distance from each memory cell to the driver is called the target distance, which is determined by the distance from the memory cell to the word line driver and the distance from the memory cell to the bit line driver.

[0060] As memory chips increase in size and capacity, existing memory chips often employ stacking or even zigzag arrangements of memory arrays to form a single chip, due to factors such as capacity, density, and volume. A memory chip also includes a memory controller. Based on these different physical arrangement methods, the location of the drivers varies, resulting in different target distances from memory cells to the drivers. To perform better operations on different memory cells (e.g., set, reset, read operations), it is typically necessary to dynamically adjust the voltage or current provided by the drivers based on the target distance.

[0061] The memory chip internally calculates the address of the memory cell sent by the memory controller, determines the target distance to the driver, and dynamically adjusts the voltage or current based on the target distance. As the address sequence of the memory cells increases, adjacent addresses are grouped into the same "location," thus obtaining a location distribution map within the memory chip. Both memory chip manufacturers' test personnel and memory controller manufacturers can use this location distribution map for memory chip testing and board-level debugging.

[0062] When the address sent by the storage controller (in row and column address format) is fixed, different physical stacking methods will result in different distances from the target to the driver, and consequently, different location distribution maps of the entire storage chip. When there are many location divisions, the location distribution map becomes irregular, and the addresses of two adjacent "locations" are not contiguous. For test engineers, testing compensation at the same location becomes cumbersome, and for the storage controller, accessing the address of a specific location also requires complex address calculations before providing the result to the storage chip. This increases the complexity of the storage controller and reduces the operating efficiency of the storage controller and even the entire storage system.

[0063] To address the technical problem that the addresses of two adjacent "locations" are not contiguous, this application proposes an address mapping method and a memory chip to overcome the above-mentioned problem.

[0064] On one hand, embodiments of this application provide an address mapping method for a memory chip, which can be executed by the memory chip. The memory chip includes multiple stacked memory arrays and drivers electrically connected to the memory arrays, each memory array including multiple memory cells. For example... Figure 2 As shown, the address mapping method for memory chips includes the following steps:

[0065] S101: Obtain the original addresses of multiple memory units;

[0066] S102: Determine the target distance from each storage cell to the drive;

[0067] S103: Based on the target distance, the original address is divided into multiple address regions, and each address region has region information;

[0068] S104: Based on the region information, sort the multiple address regions and reassign the original addresses in each sorted address region to obtain the first target address and the address mapping relationship. The address mapping relationship represents the mapping relationship between the first target address and the original address. The first target address in each address region is continuous, and the first target addresses in two adjacent address regions are continuous.

[0069] The following is a detailed description of an address mapping method for a memory chip provided in an embodiment of this application.

[0070] S101: Obtain the original addresses of multiple memory units.

[0071] In some embodiments, each storage unit has a unique original address. In this embodiment, there are a total of 896 storage units, and the original addresses of the 896 storage units are 0, 1, 2, 3, ..., 895.

[0072] S102: Determine the target distance from each storage cell to the drive.

[0073] In some embodiments, the driver includes a word line driver and a bit line driver.

[0074] Determine the target distances from multiple storage units to the drive, specifically including:

[0075] S1: Determine the first distance from each memory cell to the word line driver;

[0076] S2: Determine the second distance from each memory cell to the bit line driver;

[0077] S2: Determine the target distance based on the first distance and the second distance.

[0078] In some embodiments, corresponding weights can be set for the first distance and the second distance, and the first distance and the second distance can be weighted and summed to obtain the target distance.

[0079] In some embodiments, the first distance and the second distance can be summed to obtain the target distance.

[0080] Based on the above embodiments, the target distance for each storage unit is calculated.

[0081] S103: Based on the target distance, the original address is divided into multiple address regions, and each address region has region information.

[0082] In some embodiments, the original address is divided into multiple address regions based on the target distance, specifically including:

[0083] S1: Determine the range of values ​​for the target distance;

[0084] S2: Divide the range of values ​​into multiple sub-intervals and determine the original addresses included in each sub-interval;

[0085] S3: Divide multiple original addresses in the same sub-interval into an address region; and obtain the region information of the address region based on the interval attribute value of the sub-interval.

[0086] In some embodiments, the target region is set to the interval [A, B]. The interval [A, B] is then divided into multiple sub-intervals at equal intervals. This embodiment takes the division into 3 sub-intervals as an example. The 3 sub-intervals are [A, (2×A+B) / 3], ((2×A+B) / 3, (2×B+A) / 3], and ((2×B+A) / 3, B]. The original addresses included in each sub-interval are determined. Multiple original addresses in [A, (2×A+B) / 3] are divided into one address region, multiple original addresses in ((2×A+B) / 3, (2×B+A) / 3] are divided into one address region, and multiple original addresses in ((2×B+A) / 3, B] are divided into one address region, resulting in 3 different address regions.

[0087] Of course, it should be noted that the value range can also be divided into multiple sub-intervals using unequal intervals, in which case the length of each sub-interval will be different. This application does not limit the method of dividing the sub-intervals.

[0088] In some embodiments, the address region has region information that indicates how close the address region is to the driver.

[0089] Furthermore, the interval attribute values ​​of the sub-interval include: the left endpoint value of the interval, the right endpoint value of the interval, and the midpoint value of the interval.

[0090] The left endpoints of these three sub-intervals can be selected as interval attribute values, namely: A, (2×A+B) / 3, (2×B+A) / 3. A, (2×A+B) / 3, (2×B+A) / 3 are sorted in ascending order, and the result is A, (2×A+B) / 3, (2×B+A) / 3. The sequence number of the ascending order of the interval attribute values ​​is determined as the area information corresponding to the area address. If the ascending sequence number of A is 1, then the area information of the address region corresponding to [A, (2×A+B) / 3] is equal to 1 (its corresponding address region is represented as address region 1). If the ascending sequence number of (2×A+B) / 3 is 2, then the area information of the address region corresponding to ((2×A+B) / 3, (2×B+A) / 3] is equal to 2 (its corresponding address region is represented as address region 2). If the ascending sequence number of (2×B+A) / 3 is 3, then the area information of the address region corresponding to ((2×B+A) / 3, B] is equal to 3 (its corresponding address region is represented as address region 3).

[0091] Address region 1 represents the region closest to the drive, address region 3 represents the region farthest from the drive, and address region 2 is located between address region 1 and address region 3.

[0092] In some embodiments, consecutive original addresses located in the same address region are grouped.

[0093] See Figure 3 As shown, memory locations with original addresses 0-127 belong to address region 1, memory locations with original addresses 128-255 belong to address region 2, memory locations with original addresses 256-511 belong to address region 3, memory locations with original addresses 512-639 belong to address region 2, memory locations with original addresses 640-767 belong to address region 1, and memory locations with original addresses 768-895 belong to address region 3.

[0094] S104: Based on the region information, sort the multiple address regions and reassign the original addresses in each sorted address region to obtain the first target address and the address mapping relationship. The address mapping relationship represents the mapping relationship between the first target address and the original address. The first target address in each address region is continuous, and the first target addresses in two adjacent address regions are continuous.

[0095] In some embodiments, multiple address regions are sorted in ascending order based on region information, see [reference]. Figure 3As shown, the address regions are sorted in ascending order according to region address 1, region address 2, and region address 3 (i.e., sorted from closest to furthest from the target location of the driver), resulting in the sorted address regions. If two consecutive sets of original addresses belong to the same address region, for example, memory cells with original addresses equal to 0-127 belong to address region 1, and memory cells with original addresses equal to 640-767 also belong to address region 1, then the endpoint values ​​in these two sets of original addresses are compared. Since the left endpoint value 0 in the first set of original addresses is less than the left endpoint value 640 in the second set of original addresses, address region 1 corresponding to memory cells with original addresses equal to 0-127 is placed one position before address region 1 corresponding to memory cells with original addresses equal to 640-767. Similarly, it can be determined that address region 2 corresponding to the memory cell with original address equal to 128-255 is placed before address region 2 corresponding to the memory cell with original address equal to 512-639, and address region 3 corresponding to the memory cell with original address equal to 256-511 is placed before address region 3 corresponding to the memory cell with original address equal to 768-895.

[0096] See Figure 3 As shown, the original addresses in each sorted address range are reassigned: 0-127 is reassigned to 0-127, 640-767 to 128-255, 128-255 to 256-511, 512-639 to 512-639, 256-511 to 640-767, and 768-895 to 768-895. The reassigned result is used as the first target address. Based on this, the mapping process is completed, and the mapping relationship between the original address before reassignment and the new address after reassignment (the first target address) is saved as the address mapping relationship.

[0097] See Figure 4 As shown, after reassignment (mapping), the first target address and the address mapping relationship are obtained. The address mapping relationship represents the mapping relationship between the first target address and the original address. The first target address in each address region is continuous, and the first target address in two adjacent address regions is continuous.

[0098] In some embodiments, Figure 6This represents the 13 address regions before reassignment. The region information for these 13 address regions is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and 12. The horizontal coordinate (row address) range of these 13 address regions is 0-8192, and the vertical coordinate (column address) range is also 0-8192. The percentage of the address region corresponding to region information 0 is 0.00%, the percentage corresponding to region information 1 is 3.14%, the percentage corresponding to region information 2 is 12.52%, the percentage corresponding to region information 3 is 15.61%, and the percentage corresponding to region information 4 is... The percentage of the domain is 9.36%. The address region corresponding to region information 5 accounts for 9.39% of all address regions. The address region corresponding to region information 6 accounts for 9.36% of all address regions. The address region corresponding to region information 7 accounts for 9.39% of all address regions. The address region corresponding to region information 8 accounts for 15.64% of all address regions. The address region corresponding to region information 9 accounts for 12.48% of all address regions. The address region corresponding to region information 10 accounts for 3.11% of all address regions. The address region corresponding to region information 11 accounts for 0.00% of all address regions. The address region corresponding to region information 12 accounts for 0.00% of all address regions. Figure 6 The distribution of address regions is chaotic and irregular. Figure 7 express Figure 6 The corresponding 13 address regions after mapping. Figure 7In the given information, the address region corresponding to region information 0 accounts for 0.00% of all address regions; the address region corresponding to region information 1 accounts for 3.14% of all address regions; the address region corresponding to region information 2 accounts for 12.52% of all address regions; the address region corresponding to region information 3 accounts for 15.61% of all address regions; the address region corresponding to region information 4 accounts for 9.36% of all address regions; the address region corresponding to region information 5 accounts for 9.39% of all address regions; the address region corresponding to region information 6 accounts for 9.36% of all address regions; the address region corresponding to region information 7 accounts for 9.39% of all address regions; the address region corresponding to region information 8 accounts for 15.64% of all address regions; the address region corresponding to region information 9 accounts for 12.48% of all address regions; the address region corresponding to region information 10 accounts for 3.11% of all address regions; the address region corresponding to region information 11 accounts for 0.00% of all address regions; and the address region corresponding to region information 12 accounts for 0.00% of all address regions. Figure 7 The distribution of the address regions exhibits address continuity. Test engineers and memory controllers do not need to concern themselves with the mapping logic inside the memory chip. For users, the first target address they see is continuous and regular.

[0099] Based on the above embodiments, continuously distributed address regions can be obtained, where the first target address in each address region is continuous, and the first target addresses in two adjacent address regions are also continuous, making address testing more convenient. For the storage controller, since the first target addresses in the same address region are continuous, the storage controller does not need to develop additional mapping logic, reducing the logic complexity of the storage controller and the complexity of user operation. It should be noted that the address mapping relationship in the embodiments of this application is stored inside the storage chip.

[0100] In some embodiments, after obtaining the first target address, the original address before mapping can also be retained, and the user's choice can be used to determine whether to process the original address before mapping or the address after mapping.

[0101] In some embodiments, after obtaining the first target address and the address mapping relationship, the method further includes:

[0102] S1: Receive the first address to be processed, the first instruction, and the second instruction;

[0103] S2: If the second instruction is a mapping instruction, determine the second address to be processed corresponding to the first address to be processed based on the first address to be processed and the address mapping relationship;

[0104] S3: Execute the first instruction and process the memory unit corresponding to the second address to be processed.

[0105] In some embodiments, the first instruction includes any one of a set operation, a reset operation, and a read operation.

[0106] The set operation changes the phase change material of the memory cell from an amorphous state (high resistance) to a crystalline state (low resistance), and the corresponding memory logic changes from 0 to 1.

[0107] The reset operation changes the phase change material of the memory cell from a crystalline state (low resistance) to an amorphous state (high resistance), and the corresponding memory logic changes from 1 to 0.

[0108] The read operation determines whether the stored value is "0" or "1" by measuring the resistance value of the current storage cell without changing the state of the phase change material.

[0109] In some embodiments, see Figure 4 As shown, the system accepts a first address to be processed, a first instruction, and a second instruction from the user. For example, if the first address to be processed is "256-511", and the second instruction is a mapping instruction, the system determines the original address that has a mapping relationship with the first address to be processed, based on the address mapping relationship, and uses this as the second address to be processed. In the case of the first address to be processed being "256-511", the second address to be processed is "128-255". Finally, the first instruction is executed to process the memory unit corresponding to the second address to be processed. The user perceives the processed address as "256-511", but in reality, the memory unit corresponding to "128-255" is actually processed.

[0110] In some embodiments, after determining the second address to be processed corresponding to the first address to be processed based on the first address to be processed and the address mapping relationship, the method further includes:

[0111] S1: Perform location compensation on the second address to be processed;

[0112] S2: Execute the first instruction to process the memory unit corresponding to the second address to be processed after position compensation.

[0113] In some embodiments, within a memory array, an "address" is simply a logical row / column number as seen from the memory controller. When actually implemented within the memory chip, due to factors such as decoder threshold drift caused by process-temperature-aging and differences in word / bit line RC delays, the "optimal pulse parameters" corresponding to the same "address" will change at different times, temperatures, and wear stages. "Location compensation" maps these changes to fine-tuning of the "address," ensuring that subsequent operations remain centered within the process window, reducing bit error rate or write latency. Location compensation methods include: Static Lookup Table (SLT), Temperature-Voltage Two-Parameter Linear Interpolation Compensation (LIC), Adaptive Closed-Loop (ACL), Endurance-Aware Compensation (EAC), and Machine Learning-Based Compensation (MLC).

[0114] In some embodiments, after receiving the first address to be processed, the first instruction, and the second instruction, if the second instruction is a map rejection instruction, the first instruction is executed to process the storage unit corresponding to the first address to be processed. If the second instruction is a map rejection instruction, it means that the user does not need to use the address mapping relationship for mapping, and in this case, the storage unit corresponding to the first address to be processed is processed directly.

[0115] In some embodiments, after receiving the first address to be processed, the first instruction, and the second instruction, if the second instruction is a rejection mapping instruction, the first address to be processed can be positionally compensated, the first instruction can be executed, and the storage unit corresponding to the positionally compensated first address to be processed can be processed.

[0116] See Figure 5 As shown, this application embodiment provides a memory chip, including:

[0117] Multiple stacked storage arrays 80, each storage array 80 comprising multiple storage cells;

[0118] Driver 20 is configured to drive memory array 80;

[0119] Address mapping module 30 is configured as follows:

[0120] Obtain the original addresses of multiple storage units;

[0121] Determine the target distance from each storage unit to drive 20;

[0122] Based on the target distance, the original address is divided into multiple address regions, and each address region has region information;

[0123] Based on the region information, multiple address regions are sorted, and the original addresses in each sorted address region are reassigned to obtain the first target address and the address mapping relationship. The address mapping relationship represents the mapping relationship between the first target address and the original address. The first target address in each address region is continuous, and the first target addresses in two adjacent address regions are continuous.

[0124] In some embodiments, see Figure 5 As shown, the memory chip 70 also includes:

[0125] The storage controller 40 is electrically connected to the address mapping module 30 and is configured to receive a first address to be processed and a first instruction.

[0126] The judgment module 50 is electrically connected to the address mapping module 30, the processing module 60, and the storage controller 40 respectively, and is configured to receive the second instruction.

[0127] The address mapping module 30 is also configured to: when the second instruction is a mapping instruction, determine the second address to be processed corresponding to the first address to be processed based on the first address to be processed and the address mapping relationship;

[0128] The memory chip 70 also includes a processing module 60, which is electrically connected to the address mapping module 30 and the memory array 80, and is configured to execute a first instruction to process the memory cell corresponding to the second address to be processed.

[0129] In some embodiments, the processing module 60 is further configured to execute the first instruction and process the storage unit corresponding to the first address to be processed when the second instruction is a rejection mapping instruction.

[0130] In some embodiments, the determination module 50 is a mode register, through which the user can choose whether to map the first address to be processed to the second target address through the address mapping relationship.

[0131] In some embodiments, the processing module 60 includes a content-addressable memory (CAM), which can receive a second address to be processed (or a first address to be processed) and search the memory chip 70 to find the memory cell corresponding to the second address to be processed (or the first address to be processed).

[0132] In some embodiments, the memory chip 70 further includes a position compensation module, which is configured to perform position compensation on the second address to be processed when the second instruction is a mapping instruction, and to perform position compensation on the first address to be processed when the second instruction is a rejection mapping instruction.

[0133] Accordingly, the processing module 60 is configured to execute the first instruction and process the storage unit corresponding to the second address to be processed after position compensation when the second instruction is a mapping instruction; and to execute the first instruction and process the storage unit corresponding to the first address to be processed after position compensation when the second instruction is a rejection mapping instruction.

[0134] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0135] The above provides a detailed description of the address mapping method and memory chip provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An address mapping method for a memory chip, characterized in that, The memory chip includes multiple stacked memory arrays and a driver electrically connected to the memory arrays, each memory array including multiple memory cells, and the method includes: Obtain the original addresses of the multiple storage units; Determine the target distance from each of the storage cells to the drive; Based on the target distance, the original address is divided into multiple address regions, and each address region has region information; Based on the region information, the multiple address regions are sorted, and the original addresses in each sorted address region are reassigned to obtain a first target address and an address mapping relationship. The address mapping relationship represents the mapping relationship between the first target address and the original address. The first target addresses in each address region are continuous, and the first target addresses in two adjacent address regions are continuous.

2. The method according to claim 1, characterized in that, After obtaining the first target address and the address mapping relationship, the method further includes: Receive the first address to be processed, the first instruction, and the second instruction; When the second instruction is a mapping instruction, the second address to be processed corresponding to the first address to be processed is determined according to the first address to be processed and the address mapping relationship; Execute the first instruction to process the storage unit corresponding to the second address to be processed.

3. The method according to claim 2, characterized in that, The first instruction includes any one of a set operation, a reset operation, or a read operation.

4. The method according to claim 2, characterized in that, After determining the second address to be processed corresponding to the first address to be processed based on the first address to be processed and the address mapping relationship, the method further includes: Perform location compensation on the second address to be processed; Execute the first instruction to process the storage unit corresponding to the second address to be processed after position compensation.

5. The method according to claim 2, characterized in that, The method further includes: If the second instruction is a rejection mapping instruction, the first instruction is executed to process the storage unit corresponding to the first address to be processed.

6. The method according to claim 1, characterized in that, The driver includes a word line driver and a bit line driver; Determining the target distance from the plurality of said storage cells to the drive includes: Determine a first distance from each of the memory cells to the word line driver; Determine a second distance from each of the memory cells to the bit line driver; The target distance is determined based on the first distance and the second distance.

7. The method according to claim 1, characterized in that, Based on the target distance, the original address is divided into multiple address regions, including: Determine the range of values ​​for the target distance; The range of values ​​is divided into multiple sub-intervals, and the original address included in each sub-interval is determined. Multiple original addresses belonging to the same sub-interval are divided into an address region; and the region information of the address region is obtained based on the interval attribute value of the sub-interval.

8. A memory chip, characterized in that, include: Multiple stacked storage arrays, each storage array comprising multiple storage cells; A driver is configured to drive the storage array; The address mapping module is configured as follows: Obtain the original addresses of the multiple storage units; Determine the target distance from each of the storage cells to the drive; Based on the target distance, the original address is divided into multiple address regions, and each address region has region information; Based on the region information, the multiple address regions are sorted, and the original addresses in each sorted address region are reassigned to obtain a first target address and an address mapping relationship. The address mapping relationship represents the mapping relationship between the first target address and the original address. The first target addresses in each address region are continuous, and the first target addresses in two adjacent address regions are continuous.

9. The memory chip according to claim 8, characterized in that, Also includes: The storage controller, electrically connected to the address mapping module, is configured to receive a first address to be processed and a first instruction. The judgment module is electrically connected to the address mapping module, the processing module, and the storage controller, and is configured to receive a second instruction. The address mapping module is further configured to: when the second instruction is a mapping instruction, determine the second address to be processed corresponding to the first address to be processed based on the first address to be processed and the address mapping relationship; The memory chip also includes the processing module, which is electrically connected to the address mapping module and the memory array, and is configured to execute the first instruction to process the memory cell corresponding to the second address to be processed.

10. The memory chip according to claim 9, characterized in that, The processing module is further configured to execute the first instruction and process the storage unit corresponding to the first address to be processed when the second instruction is a rejection mapping instruction.

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