Control method of storage chip, storage controller, storage system and electronic equipment

Abstract

The embodiment of the invention belongs to the technical field of storage, and particularly relates to a control method of a storage chip, a storage controller, a storage system and electronic equipment. The storage chip comprises P storage arrays, each storage array comprises M rows and N columns, P storage units with the same row and column address in the P storage arrays are an operation unit, each storage array comprises a storage area and a redundancy area, the redundancy area comprises a detection row and / or a detection column, the detection row comprises N storage units, and the detection column comprises M storage units. The control method comprises the following steps: respectively executing a first operation or a second operation on N operation units of a detection row or a detection column, namely applying a read voltage on P storage units in the operation units, and refreshing data in the storage units in the same column or the same row as the P storage units in the storage area when the failure rate of the operation units exceeds a threshold value. According to the invention, the stability of data storage of the storage unit can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, in particular to a control method of a storage chip, a storage controller, a storage system and an electronic device. BACKGROUND

[0002] With the development of storage technology, the number of storage arrays included in the storage chip is increasing, and the storage performance of the storage chip is also increasing.

[0003] When reading and writing the storage unit in the storage chip, the storage units at the same position in multiple storage arrays can be selected, and then operation voltages are applied to the word lines and bit lines connected to the selected storage units respectively, so that the operation voltages applied by the word lines and the bit lines are superimposed on the selected storage units, and then the reading and writing operation of the selected storage units is realized.

[0004] However, other storage units at the same bit line or the same word line as the selected storage unit will also be applied with voltages at the same time, which increases the possibility of threshold voltage drift of the other storage units, and then affects the accuracy of the data stored in the other storage units. SUMMARY

[0005] The embodiments of the present application provide a control method of a storage chip, a storage controller, a storage system and an electronic device, which can improve the accuracy of the data stored in the storage chip. The corresponding technical solutions are as follows:

[0006] In a first aspect, a storage controller of a storage chip is provided, the storage chip including P storage arrays, each storage array including M rows and N columns, P storage units with the same row and column address in the P storage arrays being an operation unit, each storage array including a storage area and a redundant area, the redundant area including a first detection row and / or a first detection column, the detection row including N storage units, and the detection column including M storage units.

[0007] The storage controller is configured to perform a first operation on N operation units corresponding to P first detection rows of the P storage arrays respectively, wherein the time interval corresponding to two adjacent first operations is T1, and the first operation includes applying a read voltage to P storage units in the first operation unit. It is determined whether the failure rate of the first operation unit exceeds a first threshold value according to the number of failed storage units in the P storage units. When the failure rate of the first operation unit exceeds the first threshold value, the data in the storage units in the storage area which are at the same column as the P storage units is refreshed; and / or,

[0008] The storage controller is configured to perform a second operation on each of the M operation units corresponding to the P first detection columns of the P storage arrays, wherein a time interval between two adjacent second operations is T2, and the second operation comprises: applying a read voltage to the P storage units in the second operation unit. It is determined whether the failure rate of the second operation unit exceeds a second threshold according to the number of failed storage units in the P storage units. When the failure rate of the second operation unit exceeds the second threshold, the data in the storage units in the storage area which are in the same row as the P storage units is refreshed.

[0009] In the scheme provided in the present application, since the storage units in the storage area and the storage units in the redundant area are in the same row or the same column, when the read / write operation is performed on the storage units in the storage area, the corresponding operation voltage is also applied to the other storage units in the storage area which are in the same row and the same column as the storage units, and the storage units in the redundant area which are in the same row or the same column as the storage units. Therefore, the storage units in the redundant area and the storage units in the storage area which are not operated are affected by the operation voltage to the same extent, so in the scheme provided in the present application, the storage units in the redundant area can be used to reflect the extent of threshold voltage drift of the storage units in the storage area affected by the operation voltage.

[0010] Therefore, in the scheme provided in the present application, the storage units in the redundant area can be detected periodically, and if the failure rate of the storage units in the redundant area at a certain address is high, it indicates that the threshold voltage drift of the storage units in the storage area which are in the same column or the same column as the storage units at the address is large, so the data stored in the storage units in the storage area which are in the same column or the same column as the storage units at the address can be refreshed to ensure the accuracy of the data stored in the storage units in the storage area. Wherein, refreshing the data stored in the storage units means correcting the read result obtained after reading the storage units, and writing the corrected read result into the storage units.

[0011] In an implementable manner, the storage controller is further configured to: when the failure rate of the first operation unit exceeds the first threshold, refresh the data in the P storage units in the first operation unit and the storage units in the redundant area which are in the same column as the P storage units in the first operation unit; and / or, when the failure rate of the second operation unit exceeds the second threshold, refresh the data in the P storage units in the second operation unit and the storage units in the redundant area which are in the same row as the P storage units in the first operation unit.

[0012] In the scheme provided in the present application, after determining that the operation unit failure rate of the redundancy area exceeds the threshold value, the data of the operation unit and the storage units in the redundancy area which are in the same row or the same column as the storage units included in the operation unit can be refreshed. In this way, the data in the storage units of the storage area and the redundancy area are refreshed at the same time, which can eliminate the threshold voltage drift of the storage units of the storage area and the redundancy area, so that the storage units of the storage area and the redundancy area are affected by the operating voltage consistently, and thus the accuracy of the storage units of the redundancy area reflecting the effect of the operating voltage on the storage units of the storage area can be improved.

[0013] In an implementable manner, each storage unit of the redundancy area stores data in a low resistance state. In this way, when the storage units of the redundancy area are affected by threshold voltage drift more seriously, the storage units in the low resistance state are likely to change to storage units in a high resistance state. Therefore, when each storage unit of the redundancy area stores data corresponding to the low resistance state, the effect of threshold voltage drift on each storage unit of the redundancy area can be detected more accurately, and thus the accuracy of the storage units of the redundancy area reflecting the effect of the operating voltage on the storage units of the storage area can be further improved.

[0014] In an implementable manner, the storage controller is further configured to add 1 to the refresh number after the first operation is performed on the N operation units of the first detection row, continue to perform the first operation on the N operation units, and refresh the data stored by the storage units of all columns of the storage area when the refresh number reaches a third threshold value. Alternatively, the refresh number is added by 1 after the second operation is performed on the M operation units of the first detection column, and then the second operation is continued to be performed on the M operation units. When the refresh number reaches a fourth threshold value, the data stored by the storage units of all rows of the storage area is refreshed.

[0015] In an implementable manner, the redundancy area includes X detection rows and / or Y detection columns, the X detection rows include the first detection row, and the Y detection columns include the first detection column. The storage controller is further configured to continue to perform the first operation on the operation units corresponding to the detection rows after the first detection row after the first operation is performed on the N operation units of the first detection row, and refresh the data stored by the storage units of all columns of the storage area when the first operation is performed on the operation units corresponding to the last detection row of the X detection rows. Alternatively, the storage controller is further configured to continue to perform the second operation on the operation units corresponding to the detection columns after the first detection column after the second operation is performed on the M operation units of the first detection column, and refresh the data stored by the storage units of all columns of the storage area when the second operation is performed on the operation units corresponding to the last detection column of the Y detection columns.

[0016] In the scheme shown in the present application, after the first operation or the second operation is performed on each operation unit in the redundancy area, according to the operation result, there may be a part of the data in the storage unit in the storage area that has been refreshed, and a part of the data in the storage unit that has not been refreshed. Whether the storage unit is refreshed or not, the corresponding threshold voltage will continue to drift. In order to further ensure the accuracy of the data stored in the storage unit in the storage area, after the first operation or the second operation is performed on each operation unit in the redundancy area, the storage unit in the storage area and the redundancy area can be refreshed as a whole.

[0017] In an implementable manner, the read voltage includes multiple gear read voltages, and the storage controller is configured to: after applying the last gear read voltage to the P storage units in the first operation unit, determine whether the failure rate of the first operation unit exceeds the threshold value according to the number of failed storage units in the P storage units in the first operation unit. And / or, after applying the last gear read voltage to the P storage units in the second operation unit, determine whether the failure rate of the second operation unit exceeds the threshold value according to the number of failed storage units in the P storage units in the second operation unit.

[0018] In the scheme provided in the present application, the multiple gear read voltages are sequentially increased. After the highest gear read voltage is applied, if it is determined that the failure rate corresponding to the operation unit is greater than the threshold value, it means that the drift amount of the threshold voltage of the multiple storage units included in the operation unit is large, which may exceed the error correction capability of the error correction algorithm. That is, the drift amount of the threshold voltage of the storage unit in the same row or the same column as the operation unit in the storage area is also large, so it needs to be refreshed. In this way, the data in the storage unit can be refreshed before the failure rate corresponding to the storage unit in the storage area exceeds the error correction capability of the error correction algorithm, which can ensure the accuracy of the data stored in the storage unit on the one hand, and reduce the frequency of refreshing the data in the storage unit, thereby reducing the power consumption of the storage chip.

[0019] In an implementable manner, the storage controller is configured to: when the failure rate of the first operation unit exceeds the threshold value, apply a read voltage to the P storage units included in at least one third operation unit, wherein the third operation unit is an operation unit in the redundancy area that is in the same column as the first operation unit. According to the number of failed storage units in the P storage units in each third operation unit, determine whether the failure rate of each third operation unit exceeds the threshold value. When the number of third operation units whose failure rate exceeds the threshold value is greater than the number threshold value, the data in the storage unit in the storage area that is in the same column as the P storage units in the first operation unit is refreshed.

[0020] Correspondingly, when the failure rate of the second operation unit exceeds the threshold, read voltages are applied to P storage units included in at least one fourth operation unit, wherein the fourth operation unit is an operation unit in the redundancy area in the same row as the second operation unit. Whether the failure rate of each fourth operation unit exceeds the threshold is determined according to the number of failed storage units in the P storage units in each fourth operation unit. When the number of fourth operation units whose failure rates exceed the threshold is greater than a number threshold, data in the storage units in the storage area in the same row as the P storage units in the second operation unit is refreshed.

[0021] In the scheme shown in the present application, the failure rate of the operation unit of the redundancy area can reflect the influence of the threshold voltage drift on the operation unit of the storage area. If it is determined that the failure rate of one operation unit of the redundancy area is greater than the threshold, in order to accurately reflect that the operation unit of the storage area is greatly affected by the threshold voltage drift, the operation units in the same row or the same column as the operation unit can be detected again to further improve the accuracy of the storage unit of the redundancy area reflecting the influence of the operating voltage on the storage unit of the storage area.

[0022] In an implementable manner, before the read voltages are applied to the P storage units included in at least one third operation unit, data is re-written to the P storage units in the first operation unit, the read voltages are applied to the P storage units in the first operation unit again, and whether the failure rate of the first operation unit exceeds the threshold is determined according to the number of failed storage units in the P storage units in the first operation unit.

[0023] Correspondingly, before the read voltages are applied to the P storage units included in at least one fourth operation unit, data is re-written to the P storage units in the second operation unit, the read voltages are applied to the P storage units in the second operation unit again, and whether the failure rate of the second operation unit exceeds the threshold is determined according to the number of failed storage units in the P storage units in the second operation unit.

[0024] In the scheme shown in the present application, considering that the storage unit itself (such as the wear state of the storage unit) may also affect the failure rate of the operation unit, when it is determined that the failure rate of the operation unit of the redundancy area exceeds the threshold, data can be re-written to the storage unit corresponding to the operation unit and read. If it is determined that the failure rate of the operation unit does not exceed the threshold, it indicates that the failure rate of the operation unit detected last time exceeds the threshold and has nothing to do with the storage unit corresponding to the operation unit, and it can be determined that the storage unit corresponding to the operation unit is caused by the threshold voltage drift to exceed the threshold. In this way, the accuracy of the storage unit of the redundancy area reflecting the influence of the operating voltage on the storage unit of the storage area can be further improved.

[0025] If it is determined again that the failure rate of the operation unit exceeds the threshold value, it is said that the storage unit corresponding to the operation unit itself has a problem and cannot reflect the degree to which the storage unit in the storage area is affected by the operating voltage. Subsequently, the problem of the storage unit corresponding to the operation unit can be investigated, and the degree to which the storage unit in the storage area is affected by the operating voltage can be detected by other storage units in the same row or the same column in the redundancy area.

[0026] In a second aspect, a control method of a storage chip is provided. The storage chip includes P storage arrays, each of which includes M rows and N columns. P storage units having the same row and column addresses in the P storage arrays are an operation unit. Each of the storage arrays includes a storage area and a redundancy area. The redundancy area includes a first detection row and / or a first detection column. The first detection row includes N storage units, and the first detection column includes M storage units. The method includes:

[0027] The first operation is performed on N operation units corresponding to P first detection rows of the P storage arrays, respectively. A time interval corresponding to two adjacent first operations is T1. The first operation includes: applying a read voltage to P storage units in a first operation unit, determining whether a failure rate of the first operation unit exceeds a first threshold value according to a number of failed storage units in the P storage units, and performing refresh on data in storage units in the storage area that are in the same column as the P storage units in the first operation unit when the failure rate of the first operation unit exceeds the first threshold value. And / or,

[0028] The second operation is performed on M operation units corresponding to P first detection columns of the P storage arrays, respectively. A time interval corresponding to two adjacent second operations is T2. The second operation includes: applying a read voltage to P storage units in a second operation unit, determining whether a failure rate of the second operation unit exceeds a second threshold value according to a number of failed storage units in the P storage units, and performing refresh on data in storage units in the storage area that are in the same row as the P storage units in the second operation unit when the failure rate of the second operation unit exceeds the second threshold value.

[0029] In an implementable manner, the method further includes: when the failure rate of the first operation unit exceeds the first threshold value, performing refresh on the P storage units in the first operation unit and data in storage units in the redundancy area that are in the same column as the P storage units in the first operation unit; and / or, when the failure rate of the second operation unit exceeds the second threshold value, performing refresh on the P storage units in the second operation unit and data in storage units in the redundancy area that are in the same row as the P storage units in the second operation unit.

[0030] In an implementable manner, each storage unit of the redundancy area is in a low resistance state, and the low resistance state corresponds to data 1.

[0031] In an implementable manner, the method further comprises: when the first operation on the N operation units of the first detection row is completed, incrementing the refresh number by 1; continuing to perform the first operation on the N operation units, and when the refresh number reaches a third threshold, refreshing the data stored in the storage units of all columns of the storage area; or when the second operation on the M operation units of the first detection column is completed, incrementing the refresh number by 1, and then continuing to perform the second operation on the M operation units, and when the refresh number reaches a fourth threshold, refreshing the data stored in the storage units of all rows of the storage area.

[0032] In an implementable manner, the redundant area includes X detection rows and / or Y detection columns, the X detection rows include the first detection row, and the Y detection columns include the first detection column. The method further comprises: after the first operation on the N operation units of the first detection row is completed, continuing to perform the first operation on the operation units corresponding to the detection rows after the first detection row until the first operation on the operation units corresponding to the last detection row of the X detection rows is completed, and then refreshing the data stored in the storage units of all columns of the storage area. Or, after the second operation on the M operation units of the first detection column is completed, continuing to perform the second operation on the operation units corresponding to the detection columns after the first detection column until the second operation on the operation units corresponding to the last detection column of the Y detection columns is completed, and then refreshing the data stored in the storage units of all columns of the storage area.

[0033] In an implementable manner, the read voltage includes multiple read voltages of different levels. The determination of whether the failure rate of the first operation unit exceeds the first threshold according to the number of failed storage units in the P storage units includes: determining whether the failure rate of the first operation unit exceeds the threshold according to the number of failed storage units in the P storage units in the first operation unit after the last level of read voltage is applied to the P storage units in the first operation unit. The determination of whether the failure rate of the second operation unit exceeds the second threshold according to the number of failed storage units in the P storage units includes: determining whether the failure rate of the second operation unit exceeds the threshold according to the number of failed storage units in the P storage units in the second operation unit after the last level of read voltage is applied to the P storage units in the second operation unit.

[0034] In a third aspect, a storage system is provided, which includes a storage controller and a storage chip. The storage chip includes P storage arrays, each of which includes M rows and N columns. P storage units with the same row and column addresses in the P storage arrays form an operation unit. Each storage array includes a storage area and a redundant area. The redundant area includes a first detection row and / or a first detection column. The first detection row includes N storage units, and the first detection column includes M storage units.

[0035] The storage controller is configured to perform a first operation on each of N operation units corresponding to P first detection rows of the P storage arrays, wherein a time interval between two adjacent first operations is T1, and the first operation comprises applying a read voltage to P storage units in the first operation unit. The storage controller is configured to determine whether a failure rate of the first operation unit exceeds a first threshold value according to a number of failed storage units in the P storage units. When the failure rate of the first operation unit exceeds the first threshold value, the storage controller is configured to perform a refresh operation on data stored in storage units in the same column as the P storage units in a storage region of the storage array. And / or,

[0036] The storage controller is configured to perform a second operation on each of M operation units corresponding to P first detection columns of the P storage arrays, wherein a time interval between two adjacent second operations is T2, and the second operation comprises applying a read voltage to P storage units in the second operation unit. The storage controller is configured to determine whether a failure rate of the second operation unit exceeds a second threshold value according to a number of failed storage units in the P storage units. When the failure rate of the second operation unit exceeds the second threshold value, the storage controller is configured to perform a refresh operation on data stored in storage units in the same row as the P storage units in a storage region of the storage array.

[0037] In an implementable manner, the storage controller is configured to perform a refresh operation on the P storage units in the first operation unit and data stored in storage units in the same column as the P storage units in the first operation unit in a redundancy region when the failure rate of the first operation unit exceeds the first threshold value. And / or, the storage controller is configured to perform a refresh operation on the P storage units in the second operation unit and data stored in storage units in the same row as the P storage units in the second operation unit in a redundancy region when the failure rate of the second operation unit exceeds the second threshold value.

[0038] In an implementable manner, each storage unit in the redundancy region is in a low resistance state, and the low resistance state corresponds to data 1.

[0039] In an implementable manner, the storage controller is further configured to add 1 to a refresh count when the first operation is performed on each of the N operation units corresponding to the first detection rows, and continue to perform the first operation on the N operation units, and perform a refresh operation on data stored in all storage units in all columns of the storage region when the refresh count reaches a third threshold value. Or, the storage controller is configured to add 1 to the refresh count when the second operation is performed on each of the M operation units corresponding to the first detection columns, and continue to perform the second operation on the M operation units, and perform a refresh operation on data stored in all storage units in all rows of the storage region when the refresh count reaches a fourth threshold value.

[0040] In an implementable manner, the redundant area includes X detection rows and / or Y detection columns, the X detection rows include the first detection row, and the Y detection columns include the first detection column. The storage controller is further configured to, after the first operation is performed on the N operation units of the first detection row, continue to perform the first operation on operation units corresponding to detection rows after the first detection row until the first operation is performed on operation units corresponding to the last detection row of the X detection rows, and then flush the data stored in the storage units of all columns of the storage area; or, after the second operation is performed on the M operation units of the first detection column, continue to perform the second operation on operation units corresponding to detection columns after the first detection column until the second operation is performed on operation units corresponding to the last detection column of the Y detection columns, and then flush the data stored in the storage units of all columns of the storage area.

[0041] In an implementable manner, the read voltage includes multiple levels of read voltages, and the storage controller is configured to: after the last level of read voltage is applied to the P storage units in the first operation unit, determine whether the failure rate of the first operation unit exceeds a threshold value according to the number of failed storage units in the P storage units in the first operation unit; and / or, after the last level of read voltage is applied to the P storage units in the second operation unit, determine whether the failure rate of the second operation unit exceeds a threshold value according to the number of failed storage units in the P storage units in the second operation unit.

[0042] In a fourth aspect, an electronic device is provided, which includes a processor and a storage system as described in the third aspect above. The processor is configured to send read-write instructions to the storage system to enable the storage system to perform read-write operations. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 is a structural schematic diagram of a storage chip provided by an embodiment of the present application;

[0044] Figure 2 is a structural schematic diagram of a control circuit provided by an embodiment of the present application;

[0045] Figure 3 is a structural schematic diagram of a storage system provided by an embodiment of the present application;

[0046] Figure 4 is a schematic diagram of operating a storage array provided by an embodiment of the present application;

[0047] Figure 5 is a schematic diagram of operating a storage array provided by an embodiment of the present application;

[0048] Figure 6 is a schematic diagram of a storage array provided by an embodiment of the present application;

[0049] Figure 7 is a control method flowchart of a storage chip provided by an embodiment of the present application;

[0050] Figure 8 is a storage array schematic diagram provided by an embodiment of the present application;

[0051] Figure 9 is a storage array schematic diagram provided by an embodiment of the present application;

[0052] Figure 10 is a control method flowchart of a storage chip provided by an embodiment of the present application;

[0053] Figure 11 is a control method flowchart of a storage chip provided by an embodiment of the present application;

[0054] Figure 12 is a structural schematic diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0056] Some terms involved in the embodiments of the present application are explained as follows:

[0057] Resistive memory: data is stored or read by using the change of resistance. For example, resistive memory can store "0" when in a high resistance state, and can store "1" when in a low resistance state.

[0058] Phase change memory (PCM): a new type of non-volatile semiconductor memory based on chalcogenide compounds, which belongs to a type of resistive memory. The resistive memory can store "0" and "1" by using the different resistances of the phase change material in crystalline and amorphous states. When the phase change material is in an amorphous state, the phase change material is in a high resistance state, i.e., has a high resistance value, and is defined as a RESET (0) state. When the phase change material is in a crystalline state, the phase change material is in a low resistance state, i.e., has a low resistance value, and is defined as a SET (1) state.

[0059] Ovonic Threshold Switch (OTS): A new type of bidirectional gating device based on chalcogenide compounds. When an arbitrary electric pulse with a low amplitude and in a certain direction is applied to the OTS, the response current is small, and the OTS is in a high-resistance non-conducting state. When an arbitrary electric pulse with a high amplitude and in a certain direction is applied to the OTS, the response current is large, and the OTS is in a low-resistance conducting state.

[0060] 1S1R memory cell: A memory cell composed of an OTS and a PCM. In an implementable manner, when the PCM in the 1S1R memory cell is in the RESET (0) state, the 1S1R memory cell stores "0", and at this time, the 1S1R memory cell has a high threshold voltage Vthr. When the PCM in the 1S1R memory cell is in the SET (1) state, the 1S1R memory cell stores "1", and at this time, the 1S1R memory cell has a low threshold voltage Vths. Wherein, Vthr is equal to the threshold voltage of the OTS plus the threshold voltage corresponding to the PCM in the RESET (0) state, and Vths is equal to the threshold voltage of the OTS plus the threshold voltage corresponding to the PCM in the SET (1) state.

[0061] Based on the above characteristics, when the 1S1R memory cell stores "0", the response current of the 1S1R device cell is small under a certain read voltage Vread (greater than Vths and less than Vthr); when the 1S1R memory cell stores "1", the response current of the 1S1R device cell is large under a certain read voltage Vread. Thus, the data stored in the 1S1R memory cell can be read by applying a read voltage Vread.

[0062] Erasing operation: It is realized by applying a high-amplitude and narrow-width electric pulse to the 1S1R memory cell. The amplitude of the electric pulse is higher than the threshold voltage of the OTS, and under the action of the electric pulse, the temperature of the PCM in the 1S1R memory cell is rapidly raised above the melting temperature and then quenched. Since the micro atoms do not have sufficient time to crystallize, they remain in a high-resistance amorphous state, i.e. "0" storage is realized.

[0063] Writing operation: It is realized by applying an electric pulse with a relatively low amplitude but a relatively long duration to the 1S1R memory cell. The amplitude of the electric pulse is higher than the threshold voltage of the OTS, and under the action of the electric pulse, the temperature of the PCM in the 1S1R memory cell is raised above the crystallization temperature and below the melting temperature. The PCM can be converted into a low-resistance state through a thermal crystallization process, i.e. "1" storage is realized.

[0064] Read operation: the read operation of the data stored in the 1S1R memory cell can be realized according to the response current of the 1S1R memory cell by applying a fixed read voltage Vread at both ends of the 1S1R memory cell.

[0065] Word line: the signal line required for selecting a row of 1S1R memory cells in the storage array, which can select a 1S1R memory cell together with the bit line.

[0066] Bit line: the signal line required for selecting a column in the storage array, which can select a 1S1R memory cell together with the word line. By applying corresponding electrical pulses to the word line and the bit line, the above-mentioned write operation, erase operation or read operation can be performed on the selected 1S1R memory cell.

[0067] Threshold voltage drift of OTS: the threshold voltage of the OTS changes over time due to the voltage applied to the OTS from the last opening to the current opening, the environmental temperature and other factors, which is called the threshold voltage drift of the OTS.

[0068] OTS has a large current conduction capacity under the action of a voltage greater than the threshold voltage, which is caused by the transition of the originally balanced non-conductive electrons in the low-energy state to the unbalanced conductive state in the high-energy state under the action of high voltage. When the voltage applied to the OTS is removed, the high-energy unbalanced carriers in the OTS will not all return to the balanced state at once, but will gradually return to the low-energy balanced non-conductive state according to a certain probability. Therefore, after each operation of the 1S1R memory cell, the threshold voltage of the OTS in the 1S1R memory cell will suddenly decrease, and then gradually increase over time. Among them, the greater the voltage applied to the OTS, the more the threshold voltage of the OTS will decrease, and then the higher the temperature of the environment in which the OTS is placed, the faster the threshold voltage will drift upward. In addition, when the OTS is placed for a long time, its threshold voltage will also drift to a higher state.

[0069] Figure 1 Fig. 1 is a structural schematic diagram of a storage chip provided by an embodiment of the present application. As shown in Fig. 1, the storage chip comprises a plurality of 1S1R memory cells 100, a plurality of word lines 200 and a plurality of bit lines 300. Figure 1As shown, the memory chip 100 includes a control circuit 110 and at least one memory bank 120 (Bank 120), and each Bank 120 includes a plurality of memory arrays 121. The plurality of memory arrays 121 included in the plurality of Banks 120 can generally be tiled on the same plane, or can be stacked in three-dimensional space. Each memory array 121 includes memory cells arranged in rows and columns, and when performing read / write operations on the memory cells of the memory chip 100, a memory cell can be selected in each memory array 121 to perform read / write operations on the selected memory cells. In this way, the storage capacity and storage performance of the memory chip can be improved without increasing the area occupied by the memory chip.

[0070] The memory array 121 includes a plurality of memory cells arranged in an array. In the plurality of memory cells, the memory cells in the same row are connected to the same word line (WL), and the memory cells in the same column are connected to the same bit line (BL). Each memory cell can be composed of a memory device and a gating device. The memory device can be a resistive memory device, such as a phase change memory, a ferroelectric memory, a magnetic random access memory, and a resistive random access memory. The gating device can be a bidirectional threshold switch. When the memory device is a PCM, the memory cell can be referred to as a 1S1R memory cell, and the memory chip can be referred to as a phase change memory chip.

[0071] Figure 2 FIG. 1 is a schematic diagram of a control circuit 110 according to an embodiment of the present application. As shown, the control circuit 110 includes a logic control circuit 111, a driving circuit 112, a word line control circuit 113, and a bit line control circuit 114. Figure 2

[0072] The logic control circuit 111, upon receiving an operation request corresponding to a read operation, a write operation, or an erase operation, can control the driving circuit 122 to apply an operation voltage corresponding to the read operation, the write operation, or the erase operation to one or more memory cells corresponding to the operation request, so as to implement the read operation, the write operation, or the erase operation on the memory cells.

[0073] The driving circuit 112 can select the memory cells corresponding to the operation request by controlling the word line control circuit 113 and the bit line control circuit 114, and then apply the corresponding operation voltage to the selected memory cells.

[0074] The word line control circuit 113 includes a word line switch circuit 1131 and a first sensing circuit 1132, and the bit line control circuit 114 includes a bit line switch circuit 1141 and a second sensing circuit 1142. The word line switch circuit 1131 is connected to each word line in the memory array 121 through a switch tube, and the bit line switch circuit 1141 is connected to each bit line in the memory array 121 through a switch tube. Figure 2 ​(Not shown in the image). Word line control circuit 113 can activate the word line connected to the selected memory cell. Bit line switch circuit 1141 is connected to each bit line in memory array 121 via a switching transistor. Figure 2 (Not shown in the image).

[0075] The word line control circuit 1131 can turn on the switch corresponding to the word line connected to a memory cell, and the bit line switch circuit 1141 can turn on the switch corresponding to the bit line connected to the memory cell, thereby selecting the memory cell so that the drive circuit 112 applies the corresponding operating voltage to the selected memory cell.

[0076] The first sensing circuit 1132 or the second sensing circuit 1142 can be used to detect the current magnitude on the word line or bit line connected to the selected memory cell, thereby realizing the perception of the memory state corresponding to the memory cell.

[0077] Figure 3 This is a schematic diagram of a storage system provided in an embodiment of this application. Figure 3 As shown, the storage system 300 includes a storage controller 200 and one or more other components such as... Figure 1 The storage chip 100 is shown. The storage controller 200 is a hardware device used to control the storage chip 100 to perform read and write operations. The storage controller 200 can send operation requests corresponding to read, write, or erase operations to the storage chip 100, so that the control circuit 110 in the storage chip 100 selects the storage cell through word lines and bit lines, and applies read voltage, write voltage, or erase voltage to the selected storage cell, thereby realizing the execution of the read, write, or erase operation. To cope with reading errors of storage cells, the storage controller 200 is also equipped with an error correction algorithm. This error correction algorithm can verify and correct the read results of the storage chip to avoid or reduce the amount of data read incorrectly. In the storage system provided in this application embodiment, the storage controller 200 can also execute the control method provided in this application embodiment, which can improve the stability of data stored in the storage cells of the storage chip.

[0078] Figure 4 This is a schematic diagram illustrating the operation of a storage unit according to an embodiment of this application. For example... Figure 4As shown, when operating the memory cell 401 in the memory array, an operating voltage can be applied to the memory cell 401 through the BL and the WL connected to the memory cell 401, respectively, so as to realize the read / write operation of the memory cell 401 by superimposing the operating voltage applied to the BL and the WL on the memory cell 401. When the operating voltage is applied to the memory cell 401 through the BL, the operating voltage is also applied to other memory cells in the same column as the memory cell 401. Similarly, when the operating voltage is applied to the memory cell 401 through the WL, the operating voltage is also applied to other memory cells in the same row as the memory cell 401. For the memory cells to which the operating voltage is applied only through the BL or the WL, although the operating voltage applied to the memory cells is lower than the minimum voltage required for the read / write operation, the threshold voltage of the memory cells is accelerated to drift, so that the threshold voltage of the memory cells is rapidly increased. For the selected memory cell, since the operating voltage will be applied to the memory cell for operation in the subsequent process, the threshold voltage of the memory cell is refreshed, i.e., the threshold voltage is refreshed to the level before the drift.

[0079] In the embodiment of the present application, the selected memory cell can be referred to as an Aggressor unit, and the memory cell to which the operating voltage is applied and which is not selected can be referred to as a Victim unit. The threshold voltage drift of the Victim unit caused by the influence of the operating voltage can be referred to as bias drift. Further as shown, Figure 5 As shown, after the memory array is operated for multiple times, in a row or a column, multiple memory cells can be selected as Aggressor units, respectively, and in the same row or column, multiple memory cells can be not selected every time, and are used as Victim units every time. In this way, the Victim units in the row or the column are applied with the operating voltage for multiple times, and are greatly affected by the bias drift, and the threshold voltage is greatly increased. In the Victim units, the threshold voltage of the memory cell in the low resistance state (storing "1") can drift beyond the read voltage, and thus the data error can be caused.

[0080] Figure 6 FIG. 1 is a schematic diagram of a memory array provided by an embodiment of the present application. As shown, Figure 6As shown, each memory array includes a storage area and a redundancy area. The storage area stores memory cells for providing normal read and write operations to an external device, such as a host device connected to the memory chip. Since the memory cells in the storage area and the redundancy area share word lines or share bit lines, when a memory cell in the storage area is operated, a memory cell in the redundancy area that shares the same word line or the same bit line with the operated memory cell becomes a victim cell. That is, in a row of memory cells (memory cells sharing a word line) in the memory array, when any memory cell in the storage area is operated, the memory cells in the storage area that are not operated and the memory cells in the redundancy area all become victim cells. Similarly, in a column of memory cells (memory cells sharing a bit line) in the memory array, when any memory cell in the storage area is operated, the memory cells in the storage area that are not operated and the memory cells in the redundancy area all become victim cells. That is, in the same row or the same column, the memory cells in the redundancy area and the memory cells in the storage area are affected by bias drift in a substantially uniform manner, and the memory cells in the storage area that are operated less frequently are affected by bias drift in a manner that is closer to the memory cells in the redundancy area. Therefore, the memory cells in the redundancy area can reflect the bias drift affecting the memory cells in the storage area.

[0081] In an example, reference can be continued to Figure 6 The redundancy area in each memory array can include a row redundancy area and / or a column redundancy area. The row redundancy area includes X detection rows, and each detection row can include at least N memory cells. The N memory cells in one detection row can share a bit line BL with N memory cells in a column of the storage area. In this way, any memory cell in each detection row can be used to reflect the bias drift affecting the memory cells in the storage area that are in the same column as the any memory cell. Similarly, the column redundancy area includes Y detection columns, and each detection column can include at least M memory cells. The M memory cells in one detection column can share a word line WL with M memory cells in a row of the storage area. In this way, any memory cell in each detection column can be used to reflect the bias drift affecting the memory cells in the storage area that are in the same row as the any memory cell. The values of X and Y can be 1 or greater than 1.

[0082] Generally, when performing read and write operations on the storage units of the storage array, the storage units corresponding to the same address in the plurality of storage arrays can be operated according to the address of the storage unit. Since the storage units corresponding to the same address are located at the same position in the storage array, the plurality of storage units operated each time are located at the same row and column in the storage array. In this way, each time the storage units in the plurality of storage arrays are operated, the storage units as Aggressor units in each storage array correspond to the same position, and the storage units as Victim units also correspond to the same position. For ease of description, in the embodiments of the present application, the storage units corresponding to the same address in the plurality of storage arrays can be referred to as operation units, and the operation units in the row redundancy area can be referred to as first operation units, and the operation units in the column redundancy area can be referred to as second operation units.

[0083] The embodiments of the present application provide a control method of a storage chip, which can determine the degree of influence of bias drift on the operation units in the storage area according to the failure rate of the operation units in the redundancy area. In the case where the degree of influence of bias drift on the operation units in the storage area is large, the data stored in each storage unit of the operation units in the storage area is refreshed to ensure the accuracy of the data of the storage unit. The method can be executed by a storage controller connected externally to the storage chip, or can be executed by a control circuit internally in the storage chip. The control method is described below by taking the execution of the control method by the storage controller as an example.

[0084] In an implementable manner, each storage array of the storage chip includes a row redundancy area. The storage controller of the storage chip can perform a first operation on the N operation units corresponding to the P first detection rows of the P storage arrays, respectively.

[0085] Figure 7 is a flowchart of a control method of a storage chip provided by the embodiments of the present application, referring to Figure 7 The corresponding first operation includes:

[0086] Step 701, a read voltage is applied to the P storage units in the first operation unit.

[0087] The first operation unit refers to the unit that performs the first operation in the redundancy area each time. In an example, the row redundancy area in each storage array can include one detection row. The storage controller can perform the first operation on the operation units on the P storage arrays in sequence according to the address order of the operation units in the process of performing the first operation in sequence. The interval between the execution times of two first operations can be T1, and the specific duration of T1 can be set by the technician in advance, which is not limited in the embodiments of the present application.

[0088] In an example, the row redundancy area in each storage array can include a plurality of detection rows. The first detection row can be any detection row in the row redundancy area, such as the first detection row. In the process of sequentially performing the first operation, the storage controller can sequentially perform the first operation on each operation unit according to the order of the detection rows. Wherein, the order of the detection rows in the row redundancy area can be set by the technician in advance, and the N operation units corresponding to the detection rows can be N operation units composed of N storage units included in the detection rows with the same position in the plurality of storage arrays. The storage controller can sequentially perform the first operation on the N operation units corresponding to the detection rows according to the order of the detection rows, which can be that the storage controller first performs the first operation on the N operation units corresponding to the first detection row, then performs the first operation on the N operation units corresponding to the second detection row, and so on, and finally performs the first operation on the N operation units corresponding to the Xth detection row. After performing the first operation on the last operation unit of the Xth detection row, the storage controller can sequentially perform the first operation on the N operation units corresponding to the detection rows according to the order of the detection rows. Wherein, in the process of sequentially performing the first operation on the N operation units corresponding to the detection rows according to the order of the detection rows, the interval between the execution times of the first operation corresponding to the adjacent two times can be T1, and the specific duration of T1 can be set by the technician in advance, which is not limited in the embodiments of the present application.

[0089] In step 702, it is determined whether the failure rate of the first operation unit exceeds a first threshold value according to the number of failed storage units in the P storage units.

[0090] In implementation, the P storage units included in the first operation unit can perform a read operation, the failure rate corresponding to the P storage units is determined, and the degree of influence of the bias drift on the P storage units as Victim units is determined according to the failure rate corresponding to the P storage units. The higher the failure rate, the greater the degree of influence of the bias drift, and the higher the possibility of data error. Similarly, the higher the failure rate, the greater the degree of influence of the bias drift on the storage units in the same column of the plurality of storage arrays and the P storage units, and the higher the possibility of data error. Therefore, in the embodiments of the present application, the first threshold value can be set for the failure rate to determine whether the storage units are seriously affected by the bias drift. If the failure rate of the P storage units included in the first operation unit exceeds the first threshold value, it can be determined that the P storage units and the storage units in the same column as the P storage units in the plurality of storage arrays are seriously affected by the bias drift, and the probability of data error is large. Wherein, the first threshold value can be set by the technician in advance, and the specific value is not limited in the embodiments of the present application.

[0091] In an example, after performing the read operation on the P memory cells in the first operation unit, the number of memory cells with data read error in the P memory cells can be obtained by a check algorithm or an error correction algorithm provided in the memory chip, for example, a failure bit count (FBC) obtained by the check algorithm, or a number of bits corrected by an error checking and correcting (ECC) algorithm. The number of failed memory cells in the P memory cells can be used to indicate the failure rate of the P memory cells. Alternatively, the failure rate of the P memory cells can be calculated based on the number of failed memory cells in the P memory cells, for example, the ratio of the number of failed memory cells in the P memory cells to P.

[0092] In an example, the memory cells in the redundancy area can all store data corresponding to the low resistance state, for example, "1". Since the threshold voltage of the memory cell storing the low resistance state data is low, the corresponding threshold voltage is easy to exceed the read voltage after being affected by the bias drift, and can be detected by the read operation. Therefore, the memory cells in the redundancy area can all store data corresponding to the low resistance state, which can improve the accuracy of determining the failure rate of the P memory cells included in the first operation unit. Moreover, in the case that the memory cells in the redundancy area can all store data corresponding to the low resistance state, the failure rate of the first operation unit can be determined based on the number of data corresponding to the high resistance state, for example, the number of "0", in the read result, without the need for detection by the check algorithm or the error correction algorithm, which can improve the efficiency of determining the failure rate of the first operation unit.

[0093] In step 703, when the failure rate of the first operation unit exceeds the first threshold value, the data in the memory cells in the storage area which are in the same column as the P memory cells is refreshed.

[0094] In implementation, if it is determined that the failure rate of the P memory cells included in the first operation unit exceeds the first threshold value, it indicates that the memory cells in the same column as the P memory cells are more seriously affected by the bias drift, and the probability of data error is larger. Therefore, the refresh processing can be performed on the memory cells in the storage area which are in the same column as the P memory cells.

[0095] In an example, performing the refresh processing on the memory cells can include performing a read operation on the memory cells to obtain a read result, performing error correction processing on the read result by an error correction algorithm (such as ECC) to obtain a read result after error correction processing, and then writing the read result after error correction processing back to the first memory cell. In this way, the correct data can be written back to the memory cells in the storage area, and the first memory cell can be prevented from being affected by the bias drift too seriously, which can cause data error in the memory cell.

[0096] In an example, the first threshold value can be set according to the error correction capability of the error correction algorithm. For example, the first threshold value is less than the maximum failure rate that can be corrected by the error correction algorithm. Since the P operation units corresponding to the first operation unit are always used as the victim unit during the read / write operation of the storage unit in the storage array, the P operation units are generally affected by the bias drift greater than or equal to the storage unit in the storage area, i.e., the failure rate corresponding to the storage unit in the storage area is less than the failure rate corresponding to the storage unit in the redundant area. Therefore, setting the first threshold value according to the error correction capability of the error correction algorithm can ensure that the error correction algorithm corrects the storage unit with data error in the storage area, and can avoid the problem that the number of storage units with data error in the storage area is too large to be corrected.

[0097] In an example, the failure rate of the first operation unit in the embodiment of the present application can refer to the failure rate obtained after using the highest grade read voltage. In the implementation, when performing the read operation on the storage unit, the lowest grade read voltage can be used to read the data first. If the read is wrong, the error correction algorithm can be used to correct the read result. If the error correction fails, the middle grade read voltage can be used to read the data. If the read is wrong again, the error correction algorithm can be used to correct the read result. If the error correction fails again, the highest grade read voltage can be used to read the data. If the error correction fails again, the problem of being unable to correct occurs.

[0098] During the read operation on the P storage units corresponding to the first operation unit, if the highest grade read voltage is not triggered to read the data of the P storage units, it indicates that the P storage units and the storage units in the same column as the P storage units are less affected by the bias drift, and the error correction algorithm can normally correct the storage unit in the storage area. Therefore, the refresh processing on the storage unit in the storage area is not needed. During the read operation on the P storage units corresponding to the first operation unit, if the highest grade read voltage is triggered to read the data of the P storage units, and the corresponding failure rate is greater than the first threshold value, it indicates that the P storage units and the storage units in the same column as the P storage units are greatly affected by the bias drift, and the failure rate corresponding to the storage unit in the storage area can be close to the maximum error correction capability of the error correction algorithm. Therefore, the refresh processing on the storage unit in the storage area can be performed to avoid the problem of being unable to correct.

[0099] In this way, the data in the storage unit is refreshed before the failure rate corresponding to the storage unit in the storage area exceeds the error correction capability of the error correction algorithm. On the one hand, the accuracy of the data stored in the storage unit can be ensured, and on the other hand, the frequency of refreshing the data in the storage unit can be reduced, and the power consumption of the storage chip can be reduced.

[0100] In one example, when the failure rate of the first operation unit exceeds a first threshold, the data in the P storage cells of the first operation unit can be refreshed. If the row redundancy area includes multiple redundant rows, the data in the storage cells in the row redundancy area that are in the same column as the P storage cells in the first operation unit can also be refreshed.

[0101] When the failure rate of the first operating unit exceeds a first threshold, the data in the storage cells in the storage area that are in the same column as the P storage cells included in the first operating unit is refreshed. This refreshes the threshold voltage of the storage cells in the storage area to the level before the threshold voltage drift occurred. Since the storage cells in the redundant area are used to reflect the degree of threshold voltage drift of the storage cells in the storage area, the degree of threshold voltage drift of the storage cells in the redundant area needs to be consistent with the degree of threshold voltage drift of the storage cells in the storage area. Therefore, refreshing the data in the storage cells in the storage area can also refresh the data in the storage cells in the redundant area, thus improving the accuracy of the redundant area's reflection of the impact of the operating voltage on the storage cells in the storage area. For example, if the storage cells in the redundant area are storing "1", when refreshing the data in the storage cells of the storage area, the P storage cells included in the first operating unit can also be rewritten with "1".

[0102] Figure 8 This application provides a schematic diagram of a storage array. For example... Figure 8 As shown, the row redundancy area of ​​the storage array includes only one redundant row. At each detection cycle (T1), the storage controller sequentially performs read operations on the first operation unit of the row redundancy area to obtain the corresponding FBC. If the obtained FBC is greater than the set FBC threshold, the storage units included in the operation unit in the same column as the first operation unit in the storage area can be refreshed. In this way, the degree of bias drift affecting the first storage unit in each column of the storage area can be detected sequentially according to the set detection cycle, and the storage units with a higher degree of influence can be refreshed, thereby maintaining the accuracy of the data stored in the storage units.

[0103] exist Figure 8 In the first operation unit, for which the FBC is greater than the set FBC threshold, the data corresponding to the low-impedance state can be rewritten to the memory cells included in the first operation unit, such as rewriting "1". This refreshes the memory cells included in the first operation unit and all memory cells in the same column of the memory area, ensuring that the threshold voltage drift of the memory cells in the redundant area is consistent with the threshold voltage drift of the memory cells in the main memory area. This improves the accuracy of the redundant area's memory cells in reflecting the extent of bias drift affecting the memory cells in the main memory area.

[0104] Figure 9The embodiment of the present application provides a storage array schematic diagram. In an example, a row redundancy area of the storage array comprises a plurality of redundancy rows. At each time when a detection period is reached, a storage controller can perform a read operation on a first operation unit of the row redundancy area in sequence, and obtain a corresponding FBC. If the obtained FBC is greater than a set FBC threshold, the storage units included in the operation units in the same column as the first operation unit in the storage area can be subjected to refresh processing. In this way, the influence degree of the bias drift on each column of the first storage units in the storage area can be detected in sequence according to the set detection period, and the storage units with a greater influence degree are subjected to refresh processing, thereby maintaining the accuracy of the stored data in the storage units.

[0105] In Figure 9 , for the first operation unit with the FBC greater than the set FBC threshold, the storage units included in the first operation unit and the storage units included in the operation units in the same column as the first operation unit in the row redundancy area are re-written with data corresponding to the low resistance state, such as re-writing "1". In this way, the storage units in the same column of the row redundancy area and the storage units in the storage area are refreshed, so that the threshold voltage drift degree of the storage units in the row redundancy area and the threshold voltage drift degree of the storage units in the storage area are kept consistent, and the accuracy of the storage units in the row redundancy area reflecting the influence degree of the bias drift on the storage units in the storage area is improved.

[0106] Figure 10 The embodiment of the present application provides a method for detecting and refreshing on the storage array shown in Figure 9 , and a flowchart of the method is shown in Figure 10 , and the method comprises the following steps.

[0107] Step 1001, the storage controller is powered on and initialized.

[0108] In the implementation, after the storage controller is powered on, the timer can be cleared and started. Meanwhile, the redundancy rows of the row redundancy area can be initialized. The initialization comprises writing "1" to the storage units included in each redundancy row. After the initialization is completed, the normal read mode can be entered, that is, the storage units in the storage area can be normally read and written.

[0109] Step 1002, at each time when the detection period T is reached, in the row redundancy area, a first operation unit to be read is determined according to a set sequence.

[0110] At each time when the detection period T is reached, the first operation unit in the row redundancy area can be determined according to the set order. For example, at the time when the timer reaches 1T, the operation unit in the first column of the first redundancy row can be read. At the time when the timer reaches 2T, the operation unit in the second column of the first redundancy row can be read. At the time when the timer reaches XT, the operation unit in the Xth column of the first redundancy row can be read, where X is the number of operation units corresponding to the redundancy row. At the time when the timer reaches (X+1)T, the operation unit in the first column of the second redundancy row can be read. At the time when the timer reaches (iX+j)T, the operation unit in the jth column of the ith redundancy row can be read.

[0111] Step 1003, performing a read operation on the first operation unit.

[0112] Step 1004, determining whether the FBC obtained after the read operation is greater than the FBC threshold.

[0113] If it is determined that the FBC corresponding to the first operation unit after the read operation is greater than the FBC threshold, it indicates that the storage units in the same column are greatly affected by bias drift, and step 1005 is performed. If it is determined that the FBC corresponding to the first operation unit after the read operation is less than or equal to the FBC threshold, it indicates that the storage units in the same column are less affected by bias drift, and it can be considered that the read error rate of the storage units in the column is low, and the detection operation can be ended by going to step 1006.

[0114] Step 1005, refreshing the storage units in the same column as the first operation unit.

[0115] If it is determined that the FBC corresponding to the first operation unit after the read operation is greater than the FBC threshold, the storage units included in the operation units in the same column as the first operation unit can be refreshed, that is, the storage units included in the operation units in the same column are refreshed, and the operation units in the same column (including the first operation unit detected) are re-written into the low resistance state corresponding data in the redundancy area.

[0116] Step 1006, ending.

[0117] In the embodiments of the present application, each operation unit can be read in turn according to the period, and the influence of bias drift on the operation units in the same column can be determined according to the failure rate of the operation units. When the operation units in the same column are greatly affected by bias drift, the operation units in the same column can be refreshed to maintain the accuracy of the data stored in the storage units in the storage area.

[0118] In the embodiments of the present application, in order to further improve the accuracy of the storage units in the redundancy area reflecting the degree of the first storage unit affected by the bias drift, a detection method for the storage units in the redundancy area is further provided, and the processing of step 702 can also be as follows:

[0119] Step 7021, when the failure rate of the first operation unit exceeds the threshold, a read voltage is applied to the P storage units included in each of the at least one third operation unit, and the third operation unit is an operation unit in the same column as the first operation unit in the redundancy area.

[0120] After the storage controller determines that the FBC corresponding to the read first operation unit is greater than the FBC threshold, in order to further verify that the first storage unit is greatly affected by the bias drift, a read operation can be performed on other third operation units in the same column in the redundancy area. Wherein, the number of third operation units read again in each storage array can be set by the technician in advance.

[0121] Optionally, before reading the third operation unit, it can be determined whether the storage unit corresponding to the currently read first operation unit has a high failure rate caused by other factors, such as severe wear. Therefore, before reading the third operation unit, data is re-written to the storage unit corresponding to the currently read first operation unit, and then read again. Since the threshold voltage of the storage unit is refreshed after re-writing the data, the bias drift effect is eliminated. Therefore, if the corresponding failure rate is small after reading again, it means that the first operation unit itself has no problem, and the high failure rate is mainly caused by the bias drift, so the third operation unit can be read again for verification. If the corresponding failure rate is still large after reading the first operation unit again, it means that the storage unit corresponding to the first operation unit is likely to be affected by other factors, resulting in a high failure rate. In this case, an error can be reported and other processing can be performed to investigate the cause of the high failure rate of the first operation unit. Subsequently, other operation units in the same column in the row redundancy area can be used to detect the bias drift effect on the storage units in the same column in the storage area.

[0122] Step 7022, according to the number of failed storage units in the P storage units in each third operation unit, it is determined whether the failure rate of each third operation unit exceeds the threshold.

[0123] Step 7023, when the number of third operation units with failure rates exceeding the threshold is greater than the number threshold, the data in the storage units in the same column as the P storage units in the first operation unit in the storage area is refreshed.

[0124] If there are still third operation units whose corresponding FBCs are greater than the FBC threshold in the plurality of third operation units read by the storage controller again, it can be determined that the storage units in the same column are indeed greatly affected by bias drift, and thus the storage units in the same column can be subjected to refresh processing to ensure the accuracy of the data stored by the storage units.

[0125] In an example, m third operation units can be read, and if there are n third operation units whose corresponding FBCs are greater than the FBC threshold in the m third operation units, it can be determined that the storage units in the same column are indeed greatly affected by bias drift, and thus the storage units in the same column can be subjected to refresh processing to ensure the accuracy of the data stored by the storage units. Here, m is greater than n, and the values of m and n can be pre-set by a technician, which is not limited in the embodiments of the present application.

[0126] Optionally, after performing the first operation on each operation unit of each detection row in the redundancy area, the data in the storage units in each column included in the storage area and the redundancy area is refreshed in turn according to a refresh period.

[0127] In implementation, after performing the first operation on each operation unit of the redundancy area, according to different operation results, there can be a part of the data in the storage units in the storage area that has been refreshed and a part of the data in the storage units that has not been refreshed. In order to further ensure the accuracy of the data stored by the storage units in the storage area, the storage units in each column in the redundancy area can be refreshed after performing the first operation on each operation unit of the redundancy area once or multiple times, so as to reduce the failure rate of reading the storage units.

[0128] Here, in the case where the redundancy area only includes one detection row, when the first operation is performed on the N operation units of the first detection row, the refresh number is increased by 1, and the first operation is continued to be performed on the N operation units. When the refresh number reaches a third threshold, the data stored by the storage units in all columns of the storage area is refreshed.

[0129] In implementation, the storage controller can perform the first operation on the N operation units corresponding to the first detection row cyclically in a detection period T1. And the number of times (i.e. the refresh number) of performing the first operation on the N operation units corresponding to the first detection row once can be recorded. When the refresh number reaches a third threshold value, the data stored in the storage units of each column of the storage area in the P storage arrays can be refreshed in the order of the columns, and the refresh number can be updated to 0. In addition, in order to keep the storage units of the storage area and the storage units of the row redundancy area affected by the threshold voltage drift consistent, the data stored in the storage units of the storage area and the row redundancy area in the P storage arrays can be refreshed. The specific value of the third threshold value can be set by the technician in advance, which is not limited in the embodiment of the present application. In this way, the data of all the storage units in the storage area can be refreshed every certain time, which can further ensure the stability of the data stored in the storage units.

[0130] In the case where the redundancy area includes a plurality of detection rows, the storage controller is further configured to continue to perform the first operation on the operation units corresponding to the detection rows after the first detection row after the N operation units of the first detection row have performed the first operation, and refresh the data stored in the storage units of all the columns of the storage area when the operation units corresponding to the last detection row of the X detection rows have performed the first operation.

[0131] In implementation, the storage controller can cyclically perform the first operation on the N operation units corresponding to each detection row in turn. After performing the first operation on all the operation units of the redundancy area each time, the data stored in the storage units of each column of the storage area in the P storage arrays can be refreshed in the order of the columns. In order to keep the storage units of the storage area and the storage units of the row redundancy area affected by the threshold voltage drift consistent, the data stored in the storage units of the storage area and the row redundancy area in the P storage arrays can also be refreshed. In this way, the data of all the storage units in the storage area can be refreshed every certain time, which can further ensure the stability of the data stored in the storage units.

[0132] In an implementable manner, each storage array of the storage chip includes a column redundancy area. The storage controller of the storage chip performs a second operation on the N operation units corresponding to the detection column respectively.

[0133] Figure 11 is a control method flowchart of a storage chip provided by the embodiment of the present application, referring to Figure 11 The corresponding second operation includes:

[0134] Step 1101, applying a read voltage to the P storage units in the second operation unit.

[0135] The second operation unit refers to a unit performing the second operation in the redundancy area each time. In an example, one detection column can be included in the column redundancy area in each storage array. The storage controller can sequentially perform the second operation on the operation units on the P storage arrays in the address order of the operation units in the process of sequentially performing the second operation. The interval of the execution time corresponding to two second operations can be T2, and the specific duration of T2 can be set by the technician in advance, which is not limited in the embodiment of the application. In an example, a plurality of detection columns can be included in the column redundancy area in each storage array. The first detection column can be any detection column in the row redundancy area, such as the first detection column. The storage controller can sequentially perform the second operation on each operation unit in the order of the detection columns in the process of sequentially performing the second operation.

[0136] Step 1102: determining whether the failure rate of the second operation unit exceeds a second threshold value according to the number of failed storage units in the P storage units.

[0137] Step 1103: performing refresh on the data in the storage units in the same row as the P storage units in the storage area when the failure rate of the second operation unit exceeds the second threshold value.

[0138] Optionally, when the failure rate of the second operation unit exceeds the second threshold value, the data in the P storage units in the second operation unit and the storage units in the redundancy area in the same row as the P storage units in the first operation unit are refreshed.

[0139] Optionally, each storage unit of the redundancy area stores data corresponding to a low resistance state.

[0140] Optionally, the read voltage includes read voltages of multiple gears, and the storage controller is configured to: after applying the read voltage of the last gear to the P storage units in the second operation unit, determine whether the failure rate of the second operation unit exceeds the second threshold value according to the number of failed storage units in the P storage units in the second operation unit.

[0141] Optionally, when the failure rate of the second operation unit exceeds the second threshold value, the read voltage is applied to the P storage units included in at least one fourth operation unit, and the fourth operation unit is an operation unit in the redundancy area in the same row as the second operation unit. Whether the failure rate of each fourth operation unit exceeds the second threshold value is determined according to the number of failed storage units in the P storage units in each fourth operation unit. When the number of fourth operation units whose failure rate exceeds the second threshold value is greater than a number threshold value, the data in the storage units in the storage area in the same row as the P storage units in the second operation unit is refreshed.

[0142] Optionally, before applying the read voltage to the P storage units included in the second operation unit, the data in the P storage units included in the second operation unit is re-written, and the read voltage is applied to the P storage units included in the second operation unit again. According to the number of failed storage units in the P storage units included in the second operation unit, it is determined whether the failure rate of the second operation unit exceeds the second threshold.

[0143] Optionally, after the second operation is performed on each operation unit of each detection column in the redundancy area, the data in the storage units included in each row in the storage area and the redundancy area is refreshed according to a refresh period.

[0144] Optionally, when the second operation is performed on the M operation units of the first detection column, the refresh number is increased by 1, and then the second operation is continued to be performed on the M operation units. When the refresh number reaches a fourth threshold, the data stored in the storage units of all rows in the storage area is refreshed.

[0145] Optionally, the storage controller is further configured to, after the second operation is performed on the M operation units of the first detection column, continue to perform the second operation on the operation units corresponding to the detection columns after the first detection column until the second operation is performed on the operation units corresponding to the last detection column of the Y detection columns, and then refresh the data stored in the storage units of all columns in the storage area.

[0146] The second operation is described above, and the description of the second operation is similar to the description of the first operation. Therefore, the description of the second operation is not repeated here. Figures 7 to 10 The embodiments corresponding to the second operation are similar to the embodiments of the first operation. For example, the "row" in the embodiments of the first operation can be replaced by "column", the "column" can be replaced by "row", the "first operation unit" can be replaced by "second operation unit", and so on. Therefore, the embodiments corresponding to the second operation can be obtained by replacing the "row" in the embodiments of the first operation by "column", replacing the "column" by "row", and replacing the "first operation unit" by "second operation unit", and so on. Therefore, the embodiments corresponding to the second operation can refer to the embodiments of the first operation. Figures 7 to 10 The embodiments corresponding to the second operation are similar to the embodiments of the first operation. For example, the "row" in the embodiments of the first operation can be replaced by "column", the "column" can be replaced by "row", the "first operation unit" can be replaced by "second operation unit", and so on. Therefore, the embodiments corresponding to the second operation can be obtained by replacing the "row" in the embodiments of the first operation by "column", replacing the "column" by "row", and replacing the "first operation unit" by "second operation unit", and so on. Therefore, the embodiments corresponding to the second operation can refer to the embodiments of the first operation.

[0147] In another implementation manner, each storage array of the storage chip includes a row redundancy area and a column redundancy area. The storage controller of the storage chip performs a first operation on N operation units corresponding to a detection row and performs a second operation on N operation units corresponding to a detection column. The implementation manner can refer to the embodiments of the first operation and the second operation, and the description of the embodiments of the first operation and the second operation is not repeated here. Figures 7 to 11

[0148] ​In the embodiments of the present application, the storage units in the row redundancy area are read to detect the influence of bias drift on the storage units in each column of the storage area, and the storage units in the column redundancy area are read to detect the influence of bias drift on the storage units in each row of the storage area. When it is determined that the storage units in a row or a column are influenced by bias drift to a high degree, the data of the storage units in the row or the column is refreshed to improve the stability of the stored data of the storage units.

[0149] Based on the same inventive concept, the embodiments of the present application also provide a storage controller of a storage chip, which can be the storage controller 200 shown in the storage system 300 shown in Figure 3 The storage controller 200 is connected to the storage chip including P storage arrays, each of which includes M rows and N columns, and P storage units with the same row and column address in the P storage arrays are an operation unit. Each storage array includes a storage area and a redundancy area, and the redundancy area includes a detection row and / or a detection column. The detection row includes N storage units, and the detection column includes M storage units. The storage controller can be used to perform the control method shown in the above embodiments, can detect the degree of threshold voltage drift of the storage units in the storage area through the storage units in the redundancy area, and refresh the data of the storage units in the storage area, so as to improve the stability of the stored data of the storage units.

[0150] Based on the same inventive concept, a storage system is provided, which can be the storage system 300 shown in Figure 3 The storage system includes a storage controller and a storage chip. The storage chip includes P storage arrays, each of which includes M rows and N columns, and P storage units with the same row and column address in the P storage arrays are an operation unit. Each storage array includes a storage area and a redundancy area, and the redundancy area includes a first detection row and / or a first detection column. The first detection row includes N storage units, and the first detection column includes M storage units.

[0151] The storage controller is configured to: perform a first operation on N operation units corresponding to P first detection rows of the P storage arrays respectively, wherein the time interval between two adjacent first operations is T1, and the first operation includes applying a read voltage to the P storage units in the first operation unit. Determine whether the failure rate of the first operation unit exceeds a first threshold value according to the number of failed storage units in the P storage units. When the failure rate of the first operation unit exceeds the first threshold value, refresh the data of the storage units in the storage area that are in the same column as the P storage units. And / or,

[0152] The storage controller is configured to: perform a second operation on the M operation units corresponding to the P first detection columns of the P storage arrays respectively, wherein a time interval between two adjacent second operations is T2, and the second operation comprises: applying a read voltage to the P storage units in the second operation unit. Determine whether the failure rate of the second operation unit exceeds a second threshold according to the number of failed storage units in the P storage units. When the failure rate of the second operation unit exceeds the second threshold, the data in the storage units in the same row as the P storage units in the storage area is refreshed.

[0153] In an implementable manner, the storage controller is configured to: when the failure rate of the first operation unit exceeds the first threshold, refresh the P storage units in the first operation unit and the data in the storage units in the redundancy area which are in the same column as the P storage units in the first operation unit. And / or, when the failure rate of the second operation unit exceeds the second threshold, refresh the P storage units in the second operation unit and the data in the storage units in the redundancy area which are in the same row as the P storage units in the second operation unit.

[0154] In an implementable manner, each storage unit of the redundancy area is in a low resistance state, and the low resistance state corresponds to data 1.

[0155] In an implementable manner, the storage controller is further configured to: when the first operation on the N operation units of the first detection row is completed, increment the refresh count by 1; continue to perform the first operation on the N operation units, and when the refresh count reaches a third threshold, refresh the data stored in the storage units of all columns of the storage area. Or, when the second operation on the M operation units of the first detection column is completed, the refresh count is incremented by 1, and then the second operation on the M operation units is continued, and when the refresh count reaches a fourth threshold, the data stored in the storage units of all rows of the storage area is refreshed.

[0156] In an implementable manner, the redundancy area includes X detection rows and / or Y detection columns, the X detection rows include the first detection row, and the Y detection columns include the first detection column. The storage controller is further configured to: after the first operation on the N operation units of the first detection row is completed, continue to perform the first operation on the operation units corresponding to the detection rows after the first detection row until the first operation on the operation units corresponding to the last detection row of the X detection rows is completed, and then refresh the data stored in the storage units of all columns of the storage area. Or, the storage controller is further configured to: after the second operation on the M operation units of the first detection column is completed, continue to perform the second operation on the operation units corresponding to the detection columns after the first detection column until the second operation on the operation units corresponding to the last detection column of the Y detection columns is completed, and then refresh the data stored in the storage units of all columns of the storage area.

[0157] In an implementable manner, the read voltage includes multiple levels of read voltages, and the storage controller is configured to: after applying the last level of read voltage to the P storage units in the first operation unit, determine whether the failure rate of the first operation unit exceeds the threshold value according to the number of failed storage units in the P storage units in the first operation unit; and / or, after applying the last level of read voltage to the P storage units in the second operation unit, determine whether the failure rate of the second operation unit exceeds the threshold value according to the number of failed storage units in the P storage units in the second operation unit.

[0158] In the storage system provided by the embodiments of the present application, the storage controller included in the storage system can be configured to perform the control method shown in the above embodiments, can detect the degree of threshold voltage drift of the storage units in the storage area through the storage units in the redundancy area, and refresh the data of the storage units in the storage area, so that the stability of the storage units in storing data can be improved.

[0159] The embodiments of the present application also provide a structural schematic diagram of an electronic device, as shown in Figure 12 The electronic device includes a processor and a storage system as described in the above embodiments. The processor is configured to send read-write instructions to the storage system to enable the storage system to perform read-write operations. During the read-write operations performed by the storage system, the storage controller included in the storage system or the control circuit in the storage chip can be configured to perform the control method shown in the above embodiments, can detect the degree of threshold voltage drift of the storage units in the storage area through the storage units in the redundancy area, and refresh the data of the storage units in the storage area, so that the stability of the storage units in storing data can be improved.

[0160] In the present application, the terms "first", "second", and the like are used to distinguish between the same or similar items having substantially the same function and effect, and it should be understood that there is no logical or time sequence dependency between "first" and "second", and the quantity and execution order are not limited. It should also be understood that although the following description uses the terms first, second, and the like to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of various examples, the first operation unit can be referred to as the second operation unit, and similarly, the second operation unit can be referred to as the first operation unit. The first operation unit and the second operation unit can both be collectively referred to as operation units, and in some cases, can refer to different operation units, respectively.

[0161] In the present application, the term "at least one" means one or more, and the term "multiple" means two or more.

[0162] The above description is only the specific implementation of the present application, but the protection scope of the present application is not limited to this, any skilled person in the art can easily think of various equivalent modifications or replacements within the technical range disclosed by the present application, and these modifications or replacements should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A memory controller connected to a memory chip, characterized by, The memory chip comprises P memory arrays, each memory array comprises M rows and N columns, P memory units with the same row and column address in the P memory arrays are an operation unit, each memory array comprises a memory area and a redundant area, the redundant area comprises a first detection row and / or a first detection column, the first detection row comprises N memory units, and the first detection column comprises M memory units; The memory controller is configured to: perform a first operation on N operation units corresponding to P first detection rows of the P memory arrays respectively, wherein a time interval corresponding to two adjacent first operations is T1, and the first operation comprises: applying a read voltage to P memory units in a first operation unit; determining whether a failure rate of the first operation unit exceeds a first threshold value according to a number of failed memory units in the P memory units; when the failure rate of the first operation unit exceeds the first threshold value, performing refresh on data stored in memory units in the same column as the P memory units in the memory area; and / or, The memory controller is configured to: perform a second operation on M operation units corresponding to P first detection columns of the P memory arrays respectively, wherein a time interval corresponding to two adjacent second operations is T2, and the second operation comprises: applying a read voltage to P memory units in a second operation unit; determining whether a failure rate of the second operation unit exceeds a second threshold value according to a number of failed memory units in the P memory units; when the failure rate of the second operation unit exceeds the second threshold value, performing refresh on data stored in memory units in the same row as the P memory units in the memory area.

2. The storage controller of claim 1, wherein, The memory controller is further configured to: when the failure rate of the first operation unit exceeds the first threshold value, performing refresh on P memory units in the first operation unit and data stored in memory units in the redundant area which are in the same column as the P memory units in the first operation unit; and / or, when the failure rate of the second operation unit exceeds the second threshold value, performing refresh on P memory units in the second operation unit and data stored in memory units in the redundant area which are in the same row as the P memory units in the second operation unit.

3. The storage controller of claim 1 or 2, wherein, Each memory unit of the redundant area is in a low resistance state, and the low resistance state corresponds to data 1.

4. The storage controller of any one of claims 1 to 3, wherein, The memory controller is further configured to: when the first operation on the N operation units of the first detection row is completed, incrementing a refresh number by 1; continuing to perform the first operation on the N operation units, and when the refresh number reaches a third threshold value, performing refresh on data stored in all columns of the memory area; or when the second operation on the M operation units of the first detection column is completed, then the refresh number is incremented by 1, and then the second operation on the M operation units is continued, and when the refresh number reaches a fourth threshold value, then refresh is performed on data stored in all rows of the memory area.

5. The storage controller of any one of claims 1 to 3, wherein, The redundant area includes X detection rows and / or Y detection columns, the X detection rows include the first detection row, and the Y detection columns include the first detection column; The storage controller is further configured to, after the N operation units of the first detection row complete the first operation, continue to perform the first operation on operation units corresponding to detection rows after the first detection row until the operation units corresponding to the last detection row of the X detection rows complete the first operation, and then perform refresh on data stored in storage units of all columns of the storage area; or The storage controller is further configured to, after the M operation units of the first detection column complete the second operation, continue to perform the second operation on operation units corresponding to detection columns after the first detection column until the operation units corresponding to the last detection column of the Y detection columns complete the second operation, and then perform refresh on data stored in storage units of all columns of the storage area.

6. The storage controller of any one of claims 1 to 3, wherein, The read voltage includes read voltages of multiple gears, and the storage controller is configured to: after applying the read voltage of the last gear to the P storage units in the first operation unit, determine whether the failure rate of the first operation unit exceeds a threshold according to the number of failed storage units in the P storage units in the first operation unit; and / or after applying the read voltage of the last gear to the P storage units in the second operation unit, determine whether the failure rate of the second operation unit exceeds a threshold according to the number of failed storage units in the P storage units in the second operation unit. The storage chip includes P storage arrays, each storage array includes M rows and N columns, P storage units with the same row and column address in the P storage arrays are an operation unit, each storage array includes a storage area and a redundant area, the redundant area includes a first detection row and / or a first detection column, the first detection row includes N storage units, and the first detection column includes M storage units, and the method includes:

7. A control method of a memory chip, characterized by, performing a first operation on N operation units corresponding to P first detection rows of the P storage arrays respectively, wherein the time interval corresponding to adjacent two times of the first operation is T1, and the first operation includes: applying a read voltage to the P storage units in the first operation unit; determining whether the failure rate of the first operation unit exceeds a first threshold according to the number of failed storage units in the P storage units; when the failure rate of the first operation unit exceeds the first threshold, refreshing data in storage units in the same column as the P storage units in the storage area; and / or performing a second operation on M operation units corresponding to P first detection columns of the P storage arrays respectively, wherein the time interval corresponding to adjacent two times of the second operation is T2, and the second operation includes: applying a read voltage to the P storage units in the second operation unit; determining whether the failure rate of the second operation unit exceeds a second threshold according to the number of failed storage units in the P storage units; and / or ​ When the failure rate of the second operation unit exceeds the second threshold, data in the P storage units in the second operation unit and in the storage units in the redundancy area which are in the same row as the P storage units in the second operation unit are refreshed.

8. The method of claim 7, wherein, The method further comprises: When the failure rate of the first operation unit exceeds the first threshold, data in the P storage units in the first operation unit and in the storage units in the redundancy area which are in the same column as the P storage units in the first operation unit are refreshed; and / or, When the failure rate of the second operation unit exceeds the second threshold, data in the P storage units in the second operation unit and in the storage units in the redundancy area which are in the same row as the P storage units in the second operation unit are refreshed.

9. The method according to claim 7 or 8, characterized in that, Each storage unit in the redundancy area is in a low resistance state, and the low resistance state corresponds to data 1.

10. The method according to any one of claims 7 to 9, characterized in that, The method further comprises: When the first operation on the N operation units in the first detection row is completed, the number of refreshes is increased by 1, and the first operation is continued to be performed on the N operation units; when the number of refreshes reaches a third threshold, data stored in all columns of storage units in the storage area are refreshed; or, When the second operation on the M operation units in the first detection column is completed, the number of refreshes is increased by 1, and the second operation is continued to be performed on the M operation units; when the number of refreshes reaches a fourth threshold, data stored in all rows of storage units in the storage area are refreshed.

11. The method according to any one of claims 7 to 9, characterized in that, The redundancy area comprises X detection rows and / or Y detection columns, the X detection rows comprise the first detection row, and the Y detection columns comprise the first detection column, and the method further comprises: When the first operation on the N operation units in the first detection row is completed, the first operation is continued to be performed on operation units corresponding to detection rows after the first detection row, until the first operation on operation units corresponding to a last detection row of the X detection rows is completed, and data stored in all columns of storage units in the storage area are refreshed; or, When the second operation on the M operation units in the first detection column is completed, the second operation is continued to be performed on operation units corresponding to detection columns after the first detection column, until the second operation on operation units corresponding to a last detection column of the Y detection columns is completed, and data stored in all columns of storage units in the storage area are refreshed.

12. The method according to any one of claims 7 to 9, characterized in that, The read voltage comprises read voltages of multiple gears, and the determination of whether the failure rate of the first operation unit exceeds the first threshold according to the number of failed storage units in the P storage units comprises: The determination of whether the failure rate of the first operation unit exceeds the threshold according to the number of failed storage units in the P storage units in the first operation unit after the last-gear read voltage is applied to the P storage units in the first operation unit; The determination of whether the failure rate of the second operation unit exceeds the second threshold according to the number of failed storage units in the P storage units comprises: According to a number of failed storage units in the P storage units in the second operation unit after applying the last gear read voltage to the P storage units in the second operation unit, it is determined whether the failure rate of the second operation unit exceeds a threshold value.

13. A storage system, characterized by The storage system comprises a storage controller and a storage chip, the storage chip comprises P storage arrays, each storage array comprises M rows and N columns, P storage units with the same row and column address in the P storage arrays are an operation unit, each storage array comprises a storage area and a redundant area, the redundant area comprises a first detection row and / or a first detection column, the first detection row comprises N storage units, and the first detection column comprises M storage units; The storage controller is configured to: perform a first operation on N operation units corresponding to P first detection rows of the P storage arrays respectively, wherein a time interval corresponding to two adjacent first operations is T1, and the first operation comprises: applying a read voltage to P storage units in a first operation unit; determining whether a failure rate of the first operation unit exceeds a first threshold value according to a number of failed storage units in the P storage units; when the failure rate of the first operation unit exceeds the first threshold value, refreshing data stored in storage units in the same column as the P storage units in the storage area; and / or, The storage controller is configured to: perform a second operation on M operation units corresponding to P first detection columns of the P storage arrays respectively, wherein a time interval corresponding to two adjacent second operations is T2, and the second operation comprises: applying a read voltage to P storage units in a second operation unit; determining whether a failure rate of the second operation unit exceeds a second threshold value according to a number of failed storage units in the P storage units; when the failure rate of the second operation unit exceeds the second threshold value, refreshing data stored in storage units in the same row as the P storage units in the storage area. The storage controller is configured to: when the failure rate of the first operation unit exceeds the first threshold value, refreshing data stored in the P storage units in the first operation unit and storage units in the redundant area in the same column as the P storage units in the first operation unit; and / or, 14. The storage system of claim 13, wherein, when the failure rate of the second operation unit exceeds the second threshold value, refreshing data stored in the P storage units in the second operation unit and storage units in the redundant area in the same row as the P storage units in the second operation unit. Each storage unit in the redundant area is in a low resistance state, and the low resistance state corresponds to data 1. The storage controller is further configured to: when the first operation on the N operation units of the first detection row is completed, incrementing a refresh number by 1; continuing to perform the first operation on the N operation units, and when the refresh number reaches a third threshold value, refreshing data stored in all columns of the storage area; or, 15. The storage system of claim 13 or 14, wherein, when the second operation on the M operation units of the first detection column is completed, incrementing the refresh number by 1; continuing to perform the second operation on the M operation units, and when the refresh number reaches a fourth threshold value, refreshing data stored in all rows of the storage area.

16. The storage system of any one of claims 13 to 15, wherein, ​ ​ When the second operation is performed on the M operation units of the first detection column, the refresh number is increased by 1, and then the second operation is continuously performed on the M operation units; when the refresh number reaches a fourth threshold, the data stored in the storage units of all rows of the storage area is refreshed.

17. The storage system of any one of claims 13 to 15, wherein, The redundant area includes X detection rows and / or Y detection columns, the X detection rows include the first detection row, and the Y detection columns include the first detection column. The storage controller is further configured to, after the first operation is performed on the N operation units of the first detection row, continue to perform the first operation on the operation units corresponding to the detection rows after the first detection row until the first operation is performed on the operation units corresponding to the last detection row of the X detection rows, and then refresh the data stored in the storage units of all columns of the storage area; or The storage controller is further configured to, after the second operation is performed on the M operation units of the first detection column, continue to perform the second operation on the operation units corresponding to the detection columns after the first detection column until the second operation is performed on the operation units corresponding to the last detection column of the Y detection columns, and then refresh the data stored in the storage units of all columns of the storage area.

18. The storage system of any one of claims 13 to 15, wherein, The read voltage includes multiple levels of read voltages, and the storage controller is configured to: After the last level of read voltage is applied to the P storage units in the first operation unit, determine whether the failure rate of the first operation unit exceeds a threshold according to the number of failed storage units in the P storage units in the first operation unit; and / or, After the last level of read voltage is applied to the P storage units in the second operation unit, determine whether the failure rate of the second operation unit exceeds a threshold according to the number of failed storage units in the P storage units in the second operation unit.

19. An electronic device, comprising: The electronic device includes a processor and a storage system as claimed in any one of claims 13 to 18; The processor is configured to send read-write instructions to the storage system to enable the storage system to perform read-write operations. The processor is configured to send read-write instructions to the storage system to enable the storage system to perform read-write operations.

Images