Programmable frequency divider, phase-locked loop circuit, chip and electronic device thereof

Abstract

The application provides a programmable frequency divider, a phase-locked loop circuit, a chip and an electronic device, and the programmable frequency divider comprises: a frequency division module, which comprises n frequency division unit cascades, each frequency division unit is controlled by shielding based on a respective reset signal and is controlled by frequency division based on a respective frequency division control bit and a mode input signal, so as to perform frequency division operation on a respective input clock, wherein n is a natural number greater than 1; a control module, which is connected with the frequency division control end and the reset end of each frequency division unit in the frequency division module, and is used for providing a corresponding frequency division control bit and a corresponding reset signal to each frequency division unit; and an output sampling module, which is connected with the mode output end of the second frequency division unit in the frequency division module, and samples the mode output signal of the second frequency division unit based on the input clock of the first frequency division unit to obtain a final frequency division clock. The application solves the problem that the existing programmable frequency divider cannot realize a wide frequency division range.

Description

Technical Field

[0001] This invention relates to the fields of electronic communication and signal processing, and in particular to a programmable frequency divider, a phase-locked loop circuit, a chip, and electronic devices thereof. Background Technology

[0002] A phase-locked loop (PLL) circuit is a feedback control circuit used to keep the phase of the output signal synchronized with the phase of the input signal. A programmable frequency divider is a circuit device that can divide the input signal according to a user-defined division ratio. As a commonly used component of a PLL circuit, the programmable frequency divider performs variable frequency division on the clock signal.

[0003] In existing technologies, programmable frequency dividers are implemented by cascading n (n≥2) divide-by-2 / divide-by-3 frequency divider units, and their frequency division range is 2. n ~2 n+1 -1 is insufficient for applications requiring a wide frequency division range. Furthermore, extending the frequency division range necessitates designing complex output selection circuits, increasing hardware complexity and leading to higher power consumption and area costs.

[0004] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a programmable frequency divider, a phase-locked loop circuit, a chip and electronic equipment thereof, to solve the problem that existing programmable frequency dividers cannot achieve a wide frequency division range.

[0006] To achieve the above and other related objectives, the present invention provides a programmable frequency divider, comprising:

[0007] The frequency divider module includes n cascaded frequency divider units. Each frequency divider unit performs shielding control based on its own reset signal and frequency division control based on its own frequency division control bit and mode input signal to perform frequency division operation on its own input clock, where n is a natural number greater than 1.

[0008] The control module is connected to the frequency division control terminal and reset terminal of each level of the frequency division unit in the frequency division module, and is used to provide the corresponding frequency division control bit and the corresponding reset signal to each level of the frequency division unit;

[0009] The output sampling module is connected to the mode output terminal of the second-stage frequency divider unit in the frequency divider module. It samples the mode output signal of the second-stage frequency divider unit based on the input clock of the first-stage frequency divider unit to obtain the final frequency divider clock.

[0010] Optionally, the frequency division unit includes a divide-by-2 / divide-by-3 frequency division unit, wherein:

[0011] The divide-by-2 / divide-by-3 frequency divider unit operates when the reset signal is at the first potential and is disabled when the reset signal is at the second potential; when the divide-by-2 / divide-by-3 frequency divider unit is disabled, the corresponding output clock and mode output signal are both at the first potential;

[0012] The divide-by-2 / divide-by-3 frequency division unit performs a divide-by-three operation when both the frequency division control bit and the mode input signal are at the first potential, and performs a divide-by-two operation when at least one of the frequency division control bit and the mode input signal is at the second potential.

[0013] Optionally, the first potential includes a high potential, and the second potential includes a low potential.

[0014] Optionally, the divide-by-2 / divide-by-3 frequency divider unit includes a first D flip-flop, a second D flip-flop, a first NAND gate, a second NAND gate, a first AND gate, a first inverter, and a second inverter, wherein:

[0015] The clock inputs of the first D flip-flop and the second D flip-flop are connected to each other and serve as the clock inputs of the divide-by-2 / divide-by-3 frequency divider unit. The reset inputs of the first D flip-flop and the second D flip-flop are connected to each other and serve as the reset inputs of the divide-by-2 / divide-by-3 frequency divider unit. The data input of the first D flip-flop is connected to the output of the first NAND gate. The non-inverting output of the first D flip-flop is connected to the first input of the second NAND gate. The data input of the second D flip-flop is connected to the output of the second NAND gate. The non-inverting output of the second D flip-flop is connected to the second input of the second NAND gate and serves as the clock output of the divide-by-2 / divide-by-3 frequency divider unit via the first inverter. The non-inverting output of the second D flip-flop is also connected to the first input of the first AND gate via the second inverter. The second input of the first AND gate serves as the mode input of the divide-by-2 / divide-by-3 frequency divider unit. The output of the first AND gate serves as the mode output of the divide-by-2 / divide-by-3 frequency divider unit and is connected to the first input of the first NAND gate. The second input of the first NAND gate serves as the frequency division control input of the divide-by-2 / divide-by-3 frequency divider unit.

[0016] Optionally, the first D flip-flop and the second D flip-flop are implemented using a static transmission gate structure D flip-flop; the static transmission gate structure D flip-flop is referred to as a static D flip-flop, and when the static D flip-flop is reset, its non-inverting output terminal is set to the second potential.

[0017] Optionally, the static D flip-flop includes a third inverter, a fourth inverter, a third NAND gate, a first transmission gate, a first latch, a second transmission gate, a second latch, an output inverter, and a first reset control unit, wherein:

[0018] The input terminal of the third inverter serves as the clock terminal of the static D flip-flop to receive the corresponding input clock, and the output terminal of the third inverter outputs an inverted clock.

[0019] The input terminal of the fourth inverter serves as the reset terminal of the static D flip-flop to receive the corresponding reset signal, and the output terminal of the fourth inverter outputs an inverted reset signal.

[0020] The first input terminal of the third NAND gate serves as the data terminal of the static D flip-flop. The second input terminal of the third NAND gate is connected to the reset terminal of the static D flip-flop. The output terminal of the third NAND gate is connected to the input terminal of the output inverting section via the first transmission gate, the first latch, the second transmission gate, and the second latch in sequence. The output terminal of the output inverting section serves as the non-inverting output terminal of the static D flip-flop.

[0021] The first transmission gate is turned on when the input clock is at the second potential and turned off when the input clock is at the first potential;

[0022] The first latching unit inverts its input signal when the first transmission gate is turned on, and latches the input signal when the first transmission gate is turned off.

[0023] The second transmission gate is turned on when the input clock is at the first potential and turned off when the input clock is at the second potential;

[0024] The second latching unit inverts its input signal when the second transmission gate is turned on, and latches the input signal when the second transmission gate is turned off;

[0025] The output inverting section is used to invert its input signal and output it in phase.

[0026] The first reset control section is connected to the first latch section and the second transmission gate respectively, and performs a reset operation on the static D flip-flop based on the reset signal.

[0027] Optionally, the first reset control unit includes a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor, wherein:

[0028] The gate of the first PMOS transistor is connected to the reset terminal of the static D flip-flop to receive the reset signal. The source of the first PMOS transistor is connected to the power supply voltage. The drain of the first PMOS transistor is connected to the input terminal of the first latch. The gate of the first NMOS transistor receives the inverted reset signal. The source of the first NMOS transistor is connected to reference ground. The drain of the first NMOS transistor is connected to the input terminal of the second transmission gate. The gate of the second NMOS transistor receives the inverted reset signal. The source of the second NMOS transistor is connected to reference ground. The drain of the second NMOS transistor is connected to the output terminal of the second transmission gate.

[0029] Optionally, the divide-by-2 / divide-by-3 frequency divider unit includes a third D flip-flop, a fourth D flip-flop, a second AND gate, a third AND gate, and a fourth NAND gate, wherein:

[0030] The clock inputs of the third and fourth D flip-flops are connected to each other and serve as the clock inputs of the divide-by-2 / divide-by-3 frequency divider unit. The reset inputs of the third and fourth D flip-flops are connected to each other and serve as the reset inputs of the divide-by-2 / divide-by-3 frequency divider unit. The data input of the third D flip-flop is connected to the output of the second AND gate. The non-inverting output of the third D flip-flop serves as the mode output of the divide-by-2 / divide-by-3 frequency divider unit and is connected to the first input of the fourth NAND gate. The inverting output of the third D flip-flop is left floating. The data terminal of the fourth D flip-flop is connected to the output terminal of the third AND gate. The non-inverting output terminal of the fourth D flip-flop serves as the clock output terminal of the divide-by-2 / divide-by-3 frequency divider unit and is connected to the first input terminal of the second AND gate. The inverting output terminal of the fourth D flip-flop is connected to the first input terminal of the third AND gate. The second input terminal of the second AND gate serves as the mode input terminal of the divide-by-2 / divide-by-3 frequency divider unit. The second input terminal of the fourth NAND gate serves as the frequency division control terminal of the divide-by-2 / divide-by-3 frequency divider unit. The output terminal of the fourth NAND gate is connected to the second input terminal of the third AND gate.

[0031] Optionally, the third D flip-flop and the fourth D flip-flop are implemented using a true single-phase clock structure D flip-flop; the true single-phase clock structure D flip-flop is referred to as a dynamic D flip-flop, and when the dynamic D flip-flop is reset, its non-inverting output terminal is set to the first potential.

[0032] Optionally, the dynamic D flip-flop includes a fifth inverter, a first-stage inverting section, a second-stage inverting section, a third-stage inverting section, an output stage inverting section, and a second reset control section, wherein:

[0033] The input terminal of the fifth inverter serves as the reset terminal of the dynamic D flip-flop to receive the corresponding reset signal, and the output terminal of the fifth inverter outputs an inverted reset signal.

[0034] The first-stage inverting section includes a clock terminal and a data terminal of the dynamic D flip-flop to receive the corresponding input clock and input signal respectively, and samples the input signal based on the input clock to obtain a first voltage;

[0035] The second-stage inverting section is connected to the first-stage inverting section, and obtains the second voltage based on the input clock and the first voltage;

[0036] The third-stage inverting section is connected to the second-stage inverting section, and obtains the third voltage based on the input clock and the second voltage;

[0037] The output stage inverting section is connected to the third stage inverting section, including the non-inverting output terminal and the inverting output terminal of the dynamic D flip-flop, and outputs the third voltage inverted.

[0038] The second reset control section is connected to the second-stage inverting section and the third-stage inverting section respectively, and performs a reset operation on the dynamic D flip-flop based on the reset signal.

[0039] Optionally, the second reset control unit includes a second PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor, wherein:

[0040] The gate of the second PMOS transistor is connected to the reset terminal of the dynamic D flip-flop to receive the reset signal. The source of the second PMOS transistor is connected to the power supply voltage, and the drain of the second PMOS transistor is connected to the output terminal of the second-stage inverting section. The third NMOS transistor is connected between the second-stage inverting section and the reference ground. The gate of the third NMOS transistor is connected to the reset terminal of the dynamic D flip-flop to receive the reset signal. The gate of the fourth NMOS transistor receives the inverted reset signal. The source of the fourth NMOS transistor is connected to the reference ground, and the drain of the fourth NMOS transistor is connected to the output terminal of the third-stage inverting section.

[0041] Optionally, when the number of frequency division units is equal to two, the control module includes a first control unit for providing three frequency division control bits and a total reset signal, wherein the least significant frequency division control bit and the second least significant frequency division control bit are respectively connected to the frequency division control terminals of the first-level frequency division unit and the second-level frequency division unit, and the total reset signal and the most significant frequency division control bit are respectively connected to the reset terminals of the first-level frequency division unit and the second-level frequency division unit.

[0042] Optionally, when the number of frequency division units is greater than two, the control module includes a first control unit and a second control unit, wherein:

[0043] The first control unit is used to provide (n+1) frequency division control bits and a total reset signal, wherein the least significant frequency division control bit to the second most significant frequency division control bit are respectively connected to the frequency division control terminals of the first-level frequency division unit to the nth-level frequency division unit, the total reset signal is connected to the reset terminal of the first-level frequency division unit, and the most significant frequency division control bit is connected to the reset terminal of the nth-level frequency division unit.

[0044] The second control unit obtains the reset signal of the (i-1)th level frequency divider unit based on the frequency divider control bit and reset signal of the i-th level frequency divider unit, where i is a natural number greater than 2 and less than or equal to n.

[0045] Optionally, the second control unit is implemented using (n-2) OR gates.

[0046] Optionally, the output sampling module includes a buffer and a fifth D flip-flop, wherein:

[0047] The data terminal of the fifth D flip-flop is connected to the mode output terminal of the second-stage frequency divider unit, the clock terminal of the fifth D flip-flop receives the input clock of the first-stage frequency divider unit, and the non-inverting output terminal of the fifth D flip-flop outputs the final frequency-divided clock.

[0048] The present invention also provides a phase-locked loop circuit, including the programmable frequency divider as described in any of the above claims.

[0049] The present invention also provides a chip including the phase-locked loop circuit described above.

[0050] The present invention also provides an electronic device comprising the chip described above.

[0051] As described above, the programmable frequency divider, phase-locked loop circuit, chip, and electronic device of the present invention propose a variable continuous integer frequency division scheme, which can divide the frequency range from 2... n ~2 n+1 -1 expands downwards to 2~2 n+1 -1 significantly widens the frequency division range, increases flexibility, and is simple and easy to implement. The frequency division module uses multiple cascaded frequency division units. By cooperating with the control module to control the shielding of each frequency division unit, the effective number of cascaded frequency division units in the frequency division module can be set, enabling different integer frequency division designs and effectively controlling the changes in the frequency division range, thus achieving flexible frequency division. The output sampling module samples the mode output signal of the second-stage frequency division unit based on the input clock of the first-stage frequency division unit to obtain the final frequency division clock, which can achieve better noise performance. Attached Figure Description

[0052] Figure 1 The diagram shown is a schematic representation of the programmable frequency divider in an embodiment of the present invention.

[0053] Figure 2 The diagram shown is a structural schematic of a divide-by-2 / divide-by-3 frequency divider unit in an embodiment of the present invention.

[0054] Figure 3 The diagram shown is a structural schematic of a static D flip-flop in an embodiment of the present invention.

[0055] Figure 4 This is a schematic diagram of another structure of the divide-by-2 / divide-by-3 frequency divider unit in an embodiment of the present invention.

[0056] Figure 5 The diagram shown is a schematic representation of the structure of a dynamic D flip-flop in an embodiment of the present invention.

[0057] Figure 6 The diagram shown is a structural schematic of a control module in an embodiment of the present invention.

[0058] Figure 7 This is a schematic diagram of another structure of the control module in an embodiment of the present invention.

[0059] Figure 8 The diagram shown is a structural schematic of the output sampling module in an embodiment of the present invention.

[0060] Figure 9 Displayed as Figure 7 Timing diagrams of key nodes in the corresponding programmable frequency divider.

[0061] Component designation explanation

[0062] 10 Programmable frequency divider 100 Frequency divider module 110 Frequency division unit 111 Static D flip-flop 111a First latch section 111b Second latch section 111c Output inverting part 111d First Reset Control Unit 112 Dynamic D flip-flop 112a First-stage phase inversion part 112b Second-stage inversion part 112c Third-stage phase inversion part 112d Output stage inverting part 112e Second reset control unit 200 Control module 210 First control unit 220 Second control unit 300 Output sampling module Detailed Implementation

[0063] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0064] Please see Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0065] like Figure 1 As shown, this embodiment provides a programmable frequency divider 10, including a frequency divider module 100, a control module 200, and an output sampling module 300.

[0066] The frequency divider module 100 includes n cascaded frequency divider units 110. Each frequency divider unit 110 performs shielding control based on its own reset signal and frequency division control based on its own frequency division control bit and mode input signal to perform frequency division operation on its own input clock, where n is a natural number greater than 1.

[0067] It should be noted that when n frequency divider units 110 are cascaded, the clock output terminal (i.e., Fout terminal) of the previous frequency divider unit 110 is connected to the clock input terminal (i.e., Fin terminal) of the next frequency divider unit 110, and the mode output terminal (i.e., MODout terminal) of the next frequency divider unit 110 is connected to the mode input terminal (i.e., MODin terminal) of the previous frequency divider unit 110. In addition, the clock input terminal (i.e., Fin terminal) of the first frequency divider unit 110 receives the external clock CKIN, which can also be called the clock to be divided, and the mode input terminal (i.e., MODin terminal) of the nth frequency divider unit 110 receives the external potential TIEH, where the external potential TIEH is the first potential.

[0068] For any level frequency divider unit 110, the clock input terminal (i.e., Fin terminal) corresponds to the input clock, the clock output terminal (i.e., Fout terminal) corresponds to the output clock, the mode input terminal (i.e., MODin terminal) corresponds to the mode input signal, the mode output terminal (i.e., MODout terminal) corresponds to the mode output signal, the frequency divider control terminal (i.e., P terminal) corresponds to the frequency divider control bit, and the reset terminal (i.e., RSTN terminal) corresponds to the reset signal.

[0069] In this embodiment, the frequency divider unit 110 includes a 2 / 3 divider unit. Specifically: the 2 / 3 divider unit operates when the reset signal is at a first potential and is disabled when the reset signal is at a second potential; when the 2 / 3 divider unit is disabled, both the corresponding output clock and mode output signal are at the first potential; when the 2 / 3 divider unit operates, it divides the input clock by two or three to adjust the output clock and mode output signal. Furthermore, the 2 / 3 divider unit performs a three-way division when both the frequency division control bit and the mode input signal are at the first potential, and performs a two-way division when at least one of the frequency division control bit and the mode input signal is at the second potential. As an optional configuration, the first potential includes a high potential (also called a high level), and the second potential includes a low potential (also called a low level).

[0070] By implementing shielding and frequency division control for each level of frequency divider unit 110, different integer frequency division designs can be achieved, thereby effectively widening the frequency division range. In practical applications, when shielding each level of frequency divider unit 110, the shielding is performed sequentially from the nth level to the first level. For example, when there is only one unit to be shielded, the nth level frequency divider unit 110 is shielded; when there are two units to be shielded, the nth level frequency divider unit 110 and the (n-1)th level frequency divider unit 110 are shielded; when there are three units to be shielded, the nth level frequency divider unit 110, the (n-1)th level frequency divider unit 110, and the (n-2)th level frequency divider unit 110 are shielded, and so on. This allows for the shielding of any number of frequency divider units 110.

[0071] As an example, such as Figure 2 As shown, the divide-by-2 / divide-by-3 frequency divider unit includes a first D flip-flop DFF1, a second D flip-flop DFF2, a first NAND gate NAND1, a second NAND gate NAND2, a first AND gate AND1, a first inverter INV1, and a second inverter INV2. Wherein: the clock input (i.e., CK input) of the first D flip-flop DFF1 and the clock input (i.e., CK input) of the second D flip-flop DFF2 are connected to each other and serve as the clock input (i.e., Fin input) of the divide-by-2 / divide-by-3 frequency divider unit to receive the corresponding input clock; the reset input (i.e., RSTN input) of the first D flip-flop DFF1 and the reset input (i.e., RSTN input) of the second D flip-flop DFF2 are connected to each other and serve as the reset input (i.e., RSTN input) of the divide-by-2 / divide-by-3 frequency divider unit to receive the corresponding reset signal; the data input (i.e., D input) of the first D flip-flop DFF1 is connected to the output of the first NAND gate NAND1; the non-inverting output (i.e., Q input) of the first D flip-flop DFF1 is connected to the first input of the second NAND gate NAND2; the data input (i.e., D input) of the second D flip-flop DFF2 is connected to the output of the second NAND gate NAND2; the second D flip-flop DFF2... The non-inverting output (i.e., Q) is connected to the second input of the second NAND gate NAND2 and the input of the first inverter INV1. The non-inverting output (i.e., Q) of the second D flip-flop DFF2 is also connected to the first input of the first AND gate AND1 via the second inverter INV2. The second input of the first AND gate AND1 serves as the mode input (i.e., MODin) of the divide-by-2 / divide-by-3 frequency divider unit to receive the corresponding mode input signal. The output of the first AND gate AND1 serves as the mode output (i.e., MODout) of the divide-by-2 / divide-by-3 frequency divider unit and is connected to the first input of the first NAND gate NAND1. The second input of the first NAND gate NAND1 serves as the frequency division control (i.e., P) of the divide-by-2 / divide-by-3 frequency divider unit to receive the corresponding frequency division control bit. The output of the first inverter INV1 serves as the clock output (i.e., Fout) of the divide-by-2 / divide-by-3 frequency divider unit.

[0072] It is important to note that a D flip-flop (DFF) is a synchronous flip-flop that can update the output signal according to the state of the input signal under the control of a clock signal. The main function of a D flip-flop is to "latch" the state of the input signal to the output terminal until the next clock signal arrives.

[0073] In one embodiment, the first D flip-flop DFF1 and the second D flip-flop DFF2 are implemented using a static transmission gate structure to enable operation at lower frequencies. However, this structure requires a large number of components, has a large layout area, and consumes more power. The static transmission gate structure D flip-flop is referred to as static D flip-flop 111. When static D flip-flop 111 is reset, its non-inverting output terminal (i.e., Q terminal) is set to a second potential, for example, a low potential. In this embodiment, static D flip-flop 111 includes a third inverter INV3, a fourth inverter INV4, a third NAND gate NAND3, a first transmission gate TG1, a first latch 111a, a second transmission gate TG2, a second latch 111b, an output inverter 111c, and a first reset control unit 111d, as shown below. Figure 3 As shown. Wherein:

[0074] The input of the third inverter INV3 serves as the clock input (i.e., CK input) of the static D flip-flop 111 to receive the corresponding input clock, and the output of the third inverter INV3 outputs the inverted clock CKN; the input of the fourth inverter INV4 serves as the reset input (i.e., RSTN input) of the static D flip-flop 111 to receive the corresponding reset signal, and the output of the fourth inverter INV4 outputs the inverted reset signal RST; the first input of the third NAND gate NAND3 serves as the data input (i.e., D input) of the static D flip-flop 111, the second input of the third NAND gate NAND3 is connected to the reset input (i.e., RSTN input) of the static D flip-flop 111, and the output of the third NAND gate NAND3 is connected to the input of the output inverting section 111c in sequence via the first transmission gate TG1, the first latch 111a, the second transmission gate TG2, and the second latch 111b, and the output of the output inverting section 111c serves as the non-inverted output (i.e., Q input) of the static D flip-flop 111.

[0075] The first transmission gate TG1 is turned on when the input clock is at a second potential (e.g., a low potential) and turned off when the input clock is at a first potential (e.g., a high potential). Specifically, the first transmission gate TG1 is implemented using two complementary transistors connected in parallel, for example, using a PMOS transistor (i.e., a P-channel metal-oxide-semiconductor field-effect transistor) and an NMOS transistor (i.e., an N-channel metal-oxide-semiconductor field-effect transistor) connected in parallel. The PMOS transistor is controlled to turn on or off by the input clock, and the NMOS transistor is controlled to turn on or off by an inverted clock, so as to control the conduction or cutoff of the first transmission gate TG1.

[0076] The second transmission gate TG2 is turned on when the input clock is at a first potential (e.g., a high potential) and turned off when the input clock is at a second potential (e.g., a low potential). Specifically, the second transmission gate TG2 is implemented using two complementary transistors connected in parallel, for example, using a PMOS transistor and an NMOS transistor connected in parallel. The PMOS transistor is controlled to turn on or off by an inverting clock, and the NMOS transistor is controlled to turn on or off by the input clock, so as to control the conduction or cutoff of the second transmission gate TG2.

[0077] The first latch unit 111a inverts its input signal and outputs it when the first transmission gate TG1 is turned on, and latches the input signal when the first transmission gate TG1 is turned off. Specifically, the first latch unit 111a includes a sixth inverter INV6, a seventh inverter INV7, and a third transmission gate TG3. The input terminal of the sixth inverter INV6 serves as the input terminal of the first latch unit 111a and is connected to the output terminal of the first transmission gate TG1. The output terminal of the sixth inverter INV6 serves as the output terminal of the first latch unit 111a and is connected to the input terminal of the third transmission gate TG3 via the seventh inverter INV7. The output terminal of the third transmission gate TG3 is connected to the input terminal of the sixth inverter INV6. The third transmission gate TG3 is turned on when the input clock is at a first potential (e.g., a high potential) and turned off when the input clock is at a second potential (e.g., a low potential). Its structure is the same as that of the second transmission gate TG2, so it will not be described again here.

[0078] The second latch unit 111b inverts its input signal when the second transmission gate TG2 is turned on, and latches the input signal when the second transmission gate TG2 is turned off. Specifically, the second latch unit 111b includes an eighth inverter INV8, a ninth inverter INV9, and a fourth transmission gate TG4. The input terminal of the eighth inverter INV8 serves as the input terminal of the second latch unit 111b and is connected to the output terminal of the second transmission gate TG2. The output terminal of the eighth inverter INV8 serves as the output terminal of the second latch unit 111b and is connected to the input terminal of the fourth transmission gate TG4 via the ninth inverter INV9. The output terminal of the fourth transmission gate TG4 is connected to the input terminal of the eighth inverter INV8. The fourth transmission gate TG4 is turned on when the input clock is at a second potential (e.g., a low potential) and turned off when the input clock is at a first potential (e.g., a high potential). Its structure is the same as that of the first transmission gate TG1, so it will not be described again here.

[0079] The output inverting section 111c is used to invert its input signal and output it. Specifically, the output inverting section 111c includes a tenth inverter INV10, wherein: the input terminal of the tenth inverter INV10 serves as the input terminal of the output inverting section 111c and is connected to the output terminal of the second latch section 111b, and the output terminal of the tenth inverter INV10 serves as the non-inverting output terminal of the static D flip-flop 111.

[0080] The first reset control unit 111d is connected to the first latch unit 111a and the second transmission gate TG2 respectively. It performs a reset operation on the static D flip-flop 111 based on the reset signal to achieve shielding control. Specifically, the first reset control unit 111d includes a first PMOS transistor MP1, a first NMOS transistor MN1, and a second NMOS transistor MN2, wherein: the gate terminal of the first PMOS transistor MP1 is connected to the reset terminal of the static D flip-flop 111 to receive the reset signal RSTN; the source terminal of the first PMOS transistor MP1 is connected to the power supply voltage; the drain terminal of the first PMOS transistor MP1 is connected to the input terminal of the first latch unit 111a (i.e., the input terminal of the sixth inverter INV6); the gate terminal of the first NMOS transistor MN1 receives the inverted reset signal RST; the source terminal of the first NMOS transistor MN1 is connected to the reference ground; the drain terminal of the first NMOS transistor MN1 is connected to the input terminal of the second transmission gate TG2; the gate terminal of the second NMOS transistor MN2 receives the inverted reset signal RST; the source terminal of the second NMOS transistor MN2 is connected to the reference ground; and the drain terminal of the second NMOS transistor MN2 is connected to the output terminal of the second transmission gate TG2.

[0081] When the static D flip-flop 111 is reset, the reset signal RSTN is at the second potential, for example, a low potential, and the inverting reset signal RST is at the first potential, for example, a high potential. At this time, the first PMOS transistor MP1, the first NMOS transistor MN1, and the second NMOS transistor MN2 are all turned on, and their non-inverting output terminals are set to the second potential, for example, a low potential. This sets the clock output terminal (i.e., Fout terminal) of the divide-by-2 / divide-by-3 frequency divider unit to the first potential, for example, a high potential. Since the mode input signal connected to the mode input terminal (i.e., MODin terminal) is at the first potential, for example, a high potential, its mode output terminal (i.e., MODout terminal) is also set to the first potential, for example, a high potential. In this way, the shielding of the divide-by-2 / divide-by-3 frequency divider unit is achieved. It should be noted that if the currently shielded divider unit (excluding 2 / 3) is the nth level divider unit, the mode input terminal (i.e., MODin terminal) of the nth level divider unit is connected to the external potential TIEH, i.e., the first potential; if the currently shielded divider unit (excluding 2 / 3) is a divider unit of another level other than the nth level divider unit, the shielding order follows from the nth level to the first level. Since the next level divider unit has been shielded, its mode input terminal (i.e., MODin terminal) is also connected to the first potential.

[0082] As another example, such as Figure 4As shown, the divide-by-2 / divide-by-3 frequency divider unit includes a third D flip-flop DFF3, a fourth D flip-flop DFF4, a second AND gate AND2, a third AND gate AND3, and a fourth NAND gate NAND4. Specifically: the clock inputs (CK inputs) of the third D flip-flop DFF3 and the fourth D flip-flop DFF4 are connected to each other and serve as the clock inputs (Fin inputs) of the divide-by-2 / divide-by-3 frequency divider unit to receive the corresponding input clock; the reset inputs (RSTN inputs) of the third D flip-flop DFF3 and the fourth D flip-flop DFF4 are connected to each other and serve as the reset inputs (RSTN inputs) of the divide-by-2 / divide-by-3 frequency divider unit to receive the corresponding reset signal; the data input (D input) of the third D flip-flop DFF3 is connected to the output of the second AND gate AND2; the non-inverting output (Q input) of the third D flip-flop DFF3 serves as the mode output (MODout input) of the divide-by-2 / divide-by-3 frequency divider unit and is connected to the first input of the fourth NAND gate NAND4; the inverting output of the third D flip-flop DFF3... The phase output terminal (i.e., QB terminal) is left floating. The data terminal (i.e., D terminal) of the fourth D flip-flop DFF4 is connected to the output terminal of the third AND gate AND3. The non-inverting output terminal (i.e., Q terminal) of the fourth D flip-flop DFF4 serves as the clock output terminal (i.e., Fout terminal) of the divide-by-2 / divide-by-3 frequency divider unit and is connected to the first input terminal of the second AND gate AND2. The inverting output terminal (i.e., QB terminal) of the fourth D flip-flop DFF4 is connected to the first input terminal of the third AND gate AND3. The second input terminal of the second AND gate AND2 serves as the mode input terminal (i.e., MODin terminal) of the divide-by-2 / divide-by-3 frequency divider unit to receive the corresponding mode input signal. The second input terminal of the fourth NAND gate NAND4 serves as the frequency division control terminal (i.e., P terminal) of the divide-by-2 / divide-by-3 frequency divider unit to receive the corresponding frequency division control bit. The output terminal of the fourth NAND gate NAND4 is connected to the second input terminal of the third AND gate AND3.

[0083] In one embodiment, the third D flip-flop DFF3 and the fourth D flip-flop DFF4 are implemented using a true single-phase clock (TSPC) D flip-flop structure to reduce the number of components, shrink the layout area, and lower power consumption. However, this structure cannot operate at lower frequencies. The true single-phase clock structure D flip-flop is referred to as dynamic D flip-flop 112. When dynamic D flip-flop 112 is reset, its non-inverting output terminal (i.e., Q terminal) is set to a first potential, for example, a high potential. In this embodiment, dynamic D flip-flop 112 includes a fifth inverter INV5, a first-stage inverter 112a, a second-stage inverter 112b, a third-stage inverter 112c, an output stage inverter 112d, and a second reset control unit 112e, as follows... Figure 5 As shown, where:

[0084] The input terminal of the fifth inverter INV5 serves as the reset terminal (i.e., RSTN terminal) of the dynamic D flip-flop 112 to receive the corresponding reset signal, and the output terminal of the fifth inverter INV5 outputs the inverted reset signal RST.

[0085] The first-stage inverting section 112a includes a clock terminal (i.e., CK terminal) and a data terminal (i.e., D terminal) of a dynamic D flip-flop 112 to receive the corresponding input clock and input signal, respectively, and samples the input signal based on the input clock to obtain a first voltage V1. Specifically, the first-stage inverting section 112a includes a first MOSFET M1, a second MOSFET M2, and a third MOSFET M3. The gate terminals of the first MOSFET M1 and the third MOSFET M3 are connected to each other and serve as the data terminal (i.e., D terminal) of the dynamic D flip-flop 112. The source terminal of the first MOSFET M1 is connected to the power supply voltage VDD. The drain terminal of the first MOSFET M1 is connected to the source terminal of the second MOSFET M2. The gate terminal of the second MOSFET M2 serves as the clock terminal (i.e., CK terminal) of the dynamic D flip-flop 112. The drain terminal of the second MOSFET M2 is connected to the drain terminal of the third MOSFET M3 and serves as the output terminal of the first-stage inverting section 112a. The source terminal of the third MOSFET M3 is connected to the reference ground. Among them, the first MOS transistor M1 and the second MOS transistor M2 are PMOS transistors, and the third MOS transistor M3 is an NMOS transistor.

[0086] The second-stage inverting section 112b is connected to the first-stage inverting section 112a, and obtains the second voltage V2 based on the input clock and the first voltage V1. Specifically, the second-stage inverting section 112b includes a fourth MOSFET M4, a fifth MOSFET M5, and a sixth MOSFET M6. The gate of the fourth MOSFET M4 is connected to the clock terminal (i.e., the CK terminal) of the dynamic D flip-flop 112. The source terminal of the fourth MOSFET M4 is connected to the power supply voltage VDD. The drain terminal of the fourth MOSFET M4 is connected to the drain terminal of the fifth MOSFET M5 and serves as the output terminal of the second-stage inverting section 112b. The gate terminal of the fifth MOSFET M5 serves as the input terminal of the second-stage inverting section 112b and is connected to the output terminal of the first-stage inverting section 112a. The source terminal of the fifth MOSFET M5 is connected to the drain terminal of the sixth MOSFET M6. The gate terminal of the sixth MOSFET M6 is connected to the clock terminal (i.e., the CK terminal) of the dynamic D flip-flop 112. The source terminal of the sixth MOSFET M6 is connected to the reference ground through a portion of the structure in the second reset control section 112e (e.g., the third NMOS transistor MN3). The fourth MOSFET M4 is a PMOS transistor, and the fifth MOSFET M5 and the sixth MOSFET M6 are NMOS transistors.

[0087] The third-stage inverting section 112c is connected to the second-stage inverting section 112b and obtains the third voltage V3 based on the input clock and the second voltage V2. Specifically, the third-stage inverting section 112c includes a seventh MOSFET M7, an eighth MOSFET M8, and a ninth MOSFET M9. The gate terminals of the seventh MOSFET M7 and the ninth MOSFET M9 are connected to each other as the input terminals of the third-stage inverting section 112c and connected to the output terminals of the second-stage inverting section 112b. The source terminal of the seventh MOSFET M7 is connected to the power supply voltage VDD, and the drain terminal of the seventh MOSFET M7 is connected to the drain terminal of the eighth MOSFET M8 and serves as the output terminal of the third-stage inverting section 112c. The gate terminal of the eighth MOSFET M8 is connected to the clock terminal (i.e., the CK terminal) of the dynamic D flip-flop 112, and the source terminal of the eighth MOSFET M8 is connected to the drain terminal of the ninth MOSFET M9. The source terminal of the ninth MOSFET M9 is connected to the reference ground. Among them, the seventh MOSFET M7 is a PMOS transistor, and the eighth MOSFET M8 and the ninth MOSFET M9 are NMOS transistors.

[0088] The output stage inverting section 112d is connected to the third stage inverting section 112c, and includes the non-inverting output terminal (i.e., Q terminal) and the inverting output terminal (i.e., QB terminal) of the dynamic D flip-flop 112, and outputs the third voltage V3 inverted. Specifically, the output stage inverting section 112d includes an eleventh inverter INV11, wherein the input terminal of the eleventh inverter INV11 serves as the inverting output terminal (i.e., QB terminal) of the dynamic D flip-flop 112 and is connected to the output terminal of the third stage inverting section 112c, and the output terminal of the eleventh inverter INV11 serves as the non-inverting output terminal (i.e., Q terminal) of the dynamic D flip-flop 112.

[0089] The second reset control unit 112e is connected to the second-stage inverting unit 112b and the third-stage inverting unit 112c respectively, and performs a reset operation on the dynamic D flip-flop 112 based on the reset signal.

[0090] Specifically, the second reset control unit 112e includes a second PMOS transistor MP2, a third NMOS transistor MN3, and a fourth NMOS transistor MN4. The gate of the second PMOS transistor MP2 is connected to the reset terminal (i.e., the RSTN terminal) of the dynamic D flip-flop 112 to receive the corresponding reset signal. The source terminal of the second PMOS transistor MP2 is connected to the power supply voltage VDD, and the drain terminal of the second PMOS transistor MP2 is connected to the output terminal of the second-stage inverting unit 112b. The third NMOS transistor MN3 is connected between the second-stage inverting unit 112b and the reference ground. That is, the drain of the third NMOS transistor MN3 is connected to the source of the sixth MOS transistor M6 in the second-stage inverting section 112b, the source of the third NMOS transistor MN3 is connected to the reference ground, the gate of the third NMOS transistor MN3 is connected to the reset terminal (i.e., the RSTN terminal) of the dynamic D flip-flop 112 to receive the corresponding reset signal, the gate of the fourth NMOS transistor MN4 receives the inverted reset signal RST, the source of the fourth NMOS transistor MN4 is connected to the reference ground, and the drain of the fourth NMOS transistor MN4 is connected to the output terminal of the third-stage inverting section 112c.

[0091] When the dynamic D flip-flop 112 is reset, the reset signal RSTN is at the second potential, for example, a low potential, and the inverting reset signal RST is at the first potential, for example, a high potential. At this time, the second PMOS transistor MP2 and the fourth NMOS transistor MN4 are turned on, and their non-inverting output terminals are set to the first potential, for example, a high potential. This sets the clock output terminal (i.e., Fout terminal) and the mode output terminal (i.e., MODout terminal) of the divide-by-2 / divide-by-3 frequency divider unit to the first potential, for example, a high potential. In this way, the divide-by-2 / divide-by-3 frequency divider unit is shielded.

[0092] The control module 200 is connected to the frequency division control terminal (i.e., P terminal) and reset terminal (i.e., RSTN terminal) of each level of frequency division unit 110 in the frequency division module 100. It is used to provide the corresponding frequency division control bit and the corresponding reset signal to each level of frequency division unit 110 so as to perform shielding control and frequency division control on each level of frequency division unit 110.

[0093] In practical applications, the structure of the control module 200 is related to the number of frequency division units 110 in the frequency division module 100. When the number of frequency division units 110 in the frequency division module 100 is equal to two, the control module 200 corresponds to one structure. When the number of frequency division units 110 in the frequency division module 100 is greater than two, the control module 200 corresponds to another structure.

[0094] When the number of frequency division units 110 in the frequency division module 100 is equal to two:

[0095] As an example, such as Figure 6As shown, the control module 200 includes a first control unit 210, which provides three frequency division control bits P. <1> ~P <3> And a global reset signal RSTN1; wherein, the least significant bit of the frequency division control bit P <1> The frequency division control terminal (i.e., P terminal) connected to the first-stage frequency division unit 110, the second lowest frequency division control bit P <2> The frequency division control terminal (i.e., P terminal) of the second-stage frequency divider unit 110 is connected, and the total reset signal RSTN1 is connected to the reset terminal (i.e., RSTN terminal) of the first-stage frequency divider unit 110. The most significant bit of the frequency division control bit P... <3> The reset terminal (i.e., RSTN terminal) of the second-stage frequency divider unit 110 is connected. In practical applications, the total reset signal RSTN1 can be regarded as the reset signal of the frequency divider module 100, used to control whether the frequency divider module 100 is working; when the frequency divider module 100 is working, the total reset signal RSTN1 is always at the first potential, for example, a high potential. In addition, the three frequency division control bits P <1> ~P <3> The design should be tailored to the specific scenario, and there are no restrictions on it.

[0096] When the number of frequency division units 110 in frequency division module 100 is greater than two:

[0097] As an example, such as Figure 7 As shown, the control module 200 includes a first control unit 210 and a second control unit 220. Wherein:

[0098] The first control unit 210 is used to provide (n+1) frequency division control bits P <1> ~P<n+1> And a global reset signal RSTN1; wherein, the least significant bit of the frequency division control bit P <1> Frequency division control bit P up to the second highest bit <n>The frequency division control terminals (i.e., P terminals) of the first-stage frequency division unit 110 to the nth-stage frequency division unit 110 are respectively connected. The total reset signal RSTN1 is connected to the reset terminal (i.e., RSTN terminal) of the first-stage frequency division unit 110. The most significant bit of the frequency division control bit P<n+1> The reset terminal (i.e., RSTN terminal) of the nth-stage frequency divider unit 110 is connected. In practical applications, the total reset signal RSTN1 can be regarded as the reset signal of the frequency divider module 100, used to control whether the frequency divider module 100 is working; when the frequency divider module 100 is working, the total reset signal RSTN1 is always at the first potential, for example, a high potential. In addition, there are (n+1) frequency divider control bits P <1> ~P<n+1> The design should be tailored to the specific scenario, and there are no restrictions on it.

[0099] The second control unit 220 obtains the reset signal of the (i-1)th stage frequency divider unit 110 based on the frequency division control bit and reset signal of the i-th stage frequency divider unit 110, where i is a natural number greater than 2 and less than or equal to n. In one embodiment, the second control unit 220 is implemented using (n-2) OR gates.

[0100] Taking n=5 as an example, the second control unit 220 includes three OR gates. The first input of the first OR gate OR1 is connected to the reset terminal (i.e., RSTN terminal) of the fifth-level frequency divider unit 110. The second input of the first OR gate OR1 is connected to the frequency division control terminal (i.e., P terminal) of the fifth-level frequency divider unit 110. The output of the first OR gate OR1 is connected to the reset terminal (i.e., RSTN terminal) of the fourth-level frequency divider unit 110 and to the first input of the second OR gate OR2. The second input of the second OR gate OR2 is connected to the frequency division control terminal (i.e., P terminal) of the fourth-level frequency divider unit 110. The output of the second OR gate OR2 is connected to the reset terminal (i.e., RSTN terminal) of the third-level frequency divider unit 110 and to the first input of the third OR gate OR3. The second input of the third OR gate OR3 is connected to the frequency division control terminal (i.e., P terminal) of the third-level frequency divider unit 110. The output of the third OR gate OR3 is connected to the reset terminal (i.e., RSTN terminal) of the second-level frequency divider unit 110.

[0101] The output sampling module 300 is connected to the mode output terminal (i.e., MODout terminal) of the second-stage frequency divider unit 110 in the frequency divider module 100. Based on the input clock (i.e., the clock to be divided) of the first-stage frequency divider unit 110, the mode output signal mod1 of the second-stage frequency divider unit 110 is sampled to obtain the final frequency divider clock CKOUT, thereby obtaining better noise performance.

[0102] As an example, such as Figure 8 As shown, the output sampling module 300 includes a fifth D flip-flop DFF5. Specifically: the data terminal (D terminal) of the fifth D flip-flop DFF5 is connected to the mode output terminal (MODout terminal) of the second-stage frequency divider unit 110 to receive the mode output signal mod1; the clock terminal (CK terminal) of the fifth D flip-flop DFF5 receives the input clock of the first-stage frequency divider unit 110; and the non-inverting output terminal (Q terminal) of the fifth D flip-flop DFF5 outputs the final divided clock CKOUT. Further, the output sampling module 300 also includes a buffer BUF, connected between the mode output terminal (MODout terminal) of the second-stage frequency divider unit 110 and the data terminal (D terminal) of the fifth D flip-flop DFF5. That is, the input terminal of the buffer BUF is connected to the mode output terminal (MODout terminal) of the second-stage frequency divider unit 110, and the output terminal of the buffer BUF is connected to the data terminal (D terminal) of the fifth D flip-flop DFF5. In one embodiment, the buffer BUF is implemented using two inverters connected in series. It should be noted that the fifth D flip-flop, DFF5, can be implemented using any existing known flip-flop structure, without any restrictions.

[0103] It should be noted that in the programmable frequency divider 10 of this embodiment, each component, especially each logic device, such as AND gate, NAND gate, inverter, etc., can be implemented not only with the specific structure described above, but also with other structures or even combined structures with the same function. This has no substantial impact on the implementation of the solution in this embodiment. In fact, these should all be considered equivalent alternatives to this embodiment and should fall within the protection scope of this invention.

[0104] by Figure 7 Taking the cascaded five frequency division units 110 shown as an example, the working process of the programmable frequency divider 10 in this embodiment will be described in detail.

[0105] Assuming the frequency division control word (including six frequency division control bits) is "010010", which corresponds to 18 in decimal, and the total reset signal RSTN1 is "1", then: the reset signal corresponding to the fifth-level frequency division unit 110 is "0". Since the frequency division control bit corresponding to the fifth-level frequency division unit 110 is "1", the reset signals corresponding to the fourth-level frequency division unit 110, the third-level frequency division unit 110, and the second-level frequency division unit 110 are all "1", and the reset signal corresponding to the first-level frequency division unit 110 is also "1". Therefore, the first-level frequency division unit 110 to the fourth-level frequency division unit 110 are working, and the fifth-level frequency division unit 110 is disabled.

[0106] Since the frequency division control bits corresponding to the first-level frequency division unit 110, the third-level frequency division unit 110, and the fourth-level frequency division unit 110 are all "0", the first-level frequency division unit 110, the third-level frequency division unit 110, and the fourth-level frequency division unit 110 all perform frequency division by two; where F1 is the result of frequency division by two of CKIN, F3 is the result of frequency division by two of F2, and F4 is the result of frequency division by two of F3.

[0107] The frequency division control bit corresponding to the second-level frequency division unit 110 is "1". Therefore, when the corresponding mode input signal is "1", the second-level frequency division unit 110 performs a three-way frequency division, and F2 is the result of the three-way frequency division of F1; when the corresponding mode input signal is "0", the second-level frequency division unit 110 performs a two-way frequency division, and F2 is the result of the two-way frequency division of F1.

[0108] During the operation of each frequency divider unit 110, under the influence of its respective input clock, its output clock and mode output signal are adjusted accordingly; the timing of each key node is as follows: Figure 9 As shown. From Figure 9 As can be seen, the final divided clock CKOUT is divided by 18 compared to the clock CKIN to be divided, which is consistent with the decimal number converted from the frequency division control word. Therefore, the frequency division design using the programmable frequency divider in this embodiment is not only simple in structure but also facilitates understanding and calculation.

[0109] Wherein, CKIN is the input clock corresponding to the first-stage frequency divider unit 110, that is, the clock to be divided; RSTN1 is the reset signal corresponding to the first-stage frequency divider unit 110, that is, the total reset signal; F1~F4 are the output clocks of the first-stage frequency divider unit 110~the fourth-stage frequency divider unit 110 triggered by their respective input clocks; mod1~mod3 are the mode output signals of the second-stage frequency divider unit 110~the fourth-stage frequency divider unit 110 triggered by their respective mode input signals; and CKOUT is the final frequency divider clock.

[0110] It should be noted that since the fifth-stage frequency divider unit 110 is shielded, the output clock F5 and the mode output signal mod4 corresponding to the fifth-stage frequency divider unit 110 are always "1".

[0111] This embodiment also provides a phase-locked loop circuit, including a programmable frequency divider 10. Of course, it may also include other functional devices, such as a phase detector, a loop filter, a voltage-controlled oscillator, etc., without limitation. The programmable frequency divider 10 is implemented using the device structure described above, which will not be repeated here.

[0112] This embodiment also provides a chip including a phase-locked loop circuit. Of course, it may also include other functional circuits, such as power management circuits, clock distribution circuits, storage circuits, etc., without limitation. The phase-locked loop circuit is implemented using the circuit structure described above, which will not be repeated here.

[0113] This embodiment also provides an electronic device, including a chip; wherein the chip is implemented using the chip structure described above, which will not be repeated here.

[0114] In summary, the programmable frequency divider, phase-locked loop circuit, chip, and electronic device of the present invention propose a variable continuous integer frequency division scheme that can expand the frequency division range from 2... n ~2 n+1 -1 expands downwards to 2~2 n+1 -1 significantly widens the frequency division range, increases flexibility, and boasts a simple structure that is easy to implement. The frequency division module employs multiple cascaded frequency division units. By cooperating with the control module to control the shielding of each unit, the effective number of cascaded frequency division units in the module can be set, enabling different integer frequency division designs and effectively controlling variations in the frequency division range, thus achieving flexible frequency division. The output sampling module samples the mode output signal of the second-stage frequency division unit based on the input clock of the first-stage unit to obtain the final frequency division clock, resulting in better noise performance. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and possesses high industrial applicability.

[0115] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.< / n>

Claims

1. A programmable frequency divider, characterized in that, include: The frequency divider module includes n cascaded frequency divider units. Each frequency divider unit performs shielding control based on its own reset signal and frequency division control based on its own frequency division control bit and mode input signal to perform frequency division operation on its own input clock, where n is a natural number greater than 1. The control module is connected to the frequency division control terminal and reset terminal of each level of the frequency division unit in the frequency division module, and is used to provide the corresponding frequency division control bit and the corresponding reset signal to each level of the frequency division unit; The output sampling module is connected to the mode output terminal of the second-stage frequency divider unit in the frequency divider module. It samples the mode output signal of the second-stage frequency divider unit based on the input clock of the first-stage frequency divider unit to obtain the final frequency divider clock. The frequency division unit includes a divide-by-2 / divide-by-3 frequency division unit, which operates when the reset signal is at a first potential and is disabled when the reset signal is at a second potential. When the divide-by-2 / divide-by-3 frequency division unit is disabled, the corresponding output clock and mode output signal are both at the first potential. The divide-by-2 / divide-by-3 frequency division unit performs a 3-way division when both the frequency division control bit and the mode input signal are at the first potential, and performs a 2-way division when at least one of the frequency division control bit and the mode input signal is at the second potential. The divide-by-2 / divide-by-3 frequency divider unit includes a first D flip-flop, a second D flip-flop, a first NAND gate, a second NAND gate, a first AND gate, a first inverter, and a second inverter. The clock inputs of the first D flip-flop and the second D flip-flop are connected to each other and serve as the clock inputs of the divide-by-2 / divide-by-3 frequency divider unit. The reset inputs of the first D flip-flop and the second D flip-flop are connected to each other and serve as the reset inputs of the divide-by-2 / divide-by-3 frequency divider unit. The data input of the first D flip-flop is connected to the output of the first NAND gate. The non-inverting output of the first D flip-flop is connected to the first input of the second NAND gate. The data input of the second D flip-flop is connected to the output of the second NAND gate. The non-inverting output of the second D flip-flop is connected to the second input of the second NAND gate and then... The first inverter serves as the clock output of the divide-by-2 / divide-by-3 frequency divider unit. The non-inverting output of the second D flip-flop is also connected to the first input of the first AND gate via the second inverter. The second input of the first AND gate serves as the mode input of the divide-by-2 / divide-by-3 frequency divider unit. The output of the first AND gate serves as the mode output of the divide-by-2 / divide-by-3 frequency divider unit and is connected to the first input of the first NAND gate. The second input of the first NAND gate serves as the frequency division control terminal of the divide-by-2 / divide-by-3 frequency divider unit. The first and second D flip-flops are implemented using a static transmission gate structure, referred to as a static D flip-flop. When the static D flip-flop is reset, its non-inverting output is set to the second potential. Alternatively, the divide-by-2 / divide-by-3 frequency divider unit includes a third D flip-flop, a fourth D flip-flop, a second AND gate, a third AND gate, and a fourth NAND gate. The clock inputs of the third and fourth D flip-flops are connected to each other and serve as the clock inputs of the divide-by-2 / divide-by-3 frequency divider unit. The reset inputs of the third and fourth D flip-flops are connected to each other and serve as the reset inputs of the divide-by-2 / divide-by-3 frequency divider unit. The data input of the third D flip-flop is connected to the output of the second AND gate. The non-inverting output of the third D flip-flop serves as the mode output of the divide-by-2 / divide-by-3 frequency divider unit and is connected to the first input of the fourth NAND gate. The inverting output of the third D flip-flop is left floating. The data input of the fourth D flip-flop is connected to the output of the third AND gate. The non-inverting output of the fourth D flip-flop serves as the clock output of the divide-by-2 / divide-by-3 frequency divider unit and is connected to the first input of the second AND gate. The inverting output of the fourth D flip-flop is connected to the first input of the third AND gate. The second input of the second AND gate serves as the mode input of the divide-by-2 / divide-by-3 frequency divider unit. The second input of the fourth NAND gate serves as the frequency division control terminal of the divide-by-2 / divide-by-3 frequency divider unit. The output of the fourth NAND gate is connected to the second input of the third AND gate. The third and fourth D flip-flops are implemented using a true single-phase clock structure D flip-flop, which is referred to as a dynamic D flip-flop. When the dynamic D flip-flop is reset, its non-inverting output is set to the first potential.

2. The programmable frequency divider according to claim 1, characterized in that, The first potential includes a high potential, and the second potential includes a low potential.

3. The programmable frequency divider according to claim 1, characterized in that, The static D flip-flop includes a third inverter, a fourth inverter, a third NAND gate, a first transmission gate, a first latch, a second transmission gate, a second latch, an output inverter, and a first reset control unit, wherein: The input terminal of the third inverter serves as the clock terminal of the static D flip-flop to receive the corresponding input clock, and the output terminal of the third inverter outputs an inverted clock. The input terminal of the fourth inverter serves as the reset terminal of the static D flip-flop to receive the corresponding reset signal, and the output terminal of the fourth inverter outputs an inverted reset signal. The first input terminal of the third NAND gate serves as the data terminal of the static D flip-flop. The second input terminal of the third NAND gate is connected to the reset terminal of the static D flip-flop. The output terminal of the third NAND gate is connected to the input terminal of the output inverting section via the first transmission gate, the first latch, the second transmission gate, and the second latch in sequence. The output terminal of the output inverting section serves as the non-inverting output terminal of the static D flip-flop. The first transmission gate is turned on when the input clock is at the second potential and turned off when the input clock is at the first potential; The first latching unit inverts its input signal when the first transmission gate is turned on, and latches the input signal when the first transmission gate is turned off. The second transmission gate is turned on when the input clock is at the first potential and turned off when the input clock is at the second potential; The second latching unit inverts its input signal when the second transmission gate is turned on, and latches the input signal when the second transmission gate is turned off; The output inverting section is used to invert its input signal and output it in phase. The first reset control section is connected to the first latch section and the second transmission gate respectively, and performs a reset operation on the static D flip-flop based on the reset signal.

4. The programmable frequency divider according to claim 3, characterized in that, The first reset control unit includes a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor, wherein: The gate of the first PMOS transistor is connected to the reset terminal of the static D flip-flop to receive the reset signal. The source of the first PMOS transistor is connected to the power supply voltage. The drain of the first PMOS transistor is connected to the input terminal of the first latch. The gate of the first NMOS transistor receives the inverted reset signal. The source of the first NMOS transistor is connected to reference ground. The drain of the first NMOS transistor is connected to the input terminal of the second transmission gate. The gate of the second NMOS transistor receives the inverted reset signal. The source of the second NMOS transistor is connected to reference ground. The drain of the second NMOS transistor is connected to the output terminal of the second transmission gate.

5. The programmable frequency divider according to claim 1, characterized in that, The dynamic D flip-flop includes a fifth inverter, a first-stage inverting section, a second-stage inverting section, a third-stage inverting section, an output stage inverting section, and a second reset control section, wherein: The input terminal of the fifth inverter serves as the reset terminal of the dynamic D flip-flop to receive the corresponding reset signal, and the output terminal of the fifth inverter outputs an inverted reset signal. The first-stage inverting section includes a clock terminal and a data terminal of the dynamic D flip-flop to receive the corresponding input clock and input signal respectively, and samples the input signal based on the input clock to obtain a first voltage; The second-stage inverting section is connected to the first-stage inverting section, and obtains the second voltage based on the input clock and the first voltage; The third-stage inverting section is connected to the second-stage inverting section, and obtains the third voltage based on the input clock and the second voltage; The output stage inverting section is connected to the third stage inverting section, including the non-inverting output terminal and the inverting output terminal of the dynamic D flip-flop, and outputs the third voltage inverted. The second reset control section is connected to the second-stage inverting section and the third-stage inverting section respectively, and performs a reset operation on the dynamic D flip-flop based on the reset signal.

6. The programmable frequency divider according to claim 5, characterized in that, The second reset control unit includes a second PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor, wherein: The gate of the second PMOS transistor is connected to the reset terminal of the dynamic D flip-flop to receive the reset signal. The source of the second PMOS transistor is connected to the power supply voltage, and the drain of the second PMOS transistor is connected to the output terminal of the second-stage inverting section. The third NMOS transistor is connected between the second-stage inverting section and the reference ground. The gate of the third NMOS transistor is connected to the reset terminal of the dynamic D flip-flop to receive the reset signal. The gate of the fourth NMOS transistor receives the inverted reset signal. The source of the fourth NMOS transistor is connected to the reference ground, and the drain of the fourth NMOS transistor is connected to the output terminal of the third-stage inverting section.

7. The programmable frequency divider according to claim 1, characterized in that, When the number of frequency division units is equal to two, the control module includes a first control unit for providing three frequency division control bits and a total reset signal. The least significant frequency division control bit and the second least significant frequency division control bit are respectively connected to the frequency division control terminals of the first-level frequency division unit and the second-level frequency division unit. The total reset signal and the most significant frequency division control bit are respectively connected to the reset terminals of the first-level frequency division unit and the second-level frequency division unit.

8. The programmable frequency divider according to claim 1, characterized in that, When the number of frequency division units is greater than two, the control module includes a first control unit and a second control unit, wherein: The first control unit is used to provide n+1 frequency division control bits and a total reset signal, wherein the least significant frequency division control bit to the second most significant frequency division control bit are respectively connected to the frequency division control terminals of the first-level frequency division unit to the nth-level frequency division unit, the total reset signal is connected to the reset terminal of the first-level frequency division unit, and the most significant frequency division control bit is connected to the reset terminal of the nth-level frequency division unit. The second control unit obtains the reset signal of the (i-1)th stage frequency divider unit based on the frequency divider control bit and reset signal of the i-th stage frequency divider unit, where i is a natural number greater than 2 and less than or equal to n.

9. The programmable frequency divider according to claim 8, characterized in that, The second control unit is implemented using n-2 OR gates.

10. The programmable frequency divider according to claim 1, characterized in that, The output sampling module includes a fifth D flip-flop, wherein: The data terminal of the fifth D flip-flop is connected to the mode output terminal of the second-stage frequency divider unit, the clock terminal of the fifth D flip-flop receives the input clock of the first-stage frequency divider unit, and the non-inverting output terminal of the fifth D flip-flop outputs the final frequency-divided clock.

11. A phase-locked loop circuit, characterized in that, Includes the programmable frequency divider as described in any one of claims 1 to 10.

12. A chip, characterized in that, Includes the phase-locked loop circuit as described in claim 11.

13. An electronic device, characterized in that, Including the chip as described in claim 12.

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