Video transmission device and method

Abstract

The invention provides a video transmission device and method, the video transmission device comprises a protection shell, at least two camera modules, a video processing assembly and a power supply, and the protection shell comprises an accommodating cavity; the at least two camera modules are arranged in the containing cavity, the at least two camera modules are arranged in the first direction in an angular interval mode, and the at least two camera modules are used for collecting imaging conditions in different directions in the external environment; the video processing assembly is arranged in the accommodating cavity, the video processing assembly comprises a field programmable gate array (FPGA) chip, an optical fiber transceiver and at least two connectors, and the at least two camera modules are respectively in communication connection with the corresponding connectors through flat cables; the input end of the FPGA chip is in communication connection with the connector, and the output end of the FPGA chip is in communication connection with the optical fiber transceiver; and the power supply is arranged in the accommodating cavity and is used for supplying power to the camera module and the video processing assembly. The cost of the video transmission device can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data transmission, in particular to a video transmission device and method. BACKGROUND

[0002] In the field of avionics, the video transmission device is the core equipment to ensure flight safety and support decision-making, which needs to collect multi-directional video data of the body, engine compartment, landing gear, etc. to provide comprehensive environmental monitoring information for the crew. The cockpit display system in the field of avionics needs to access multiple video sources such as forward-looking infrared, omnidirectional visible light, downward-looking synthetic aperture, etc.

[0003] In the current related technology, in order to realize multi-directional video coverage, the industry generally adopts one machine one link, that is, one independent camera device is deployed for each monitoring direction, and each camera device needs to be matched with a dedicated video transmission link. However, the existing one machine one link mode leads to complex wiring and weight increase, directly increasing the cost of aircraft modification and maintenance cost, thereby resulting in high cost of the video transmission device. SUMMARY

[0004] The video transmission device and method provided by the present application can reduce the cost of the video transmission device.

[0005] In a first aspect, the embodiments of the present application provide a video transmission device, which comprises:

[0006] A protective shell comprising a receiving cavity;

[0007] At least two camera modules arranged in the receiving cavity, at least two camera modules being arranged at an angle interval along a first direction, and the at least two camera modules being used to collect imaging conditions in different directions of an external environment;

[0008] A video processing component arranged in the receiving cavity, the video processing component comprising a field programmable gate array (FPGA) chip, an optical fiber transceiver, and at least two connectors, the at least two camera modules being respectively connected to the corresponding connectors through a wire; an input end of the FPGA chip being connected to the connectors, and an output end of the FPGA chip being connected to the optical fiber transceiver; the FPGA chip being used to perform packet encapsulation processing on the video data collected by the camera modules according to a preset protocol to obtain encapsulated data streams of the preset protocol; and the optical fiber transceiver being used to convert the encapsulated data streams into optical signals and transmit the optical signals;

[0009] A power supply arranged in the receiving cavity, the power supply being used to supply power to the camera modules and the video processing component.

[0010] In a second aspect, the application provides a video transmission method applied to the video transmission device provided in any of the embodiments of the first aspect, and the method comprises the following steps:

[0011] The at least two camera modules respectively collect video data in different directions of the external environment;

[0012] The video data is received by the connector and transmitted to the FPGA chip;

[0013] The FPGA chip performs preset protocol packet encapsulation processing on the video data to obtain encapsulated data stream of the preset protocol;

[0014] The encapsulated data stream is converted into an optical signal by the optical transceiver and transmitted.

[0015] In the video transmission device and method provided in the embodiments of the application, the device comprises a protective shell, at least two camera modules, a video processing assembly, and a power supply. The camera modules are arranged in the accommodation cavity, and two camera modules arranged at an angle interval along a first direction can collect imaging conditions in different directions of the external environment. The video processing assembly comprises an FPGA chip, an optical transceiver, and at least two connectors. The camera modules are respectively in communication connection with the corresponding connectors through the wire harness, the input end of the FPGA chip is in communication connection with the connector, and the output end is in communication connection with the optical transceiver. The FPGA chip is responsible for performing preset protocol packet encapsulation processing on the video data collected by the camera modules to obtain encapsulated data stream, and then the optical transceiver converts the encapsulated data stream into an optical signal for transmission. The arrangement of the plurality of camera modules enables the video transmission device to cover multi-directional scenes, and the video transmission device integrates at least two multi-view camera modules, a set of video processing assembly (single FPGA chip, single optical transceiver), and a power supply in the same protective shell, replaces multiple independent cameras with multiple modules, shares core processing and transmission components, thereby compressing the monitoring task originally completed by N independent camera devices into a set of hardware, avoiding repeated purchase of FPGAs and other devices, and reducing the cost of core hardware. Moreover, the video transmission device only needs to connect the camera modules and the video processing assembly through the wire harness, and finally transmits all data through a single optical fiber, which greatly reduces the number of machine body wirings, thereby effectively reducing the cost of the video transmission device. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments of the application. For those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0017] Figure 1 is a structural schematic diagram of a video transmission device provided in the embodiments of the application;

[0018] Figure 2 is a structural schematic diagram of a video processing assembly provided by an embodiment of the present application;

[0019] Figure 3 is a signal transmission schematic diagram of a video transmission device provided by an embodiment of the present application;

[0020] Figure 4 is a structural schematic diagram of an FPGA chip provided by an embodiment of the present application;

[0021] Figure 5 is a structural schematic diagram of a format conversion module provided by an embodiment of the present application;

[0022] Figure 6 is a structural schematic diagram of a serial transmission module provided by an embodiment of the present application;

[0023] Figure 7 is a structural schematic diagram of an optical fiber transceiver provided by an embodiment of the present application;

[0024] Figure 8 is a structural schematic diagram of a camera module provided by an embodiment of the present application;

[0025] Figure 9 is a flow schematic diagram of a video transmission method provided by an embodiment of the present application;

[0026] Figure 10 is a structural schematic diagram of an electronic device provided by an embodiment of the present application.

[0027] Legend of reference signs:

[0028] 100, video transmission device; 1, protective shell; 11, first side cover plate; 12, second side cover plate; 121, light window; 13, third side cover plate; 2, camera module; 21, core frame; 22, lens seat; 23, lens; 24, Sensor board; 3, video processing assembly; 31, FPGA chip; 311, format conversion module; 3111, video format judgment unit; 3112, video format conversion unit; 3113, data bit width conversion unit; 312, protocol packaging unit; 313, serial transmission module; 3131, error detection and correction unit; 3132, serial high-speed transmission unit; 32, optical fiber transceiver; 321, optical fiber transmitting unit; 322, clock recovery unit; 33, connector; 34, image signal processor; 35, upper computer communication connector; 36, power supply connector; 4, power supply; 1001, processor; 1002, memory; 1003, communication interface; 1010, bus;

[0029] X, first direction; Y, second direction; Z, third direction. Detailed Implementation

[0030] The embodiments of this application will be described in further detail below with reference to the accompanying drawings and examples. The detailed description of the following embodiments and the accompanying drawings are used to illustrate the principles of this application by way of example, but should not be used to limit the scope of this application, that is, this application is not limited to the described embodiments.

[0031] In the description of this application, it should be noted that, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. "Vertical" is not vertical in the strict sense, but within the allowable tolerance range. "Parallel" is not parallel in the strict sense, but within the allowable tolerance range.

[0032] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application can be combined with other embodiments.

[0033] The directional terms used in the following description refer to the directions shown in the figures and are not intended to limit the specific structure of this application. It should also be noted in the description of this application that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0034] In order to solve the problems existing in the related technologies, this application provides a video transmission device 100 and a method.

[0035] The video transmission device 100 provided in the embodiments of this application will be described first below. For example... Figure 1 As shown, the device specifically includes:

[0036] Protective housing 1, including a receiving cavity;

[0037] At least two camera modules 2 are arranged in the accommodation cavity, and at least two camera modules 2 are arranged at an angle interval along the first direction X. The at least two camera modules 2 are used to collect imaging conditions in different directions of an external environment.

[0038] A video processing assembly 3 is arranged in the accommodation cavity. The video processing assembly 3 includes a field programmable gate array (FPGA) chip 31, an optical fiber transceiver 32, and at least two connectors 33. The at least two camera modules 2 are respectively connected to the corresponding connectors 33 through a wire. An input end of the FPGA chip 31 is connected to the connectors 33, and an output end of the FPGA chip 31 is connected to the optical fiber transceiver 32. The FPGA chip 31 is used to perform preset protocol packet encapsulation processing on video data collected by the camera modules 2 to obtain encapsulated data streams of the preset protocol. The optical fiber transceiver 32 is used to convert the encapsulated data streams into optical signals and transmit the optical signals.

[0039] A power supply 4 is arranged in the accommodation cavity. The power supply 4 is used to supply power to the camera modules 2 and the video processing assembly 3.

[0040] Optionally, in an implementation manner of the present application, the protective shell 1 is an important component of the video transmission device 100, and the protective shell 1 can be arranged in various ways. The protective shell 1 can be designed in a cuboid shape, a cylindrical shape, or the like. Specifically, the cuboid shape can be formed by splicing multiple planar panels to form a regular accommodation cavity. This shape facilitates the orderly arrangement of the camera modules 2, the video processing assembly 3, and the power supply 4, and can realize standardized installation and compact arrangement of the device in industrial monitoring and other scenarios.

[0041] The cylindrical protective shell 1 is formed by combining a curled side plate and a circular end plate to form a cylindrical accommodation cavity. The smooth appearance of the cylindrical protective shell 1 is particularly advantageous in the fields of aviation and navigation that have requirements for air dynamics, and can uniformly disperse external pressure to better protect the internal components. In addition, there are special-shaped protective shells 1 customized according to special application scenarios. The special-shaped protective shells 1 are formed by a specific processing technique to create a unique accommodation cavity to adapt to narrow or irregular installation spaces.

[0042] Optionally, in terms of installation methods, the protective shell 1 can be wall-mounted for installation, with mounting holes or clamping slots provided on the back of the shell to facilitate fixing the video transmission device 100 on a vertical plane such as a wall, suitable for security monitoring and other scenarios, and the monitoring angle can be adjusted flexibly. Embedded installation can also be used, embedding the protective shell 1 into the internal structure of the device, so that the video transmission device 100 is integrated with the overall device, which can be used in aviation electronic devices, vehicle-mounted systems and other occasions with high requirements for space compactness and integration. Desktop installation can also be used, equipped with a special base, so that the video transmission device 100 can be placed stably on a desktop or other flat surface, suitable for some indoor monitoring or data acquisition scenarios.

[0043] In addition to the basic function of containing and protecting the internal components, the protective shell 1 can also be made of materials with electromagnetic shielding function, such as metal, which can effectively shield external electromagnetic interference and ensure the stability of video signal transmission. At the same time, shock-absorbing structures such as rubber pads and springs can be provided inside the shell to reduce the impact of external vibration on internal precision components such as the lens 23 of the camera module 2, further improving the reliability and service life of the device.

[0044] Optionally, for the camera module 2, in terms of structure, the camera module 2 can contain an optical lens 23, an image sensor (such as a complementary metal-oxide-semiconductor (CMOS) sensor), a circuit board and related electronic components. The optical lens 23 is used to focus the light in the external environment and image the scene on the image sensor. The image sensor is responsible for converting the optical image into an electrical signal. This conversion process can be achieved by capturing photons and converting them into electronic signals through the light-sensing units (such as pixel points) on the sensor. Various electronic components are integrated on the circuit board to perform preliminary processing of the electrical signals output by the image sensor, such as signal amplification, analog-to-digital conversion and other operations, thereby generating digital video signals.

[0045] Optionally, in the video transmission device 100, the camera modules 2 are ingeniously arranged in the receiving cavity of the protective shell 1, and each camera module 2 is arranged at an angle interval along the first direction X. This layout enables each camera module 2 to cover a different range of viewing angles, thereby achieving multi-angle monitoring of the surrounding environment. For example, in an aviation application scenario, different direction camera modules 2 can monitor different parts of the aircraft or the external environment in different flight directions, ensuring that various visual information during flight can be comprehensively obtained, providing multi-dimensional visual data support for flight safety. Moreover, this angular interval arrangement is also conducive to avoiding mutual interference between the camera modules 2, ensuring that each camera module 2 can work independently and stably. It should be noted that the first direction X is a reference direction (such as horizontal, vertical or inclined direction, etc.) set according to the application scenario and design requirements of the video transmission device 100, used to determine the angular interval layout of the plurality of camera modules 2 to achieve multi-directional image acquisition.

[0046] Optionally, the camera modules 2 can be firmly installed at a predetermined position in the receiving cavity by using fasteners such as screws. This installation method can ensure that the camera modules 2 can maintain a stable working state in complex aviation environments, such as facing external factors such as vibration and airflow impact. At the same time, the camera modules 2 are connected to the connectors 33 in the video processing assembly 3 through the wire harness. The wire harness has good flexibility and signal transmission performance, and can realize reliable electrical connection between the camera modules 2 and the video processing assembly 3, ensuring that video data can be efficiently and stably transmitted to subsequent processing modules.

[0047] Optionally, the main role of the camera modules 2 is to collect imaging conditions in different directions of the external environment. The camera modules 2 can convert the optical image of the external scene into an electrical signal, and then generate a digital video signal. These signals contain rich visual information.

[0048] The video processing assembly 3, the FPGA chip 31, the optical fiber transceiver 32 and the at least two connectors 33 are all indispensable components of the video transmission device 100, and they cooperate with each other to realize the complete process of video data from acquisition to transmission:

[0049] Optionally, the video processing assembly 3 is the “data hub” of the entire video transmission device 100, and the video processing assembly 3 can be in the shape of a flat rectangular parallelepiped, which is suitable for installation in the receiving cavity of the protective shell 1. The video processing assembly 3 internally integrates key components such as a field-programmable gate array (FPGA) chip, an optical fiber transceiver 32 and a connector 33, and forms a complete data processing link through precise circuit layout and wire harness connection.

[0050] When installing the video processing assembly 3, screwing or card slot embedding can be used to fix it in the receiving cavity, so as to ensure the relative position of the components is fixed and avoid the influence of factors such as vibration on signal transmission.

[0051] The core function of the video processing assembly 3 is to convert the original video data collected by the camera module 2 into a light signal conforming to a preset protocol, so as to realize efficient and stable transmission.

[0052] Optionally, the FPGA chip 31 is a chip module, and the surface is covered with fine pins for signal transmission. The FPGA chip 31 can be welded on the circuit board of the video processing assembly 3 and connected to other components through complex circuit traces. The FPGA chip 31 can realize various logic functions flexibly by virtue of its programmable characteristics. In installation, the FPGA chip 31 can be precisely positioned and welded on the circuit board to ensure stable and reliable electrical connection.

[0053] The main function of the FPGA chip 31 is to process video data. After receiving the original video data from the camera module 2, the FPGA chip 31 performs preset protocol packet encapsulation processing on the data through internal programming logic, including format conversion, data verification, protocol adaptation, etc. The original video data is converted into a transmittable encapsulated data stream, laying a foundation for subsequent transmission.

[0054] Optionally, the shell of the optical fiber transceiver 32 can be made of metal or high-strength plastic to protect the internal precise photoelectric conversion components. In terms of setting mode, it is connected to the FPGA chip 31 through a specific interface to receive the encapsulated data stream. In installation, the optical fiber transceiver 32 can be fixed on the circuit board of the video processing assembly 3 or installed in a suitable position in the receiving cavity through a support or the like.

[0055] The core function of the optical fiber transceiver 32 is to realize the conversion between electrical signals and optical signals. The optical fiber transceiver 32 can convert the encapsulated data stream processed by the FPGA chip 31 into an optical signal and transmit it at a high speed through an optical fiber. By taking advantage of the characteristics of optical signals, such as strong anti-interference ability and long transmission distance, the stable and efficient transmission of video data to the receiving end is ensured.

[0056] Optionally, in an implementation manner of the present application, the connector 33 can be a flexible printed circuit (FPC) connector 33. The FPC connector 33 forms a one-to-one connection relationship with the camera module 2 by virtue of its unique performance advantages, ensuring efficient and stable video data transmission.

[0057] In terms of setting mode, the connector 33 and the camera module 2 can adopt a one-to-one exclusive connection strategy. Each camera module 2 is equipped with an independent FPC connector 33, and the video data collected by the camera module 2 is transmitted to the FPGA chip 31 in the video processing component 3 through the wire. This one-to-one connection mode avoids interference and conflict in data transmission of multiple camera modules 2, ensures that the video data collected by each camera module 2 can be transmitted independently and stably, and provides a basis for subsequent processing of different direction video data by the FPGA chip 31.

[0058] The core role of the connector 33 is to build a dedicated data transmission channel between the camera module 2 and the FPGA chip 31. Through the connector 33, the video data of different directions in the external environment collected by the camera module 2 can be transmitted to the FPGA chip 31 in a low-loss and high-fidelity state, providing raw data for the FPGA chip 31 to perform preset protocol packaging processing. At the same time, the flexible characteristics of the FPC connector 33 can also effectively alleviate the stress influence caused by device vibration and component thermal expansion and cold contraction, further guaranteeing the reliability of video data transmission, and is an important link to realize the multi-directional video acquisition and processing function of the video transmission device 100.

[0059] Optionally, in the embodiment of the present application, the power supply 4 can adopt an independent modular design and be integrated as a complete functional unit in the receiving cavity of the protective shell 1. This design facilitates independent testing and replacement of the power supply 4. The power supply 4 can provide multiple voltage stabilizers such as 3.3V, 1.8V and 1.0V.

[0060] Optionally, in order to avoid the influence of heat and electromagnetic interference generated by the power supply 4 on other components, the power supply 4 module can be physically isolated from the video acquisition component and the video processing component 3. For example, a heat-conducting partition is used to separate the power supply 4 area from other components, and an electromagnetic shielding layer is arranged around the power supply 4 module to prevent electromagnetic radiation from interfering with the acquisition and processing of video signals.

[0061] Optionally, the power supply 4 module can be fixed in the receiving cavity of the protective shell 1 by screws, buckles or card slots, etc., to ensure that it will not be displaced due to vibration or collision during device operation. For example, mounting holes are arranged at the four corners of the power supply 4 module, and screws are used to fixedly connect the power supply 4 module to the inner wall of the protective shell 1; or a card slot is arranged on the inner wall of the protective shell 1, and the power supply 4 module is directly clamped into the card slot to realize quick installation and positioning.

[0062] The connection of the power supply 4 and other components can adopt a standardized interface design to ensure the stability and reliability of the electrical connection. For example, the output end of the power supply 4 is connected to the power supply interface of the video acquisition component and the video processing component 3 through a wire harness, and a anti-loosening design (such as a lock type connector) is adopted at the interface to prevent poor contact caused by vibration. At the same time, for the convenience of maintenance and replacement, the wiring adopts a modular design and can be quickly plugged and unplugged.

[0063] Optionally, the power supply 4 is used to provide stable power for the video acquisition component and the video processing component 3. According to the needs of different components, the power supply 4 can output multiple voltage levels to ensure the normal operation of each component. For example, a high-precision low-voltage power supply 4 is provided for the FPGA chip 31, and a stable working current is provided for the camera module 2 to ensure the stability and clarity of image acquisition.

[0064] The power supply 4 module can be built-in multiple protection circuits, such as over-voltage protection, over-current protection, short-circuit protection, and over-heat protection. When an abnormal situation occurs, the power supply 4 can be automatically cut off or take current limiting measures to prevent damage to other components, thereby improving the safety and reliability of the device.

[0065] In the video transmission device 100 provided in the embodiment of the present application, the device includes a protective shell 1, at least two camera modules 2, a video processing component 3, and a power supply 4. The camera modules 2 are arranged in the receiving cavity, and the two camera modules 2 arranged at an angle interval along the first direction X can collect imaging conditions in different directions of the external environment. The video processing component 3 includes an FPGA chip 31, an optical fiber transceiver 32, and at least two connectors 33. The camera modules 2 are respectively connected to the corresponding connectors 33 through a wire harness, the input end of the FPGA chip 31 is connected to the connectors 33, and the output end is connected to the optical fiber transceiver 32. The FPGA chip 31 is responsible for performing pre-set protocol packet encapsulation processing on the video data collected by the camera modules 2 to obtain encapsulated data stream, and then the optical fiber transceiver 32 converts the encapsulated data stream into optical signals for transmission. The arrangement of multiple camera modules 2 enables the video transmission device 100 to cover multiple directions of the scene, and the video transmission device 100 integrates at least two multi-view camera modules 2, a set of video processing components 3 (FPGA chip 31, optical fiber transceiver 32), and a power supply 4 in the same protective shell 1, so as to replace multiple independent cameras with multiple modules, share core processing and transmission components, thereby compressing the monitoring task originally completed by N independent camera devices into a set of hardware, avoiding repeated purchase of FPGA and other devices, and thereby reducing the cost of core hardware. Moreover, the video transmission device 100 only needs to connect the camera modules 2 and the video processing component 3 through a wire harness, and finally transmits all data through a single optical fiber, which greatly reduces the number of body wiring, thereby effectively reducing the cost of the video transmission device 100.

[0066] In an embodiment, as shown inFigures 2-4 The preset protocol is an ARINC818 protocol as shown in the figure.

[0067] The FPGA chip 31 comprises:

[0068] The format conversion module 311 is in communication connection with the connector 33, and is configured to perform format conversion on the video data collected by the camera module 2, so that the data format of the video data conforms to the ARINC818 protocol.

[0069] The protocol encapsulation unit 312 is in communication connection with the format conversion module 311, and is configured to perform data encapsulation on the video data that has been subjected to format conversion by the format conversion module 311 according to the ARINC818 protocol, to obtain the encapsulated data stream.

[0070] The serial transmission module 313 is in communication connection with the protocol encapsulation unit 312 and the optical fiber transceiver 32 respectively, and is configured to serially transmit the encapsulated data stream to the optical fiber transceiver 32.

[0071] Optionally, the ARINC818 protocol is an important standard for high-speed data transmission in the field of avionics, and is fully named Aeronautical Radio, Inc. Specification 818, which is formulated by the Aeronautical Radio, Inc. and is mainly used for transmission of high-definition video, images and other high-speed data inside an aircraft. The ARINC818 protocol has the characteristics of high reliability, low delay and strong anti-interference capability.

[0072] Optionally, in the embodiment of the present application, the format conversion module 311 is configured to directly communicate with the output end of the connector 33 and receive the original video data from the camera module 2. The format conversion module 311 can be integrated in the programmable array of the FPGA chip 31 in the form of a programmable logic circuit, and is electrically connected to other modules through the internal wiring resources of the chip. The format conversion module 311 can perform format conversion on the original video data to make it conform to the requirements of the ARINC818 protocol. For example, the parallel data (such as 24-bit RGB format) output by different camera modules 2 can be converted into 32-bit data format specified by the ARINC818 protocol, to provide standardized data input for subsequent protocol encapsulation.

[0073] Optionally, the protocol encapsulation unit 312 can be in communication connection with the format conversion module 311 through the internal bus of the FPGA, to receive the video data that has been subjected to format conversion. The protocol encapsulation unit 312 can also be integrated in the FPGA chip 31 in the form of a programmable logic circuit, and realizes data interaction with the format conversion module 311 and the serial transmission module 313 through a predefined interface.

[0074] Optionally, in an implementation of the present application, when the format conversion module 311 outputs 32-bit parallel valid band video data, the protocol encapsulation unit 312 first calculates the number of rows of input video data according to the ARINC818 protocol standard, and judges whether the amount of data per packet meets the frame length requirement specified by the protocol. If the number of data rows is insufficient or exceeds the standard range, the protocol encapsulation unit 312 will start the padding mechanism to add specific padding data or delete redundant information, so that the length of each frame of data meets the protocol specification, ensuring the stability and compatibility of the transmission process.

[0075] In the data encapsulation process, the protocol encapsulation unit 312 can automatically identify and match different video formats, and analyze and convert the data structure through the format adaptation module built-in the protocol encapsulation unit 312. At the same time, the protocol encapsulation unit 312 will add necessary protocol header information such as frame start marker, timestamp, frame number, etc. to each frame of video data to ensure the integrity and timing correctness of the data in the transmission process.

[0076] In addition, the protocol encapsulation unit 312 also has dynamic optimization capability, which intelligently groups and encapsulates the data stream according to the characteristics of the input video data and the transmission requirements, selects the optimal encapsulation strategy, and maximizes the data transmission efficiency and bandwidth utilization. Finally, the video data processed by the protocol encapsulation unit 312 will be converted into transmission frames that meet the ARINC818 protocol standard, laying the foundation for subsequent high-speed and stable optical signal transmission through the serial transmission module 313 to the optical fiber transceiver 32.

[0077] Optionally, the serial transmission module 313 establishes communication connection with the protocol encapsulation unit 312 and the optical fiber transceiver 32 respectively as the last link of data output. The serial transmission module 313 can be integrated inside the FPGA chip 31 and physically connected with the optical fiber transceiver 32 through a high-speed differential signal interface.

[0078] The serial transmission module 313 can convert the parallel encapsulated data stream generated by the protocol encapsulation unit 312 into a high-speed serial data stream, and perform signal conditioning according to the interface specification of the optical fiber transceiver 32. For example, 8b / 10b encoding (to ensure signal DC balance), clock recovery and data rate matching are realized, and finally the processed serial data stream is transmitted to the optical fiber transceiver 32, preparing for electro-optical conversion and long-distance transmission.

[0079] In these optional embodiments, the modular design of the FPGA chip 31 is combined with the ARINC818 protocol to realize the standardization and high efficiency of video data processing. The format conversion module 311 ensures that the multi-source video data is unified into a protocol-compatible format, eliminating compatibility problems caused by format differences; the protocol packaging unit 312 optimizes the data stream structure and improves transmission reliability through compliance frame length control and intelligent padding mechanism; the serial transmission module 313 realizes long-distance low-loss transmission by means of high-speed differential signals. The three work together to meet the stringent requirements of the avionics system for video transmission (such as real-time performance, anti-interference performance), and support flexible configuration and function expansion through the programmable characteristics of hardware, significantly reducing system complexity and cost, and providing a cost-effective solution for aviation video applications.

[0080] In an embodiment, as shown in Figure 5 The format conversion module 311 includes:

[0081] A video format determination unit 3111 is in communication with the connector 33. The video format determination unit 3111 is configured to identify the video format of the video data collected by the camera module 2.

[0082] A video format conversion unit 3112 is in communication with the video format determination unit 3111. The video format conversion unit 3112 is configured to convert the video data in YUV422 bus format into video data in RGB888 bus format when the video format determination unit 3111 determines that the video format of the video data is YUV422 bus format.

[0083] A data bit width conversion unit 3113 is in communication with the video format conversion unit 3112. The data bit width conversion unit 3113 is configured to convert the 24-bit parallel video data in RGB888 bus format into video data in 32-bit data format.

[0084] Optionally, in a feasible implementation manner of the present application, the video format determination unit 3111 can automatically identify eight mainstream video formats, including RGB888 and YUV422 bus formats, and resolutions such as 1080P (1920x1080), 720P (1280x720), 1600x1200, and 2K (2560x1440), supporting 30 frames per second (fps) and 60 fps, by analyzing external input / output (Input / Output, IO) state signals and data stream characteristics.

[0085] Optionally, the video format judging unit 3111 can be configured with multiple independent video format judging units 3111 or time-division multiplexing the same video format judging unit 3111 for the input of the multi-camera module 2, and the processing object is switched through a chip selection signal.

[0086] Optionally, when the video format judging unit 3111 identifies the YUV422 format, the video format conversion unit 3112 can perform color space conversion to convert the YUV422 data into the RGB888 format. Since the ARINC818 protocol encapsulation and subsequent data processing link are more suitable for the RGB format, and most image algorithm libraries support RGB input by default, converting to the RGB888 format can ensure the compatibility of the data format with each module of the system, and avoid protocol encapsulation errors and processing obstacles.

[0087] Optionally, the video format conversion unit 3112 is in communication connection with the video format judging unit 3111 and is located at the back end of the video format judging unit 3111, receiving the format judgment result and the corresponding video data from the video format judging unit 3111. Inside the FPGA chip 31, the layout and wiring design of the video format conversion unit 3112 fully considers the efficiency of data transmission and the logical continuity. It is connected with the subsequent processing units such as the data bit width conversion unit 3113, ensuring that the converted video data can smoothly flow into the next processing link.

[0088] Optionally, the data bit width conversion unit 3113 expands the 24-bit RGB data (R: 8 bits, G: 8 bits, B: 8 bits) into 32 bits, and organizes the expanded 32-bit data into a continuous data stream according to the requirements of the ARINC818 protocol, ensuring that the data boundary is aligned.

[0089] Optionally, in an embodiment, a 24-bit wide data bus can be configured at the input side of the data bit width conversion unit 3113, and a 32-bit wide bus can be configured at the output side, solving the bit width mismatch problem asynchronously. Protocol adaptation logic can also be added at the output end of the data bit width conversion unit 3113 to ensure that the converted 32-bit data meets the bit sequence and alignment requirements of the ARINC818 protocol.

[0090] In these optional embodiments, the video format judging unit 3111, the video format conversion unit 3112, and the data bit width conversion unit 3113 work together to ensure that the multi-source video data is efficiently converted into a protocol-compatible format, reducing system complexity and cost, and providing a high-reliability video transmission solution for the avionics system.

[0091] In an embodiment, as Figure 6As shown, the video processing component 3 further comprises a serializer / deserializer (SERDES, not shown in the figure); the SERDES is communicatively connected with the format conversion module 311 and the fiber transceiver 32, respectively;

[0092] The serial transmission module 313 comprises:

[0093] An error detection and correction unit 3131 is communicatively connected with the format conversion module 311, and the error detection and correction unit 3131 is configured to perform CRC check on the encapsulated data stream;

[0094] A serial high-speed transmission unit 3132 is communicatively connected with the error detection and correction unit 3131, and the serial high-speed transmission unit 3132 is configured to convert the CRC-checked encapsulated data stream into a serial data stream, and send the serial data stream to the fiber transceiver 32 through the SERDES.

[0095] Optionally, the SERDES is mainly used for high-speed serialization and deserialization of data between the FPGA chip 31 and the fiber transceiver 32. At the sending end, the serializer converts the parallel data from the FPGA chip 31 into a high-speed serial data stream for transmission through the fiber link. This process significantly improves the data transmission efficiency while reducing the number of physical connections required. At the receiving end, the deserializer converts the received high-speed serial data stream back into parallel data for subsequent processing.

[0096] In the video transmission device 100, the SERDES serves as the key interface between the FPGA chip 31 and the fiber transceiver 32. The SERDES can be connected to the output end of the FPGA chip 31 through a high-speed interface. After completing the encapsulation and processing of the video data, the FPGA chip 31 sends the parallel data to the SERDES module. The output end of the SERDES module is connected to the fiber transceiver 32, which converts the high-speed serial data stream into an optical signal for transmission.

[0097] Optionally, the error detection and correction unit 3131 verifies the video data using Cyclic Redundancy Check (CRC) to detect errors that may occur during data transmission. Specifically, during video data encapsulation, the error detection and correction unit 3131 calculates a CRC check value for each frame of data. After receiving the data, the receiving end recalculates the CRC value and compares it with the CRC value from the sending end to determine whether the data has changed during transmission. The error detection and correction unit 3131 can also identify frame drops in the video stream and take corresponding measures, such as requesting retransmission or compensating through interpolation. For certain types of errors detected, the error detection and correction unit 3131 can automatically correct them, thereby reducing the impact on video quality.

[0098] Optionally, the error detection and correction unit 3131 can be located at the front end of video data encapsulation and transmission to perform verification and processing before data transmission. The error detection and correction unit 3131 is closely connected to the video format conversion module 311 and the serial high-speed transmission unit 3132. In the data flow, the error detection and correction unit 3131 receives data from the video format conversion module 311, performs verification and correction, and then sends the processed data to the serial high-speed transmission unit 3132.

[0099] Optionally, the serial high-speed transmission unit 3132 is responsible for further processing the video data that has undergone error detection and correction, so as to enable high-speed transmission via the fiber optic link. Specifically, within the FPGA chip 31, the serial high-speed transmission unit 3132 achieves high-speed serialization of data by calling a high-speed interface IP core (such as a GTP IP core). The serial high-speed transmission unit 3132 configures the corresponding parameters according to the requirements of SERDES to ensure the stability and speed of data transmission.

[0100] In these alternative embodiments, the cooperative operation of the error detection and correction unit 3131 and the serial high-speed transmission unit 3132 ensures the transmission quality of video data in complex environments, meets the stringent requirements of high-resolution video transmission, and effectively improves the efficiency and stability of video transmission.

[0101] In one embodiment, such as Figure 7 As shown, the fiber optic transceiver 32 includes:

[0102] The optical fiber transmitting unit 321 is communicatively connected to the FPGA chip 31, and the optical fiber transmitting unit 321 is used to convert the packaged data stream into an optical signal.

[0103] A clock recovery unit 322 is connected with the fiber transmitting unit 321, and is configured to recover a data synchronization clock from the received optical signal.

[0104] Optionally, in the embodiment, the fiber transmitting unit 321 receives the packaged data stream (electrical signal) from the FPGA chip 31, first converts the digital signal into a current signal suitable for optical modulation through an internal driving circuit, then drives the laser to convert the current signal into an optical pulse signal, and finally couples the optical signal into the optical fiber for transmission through the optical fiber interface.

[0105] The clock recovery unit 322 works at the receiving end. After the optical signal is transmitted to the receiving module through the optical fiber, the optical signal is first converted back to an electrical signal by a photodetector, and then the clock information is extracted from the electrical signal through a phase-locked loop or a delay-locked loop to reconstruct a clock signal synchronized with the sending end, ensuring the accuracy of data sampling, and at the same time eliminating the jitter introduced in the transmission process through the clock data recovery technology to improve the stability of data reception.

[0106] Optionally, the fiber transmitting unit 321 can be connected with the SERDES output end of the FPGA through a differential electrical interface, and the laser bias current and the modulation current are configured through adjustable resistors or digital potentiometers to adapt to different transmission distances and fiber types.

[0107] The fiber transmitting unit 321 and the clock recovery unit 322 can be internally connected through microstrip lines or coplanar waveguides on a printed circuit board, and optical isolators and other devices are used to reduce optical reflection interference. The whole is packaged as a small module to adapt to the space limitation of the avionics equipment. This setting mode not only ensures the reliability of high-speed data transmission, but also simplifies system integration and maintenance through modular design.

[0108] In these optional embodiments, the fiber transmitting unit 321 converts the packaged data stream output by the FPGA into an optical signal, and uses the low-loss and anti-interference characteristics of the optical fiber to realize long-distance stable transmission; the clock recovery unit 322 recovers the synchronization clock from the received optical signal, eliminates the transmission jitter, and ensures the accuracy of data timing. The cooperation of the two not only improves the transmission efficiency and reliability, adapts to the complex electromagnetic environment of aviation, but also simplifies the system architecture, reduces the bit error rate and maintenance cost, and enhances the equipment availability.

[0109] In an embodiment, as shown in Figure 8 Fig. 1, the camera module 2 comprises:

[0110] a core frame 21;

[0111] a lens seat 22 mounted on the core frame 21;

[0112] A lens 23 is mounted on the lens seat 22; the optical axes of the lenses 23 corresponding to different camera modules 2 form a preset included angle in space.

[0113] A sensor board 24 is fixed on the core frame 21 and arranged opposite to the lens 23, and the sensor board 24 is used to convert the optical image focused by the lens 23 into an electrical signal.

[0114] Optionally, the core frame 21 is the basic support structure of the camera module 2, which can be a cuboid or an irregular shape, and the specific shape depends on the overall design and installation space of the camera module 2. The core frame 21 is located at the outermost layer of the camera module 2, and provides an installation and fixing platform for the internal components of the camera module 2.

[0115] The core frame 21 can be fixed in the protective shell 1 of the video transmission device 100 through mechanical structures such as screws or buckles. The core frame 21 can be installed at a specific position of the shell to ensure long-term stability.

[0116] The main function of the core frame 21 is to provide mechanical support and protection for the internal components of the camera module 2, such as the lens seat 22, the lens 23 and the sensor board 24. It ensures the stable operation of the camera module 2 in complex environments and prevents the internal components from being damaged due to external factors such as vibration or impact.

[0117] Optionally, the lens seat 22 is installed on the core frame 21 and can be located at the front end of the core frame 21 to align with the lens 23 and the sensor board 24. The lens seat 22 can be fixed on the core frame 21 by means of screws or adhesives. This installation method ensures that the connection between the lens seat 22 and the core frame 21 is tight and stable.

[0118] The lens seat 22 is used to fix and position the lens 23, ensuring the accurate distance and angle between the lens 23 and the sensor board 24, so as to ensure that the optical image can be accurately focused on the sensor board 24.

[0119] Optionally, the lens 23 is installed on the lens seat 22 and located at the front end of the camera module 2, directly contacting the external environment. The orientation and position of the lens 23 are determined by the structure of the lens seat 22 and the core frame 21 to ensure that the image in the required direction can be captured.

[0120] The lens 23 can be installed on the lens seat 22 through threads, bayonets or adhesives, ensuring that the connection between the lens 23 and the lens seat 22 is firm and stable. The installation method of the lens 23 needs to ensure that the focal length and optical axis of the lens 23 remain stable under conditions such as vibration and temperature change.

[0121] The main function of the lens 23 is to capture the light in the external environment and focus it on the Sensor board 24. The performance of the lens 23 directly affects the imaging quality of the camera module 2.

[0122] Optionally, the Sensor board 24 is fixed on the core frame 21, opposite to the lens 23, located at the rear of the lens 23. The position and angle of the Sensor board 24 are precisely adjusted to ensure that it can receive the optical image focused by the lens 23.

[0123] The Sensor board 24 can be fixed on the core frame 21 by screws or buckles, maintaining a certain distance and angle with the lens seat 22 and the lens 23. The installation of the Sensor board 24 needs to ensure that it is aligned with the optical axis of the lens 23 to achieve the best imaging effect.

[0124] The Sensor board 24 is used to convert the optical image focused by the lens 23 into an electrical signal. The Sensor board 24 can contain a CMOS sensor that can capture light signals and convert them into digital signals for subsequent processing.

[0125] In these optional embodiments, the core frame 21 provides stable support for the whole, ensuring the precise installation position of each component. The lens seat 22 is installed on the core frame 21, precisely positioning the lens 23 to ensure the accuracy of the optical axis position. The lens 23 is installed on it, opposite to the Sensor board 24, to achieve optical image focusing and transmission. The optical axes of different camera modules 2 lenses 23 form a preset angle, widening the range of shooting angles. The Sensor board 24 converts the optical image into an electrical signal, laying the foundation for subsequent processing. The overall setting not only ensures the imaging quality, but also meets the diversified shooting needs, improving the stability, accuracy and functionality of the camera module 2.

[0126] In an embodiment, the housing comprises:

[0127] The first side cover plate 11 is arranged opposite along the first direction X, the second side cover plate 12 is arranged opposite along the second direction Y, and the third side cover plate 13 is arranged opposite along the third direction Z, the first side cover plate 11, the second side cover plate 12 and the third side cover plate 13 are formed around to form the accommodation cavity, the first direction X and the second direction Y intersect, and the second direction Y and the third direction Z intersect;

[0128] The second side plate on the side close to the camera module 2 along the second direction Y has at least two light windows, each of the light windows corresponds to the position of the lens 23 of the corresponding camera module 2, for allowing light to enter the lens 23.

[0129] Optionally, the first side cover plate 11, the second side cover plate 12 and the third side cover plate 13 jointly define the spatial form of the shell. They can be connected to each other in a mutually cooperative manner by welding, screw fastening or snap connection, etc. to form a closed or semi-closed receiving cavity.

[0130] The first side cover plate 11, the second side cover plate 12 and the third side cover plate 13 jointly constitute the shell, which plays a protective role on the internal components of the shell, blocks the entry of external dust and water vapor, and enhances the structural strength and stability of the shell.

[0131] In an embodiment, the first direction X, the second direction Y and the third direction Z are perpendicular to each other, forming a three-dimensional coordinate system, which clearly defines the position and direction of each part of the shell in space, so that the positions and relative relationships of the first side cover plate 11, the second side cover plate 12, the third side cover plate 13 and the light window, etc. are accurately determined, the structural layout of the entire shell is standardized, and the orderly arrangement and function realization of the shell and the internal camera module 2, etc. are ensured.

[0132] Optionally, the light window is arranged on the second side plate on the side close to the camera module 2 along the second direction Y, and the number is at least two, and it is accurately corresponding to the position of the corresponding camera module 2 lens 23, and the material of the light window is generally a material with good light transmission such as optical glass, etc.

[0133] The light window can be installed on the second side plate by gluing, inlaying, etc. and will be sealed to prevent water vapor, dust, etc. from entering to affect the light transmission. As the light incident channel, the light window ensures that the external light can accurately enter the camera module 2 lens 23, which is a necessary structure for realizing optical imaging.

[0134] In these optional embodiments, a closed receiving cavity is constructed by multi-dimensional cover plates to provide all-round protection for the camera module 2 and enhance the structural stability; the three directions intersect to form a three-dimensional frame, which optimizes the internal space layout and facilitates the orderly installation of components; the second side plate light window accurately corresponds to the lens 23 to ensure efficient light entry and improve imaging quality; the multi-light window design supports multiple lens 23 modules to work simultaneously, which widens the shooting angle range; the overall design takes into account the protection and functionality, which not only isolates external interference but also guarantees optical performance, meeting the use requirements in complex environments.

[0135] In an embodiment, the video processing component 3 further comprises:

[0136] An image signal processor 34 is in communication connection with the connector 33 and the FPGA chip 31 respectively, and the image signal processor 34 is used for image optimization on the image data collected by the camera module 2, and transmits the image data after image optimization to the input end of the FPGA chip 31.

[0137] Optionally, in the embodiments of the present application, the image signal processor 34 (Image Signal Processor, ISP) plays a key role in the video processing component 3, mainly responsible for optimizing the image data collected by the camera module 2. The ISP is in communication connection with the connector 33 and the FPGA chip 31, constituting an important link in the video processing process. After receiving the image data from the connector 33, the ISP performs white balance adjustment, detects the color information in the image through an algorithm, automatically adjusts the color balance, ensures accurate color restoration of the image, and avoids color deviation. Then the image is sharpened, the image edge contrast is enhanced, the image details are more clear and prominent, and the visual clarity is improved. At the same time, in order to remove image noise, the ISP can use a filtering algorithm to denoise the image data, preserve image details while reducing noise, and improve image purity. After completing these basic optimization operations, the ISP transmits the optimized image data to the input end of the FPGA chip 31 through the RGB888 or YUV422 bus, preparing for subsequent video processing.

[0138] In these optional embodiments, in the video processing component 3, the image signal processor 34 is connected with the connector 33 and the FPGA chip 31, and can perform denoising, white balance adjustment, sharpening and other optimization processing on the original image data collected by the camera module 2, and output high-quality images. This can not only reduce the FPGA computing pressure and enable it to focus on protocol packaging and transmission, but also enhance system compatibility through standard format output, and modular design facilitates algorithm upgrade, improving system flexibility and overall processing efficiency.

[0139] In an embodiment, the video processing component 3 further comprises:

[0140] The host computer communication connector 35 is in communication connection with the FPGA chip 31, and is used to receive control instructions sent by the host computer to control the video transmission device 100.

[0141] Optionally, in the embodiments of the present application, the host computer communication connector 35 can realize communication with the FPGA chip 31 through a hardware interface and a protocol adaptation. On the hardware side, standard interfaces such as RS-485, Ethernet or USB can be used to connect the host computer and the FPGA through a cable, ensuring stable signal transmission; on the protocol level, TCP / IP or a custom protocol can be supported to parse the control instructions (such as video acquisition parameter adjustment and transmission rate setting) sent by the host computer into digital signals recognizable by the FPGA. The connector 33 is internally integrated with a level conversion and signal isolation module to avoid interference and perform checksum and error correction on the instructions, ensuring accurate and error-free transmission of the instructions to the FPGA and precise control of the video transmission device 100.

[0142] In these optional embodiments, the host computer communication connector 35 is connected with the FPGA chip 31, realizing the remote control of the video transmission device 100 by the host computer. It can accurately receive and transmit control instructions, flexibly adjust video acquisition parameters, transmission rate and other functions, and improve the operability and flexibility of the system; at the same time, by establishing a stable communication link, the device state monitoring and remote management are realized, which is convenient for timely maintenance and optimization, and enhances the practicability and intelligent level of the video transmission device 100.

[0143] In an embodiment, the video processing assembly 3 further comprises:

[0144] The power supply connector 36 is electrically connected with the power supply 4, for supplying power to the video processing assembly 3.

[0145] In these optional embodiments, the power supply connector 36 provides stable power input, ensuring the normal operation of each component, avoiding data processing abnormalities or equipment failure caused by unstable power supply; at the same time, the standardized connection method facilitates the replacement and maintenance of the power supply 4, enhancing the reliability of the system; in addition, the power can be allocated as needed, optimizing the energy utilization efficiency, laying a foundation for the continuous and stable work of the video processing assembly 3.

[0146] Figure 9 A flowchart of a video transmission method provided by another embodiment of the application is shown. The video transmission method provided by the embodiment of the application is applied to the video transmission device 100 of any of the foregoing embodiments, and the method comprises:

[0147] S100, collecting video data in different directions in the external environment by at least two camera modules 2 respectively;

[0148] S200, receiving the video data by the connector 33 and transmitting the video data to the FPGA chip 31;

[0149] S300, performing preset protocol packet encapsulation processing on the video data by the FPGA chip 31, to obtain encapsulated data stream of the preset protocol;

[0150] S400, converting the encapsulated data stream into an optical signal by the optical fiber transceiver 32 and transmitting it.

[0151] In these optional embodiments, the video transmission method realizes efficient and reliable data transmission through the cooperation of multiple modules: at least two camera modules 2 are used to collect videos in different directions, widening the monitoring field of view; the connector 33 converges data to the FPGA chip 31, which is packaged and encapsulated according to a preset protocol (such as ARINC818), realizes format standardization and integrates error detection; finally, the packaged data stream is converted into optical signal transmission through the optical fiber transceiver 32, which takes advantage of the low loss and anti-interference characteristics of optical fiber to ensure the stability and real-time performance of long-distance high-speed transmission, meeting the needs of wide-area monitoring and reliable transmission in complex scenarios such as avionics.

[0152] In an embodiment, the preset protocol is the ARINC818 protocol.

[0153] The pre-set protocol packet encapsulation processing of the video data by the FPGA chip 31 obtains the encapsulated data stream of the preset protocol, which includes:

[0154] In the case where the video format of the video data is YUV422 bus format, the video data in YUV422 bus format is converted into video data in RGB888 bus format;

[0155] The 24-bit parallel video data in RGB888 bus format is converted into video data in 32-bit data format;

[0156] According to the video format of the video data in 32-bit data format, the number of rows and the padding mechanism are calculated according to the protocol requirements of the ARINC818 protocol, and the video data in 32-bit data format is encapsulated according to the number of rows and the padding mechanism to obtain the encapsulated data stream.

[0157] In the case where the CRC check of the encapsulated data stream is passed, the encapsulated data stream in parallel format is converted into encapsulated data stream in serial format, and the encapsulated data stream in serial format is sent to the optical fiber transceiver 32.

[0158] Optionally, in the ARINC818 protocol encapsulation process, the FPGA chip 31 first detects the video format, and when it is confirmed to be a YUV422 bus format, it is converted to an RGB888 format through color space conversion; then, 24-bit RGB data is reorganized into a 32-bit format in a 4-byte-per-cycle manner through bit width expansion, and the high bits are filled with zeros to achieve alignment; subsequently, according to the requirements of the ARINC818 protocol, the number of effective rows is calculated based on the video format, and a specific number of empty packets are filled at the end of each row to meet the requirements of the protocol on frame structure, forming a data packet that meets the specifications; finally, the encapsulated data stream is subjected to CRC check, and the parallel data stream is converted into a serial format through the high-speed transceiver IP core, and after 8b / 10b encoding, it is sent to the optical fiber transceiver 32, ensuring the reliability of data in high-speed transmission.

[0159] In these optional embodiments, YUV422 is converted to RGB888 to enhance color representation, and expansion to 32-bit data matches bus transmission efficiency; the number of rows is calculated according to the ARINC818 protocol and empty packets are filled to ensure compliance with the frame structure, supporting multi-channel synchronization and error detection; CRC check eliminates transmission error data, and parallel-to-serial conversion adapts to the characteristics of optical fiber high-speed transmission, ultimately realizing low-delay, high-fidelity aviation-level video data transmission, meeting the real-time and stability requirements in complex scenarios.

[0160] In an embodiment, the conversion of the encapsulated data stream into an optical signal by the optical fiber transceiver 32 and the transmission thereof include:

[0161] The optical fiber transceiver 32 receives the encapsulated data stream and reconstructs the synchronization clock of the encapsulated data stream according to the clock signal in the encapsulated data stream;

[0162] According to the synchronization clock, the encapsulated data stream is converted into an optical signal, and the optical signal is transmitted;

[0163] Wherein, during the transmission of the optical signal, according to the synchronization clock, the transmission timing of the optical signal is ensured to match the receiving end.

[0164] Optionally, in a specific implementation of the present application, first, the encapsulated data stream is received, the clock signal is extracted from the data stream by using a built-in clock and data recovery (CDR) circuit and a phase-locked loop, a clock synchronized with the data is reconstructed, and transmission jitter is eliminated; then, based on the synchronized clock, the parallel data stream is converted into a serial stream by a high-speed serializer, an electro-optical device such as a laser is driven, and an electrical signal is converted into an optical pulse signal (e.g., high level corresponds to light emission, and low level corresponds to no light emission); during transmission, the synchronized clock serves as a timing reference, the sending end sends data at its rhythm, the receiving end recovers the clock by the same CDR mechanism and synchronously samples, and at the same time, compensates for the delay fluctuation of the optical fiber transmission by means of adaptive equalization technology, so as to ensure the bit synchronization, frame synchronization and strict matching of the sending and receiving timing of the optical signal, realize low-error-rate high-speed stable transmission, and meet the stringent requirements of real-time performance and reliability in the aviation electronic field.

[0165] In these optional embodiments, the stability and accuracy of optical signal transmission are ensured by the synchronized clock mechanism: the synchronized clock is reconstructed from the encapsulated data stream, transmission jitter is eliminated, and the clock of the sending and receiving ends is synchronized; the electro-optical conversion is completed based on the synchronized clock, so as to ensure that the data bits strictly correspond to the optical pulses; during transmission, the sending and receiving timing is matched based on the clock, bit synchronization and frame synchronization are realized, and data misplacement or loss caused by timing deviation is avoided. Finally, reliable transmission with high speed and low error rate is realized, and the stringent synchronization requirements of long-distance real-time video transmission in the aviation electronic field are met.

[0166] It should be noted that the various optional implementations introduced in the embodiments of the present application can be combined with each other to be implemented, or can be implemented alone, and the embodiments of the present application do not limit this.

[0167] In order to facilitate understanding of the video transmission device 100 and the method provided in the above embodiments, the video transmission device 100 and the method are described below in a specific scene embodiment.

[0168] Optionally, in the embodiments of the present application, a video transmission device 100 and a method are disclosed, which realize multi-resolution and multi-frame-rate video data transmission through hardware-like adaptive encapsulation and high-speed transmission. The video transmission device 100 includes a protective shell 1, at least two camera modules 2, a video processing component 3, and a power supply 4. The at least two camera modules 2 realize image acquisition in a target field of view. The video processing component 3 supports video stream processing in multiple resolution formats, including ARINC818 protocol encapsulation, timing control, error code detection, and high-speed serial transmission. And uses a fiber transceiver 32 to realize long-distance high-reliability data transmission. The present application adopts a high-performance FPGA chip 31, supports high-resolution image low-delay transmission, combines with optical fiber communication to improve the anti-interference ability, and is suitable for aviation electronic high-reliability video transmission systems.

[0169] ARINC 818 protocol is a video transmission protocol specially used for avionics system, which is widely used in cockpit display system, flight recorder and airborne monitoring equipment. The traditional airborne video transmission system is limited by bandwidth, signal integrity and anti-interference ability, and cannot meet the real-time video transmission demand of high resolution and low delay. The embodiment of the application combines FPGA processing, optical fiber communication and error detection technology to improve transmission stability and real-time performance.

[0170] In an embodiment, as shown in Figures 4-6 The FPGA chip 31 can include:

[0171] The video format judging unit 3111 is used for identifying and judging the format of the video data stream. Specifically, the format of the two-way input FPGA internal video data stream to be processed can be judged through external IO state, which can be applicable to 8 video format judgments, such as RGB888 / YUV422 data stream bus transmission of 1080P, 720P, 1600x1200 and 2K video format, and video data judgment of 30 frames and 60 frames refresh rate format. The application is applicable to video format of no more than 2k@60FPS.

[0172] The video format conversion unit 3112 is used for converting the YUV422 bus format video data into RGB888 bus video format when the video format judging unit 3111 judges that the video format bus is YUV422.

[0173] The data bit width conversion unit 3113 converts the 24-bit parallel effective video data of RGB888 format into 32-bit wide data conforming to the bit width format of ARINC818 protocol.

[0174] The ARINC 818 protocol packaging unit 312 is used for ensuring the compliance of ARINC818 frame length by calculating the number of rows per package and the filling mechanism according to the requirements of ARINC 818 protocol, automatically matching different video formats, and realizing optimal data stream packaging and generating transmission frame for video data.

[0175] The serial high-speed transmission unit 3132 is used for calling high-speed interface GTPIP core in the FPGA, and realizing high-speed serialization through SERDES (serializer / deserializer).

[0176] The error detection and correction unit 3131 is used for CRC check, frame loss detection and automatic error correction. Specifically, after the video data is packaged according to the ARINC818 protocol, it checks whether each frame sequence is consecutive, and calculates the corresponding CRC check before the end symbol.

[0177] Optionally, in the embodiment of the application, the optical fiber transceiver 32 can include:

[0178] The optical fiber transmitting unit 321 is used for converting an electrical signal into an optical signal and transmitting.

[0179] The clock recovery unit 322 is used for reconstructing a data synchronization clock, and improving transmission stability.

[0180] Optionally, in the embodiment of the present application, the FPGA chip 31 can adopt an Xilinx 7 series chip, supports parallel data processing and high-speed serial transmission, and the high-speed interface line bundle rate bandwidth is not less than 6.6 Gbps.

[0181] Optionally, in the embodiment of the present application, the video transmission device 100 and the method have the following beneficial effects:

[0182] FPGA real-time data processing: can adapt to various video format data according to the ARINC818 protocol packaging, improve the ARINC 818 packaging efficiency, support high frame rate and high resolution transmission.

[0183] Optical fiber high-speed communication: improve transmission bandwidth, reduce electromagnetic interference, and improve system reliability.

[0184] Error code detection and recovery: using CRC check + frame loss detection + automatic error correction to ensure the stability of the transmission data.

[0185] Compatible with multiple video formats: supporting RGB888 and YUV422 two video bus interface data input judgment, adapting multiple resolutions and frame rates of video data according to ARINC818 protocol processing under two buses.

[0186] One monitoring camera is equipped with two CMOS sensors, which monitor different positions and directions respectively. The rear-end FPGA processing module can select or simultaneously transmit two-way image data to the onboard central control display system, saving the cost of rear-end hardware. Two-way video data is realized, different video formats are adapted, and ARINC818 protocol processing is realized to output to a remote device, ensuring high bandwidth, low delay, and high reliability of video transmission.

[0187] It should be noted that the information interaction, execution process and the like between the above devices / units are based on the same concept as the method embodiments of the present application, and are devices corresponding to the above method. All implementation manners in the above method embodiments are applicable to the embodiments of the device, and the specific functions and brought technical effects can be referred to the method part, and will not be repeated here.

[0188] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above functional units and modules is taken as an example, and in actual application, the above functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of software functional unit. In addition, the specific name of each functional unit and module is only for convenient distinction, and does not limit the protection scope of the present application. The specific working process of the unit and module in the system can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0189] Figure 10 A hardware structure schematic diagram of an electronic device provided by the embodiment of the present application is shown.

[0190] The device can include a processor 1001 and a memory 1002 storing program instructions.

[0191] The processor 1001 executes the program to implement the steps in any of the method embodiments described above.

[0192] For example, the program can be divided into one or more modules / units, one or more modules / units are stored in the memory 1002 and executed by the processor 1001 to complete the present application. One or more modules / units can be a series of program instruction segments that can complete a specific function, which is used to describe the execution process of the program in the device.

[0193] Specifically, the processor 1001 described above can include a central processing unit (CPU), or a specific integrated circuit (Application Specific Integrated Circuit, ASIC), or can be configured to implement one or more integrated circuits of the embodiments of the present application.

[0194] The memory 1002 can include mass storage for data or instructions. As an example and not by way of limitation, the memory 1002 can include a hard disk drive (HDD), a floppy disk drive, flash memory, an optical disc (e.g., a compact disc (CD) or a digital versatile disc (DVD)), a solid-state drive (SSD), a USB drive, or a combination of two or more of these. Where appropriate, the memory 1002 can include removable or non-removable (or fixed) media, where appropriate. The memory 1002 can be internal or external to the integrated gateway disaster recovery appliance. In particular embodiments, the memory 1002 is non-volatile, solid-state memory.

[0195] The memory can include read-only memory (ROM), random-access memory (RAM), magnetic disk storage mediums, optical storage mediums, flash memory devices, electrical, optical, or other physically tangible / moφhological memory storage devices. Thus, in general, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., a memory device) encoded with software that, when executed (by one or more processors), is operable to perform operations described with reference to the methods according to an aspect of the present disclosure.

[0196] The processor 1001 implements any one of the above-described embodiments by reading and executing program instructions stored in the memory 1002.

[0197] In one example, the electronic device further includes a communication interface 1003 and a bus 1010. The processor 1001, the memory 1002, and the communication interface 1003 are connected through the bus 1010 and accomplish communication therebetween.

[0198] The communication interface 1003 is mainly used to realize the communication between various modules, devices, units and / or equipment in the embodiments of the present application.

[0199] Bus 1010 includes hardware, software, or both, to couple components of the online data traffic metering device to each other and to couple components to other systems. For example, but not limited to, the bus can include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an InfiniBand (IB) interconnect, a Low Pin Count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association local (VLB) bus, or another suitable bus or a combination of two or more of these. Where suitable, bus 1010 can include one or more buses. Although a particular bus arrangement is described and shown in the embodiments, the present application contemplates any suitable bus or interconnect.

[0200] In addition, in combination with the method in the above-mentioned embodiments, the embodiments of the present application can provide a storage medium for implementation. The storage medium has program instructions stored thereon; the program instructions are executed by a processor to implement any one of the methods in the above-mentioned embodiments.

[0201] The embodiments of the present application further provide a chip, which includes a processor and a communication interface, the communication interface is coupled to the processor, the processor is configured to execute programs or instructions, to implement various processes of the above-mentioned method embodiments and achieve the same technical effects. To avoid repetition, details are not described here.

[0202] It should be understood that the chip mentioned in the embodiments of the present application can also be referred to as a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0203] The embodiments of the present application provide a computer program product, which is stored in a storage medium, and the program product is executed by at least one processor to implement various processes of the above-mentioned method embodiments and achieve the same technical effects. To avoid repetition, details are not described here.

[0204] It should be understood that the present application is not limited to the specific configurations and processes described above and shown in the drawings. For the sake of brevity, detailed descriptions of well-known methods are omitted here. In the above-mentioned embodiments, several specific steps are described and shown as examples. However, the method processes of the present application are not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between steps, after understanding the spirit of the present application.

[0205] The functional modules shown in the above block diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on machine-readable media or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable media" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer grids such as the Internet, intranets, etc.

[0206] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0207] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to create a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0208] The above are merely specific embodiments of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A video transmission apparatus characterized by comprising: The device comprises: A protective shell comprising a receiving cavity; At least two camera modules arranged in the receiving cavity, at least two camera modules being arranged at an angle along a first direction, and the at least two camera modules being used to collect imaging conditions in different directions of an external environment; A video processing assembly arranged in the receiving cavity, the video processing assembly comprising a field programmable gate array (FPGA) chip, a fiber transceiver, and at least two connectors, the at least two camera modules being respectively connected to the corresponding connectors through a wire; an input end of the FPGA chip being connected to the connectors, and an output end of the FPGA chip being connected to the fiber transceiver; the FPGA chip being used to perform preset protocol packet encapsulation processing on video data collected by the camera modules to obtain encapsulated data streams of the preset protocol; and the fiber transceiver being used to convert the encapsulated data streams into optical signals and transmit the optical signals. A power supply arranged in the receiving cavity, the power supply being used to supply power to the camera modules and the video processing assembly.

2. The apparatus of claim 1, wherein, The preset protocol is an ARINC818 protocol. The FPGA chip comprises: A format conversion module connected to the connectors, the format conversion module being used to perform format conversion on the video data collected by the camera modules so that the data format of the video data conforms to the ARINC818 protocol; A protocol encapsulation unit connected to the format conversion module, the protocol encapsulation unit being used to perform data encapsulation on the video data that has been format-converted by the format conversion module according to the ARINC818 protocol to obtain the encapsulated data streams; A serial transmission module connected to the protocol encapsulation unit and the fiber transceiver, the serial transmission module being used to serially transmit the encapsulated data streams to the fiber transceiver.

3. The apparatus of claim 2, wherein, The format conversion module comprises: A video format judgment unit connected to the connectors, the video format judgment unit being used to identify the video format of the video data collected by the camera modules; A video format conversion unit connected to the video format judgment unit, the video format conversion unit being used to convert video data in YUV422 bus format into video data in RGB888 bus format when the video format judgment unit determines that the video format of the video data is YUV422 bus format; A data bit width conversion unit connected to the video format conversion unit, the data bit width conversion unit being used to convert 24-bit parallel video data in RGB888 bus format into video data in 32-bit data format.

4. The apparatus of claim 2, wherein, The video processing assembly further comprises a serializer / deserializer (SERDES), the SERDES being connected to the format conversion module and the fiber transceiver; The serial transmission module comprises: An error detection and correction unit connected to the format conversion module, the error detection and correction unit being used to perform CRC checking on the encapsulated data streams; A serial high-speed transmission unit is in communication connection with the error detection and correction unit, and is configured to convert the CRC-verified packaged data stream into a serial data stream and transmit the serial data stream to the fiber transceiver through the SERDES.

5. The apparatus of claim 1, wherein, The fiber transceiver comprises: A fiber transmission unit in communication connection with the FPGA chip, and configured to convert the packaged data stream into an optical signal; A clock recovery unit in communication connection with the fiber transmission unit, and configured to recover a data synchronization clock from the received optical signal.

6. The apparatus of claim 1, wherein, The camera module comprises: A core frame; A lens seat mounted on the core frame; A lens mounted on the lens seat; the optical axes of the lenses corresponding to different camera modules form a preset included angle in space; A Sensor board fixed to the core frame and arranged opposite to the lens, and configured to convert an optical image focused by the lens into an electrical signal.

7. The apparatus of claim 6, wherein, The housing comprises: A first side cover plate arranged opposite along the first direction, a second side cover plate arranged opposite along the second direction, and a third side cover plate arranged opposite along a third direction, the first side cover plate, the second side cover plate and the third side cover plate forming the accommodation cavity therearound, the first direction and the second direction intersecting, and the second direction and the third direction intersecting; A second side plate on a side of the camera module close to the second direction has at least two light windows, each of the light windows corresponding to a position of a lens of a corresponding camera module, for allowing light to enter the lens.

8. A video transmission method characterized by comprising: The method is applied to the video transmission device of any one of claims 1-7, and comprises: Collecting video data in different directions in an external environment through at least two camera modules respectively; Receiving the video data through the connector and transmitting the video data to the FPGA chip; Performing a preset protocol packet encapsulation processing on the video data through the FPGA chip to obtain a packaged data stream of the preset protocol; Converting the packaged data stream into an optical signal through the fiber transceiver and transmitting the optical signal.

9. The method of claim 8, wherein, The preset protocol is an ARINC818 protocol; The preset protocol packet encapsulation processing on the video data through the FPGA chip to obtain a packaged data stream of the preset protocol comprises: In a case where a video format of the video data is determined to be a YUV422 bus format, converting the video data in the YUV422 bus format into video data in an RGB888 bus format; Converting 24-bit parallel video data in the RGB888 bus format into video data in a 32-bit data format; According to a video format of the video data in the 32-bit data format, calculating a row number and a padding mechanism according to protocol requirements of the ARINC818 protocol, and performing data encapsulation on the video data in the 32-bit data format according to the row number and the padding mechanism to obtain the packaged data stream; In the case that the encapsulated data stream CRC check passes, the encapsulated data stream in parallel format is converted into encapsulated data stream in serial format, and the encapsulated data stream in serial format is sent to the fiber transceiver.

10. The method of claim 8, wherein, The conversion of the encapsulated data stream into optical signal and the transmission by the fiber transceiver include: The encapsulated data stream is received by the fiber transceiver, and a synchronous clock of the encapsulated data stream is reconstructed according to a clock signal in the encapsulated data stream; The encapsulated data stream is converted into optical signal according to the synchronous clock, and the optical signal is transmitted; In the transmission process of the optical signal, the sending timing of the optical signal is ensured to match the receiving end according to the synchronous clock.

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