Wafer array packaging module, preparation method thereof and power device

Abstract

The invention provides a wafer array packaging module, a preparation method thereof and a power device, and relates to the field of semiconductors. The wafer array packaging module comprises a carrier plate, at least one surface of which is provided with a conductive layer along the thickness direction, and the conductive layer is used for being electrically connected with the outside; each wafer comprises a first surface and a second surface which are oppositely arranged along the thickness direction, a source electrode and a grid electrode are formed on the first surface, a drain electrode is formed on the second surface, and each first surface is connected with the conductive layer along the thickness direction to form a wafer array; and the conductive radiating fin covers the plurality of wafers and is connected with the second surface of each wafer along the thickness direction so as to form a parallel drain electrode. Generally speaking, according to the wafer array packaging module, the preparation method thereof and the power device provided by the invention, the heat dissipation performance and the power density of a power component in high-power application are greatly improved, the system reliability is higher, the electrical performance is obviously optimized, the PCB is simpler to assemble and process, and the terminal maintenance is more simplified.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, in particular to a wafer array packaging module and a preparation method thereof and a power device. BACKGROUND

[0002] In high-power applications such as battery management systems (BMS), multiple discrete MOSFET wafers are usually used, which are arranged in parallel on a PCB board by surface mounting technology to form an array to make a protection board to meet the large current flow capacity.

[0003] The process includes cutting MOSFET wafers into independent MOSFET wafers, packaging the MOSFET wafers in lead frames and connecting the electrodes by wire bonding, and using epoxy resin to form a whole plastic package to form discrete devices. Then, the multiple discrete devices are welded to the PCB board to form a MOSFET wafer array to obtain a power device. Since the MOSFET wafer array generates a large amount of heat, the heat dissipation capacity of the copper layer on the PCB board is limited, and a copper strip for flow guiding is generally installed on the MOSFET wafer array, and metal heat sinks are installed on the upper and lower surfaces of the PCB board to assist in heat dissipation.

[0004] The existing technology is subject to packaging materials and packaging processes, and generally has the following defects: on the one hand, the power device has low heat dissipation efficiency, and the heat is mainly conducted through the following two high-thermal-resistance paths: the heat is conducted from the internal lead frame of the wafer to the air through the epoxy resin (a poor thermal conductor), or the heat is conducted from the bottom heat dissipation pad of the wafer to the air through the thin PCB copper layer. Both paths cannot quickly transfer a large amount of heat, resulting in serious heat accumulation. On the other hand, due to the limited heat dissipation capacity, the power carried by a single discrete device is limited, and a distance needs to be maintained between multiple discrete devices to avoid heat concentration, so heavy copper strips and heat dissipation structures need to be installed to compensate for the heat dissipation shortcomings, resulting in an increase in the volume / weight of the module and a decrease in the power density. In addition, a large number of solder joints and mechanical connections (such as fixing screws) of the heat sinks increase the risk of failure, and the inconsistency of parameters of multiple discrete devices easily causes uneven current distribution and overheating of individual devices, and maintenance requires disassembly of the module, which is inconvenient to operate. In addition, the layout of the discrete devices and the long pins and PCB wiring introduce large parasitic inductance / resistance, which makes it difficult to synchronize the switching states of each MOSFET when high current is switched at high speed, and easily causes oscillation and voltage overshoot, affecting the stability and efficiency of the system.

[0005] In view of the above, the present application is proposed. SUMMARY

[0006] The present application provides a wafer array packaging module and a preparation method thereof and a power device, which aims to solve or alleviate at least one of the problems existing in the prior art.

[0007] The first aspect of the present application provides a wafer array packaging module, comprising: a carrier plate, having a conductive layer on at least one side in the thickness direction, the conductive layer being used for external electrical connection; a plurality of wafers, each wafer comprising a first side and a second side arranged oppositely in the thickness direction, the first side being formed with a source electrode and a gate electrode, and the second side being formed with a drain electrode, each first side being connected to the conductive layer in the thickness direction to form a wafer array; and a conductive heat sink, covering the plurality of wafers and being connected to the second side of each wafer in the thickness direction to form a parallel drain electrode.

[0008] In some embodiments, the wafer array packaging module further comprises: a first solder layer, arranged between the conductive layer and the wafer in the thickness direction, and connected to the conductive layer and the first side of the wafer, respectively.

[0009] In some embodiments, the wafer array packaging module further comprises: a second solder layer, arranged between the wafer and the conductive heat sink in the thickness direction, and connected to the second side of the wafer and the conductive heat sink, respectively.

[0010] In some embodiments, the wafer array packaging module comprises at least one of the following conditions: (1) the carrier plate comprises a substrate layer, a first conductive layer and a second conductive layer, the first conductive layer and the second conductive layer being arranged in the thickness direction, the substrate layer being arranged between the first conductive layer and the second conductive layer and being connected to the first conductive layer and the second conductive layer, respectively, and the first side of the wafer being connected to the first conductive layer and / or the second conductive layer; (2) the carrier plate is selected from any one of a direct copper clad ceramic substrate, an active metal brazing ceramic substrate, an aluminum nitride ceramic substrate, a silicon nitride ceramic substrate or a glass substrate; (3) the conductive heat sink comprises any one of a copper sheet, an aluminum sheet or a copper-aluminum composite sheet; (4) the wafer array packaging module further comprises: a conductive pin, connected to the conductive layer in the thickness direction and spaced apart from the wafer.

[0011] In some embodiments, the wafer array packaging module comprises at least one of the following conditions: (5) the wafer array packaging module further comprises: a third solder layer, arranged between the conductive layer and the conductive pin in the thickness direction, and connected to the conductive layer and the conductive pin, respectively; (6) the conductive pin comprises any one of a copper pin, an aluminum pin or a copper-aluminum composite pin; (7) the wafer array packaging module further comprises: a bottom filling adhesive layer, filled in the gap between the wafer and the carrier plate and in the gap between the conductive heat sink and the wafer; and a potting adhesive layer, covering all the outer surfaces of the non-electrically connected parts of the carrier plate, the wafer and the conductive heat sink; (8) The wafer array packaging module also includes: an integrated gate driver chip, a current sensor and / or a temperature sensor, all of which are connected to the conductive layer. (9) The chip array packaging module also includes: a heat sink, which is connected along the thickness direction to the side of the carrier plate away from the chip or the side of the conductive heat sink away from the chip.

[0012] A second aspect of this application provides a method for fabricating a wafer array package module, comprising: The system provides a plurality of wafers, a carrier plate having a conductive layer on at least one side along the thickness direction, and a conductive heat sink. Each wafer has its active and gate electrodes formed on its first side, which is connected to a conductive layer along the thickness direction of the substrate. A conductive heat sink is then connected to the second side of each wafer, which has its drain electrode formed, along the thickness direction, to obtain the wafer array packaging module as described above.

[0013] In some embodiments, connecting the first surface of each wafer, where the active electrode and gate are formed, to the conductive layer along the thickness direction of the substrate includes: Eutectic bonding is used to weld the first side of the wafer onto the conductive layer; or, A first solder is printed on the conductive layer surface of a carrier board, and the first sides of several wafers are respectively mounted onto the first solder along the thickness direction and subjected to a first welding process.

[0014] In some embodiments, connecting a conductive heat sink along the thickness direction to the second surface of each wafer where a drain is formed includes: The conductive heat sink is soldered to the second side of each chip using eutectic bonding; or A second solder is printed onto the second side of each chip, and a conductive heat sink is attached to the second solder on several chips and a second soldering process is performed.

[0015] In some implementations, at least one of the following conditions is included before obtaining the wafer array package module: A. Fill the gaps between the wafer and the carrier board, as well as the gaps between the conductive heat sink and the wafer, with bottom filler adhesive and perform the first curing process; B. Use eutectic bonding to solder the conductive pins to the surface of the conductive layer of the substrate, or print a third solder on the surface of the conductive layer of the substrate, mount the conductive pins to the third solder along the thickness direction and perform a third soldering process. C. Place the carrier board loaded with the chip and conductive heat sink, or the carrier board loaded with the chip, conductive heat sink and conductive pins, into the mold, inject potting compound into the mold, and then perform a second curing process.

[0016] In some implementations, at least one of the following conditions is also included: D. The first welding process, the second welding process and / or the third welding process are any one of hot pressing, reflow soldering or local hot pressing; E. The temperature of the first welding process, the second welding process and / or the third welding process is 150°C-320°C; F. The first solder, the second solder, or the third solder is selected from at least one of silver paste, copper paste, solder, gold-tin solder, or tin-silver-copper paste.

[0017] A third aspect of this application provides a power device assembled using a wafer array packaging module as described above or a wafer array packaging module prepared by the above-described preparation method.

[0018] The wafer array packaging module, its fabrication method, and power device provided in this application exhibit several significant advantages over existing technologies, including: Through the structural design of the chip array packaging module, several chips form an array in the chip array packaging module. Each chip has a source and a gate on its first side connected to a conductive layer on a carrier plate, and a drain on its second side connected to a conductive heat sink, so that the conductive heat sink forms a parallel drain electrode. As a result, multiple chips in the chip array packaging module are highly integrated, and multiple chips can be connected in parallel. At the same time, the heat generated by each chip can be dissipated through the carrier plate and the conductive heat sink on both sides, so as to significantly reduce the thermal resistance and greatly improve the heat dissipation efficiency. Under the same operating conditions as traditional technology, the temperature of the chip array packaging module can be significantly reduced.

[0019] Furthermore, the chip array packaging module eliminates the wire bonding process, which has lower reliability in traditional technologies. The chip array is integrated between the carrier board and the conductive heat sink. The modular integrated design reduces the number of solder joints and external connections, thereby reducing the failure rate. At the same time, the compact layout of the chip array makes the working environment of each chip highly consistent, the current distribution is better, it avoids single-point overheating failure, and it is easier to maintain.

[0020] Moreover, the carrier board and conductive heat sink have both conductive and heat dissipation functions. As the main current path of the chip array, they replace the traditional leads or lead frames, shortening the electrical connection path of the chip array. This significantly reduces parasitic inductance and resistance, improves current carrying capacity, and thus makes the switching synchronization of the chip array excellent. There is no need to add additional gate resistors to match the switching time of each chip, which simplifies the design of the drive circuit, suppresses oscillation and voltage overshoot, and helps to improve the stability and efficiency of the battery management system.

[0021] Furthermore, the improved thermal efficiency of the chip array package module can reduce the use of conductive copper strips and external heat dissipation structures, resulting in a significant reduction in the overall module size. This facilitates a substantial increase in the power density of the battery management system PCB board. Due to the high integration of the chip array package module, there is no need to design complex and dispersed discrete device arrays and heat dissipation structures, simplifying PCB board design, reducing product size, and making assembly, processing, and maintenance / replacement by end users much easier.

[0022] In summary, the chip array packaging module, its fabrication method, and power devices provided in this application greatly improve the heat dissipation performance and power density of power components in high-power applications, enhance system reliability, significantly optimize electrical performance, simplify PCB board assembly and processing, and streamline terminal maintenance.

[0023] The wafer array packaging module, its fabrication method, and power device of this application also have other advantages and features, which will be further described in subsequent detailed embodiments. Attached Figure Description

[0024] To more clearly illustrate the specific embodiments in this application or the technical solutions in the prior art, the required drawings will be briefly described below. These drawings illustrate some embodiments of this application and will provide a reference for those skilled in the art, enabling them to derive other related drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the structure of a chip array packaging module according to an embodiment of this application, showing the connection relationship of the various components.

[0026] Figure 2 This is a flowchart illustrating a method for fabricating a wafer array packaging module according to another embodiment of this application, specifically depicting the interconnections and execution sequence of each step.

[0027] The attached figures are labeled as follows: 100. Chip array packaging module; 10. Carrier board; 11. Conductive layer; 12. Substrate layer; 20. Chip; 30. Conductive heat sink; 40. First solder layer; 50. Second solder layer; 60. Conductive pin; 70. Third solder layer. Detailed Implementation

[0028] To more clearly illustrate the features and advantages of this application, the specific embodiments of the present invention are further described in detail below with reference to the accompanying drawings. It should be noted that the embodiments described herein are merely illustrative and intended to provide guidance to those skilled in the art, rather than limiting the technical solutions.

[0029] In existing technologies, traditional BMS (Battery Management System) protection boards typically employ multiple discrete MOSFET chips, arranged in parallel on a PCB board using surface mount technology to form an array. The number of MOSFET chips varies depending on the current, leading to low heat dissipation efficiency, low power density, large size, poor reliability, difficult maintenance, and high parasitic inductance / resistance parameters, limiting switching performance. The inventive concept of this application modularizes the MOSFET chip array, changing the traditional heat dissipation principle and eliminating traditional leads or lead frame structures. The chip array is directly connected between the conductive layer of the carrier board and the conductive heat sink, forming a chip array packaging module 100. This reduces the load area on the PCB board to one-third to one-fifth of the original area for the same power, significantly improving the heat dissipation performance and power density of power devices in high-power applications, enhancing system reliability, significantly optimizing electrical performance, simplifying PCB board assembly and processing, and simplifying terminal maintenance.

[0030] Based on the above concept, and referring to Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of a chip array packaging module according to an embodiment of the present application, showing the connection relationship of the various components. Only the connection between a single chip 20 and the carrier board 10 and the conductive heat sink 30 is shown in the example.

[0031] This application provides a wafer array packaging module 100, including: a carrier plate 10 having a conductive layer 11 on at least one side along the thickness direction, the conductive layer 11 being used for electrical connection with the outside; a plurality of wafers 20, each wafer 20 including a first side and a second side disposed opposite to each other along the thickness direction, the first side forming an active electrode and a gate electrode, the second side forming a drain electrode, each first side being connected to the conductive layer 11 along the thickness direction to form a wafer array; and a conductive heat sink 30 covering the plurality of wafers 20 and connected to the second side of each wafer 20 along the thickness direction to form a parallel drain electrode.

[0032] It should be noted that in the embodiments of this application, the wafer 20 is a MOSFET wafer, which is an independent functional unit of a metal-oxide-semiconductor field-effect transistor, and is obtained by wafer dicing from a silicon wafer.

[0033] The first side (i.e., the front side) of the MOSFET wafer 20 has metallized pads, including the gate (G) and the source (S), and the second side (i.e. the back side) is a full-surface metal layer to serve as the drain (D). The current between the source and the drain can be controlled by the gate voltage, and it is used as a high-speed power switch.

[0034] Understandably, the chip 20 can be flip-chip bonded so that its front side (gate / source) is connected downwards to the conductive layer 11 of the carrier 10, and its back drain is connected upwards to the conductive heat sink 30. Since multiple chips 20 form an array connected between the conductive layer 11 of the carrier 10 and the conductive heat sink 30, the drains of each chip 20 are connected in parallel through the conductive heat sink 30, while the gate / source are connected to the conductive layer 11. This replaces the traditional lead or lead frame design, significantly shortening the current path and increasing the area of ​​the electrical contact parts of the chip 20. This greatly reduces parasitic inductance and resistance, improves current carrying capacity, and results in excellent switching synchronization of the chip array. Furthermore, it eliminates the need for additional gate resistors to match the switching times of each chip 20, simplifying the drive circuit design, suppressing oscillations and voltage overshoot, and improving the stability and efficiency of the battery management system.

[0035] Furthermore, the reduced use of traditional leads or lead frames leads to fewer wire bonds, which in turn reduces the number of solder joints and external connections, thereby lowering the failure rate. At the same time, the compact layout of the chip 20 array ensures that the working environment of each chip 20 is highly consistent, the current distribution is better, single-point overheating failure is avoided, and maintenance is easier.

[0036] Crucially, the heat generated by each chip 20 can be vertically discharged from both sides through the carrier board 10 and the conductive heat sink 30, which significantly reduces thermal resistance and greatly improves heat dissipation efficiency. Under the same operating conditions as traditional technology, the temperature of the chip array packaging module 100 can be significantly reduced. The improved heat dissipation efficiency of the chip array packaging module 100 can also reduce the use of current-conducting copper strips and external heat dissipation structures, resulting in a significant reduction in the overall size of the module, which is conducive to significantly improving the power density of the battery management system PCB board.

[0037] The highly integrated chip array packaging module 100 provided in this application eliminates the need to design complex and dispersed discrete device arrays and heat dissipation structures, thereby simplifying PCB board structure design, reducing product size, and making assembly, processing, and maintenance / replacement by end users easier.

[0038] It should be noted that, in the embodiments of this application, the carrier plate 10 may have a conductive layer 11 on only one side or on both sides in the thickness direction.

[0039] Taking a carrier plate 10 with conductive layers 11 on both sides as an example, in some embodiments, the carrier plate 10 includes a substrate layer 12, a first conductive layer 11 and a second conductive layer 11. The first conductive layer 11 and the second conductive layer 11 are spaced apart along the thickness direction. The substrate layer 12 is disposed between the first conductive layer 11 and the second conductive layer 11 and is connected to the first conductive layer 11 and the second conductive layer 11 respectively. The first side of the wafer 20 is connected to the first conductive layer 11 and / or the second conductive layer 11.

[0040] like Figure 1 As shown, the first conductive layer 11 is located on the top of the carrier board 10 and serves as a pad for matching the wafer 20. The first conductive layer 11 can be etched to form an electrode pattern. The second conductive layer 11 is located on the bottom of the carrier board 10 and can extend the electrical connection surface for connecting to a PCB board or heat sink.

[0041] It should be clarified that, in order to avoid obscuring this application, unless otherwise specified, the conductive layer 11 in the embodiments of this application refers to the first conductive layer 11 facing the wafer side.

[0042] Furthermore, the chip 20 can be soldered to the conductive layer 11 or the conductive heat sink 30 using solder, or it can be directly soldered to the conductive layer 11 or the conductive heat sink 30 via eutectic bonding without solder. Direct eutectic bonding to the conductive layer 11 or the conductive heat sink 30 is more conducive to achieving vertical ultra-short path connections, thereby further reducing parasitic inductance and resistance. For example, when the conductive layer 11 is made of copper, the chip 20 is directly soldered to the conductive layer 11 via eutectic bonding, resulting in no solder layer between the chip 20 and the conductive layer 11; similarly, when the conductive heat sink 30 is made of copper sheet, the chip 20 is directly soldered to the conductive heat sink 30 via eutectic bonding, resulting in no solder layer between the chip 20 and the conductive heat sink 30.

[0043] In this application embodiment, the carrier 10 is preferably a carrier 10 with high thermal conductivity. In some embodiments, the carrier 10 may be selected from double-sided copper-clad ceramic substrates (DBC), active metal brazing ceramic substrates (AMB), aluminum nitride ceramic substrates (AIN), and silicon nitride (Si). i3 N4) Any of the ceramic substrates or glass substrates to obtain better thermal conductivity or mechanical strength, which is beneficial for the vertical heat dissipation of the wafer array.

[0044] The conductive heat sink 30 in this application embodiment has both heat dissipation and conductivity functions. In some embodiments, the conductive heat sink 30 includes any one of copper sheet, aluminum sheet, or copper-aluminum composite metal sheet. These metal sheets have high electrical and thermal conductivity, so that the connection surface between the chip 20 and the conductive heat sink 30 has lower contact resistance and improves the product lifespan.

[0045] In some embodiments, the conductive heat sink 30 may also be an electroplated copper or aluminum sheet, and the electroplating layer may be a silver or gold layer to further improve electrical and thermal conductivity.

[0046] When the chip 20 is soldered onto the conductive heat sink 30, in some embodiments, the chip array packaging module 100 further includes a first solder layer 40, which is disposed along the thickness direction between the conductive layer 11 and the chip 20, and is connected to the first surface of the conductive layer 11 and the chip 20 respectively. The first solder layer 40 can ensure the reliability of the connection between the chip 20 and the carrier 10, realize the low impedance connection between the gate / source and the conductive layer 11 of the carrier 10, and assist the heat of the chip 20 to be vertically dissipated to the carrier 10. In addition, the thermal expansion coefficients of the carrier 10 and the chip 20 are generally different. The first solder layer 40 can absorb some of the thermal stress through the small deformation of the solder, and prevent the chip 20 and the carrier 10 from cracking due to stress concentration during operation due to the difference in thermal expansion coefficients.

[0047] The chip 20 is soldered onto the conductive heat sink 30 using solder. In some embodiments, the chip array packaging module 100 further includes a second solder layer 50, which is disposed between the chip 20 and the conductive heat sink 30 along the thickness direction and is connected to the second surface of the chip 20 and the conductive heat sink 30 respectively. The second solder layer 50 can ensure the reliability of the connection between the chip 20 and the conductive heat sink 30, and ensure that the drains are connected in parallel to reduce parasitic resistance and guide the heat of the chip 20 to be vertically discharged to the conductive heat sink 30. At the same time, the second solder layer 50 can absorb some of the thermal stress through the small deformation of the solder, and prevent the chip 20 and the conductive heat sink 30 from cracking due to stress concentration during operation due to the difference in the coefficient of thermal expansion.

[0048] To enable electrical connection to external devices, in some embodiments, the wafer array packaging module 100 further includes conductive pins 60 connected to the first conductive layer 11 along the thickness direction and spaced apart from the wafer 20.

[0049] It is understood that the gate / source of the chip array inside the chip array packaging module 100 needs to be connected to the external driving circuit, control circuit or power supply through the conductive layer 11 of the carrier board 10. The conductive pin 60 serves as a standardized interface to lead the electrical signals (such as control voltage and current) or power supply (such as input voltage) of the conductive layer 11 to the outside of the module, which is convenient for interfacing with the PCB board or other devices. The conductive pin 60 is kept at a distance from the chip array to avoid short circuits.

[0050] The conductive pin 60 can be directly connected to the conductive layer 11 of the carrier board 10. For example, when the conductive pin 60 is a copper pin and the conductive layer 11 is metallic copper, the conductive pin 60 can be directly soldered to the conductive layer 11 of the carrier board 10 using eutectic bonding.

[0051] The conductive pins 60 can also be soldered onto the conductive layer 11. In some embodiments, the wafer array packaging module 100 further includes a third solder layer 70, which is disposed between the conductive layer 11 and the conductive pins 60 along the thickness direction and is connected to the conductive layer 11 and the conductive pins 60 respectively. The third solder layer 70 can ensure the reliability of the connection between the conductive pins 60 and the carrier board 10 and ensure electrical conductivity.

[0052] In the embodiments of this application, the conductive pin 60 serves as a conductive component. In some embodiments, the conductive pin 60 includes any one of copper pins, aluminum pins, or copper-aluminum composite pins. These metal pins have high conductivity and thermal conductivity, which is more conducive to reducing contact resistance and improving product lifespan.

[0053] To alleviate thermal stress caused by the difference in thermal expansion coefficients between the carrier 10, the conductive heat sink 30, and the wafer 20, in some embodiments, the wafer array packaging module 100 further includes: a bottom filler adhesive layer, which fills the gap between the wafer 20 and the carrier 10 and the gap between the conductive heat sink 30 and the wafer 20; the bottom filler adhesive layer fills the gap and cures to form a flexible buffer layer, which absorbs part of the thermal stress, reduces the mechanical fatigue of the solder layer, and significantly improves the reliability of the solder layer.

[0054] In some embodiments, the chip array packaging module 100 further includes a potting compound layer covering all the outer surfaces of the carrier board 10, the chip 20, and the conductive heat sink 30 at non-electrical connection locations. The potting compound layer covers all the outer surfaces of the carrier board 10, the chip 20, and the conductive heat sink 30 at non-electrical connection locations to avoid affecting conductivity. Specifically, it covers the sides and top of the carrier board 10 (except for the electrical connection surfaces of the chip 20 and the conductive pins 60); covers the sides of the chip 20; and covers the sides and bottom of the conductive heat sink 30. By completely covering the outer surface of the module, the potting compound layer forms a dense protective layer, preventing the intrusion of moisture, dust, and chemicals, ensuring the reliability of the module in harsh environments (such as no degradation of electrical performance after salt spray testing). Furthermore, the potting compound layer provides high insulation to isolate the outer surface of the module from external conductive materials.

[0055] In some embodiments, the chip array package module 100 further includes: an integrated gate driver chip, a current sensor, and / or a temperature sensor. The integrated gate driver chip, current sensor, and / or temperature sensor are all connected to the conductive layer 11 to form a more complete intelligent power module (IPM). The integrated gate driver chip can serve as the core control unit of the MOSFET chip array, responsible for converting external control signals (such as PWM pulses) into voltages / currents suitable for the MOSFET gates, driving the chip array to switch quickly. The current sensor is used to monitor the current of the MOSFET chip array in real time, providing overcurrent protection, current balance monitoring, and system status feedback functions. The temperature sensor (NTC) is used to monitor the temperature of key parts of the chip array package module 100 in real time, providing overheat warning, thermal balance control, and system derating protection functions.

[0056] To further improve heat dissipation performance, in some embodiments, the chip array packaging module 100 further includes a heat sink connected along the thickness direction to the side of the carrier 10 facing away from the chip 20 or the side of the conductive heat sink 30 facing away from the chip 20. Specifically, the heat sink can be connected to the bottom second conductive layer 11 of the carrier 10 or above the top conductive heat sink 30, and interconnected through a conductive / thermal intermediate connection layer (e.g., a solder layer), thereby further improving heat dissipation efficiency without increasing the board area.

[0057] refer to Figure 2 As shown, in order to prepare the above-mentioned wafer array packaging module 100, another embodiment of this application provides a method for preparing the wafer array packaging module 100, including: The system provides a plurality of wafers 20, a carrier plate 10 having a conductive layer 11 on at least one side along the thickness direction, and a conductive heat sink 30. Each wafer 20 with an active electrode and a gate electrode is connected to the conductive layer 11 along the thickness direction of the carrier plate 10 on the first side, and a conductive heat sink 30 is connected to the second side of each wafer 20 with a drain electrode along the thickness direction to obtain the wafer array packaging module 100 as described above.

[0058] In this embodiment, the first surface of each wafer 20 with active and gate electrodes can be first connected to the conductive layer 11 along the thickness direction of the carrier plate 10, and then a conductive heat sink 30 can be connected to the second surface of each wafer 20 with drain electrodes along the thickness direction. Alternatively, the conductive heat sink 30 can be first connected to the second surface of each wafer 20 with drain electrodes along the thickness direction, and then the first surface of each wafer 20 with active and gate electrodes can be connected to the conductive layer 11 along the thickness direction of the carrier plate 10. Both methods can produce the wafer array packaging module 100 as described above.

[0059] In some embodiments, connecting the first side of each wafer 20, which forms the active electrode and the gate electrode, to the conductive layer 11 along the thickness direction of the carrier substrate 10 includes: welding the first side of the wafer 20 to the conductive layer 11 using eutectic bonding. Welding the first side of the wafer 20 to the conductive layer 11 using eutectic bonding can eliminate the need for a solder layer between the wafer 20 and the conductive layer 11, thereby achieving lower thermal resistance and higher reliability.

[0060] In some embodiments, connecting the first side of each wafer 20, which forms the active electrode and the gate electrode, to the conductive layer 11 along the thickness direction of the carrier substrate 10 includes: printing a first solder on the surface of the conductive layer 11 of the carrier substrate 10, and mounting the first sides of several wafers 20 onto the first solder along the thickness direction and performing a first welding process. The first solder can melt and solidify between the wafer 20 and the conductive layer 11 during the first welding process to form a first solder layer 40, thereby fixing the wafer 20 and the carrier substrate 10 together.

[0061] In this embodiment, solder can be applied by needle transfer or dispensing to achieve higher control over solder thickness.

[0062] In some embodiments, connecting the conductive heat sink 30 along the thickness direction to the second surface of each wafer 20 where the drain is formed includes: soldering the conductive heat sink 30 to the second surface of each wafer 20 using eutectic bonding. Soldering the conductive heat sink 30 to the second surface of each wafer 20 using eutectic bonding can eliminate the need for a solder layer between the wafer 20 and the conductive heat sink 30, thereby achieving lower thermal resistance and higher reliability.

[0063] In some embodiments, attaching a conductive heat sink 30 along the thickness direction to the second surface on which a drain is formed on each wafer 20 includes: printing a second solder onto the second surface of each wafer 20, mounting the conductive heat sink 30 onto the second solder on the plurality of wafers 20, and performing a second soldering process. During the second soldering process, the second solder melts and solidifies to form a second solder layer 50, which tightly connects each wafer 20 and the conductive heat sink 30.

[0064] In some embodiments, after the chip 20 is precisely connected to the conductive layer 11 of the carrier 10 in a flip-chip manner, a second solder can be printed at the corresponding position of the conductive heat sink 30, and the carrier 10 with the chip array fixed is flip-chip mounted on the conductive heat sink 30. It is important to ensure that the chip 20 on the carrier 10 is aligned one-to-one with the second solder position on the conductive heat sink 30, which can also achieve the fixed connection of the conductive heat sink 30.

[0065] In some embodiments, before obtaining the chip array packaging module 100, the process further includes filling the gap between the chip 20 and the carrier 10 and the gap between the conductive heat sink 30 and the chip 20 with underfill adhesive and performing a first curing process to form an underfill adhesive layer; wherein, the underfill adhesive layer may specifically be Henkel's Loctite ECI-1010, Namics' X-8415 or Toray's Toray PI-2800, to alleviate thermal stress and prevent solder layer cracking.

[0066] To achieve electrical connection between the conductive layer 11 and the outside, in some embodiments, eutectic bonding is used to weld the conductive pins 60 to the surface of the conductive layer 11 of the carrier board 10, so that there is no solder layer between the surface of the conductive layer 11 of the carrier board 10 and the conductive pins 60, thereby obtaining lower thermal resistance and higher reliability.

[0067] To achieve electrical connection between the conductive layer 11 and the outside, in some embodiments, a third solder is printed on the surface of the conductive layer 11 of the carrier board 10, and the conductive pins 60 are mounted on the third solder along the thickness direction and subjected to a third soldering process; under the third soldering process, the third solder melts and solidifies to form a third solder layer 60, and the third solder layer 60 tightly connects the conductive pins 60 and the conductive layer 11 of the carrier board 10.

[0068] In some embodiments, a carrier plate 10 carrying the chip 20 and conductive heat sink 30, or a carrier plate 10 carrying the chip 20, conductive heat sink 30 and conductive pins 60, is placed into a mold, and potting compound is injected into the mold, followed by a second curing process. The potting compound can be epoxy resin potting compound, silicone potting compound, or polyurethane potting compound. Specifically, potting compounds such as Henkel Loctite EA 9495, Dow Corning Sylgard 184, or Huntsman Araldite 2011 can be used to encapsulate the chip array packaging module 100.

[0069] In some embodiments, the wafer 20 and the conductive layer 11 are first connected by a first solder, and then the wafer 20 and the conductive heat sink 30 are connected by a second solder. This allows the wafer 20 to be soldered onto the surfaces of the conductive layer 11 and the conductive heat sink 30 respectively through a distributed temperature zone, avoiding positional shifts caused by the simultaneous sintering of multiple interface layers. This achieves multiple reliable metallurgical connections in a single thermal cycle, ensuring high yield and reliability.

[0070] In some embodiments, the wafer 20 and the conductive layer 11 are first connected by a first solder, then the wafer 20 and the conductive heat sink are connected by a second solder, and finally the conductive layer 11 and the conductive pins are connected by a third solder. This allows the wafer 20 to be soldered onto the surfaces of the conductive layer 11 and the conductive heat sink 30 respectively through a distributed temperature zone, avoiding positional shifts caused by the simultaneous sintering of multiple interface layers. This achieves multiple reliable metallurgical connections in a single thermal cycle, ensuring high yield and reliability.

[0071] It should be noted that after the solder is sintered to form a solder layer, its melting point will be greatly increased upon re-sintering. For example, after copper paste is sintered at a low temperature of 280-320℃ to form a copper solder layer, the melting point of the copper solder layer can be as high as 1000℃ or more. Therefore, the temperatures of the first, second, and third welding processes can be the same or different, and the melting points of the first, second, and third solders can be the same or different. Subsequent processes will not affect the already formed connection.

[0072] In some embodiments, the first welding process, the second welding process, and / or the third welding process are any one of hot pressing, reflow soldering, or local hot pressing; for example, the first welding process can be hot pressing, the second welding process can be reflow soldering, and the third welding process can be local hot pressing.

[0073] It should be noted that, in the embodiments of this application, hot pressing refers to placing the parts to be processed into a hot pressing device, and using high temperature and continuous pressure to cause plastic deformation and diffusion at the metal interface to form a solid metallurgical bond; reflow soldering refers to heating the solder pre-coated between the surfaces to be bonded in a reflow soldering furnace to above the melting point to form a liquid state, wetting the surfaces to be bonded, and then cooling and solidifying to achieve mechanical and electrical connection; local hot pressing uses a micro heating head to apply precise temperature and pressure to specific parts to be welded to achieve local welding, so as to avoid overall thermal damage.

[0074] In some embodiments, the temperature of the first welding process, the second welding process, and / or the third welding process is 150°C-320°C, and the connection between the carrier plate 10, the wafer 20, and / or the conductive heat sink 30 is achieved by low-temperature sintering, avoiding thermal damage during the welding process; for example, the temperature of the first welding process, the second welding process, and / or the third welding process can be any temperature value or temperature range within the range of 150°C, 160°C, 170°C, 180°C, 190°C, 200°C, 210°C, 220°C, 230°C, 240°C, 250°C, 260°C, 270°C, 280°C, 290°C, 300°C, 310°C, 320°C, or 150°C-320°C. In some embodiments, the first solder, the second solder, or the third solder is selected from at least one of silver paste, copper paste, solder, gold-tin solder, tin-silver-copper paste, nano-metal paste, and transient liquid phase diffusion soldering material.

[0075] Silver paste is a conductive paste material with silver powder as filler and epoxy resin or acrylate resin as matrix. It is applied to the connection surface through screen printing or dispensing and forms a conductive path after curing. Copper paste is a conductive paste material with copper powder as filler and epoxy resin or polyimide resin as matrix. The process is similar to silver paste, but it is sintered after curing to reduce resistance. Solder is an important industrial raw material for connecting electronic components in soldering circuits. It is a solder with a low melting point, mainly referring to solder made of tin-based alloys. Tin-silver-copper paste uses tin, silver, and copper as conductive matrix and resin matrix as carrier. It is applied to the connection surface through screen printing or dispensing and forms a conductive path after curing. Nano-metal paste is a paste material with silver and copper nano-metal particles as filler and organic matter as carrier. It forms a conductive path through low-temperature sintering and has the advantages of high conductivity and low processing temperature. Transient liquid phase diffusion welding material is a composite material composed of a low-melting-point phase (such as Sn) and a high-melting-point phase (such as Cu, Ni). By heating, the low-melting-point phase melts and undergoes a diffusion reaction with the substrate (such as carrier plate 10, wafer 20) to form a high-melting-point intermetallic compound (such as Cu6Sn5), thus achieving a high-strength connection.

[0076] It should be noted that the melting point (or sintering temperature, for non-fusible solders) of the aforementioned silver paste, copper paste, solder, gold-tin solder, or tin-silver-copper paste can have different melting point temperature ranges due to differences in their composition, particle size, additives, and processing characteristics. For example, the melting point (or sintering temperature) of two copper paste solders with nano-copper and terpineol as the main components decreases as the size of the nano-copper particles decreases.

[0077] It should be understood that, in order to match the power requirements of different components, the chip array package module 100 can have different current conduction performance. Therefore, the processes, solders and temperatures of the first welding process, the second welding process and the third welding process can be flexibly designed to form solder layers with different conduction performance.

[0078] For example, in some embodiments, the first soldering process is hot pressing, the first solder is copper paste, and the soldering temperature is 280°C; the second soldering process is reflow soldering, the second solder is tin-silver copper paste, and the soldering temperature is 240~300°C; the third soldering process is local hot pressing, the third solder is copper paste, and the soldering temperature is 280°C.

[0079] For example, in some embodiments, the first soldering process is hot pressing, the first solder is copper paste, and the soldering temperature is 280°C; the second soldering process is reflow soldering, the second solder is tin-silver copper paste, and the soldering temperature is 240~300°C; the third soldering process is hot pressing, the third solder is copper paste, and the soldering temperature is 280°C, wherein the third soldering process is completed before the second soldering process.

[0080] For example, in some embodiments, the first soldering process is hot pressing, the first solder is copper paste, and the soldering temperature is 280°C; the second soldering process is reflow soldering, the second solder is a tin-silver copper paste, and the soldering temperature is 240~300°C; the third soldering process is reflow soldering, the third solder is another tin-silver copper paste, and the soldering temperature is 240~270°C.

[0081] For example, in some embodiments, the first soldering process is hot pressing, the first solder is copper paste, and the soldering temperature is 280°C; the second soldering process is hot pressing, the second solder is copper paste, and the soldering temperature is 280°C; the third soldering process is reflow soldering, the third solder is tin-silver copper paste, and the soldering temperature is 240~300°C.

[0082] For example, in some embodiments, the first soldering process, the second soldering process, and the third soldering process are all reflow soldering processes, using three different solder pastes, and the matching temperatures are 280~300℃, 260~280℃, and 240~260℃, respectively.

[0083] For example, in some embodiments, the first welding process, the second welding process, and the third welding process are all hot pressing, the solder used is copper paste, and the matching temperature is 280°C.

[0084] For example, in some embodiments, the first soldering process is reflow soldering, using tin-silver-copper paste as the first solder, and a soldering temperature of 270~300°C; the second soldering process is reflow soldering, using another type of tin-silver-copper paste as the second solder, and a soldering temperature of 240~270°C; and the third soldering process is local hot pressing, using copper paste as the third solder, and a soldering temperature of 280°C.

[0085] To verify the performance advantages of the wafer array packaging module 100 in this application embodiment, a specific embodiment provides a wafer array packaging module 100, the preparation method of which is as follows: The carrier board 10 is a DBC double-sided copper-clad ceramic substrate. According to the circuit design, the upper and lower copper conductive layers 11 are patterned and etched. First solder is printed on the copper conductive layers 11 of the carrier board 10 using a stencil. Using a high-precision pick-and-place machine, 14 bare MOSFET chips 20 are precisely flip-chip mounted onto the printed first solder. The carrier board 10 with the mounted chips 20 is then fed into a hot press for the first soldering process, completing the sintering of the first solder and forming a "chip-carrier board" connection. A second layer of solder is uniformly printed on the back side of all mounted chips 20. Using a high-precision pick-and-place machine, copper conductive heat sinks 30 are precisely mounted onto the chip array with the second solder printed on them. The carrier board 10 with the copper conductive heat sinks 30 is then fed into a reflow oven for the second soldering process, completing the top first soldering. The melting and solidification of the second solder form a "wafer-copper sheet" connection. Using a high-precision dispensing machine, a highly fluid underfill adhesive is filled between the wafer 20 and the carrier board 10, and between the conductive heat sink 30 and the carrier board 10. A third solder is printed on the copper conductive layer 11 of the carrier board 10 through a stencil. Using a high-precision pick-and-place machine, the copper conductive pins 60 that connect to the external circuit are precisely mounted onto the carrier board 10 with the third solder printed on them. The carrier board 10 with the copper conductive pins 60 attached is sent to a hot press for a third welding process to complete the sintering of the third solder and form a "copper pin-carrier board" connection. The carrier board 10 with the copper conductive pins 60 welded is placed in a mold, and then potting compound is injected into the mold cavity. After maintaining the curing temperature for a certain time, the curing is completed, and the wafer array packaging module 100 is obtained. The first solder is a copper paste, the second solder is a tin-silver copper paste, and the third solder is a different type of copper paste. The temperature of the first soldering process is 280-320℃, the temperature of the second soldering process is 220-230℃, and the temperature of the third soldering process is 280-320℃.

[0086] Therefore, the embodiments of this application ingeniously design a reliable multi-welding process. This step-by-step temperature zone welding ensures that subsequent processes will not affect the already formed connection.

[0087] The chip array package module 100 obtained in this embodiment was tested under a continuous current of 150A. The highest temperature of the module casing was measured to be 85°C. In contrast, the conventional solution using 14 TOLL-packaged MOSFET chips with a heat sink achieved a maximum temperature of 125°C under the same conditions, representing a 40°C reduction in temperature rise compared to the chip array package module 100 in this embodiment. Further dimensional comparison reveals that the PCB area occupied by the chip array package module 100 in this embodiment is 60mm * 50mm = 30 cm², while the conventional solution requires a PCB area of ​​150mm * 80mm = 120 cm² (excluding heat sink projection). Therefore, the chip array package module 100 in this embodiment reduces the area to one-quarter of the original, achieving a significant increase in power density.

[0088] Another embodiment of this application provides a power device fabricated using the wafer array packaging module 100 described above or the wafer array packaging module 100 prepared by the above-described method. The power device may have one or more wafer array packaging modules 100. In a power device composed of multiple wafer array packaging modules 100, two or more wafer array packaging modules 100 are vertically stacked and interconnected through a conductive / thermally conductive intermediate connection layer (e.g., a solder layer), thereby doubling the power capacity without increasing the board area and further improving the power density.

[0089] It should be noted that the chip array packaging module 100 packaging technology concept provided in this application embodiment is not limited to power devices in the BMS field, but is also applicable to any high-power application scenario that requires high power density and high reliability, such as motor controllers, photovoltaic inverters, communication power supplies, on-board chargers (OBC), server power supplies, etc.

[0090] In summary, the chip array packaging module 100, its fabrication method, and power devices provided in this application greatly improve the heat dissipation performance and power density of power components in high-power applications, enhance system reliability, significantly optimize electrical performance, simplify PCB board assembly and processing, and further simplify terminal maintenance.

[0091] Although the above embodiments have been demonstrated and described in detail, it should be understood that these embodiments are merely exemplary and do not necessarily limit the scope of protection of this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application to meet different application needs.

Claims

1. A chip array packaging module, characterized in that, include: A carrier plate having a conductive layer on at least one side along its thickness direction, the conductive layer being used for electrical connection to the outside; A plurality of wafers, each wafer including a first surface and a second surface disposed opposite to each other along the thickness direction, the first surface forming an active electrode and a gate electrode, the second surface forming a drain electrode, each of the first surfaces being connected to the conductive layer along the thickness direction to form a wafer array; A conductive heat sink is applied to several wafers and connected to the second side of each wafer along the thickness direction to form a parallel drain electrode.

2. The chip array packaging module according to claim 1, characterized in that, Also includes: A first bonding layer is disposed between the conductive layer and the wafer along the thickness direction, and is connected to the first surface of both the conductive layer and the wafer. And / or, The second solder layer is disposed between the wafer and the conductive heat sink along the thickness direction, and is connected to the second surface of the wafer and the conductive heat sink respectively.

3. A wafer array packaging module according to claim 1 or 2, characterized in that, Includes at least one of the following conditions: (1) The carrier plate includes a substrate layer, a first conductive layer and a second conductive layer. The first conductive layer and the second conductive layer are spaced apart along the thickness direction. The substrate layer is disposed between the first conductive layer and the second conductive layer and is connected to the first conductive layer and the second conductive layer respectively. The first side of the wafer is connected to the first conductive layer and / or the second conductive layer. (2) The carrier is selected from any one of direct copper-clad ceramic substrate, active metal brazing ceramic substrate, aluminum nitride ceramic substrate, silicon nitride ceramic substrate or glass substrate. (3) The conductive heat sink includes any one of copper sheet, aluminum sheet or copper-aluminum composite metal sheet; (4) The wafer array packaging module further includes: conductive pins, which are connected to the conductive layer along the thickness direction and spaced apart from the wafer.

4. A chip array packaging module according to claim 3, characterized in that, Includes at least one of the following conditions: (5) The wafer array packaging module further includes: a third bonding layer, which is disposed between the conductive layer and the conductive pin along the thickness direction, and is connected to the conductive layer and the conductive pin respectively; (6) The conductive pins include any one of copper pins, aluminum pins, or copper-aluminum composite pins; (7) The wafer array packaging module further includes: a bottom filling adhesive layer, which fills the gap between the wafer and the carrier board and the gap between the conductive heat sink and the wafer; and a potting adhesive layer, which covers all the outer surfaces of the carrier board, the wafer and the conductive heat sink at non-electrical connection parts; (8) The wafer array packaging module further includes: an integrated gate driver chip, a current sensor and / or a temperature sensor, wherein the integrated gate driver chip, the current sensor and / or the temperature sensor are all connected to the conductive layer; (9) The wafer array packaging module further includes: a heat sink, which is connected along the thickness direction to the side of the carrier plate away from the wafer or the side of the conductive heat sink away from the wafer.

5. A method for fabricating a wafer array packaging module, characterized in that, include: The system provides a plurality of wafers, a carrier plate having a conductive layer on at least one side along the thickness direction, and a conductive heat sink. The first side of each wafer, which has an active electrode and a gate electrode, is connected to the conductive layer along the thickness direction of the carrier plate, and a conductive heat sink is connected to the second side of each wafer, which has a drain electrode, along the thickness direction, to obtain the wafer array packaging module as described in any one of claims 1 to 4.

6. The method for fabricating a wafer array packaging module according to claim 5, characterized in that, The step of connecting the first surface of each wafer, which forms the active electrode and the gate electrode, to the conductive layer along the thickness direction of the carrier plate includes: The first side of the wafer is bonded to the conductive layer using eutectic bonding; or... A first solder is printed on the surface of the conductive layer of the substrate, and the first sides of several wafers are respectively mounted onto the first solder along the thickness direction and subjected to a first welding process.

7. The method for fabricating a wafer array packaging module according to claim 6, characterized in that, The conductive heat sink connected along the thickness direction on the second surface of each wafer where a drain electrode is formed includes: The conductive heat sink is soldered to the second side of each wafer using eutectic bonding; or A second solder is printed onto the second side of each chip, and a conductive heat sink is attached to the second solder on several chips and a second soldering process is performed.

8. The method for fabricating a wafer array packaging module according to claim 7, characterized in that, Before obtaining the wafer array packaging module, at least one of the following conditions must be met: A. Fill the gap between the wafer and the carrier plate and the gap between the conductive heat sink and the wafer with bottom filler and perform a first curing treatment; B. The conductive pins are soldered to the surface of the conductive layer of the carrier board using eutectic bonding, or a third solder is printed on the surface of the conductive layer of the carrier board, and the conductive pins are mounted on the third solder along the thickness direction and subjected to a third soldering process. C. Place the carrier board loaded with the chip and conductive heat sink, or the carrier board loaded with the chip, conductive heat sink and conductive pins, into the mold, inject potting compound into the mold, and then perform a second curing process.

9. The method for fabricating a wafer array packaging module according to claim 8, characterized in that, It also includes at least one of the following conditions: D. The first welding process, the second welding process and / or the third welding process are any one of hot pressing, reflow soldering or local hot pressing; E. The temperature of the first welding process, the second welding process and / or the third welding process is 150°C-320°C; F. The first solder, the second solder, or the third solder is selected from at least one of silver paste, copper paste, solder, gold-tin solder, or tin-silver-copper paste.

10. A power device, characterized in that, It is assembled using the wafer array packaging module as described in claims 1 to 4 or the preparation method as described in any one of claims 5 to 9.

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