A novel common-drain double mosfet device and a method for manufacturing the same

Abstract

The application relates to the field of MOS semiconductor technology, and discloses a novel common-drain double-MOSFET device and a preparation method thereof; the cross-section profile of the gate is in an inverted "concave" shape, and an ion implantation layer is arranged through the lower part of the gate; the ion implantation layer in a single MOS cell penetrates the semiconductor epitaxial layer and divides the drain, an N substrate layer and an N diffusion layer into two parts; vertical N+ layers are arranged on the left and right sides of the ion implantation layer in the N diffusion layer. The specific ion implantation layer structure penetrating the epitaxial layer effectively divides the drain, the N substrate layer and the N diffusion layer into two parts, forms a unique common-drain double-MOS cell layout, significantly expands the current conduction path, realizes the uniform expansion of the current in the horizontal and vertical directions, greatly reduces the on-resistance of the device, improves the overall current capacity and withstand voltage capacity, and is suitable for high-power application scenarios.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of MOS semiconductor technology, and in particular to a novel common-drain double MOSFET device and a preparation method thereof. BACKGROUND

[0002] The existing common-drain double MOSFET device generally has problems such as high on-resistance, limited voltage resistance, and poor switching performance, especially in high-power application scenarios, and the traditional structure is difficult to simultaneously consider low loss and high reliability. In recent years, although some improvement schemes have improved the performance by optimizing the device layout or introducing new doping processes, the core problems such as uneven current distribution, electric field concentration, and large dynamic loss have not been effectively solved, which restricts the further improvement of the overall performance of the device and the expansion of the application range.

[0003] The existing patent discloses a drain-shared double SGT MOSFET device (publication number CN223231511U), which relates to the field of semiconductor technology, and includes a substrate and an epitaxial layer. A plurality of grooves are provided side by side on the top surface of the epitaxial layer, and the bottom side wall and inner bottom of the grooves are provided with a shielding gate oxide layer. The existing patent has problems such as high on-resistance, uneven electric field distribution leading to limited voltage resistance, large dynamic loss in the switching process, and high process complexity and increased manufacturing cost caused by the traditional structure relying on complex three-dimensional grooves and shielding gate design. SUMMARY

[0004] The present application provides a novel common-drain double MOSFET device and a preparation method thereof to solve the existing technical problems and solve the problem of being difficult to simultaneously consider low loss and high reliability.

[0005] To solve the above technical problems, according to one aspect of the present application, more specifically, a novel common-drain double MOSFET device includes a plurality of mutually juxtaposed MOS cells. A single MOS cell includes a drain, a semiconductor epitaxial layer, a source, a gate, and a gate oxide layer covering the surface of the gate. The semiconductor epitaxial layer includes an N substrate layer, an N diffusion layer, a P+ layer, an N well layer, and a P well layer. The cross-sectional profile of the gate is in the shape of an inverted "concave" character, and an ion implantation layer is provided through the gate below. The ion implantation layer in a single MOS cell penetrates the semiconductor epitaxial layer and divides the drain, the N substrate layer, and the N diffusion layer into two parts.

[0006] The inside of the N diffusion layer and the left and right sides of the ion implantation layer are each provided with a vertical N+ layer, and the upper and lower ends of the vertical N+ layer are in direct contact with the gate oxide layer and the N substrate layer, respectively.

[0007] Furthermore, the ion implantation layer includes an N+ connection layer.

[0008] Further, the N+ connection layer is formed with a plurality of P-particles that are not in contact with each other by ion implantation.

[0009] Further, the N+ connection layer is formed with a long P-layer in the middle region of the N+ connection layer by ion implantation.

[0010] Further, the ion implantation layer includes a concave N+ layer and a convex P+ layer; the cross-sectional profile of the concave N+ layer is in the shape of a "concave" character, and the cross-sectional profile of the convex P+ layer is in the shape of an inverted "convex" character.

[0011] Further, the concave N+ layer is located below the convex P+ layer, and the sidewall of the concave N+ layer is in direct contact with the drain, the N substrate layer, and the vertical N+ layer.

[0012] Further, the ion implantation layer includes a concave N+ layer and a convex P+ layer; the cross-sectional profile of the concave N+ layer is in the shape of a "concave" character, and the cross-sectional profile of the convex P+ layer is in the shape of an inverted "convex" character.

[0013] Further, the ion implantation layer further includes a P+ connection layer.

[0014] A preparation method of a novel common-drain double MOSFET device, specifically comprising:

[0015] S1, epitaxially growing an N diffusion layer on the surface of an N substrate layer, and forming a P well layer and an N well layer in the N diffusion layer by ion implantation and diffusion;

[0016] S2, forming contact regions of the source and the drain in the P well layer and the N well layer, respectively, by ion implantation;

[0017] S3, forming a gate oxide layer on the surface of the device, and forming a gate with a cross-section in the shape of an inverted "concave" character by deposition and polysilicon etching;

[0018] S4, forming an ion implantation layer that penetrates the semiconductor epitaxial layer below the gate by photolithography and ion implantation process, the ion implantation layer including a concave N+ layer and a convex P+ layer;

[0019] S5, forming a plurality of N-particles that are not in contact with each other inside the convex P+ layer by selective ion implantation, and performing high-temperature annealing to activate the implanted ions;

[0020] S6, forming vertical N+ layers on the left and right sides of the ion implantation layer in the N diffusion layer, so that the upper and lower ends thereof are in direct contact with the gate oxide layer and the N substrate layer, respectively;

[0021] S7, forming an interlayer dielectric layer by chemical vapor deposition, etching a contact hole, and depositing metal to form electrode connections of the drain, the source, and the gate.

[0022] The application provides a novel common-drain double MOSFET device and a preparation method thereof.

[0023] 1、The application effectively divides the drain, N substrate layer and N diffusion layer into two parts through a specific ion implantation layer structure penetrating the epitaxial layer, forms a unique common-drain double MOS cell layout, significantly expands the current conduction path, realizes uniform expansion of the current in the horizontal and vertical directions, thereby greatly reduces the on-resistance of the device, improves the overall current capacity and withstand voltage capacity, and is suitable for high-power application scenarios.

[0024] 2、The application introduces local doped particles or regions inside the ion implantation layer, accurately modulates the electric field distribution inside the device, effectively alleviates the common high electric field concentration problem in the traditional structure, and the improvement significantly enhances the avalanche breakdown resistance and reliability of the device, and the device still maintains good low-loss characteristics in the on state.

[0025] 3、The application forms an internal charge balance structure in the ion implantation layer by adopting continuous or discrete compensation doped regions. The design optimizes the electric field distribution of the device in the off state, improves the blocking voltage, and effectively reduces the charge storage and dynamic loss in the switching process, which helps to improve the high-frequency performance and working efficiency of the device.

[0026] 4、The application combines ion implantation layers of different shapes and conductivity types to construct complementary electron and hole conduction paths. This bipolar conduction mechanism not only significantly improves the conduction efficiency of the device, but also improves its frequency response characteristics, so that the device exhibits better performance in high-speed switching applications.

[0027] 5、The application forms carrier recombination centers in the specific ion implantation region, effectively controls the lifetime of minority carriers and the reverse recovery process. This feature significantly suppresses the reverse recovery charge and related switching loss, reduces the energy loss of the device during switching, and is particularly suitable for high-frequency and high-efficiency power conversion systems.

[0028] 6、The application further strengthens the longitudinal withstand voltage capability of the device by introducing an additional connection layer and forming an alternating P-N junction with the original structure. The structure optimizes the injection and extraction efficiency of electrons, enhances the stability and reliability of the device under high temperature and high electric field conditions, and prolongs the service life. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is a schematic diagram of example one in the application;

[0030] Figure 2 is a schematic diagram of example two in the application;

[0031] Figure 3 is a schematic diagram of Example Three in the present application;

[0032] Figure 4 is a schematic diagram of Example Four in the present application;

[0033] Figure 5 is a schematic diagram of Example Five in the present application;

[0034] Figure 6 is a schematic diagram of Example Six in the present application.

[0035] In the figure: 1, drain; 2, gate; 3, source; 4, N substrate layer; 5, N diffusion layer; 6, N+ connection layer; 7, vertical N+ layer; 8, P+ layer; 9, N well layer; 10, P well layer; 11, P- particle; 12, long P- layer; 13, convex P+ layer; 14, N- particle; 15, P+ connection layer; 601, concave N+ layer. DETAILED DESCRIPTION

[0036] In order to make the technical scheme of the present application clearer, the present application will be further described in detail below in combination with the drawings and specific examples.

[0037] As shown in the figure, a preparation method of a novel common-drain double MOSFET device specifically comprises the following steps: Figure 5

[0038] Step one, epitaxially growing an N diffusion layer 5 on the surface of an N substrate layer 4, and forming a P well layer 10 and an N well layer 9 in the N diffusion layer 5 by ion implantation and diffusion; this step lays a solid foundation for the subsequent device structure by epitaxially growing an N diffusion layer on an N substrate layer and accurately forming a P well layer and an N well layer. This process ensures the uniformity of the well region doping concentration and the accurate control of the junction depth, thereby optimizing the threshold voltage and breakdown characteristics of the device and improving the reliability and consistency of the overall device.

[0039] Step two, forming the contact areas of the source 3 and the drain 1 in the P well layer 10 and the N well layer 9 respectively by ion implantation; this step realizes the good formation of ohmic contact by performing ion implantation in the P well layer and the N well layer respectively to form the source and drain contact areas. This step optimizes the injection and extraction efficiency of the carriers, significantly reduces the contact resistance, and improves the on-state performance and switching speed of the device.

[0040] Step three, forming a gate oxide layer on the surface of the device, and forming a gate 2 with an inverted "concave" shape cross-section by deposition and polysilicon etching; this step forms a gate structure with an inverted "concave" shape cross-section by deposition and polysilicon etching process. This special shape effectively increases the effective control area of the gate, enhances the channel modulation capability, and thus improves the transconductance and current driving capability of the device.

[0041] ​Step four, forming ion implantation layer through photoetching and ion implantation process under the gate 2, the ion implantation layer includes concave N+ layer 601 and convex P+ layer 13; forming ion implantation layer through photoetching and ion implantation process under the gate, including concave N+ layer and convex P+ layer. This key step realizes the redistribution of internal electric field and the optimization of carrier path, which significantly improves the withstand voltage and on-state uniformity of the device.

[0042] Step five, forming several non-contact N-particles 14 in the convex P+ layer 13 by selective ion implantation, and performing high temperature annealing to activate the implanted ions; forming non-contact N-particles in the convex P+ layer by selective ion implantation, and activating the implanted ions by high temperature annealing. This process introduces local carrier recombination center, effectively suppresses reverse recovery current and reduces switching loss, especially suitable for high frequency application.

[0043] Step six, forming vertical N+ layer 7 on the left and right sides of the ion implantation layer in N diffusion layer 5, so that the upper and lower ends are in direct contact with the gate oxide layer and N substrate layer 4 respectively; forming vertical N+ layer on the left and right sides of the ion implantation layer, so that the upper and lower ends are in direct contact with the gate oxide layer and N substrate layer respectively. This structure enhances the longitudinal conductivity of the device, improves the current spreading characteristics, further reduces the on-state resistance and improves the overall performance of the device.

[0044] Step seven, forming interlayer dielectric layer by chemical vapor deposition, etching contact hole and depositing metal to form electrode connection of drain 1, source 3 and gate 2. Forming interlayer dielectric layer by chemical vapor deposition, etching contact hole and depositing metal to form electrode connection. This step realizes the reliable interconnection between the functional areas of the device, ensures good electrical contact and mechanical stability, and completes the preparation process of the device.

[0045] Example 1

[0046] As Figure 1As shown, a novel common-drain dual MOSFET device includes several parallel MOSFET cells. Each MOSFET cell includes a drain 1, a semiconductor epitaxial layer, a source 3, a gate 2, and a gate oxide layer covering the surface of the gate 2. The semiconductor epitaxial layer includes an N-substrate layer 4, an N-diffusion layer 5, a P+ layer 8, an N-well layer 9, and a P-well layer 10. The cross-sectional profile of the gate 2 is an inverted "U" shape, and an ion implantation layer is disposed through it below the gate 2. The ion implantation layer in a single MOSFET cell penetrates the semiconductor epitaxial layer and divides the drain 1, N-substrate layer 4, and N-diffusion layer 5 into two parts. Vertical N+ layers 7 are provided inside the N-diffusion layer 5 and on both sides of the ion implantation layer. The upper and lower ends of the vertical N+ layers 7 are in direct contact with the gate oxide layer and the N-substrate layer 4, respectively. The ion implantation layer includes an N+ connection layer 6. By introducing the N+ connection layer 6 that penetrates the epitaxial layer as an ion implantation layer, the drain 1, N-substrate layer 4, and N-diffusion layer 5 are divided into two parts, forming a common-drain dual MOSFET structure. Its innovation lies in using the N+ interconnect layer 6 to achieve dual lateral and vertical current expansion, significantly reducing on-resistance and improving the overall current carrying capacity and withstand voltage performance of the device.

[0047] Example 2

[0048] like Figure 2 As shown, a novel common-drain dual MOSFET device includes several parallel MOS cells. Each MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 3, a gate 2, and a gate oxide layer covering the surface of the gate 2. The semiconductor epitaxial layer includes an N-substrate layer 4, an N-diffusion layer 5, a P+ layer 8, an N-well layer 9, and a P-well layer 10. The cross-sectional profile of the gate 2 is an inverted "U" shape, and an ion implantation layer is disposed through it below the gate 2. The ion implantation layer in a single MOS cell penetrates the semiconductor epitaxial layer and divides the drain 1, the N-substrate layer 4, and the N-diffusion layer 5 into two parts. Vertical N+ layers 7 are provided inside the N-diffusion layer 5 and on both sides of the ion implantation layer. The upper and lower ends of the vertical N+ layers 7 are in direct contact with the gate oxide layer and the N-substrate layer 4, respectively. Several non-contact P-particles 11 are formed inside the N+ interconnection layer 6 through ion implantation. By injecting several non-contacting P-particles 11 into the N+ interconnect layer 6, the high electric field concentration phenomenon is effectively suppressed by locally modulating the electric field distribution, which enhances the avalanche breakdown tolerance of the device while maintaining good conduction characteristics.

[0049] Example 3

[0050] like Figure 3As shown, a novel common-drain dual MOSFET device includes several parallel MOS cells. Each MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 3, a gate 2, and a gate oxide layer covering the surface of the gate 2. The semiconductor epitaxial layer includes an N-substrate layer 4, an N-diffusion layer 5, a P+ layer 8, an N-well layer 9, and a P-well layer 10. The cross-sectional profile of the gate 2 is an inverted "U" shape, and an ion implantation layer is disposed through it below the gate 2. The ion implantation layer in a single MOS cell penetrates the semiconductor epitaxial layer and divides the drain 1, the N-substrate layer 4, and the N-diffusion layer 5 into two parts. Vertical N+ layers 7 are provided inside the N-diffusion layer 5 and on both sides of the ion implantation layer. The upper and lower ends of the vertical N+ layers 7 are in direct contact with the gate oxide layer and the N-substrate layer 4, respectively. A long P- layer 12 is formed inside the N+ connection layer 6 by ion implantation. The long P- layer 12 is located in the middle region of the N+ connection layer 6. A continuous long P-layer 12 is introduced into the N+ interconnect layer 6, located in its central region, forming a built-in charge compensation structure. This design can further optimize the electric field distribution, improve the device's blocking voltage, and reduce dynamic losses during switching.

[0051] Example 4

[0052] like Figure 4 As shown, a novel common-drain dual MOSFET device includes several parallel MOS cells. Each MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 3, a gate 2, and a gate oxide layer covering the surface of the gate 2. The semiconductor epitaxial layer includes an N substrate layer 4, an N diffusion layer 5, a P+ layer 8, an N well layer 9, and a P well layer 10. The cross-sectional profile of the gate 2 is an inverted "U" shape, and an ion implantation layer is disposed through the gate 2. The ion implantation layer in a single MOS cell penetrates the semiconductor epitaxial layer and divides the drain 1, the N substrate layer 4, and the N diffusion layer 5 into two parts. Vertical N+ layers 7 are provided inside the N diffusion layer 5 and on both sides of the ion implantation layer. The upper and lower ends of the vertical N+ layers 7 are in direct contact with the gate oxide layer and the N substrate layer 4, respectively. The ion implantation layer comprises a concave N+ layer 601 and a convex P+ layer 13. The cross-sectional profile of the concave N+ layer 601 is concave, while the cross-sectional profile of the convex P+ layer 13 is an inverted convex shape. The concave N+ layer 601 is located below the convex P+ layer 13, and its sidewalls are in direct contact with the drain 1, the N-substrate layer 4, and the vertical N+ layer 7. The combination of the concave N+ layer 601 and the convex P+ layer 13 forms the ion implantation layer, creating complementary carrier pathways. The concave N+ layer 601 enhances electron conduction, while the convex P+ layer 13 provides hole injection, achieving a bipolar conduction mechanism and significantly improving the device's conduction efficiency and frequency response.

[0053] Example 5

[0054] As shown in Figure 5 A new common-drain double MOSFET device includes a plurality of MOS cells arranged side by side, each MOS cell including a drain 1, a semiconductor epitaxial layer, a source 3, a gate 2, and a gate oxide layer covering the surface of the gate 2, the semiconductor epitaxial layer including an N substrate layer 4, an N diffusion layer 5, a P+ layer 8, an N well layer 9, and a P well layer 10, the cross-sectional profile of the gate 2 being in the shape of an inverted "concave" character, and an ion implantation layer being provided through the gate 2 below. The ion implantation layer in each MOS cell penetrates the semiconductor epitaxial layer and divides the drain 1, the N substrate layer 4, and the N diffusion layer 5 into two parts. A vertical N+ layer 7 is provided inside the N diffusion layer 5 and on both sides of the ion implantation layer. The upper and lower ends of the vertical N+ layer 7 are in direct contact with the gate oxide layer and the N substrate layer 4, respectively. The ion implantation layer includes a concave N+ layer 601 and a convex P+ layer 13. The cross-sectional profile of the concave N+ layer 601 is in the shape of a "concave" character, and the cross-sectional profile of the convex P+ layer 13 is in the shape of an inverted "convex" character. A plurality of N-particles 14 that do not contact each other are formed inside the convex P+ layer 13 by ion implantation. The N-particles 14 in the convex P+ layer 13 form local carrier recombination centers, effectively suppress reverse recovery charge, reduce switching loss, and are particularly suitable for high-frequency and high-voltage application scenarios.

[0055] Embodiment 6

[0056] As shown in Figure 6 A new common-drain double MOSFET device includes a plurality of MOS cells arranged side by side, each MOS cell including a drain 1, a semiconductor epitaxial layer, a source 3, a gate 2, and a gate oxide layer covering the surface of the gate 2, the semiconductor epitaxial layer including an N substrate layer 4, an N diffusion layer 5, a P+ layer 8, an N well layer 9, and a P well layer 10, the cross-sectional profile of the gate 2 being in the shape of an inverted "concave" character, and an ion implantation layer being provided through the gate 2 below. The ion implantation layer in each MOS cell penetrates the semiconductor epitaxial layer and divides the drain 1, the N substrate layer 4, and the N diffusion layer 5 into two parts. A vertical N+ layer 7 is provided inside the N diffusion layer 5 and on both sides of the ion implantation layer. The upper and lower ends of the vertical N+ layer 7 are in direct contact with the gate oxide layer and the N substrate layer 4, respectively. The ion implantation layer further includes a P+ connection layer 15. The P+ connection layer 15 is further introduced into the ion implantation layer to form an alternating P-N structure with the vertical N+ layer 7, thereby enhancing the longitudinal voltage resistance of the device. At the same time, by optimizing the carrier injection efficiency, the reliability and temperature stability of the overall device are improved.

[0057] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the present application, several modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A novel common-drain dual MOSFET device, comprising a plurality of parallel MOSFET cells, each MOSFET cell comprising a drain (1), a semiconductor epitaxial layer, a source (3), a gate (2), and a gate oxide layer covering the surface of the gate (2), wherein the semiconductor epitaxial layer comprises an N-substrate layer (4), an N-diffusion layer (5), a P+ layer (8), an N-well layer (9), and a P-well layer (10), characterized in that: The cross-sectional profile of the gate (2) is in the shape of an inverted "concave" character, and an ion implantation layer is disposed through the gate (2) below. The ion implantation layer in a single MOS cell penetrates the semiconductor epitaxial layer and divides the drain (1), the N substrate layer (4), and the N diffusion layer (5) into two parts; On both the left and right sides of the ion implantation layer inside the N diffusion layer (5), vertical N+ layers (7) are provided. The upper and lower ends of the vertical N+ layer (7) are in direct contact with the gate oxide layer and the N substrate layer (4) respectively; The ion implantation layer includes an N+ connection layer (6); Inside the N+ connection layer (6), a number of non-touching P- particles (11) are formed by ion implantation.

2. A novel common-drain dual MOSFET device, comprising a plurality of MOS cells arranged in parallel, each MOS cell comprising a drain (1), a semiconductor epitaxial layer, a source (3), a gate (2), and a gate oxide layer covering the surface of the gate (2), wherein the semiconductor epitaxial layer comprises an N-substrate layer (4), an N-diffusion layer (5), a P+ layer (8), an N-well layer (9), and a P-well layer (10), characterized in that: The cross-sectional profile of the gate (2) is in the shape of an inverted "concave" character, and an ion implantation layer is disposed through the gate (2) below. The ion implantation layer in a single MOS cell penetrates the semiconductor epitaxial layer and divides the drain (1), the N substrate layer (4), and the N diffusion layer (5) into two parts; On both the left and right sides of the ion implantation layer inside the N diffusion layer (5), vertical N+ layers (7) are provided. The upper and lower ends of the vertical N+ layer (7) are in direct contact with the gate oxide layer and the N substrate layer (4) respectively; The ion implantation layer includes an N+ connection layer (6); Inside the N+ connection layer (6), a long P- layer (12) is formed by ion implantation, and the long P- layer (12) is located in the middle region of the N+ connection layer (6).

3. A novel common-drain dual MOSFET device, comprising a plurality of parallel MOSFET cells, each MOSFET cell comprising a drain (1), a semiconductor epitaxial layer, a source (3), a gate (2), and a gate oxide layer covering the surface of the gate (2), wherein the semiconductor epitaxial layer comprises an N-substrate layer (4), an N-diffusion layer (5), a P+ layer (8), an N-well layer (9), and a P-well layer (10), characterized in that: The cross-sectional profile of the gate (2) is in the shape of an inverted "concave" character, and an ion implantation layer is disposed through the gate (2) below. The ion implantation layer in a single MOS cell penetrates the semiconductor epitaxial layer and divides the drain (1), the N substrate layer (4), and the N diffusion layer (5) into two parts; On both the left and right sides of the ion implantation layer inside the N diffusion layer (5), vertical N+ layers (7) are provided. The upper and lower ends of the vertical N+ layer (7) are in direct contact with the gate oxide layer and the N substrate layer (4) respectively; The ion implantation layer includes a concave N+ layer (601) and a convex P+ layer (13); The cross-sectional profile of the concave N+ layer (601) is in the shape of a "concave" character, and the cross-sectional profile of the convex P+ layer (13) is in the shape of an inverted "convex" character.

4. The novel common-drain dual MOSFET device according to claim 3, characterized in that: The concave N+ layer (601) is located below the convex P+ layer (13), and the side wall of the concave N+ layer (601) is in direct contact with the drain (1), the N substrate layer (4), and the vertical N+ layer (7).

5. The novel common-drain dual MOSFET device according to claim 3, characterized in that: Inside the convex P+ layer (13), a number of non-touching N- particles (14) are formed by ion implantation.

6. A method for fabricating a novel common-drain dual-MOSFET device, characterized in that, Applied to the novel common-drain dual MOSFET device described in claim 5, the preparation method of the novel common-drain dual MOSFET device specifically includes: S1. Epitaxially grow an N diffusion layer (5) on the surface of the N substrate layer (4), and form a P well layer (10) and an N well layer (9) in the N diffusion layer (5) by ion implantation and diffusion; S2. Contact regions for the source (3) and drain (1) are formed in the P-well layer (10) and N-well layer (9) respectively by ion implantation; S3. A gate oxide layer is formed on the surface of the device, and a gate with an inverted "U" shape is formed by deposition and polysilicon etching (2). S4. An ion implantation layer penetrating the semiconductor epitaxial layer is formed under the gate (2) by photolithography and ion implantation process. The ion implantation layer includes a concave N+ layer (601) and a convex P+ layer (13). S5. Several non-contacting N-particles (14) are formed inside the convex P+ layer (13) by selective ion implantation, and high-temperature annealing is performed to activate the implanted ions. S6. Vertical N+ layers (7) are formed on the left and right sides of the ion implantation layer in the N diffusion layer (5), so that their upper and lower ends are in direct contact with the gate oxide layer and the N substrate layer (4), respectively. S7. An interlayer dielectric layer is formed by chemical vapor deposition, and contact holes are etched. Metal is deposited to form the electrode connections of the drain (1), source (3) and gate (2).

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