Switch control method and device, storage medium and electronic device

Abstract

The invention discloses a switch control method and device, a storage medium and an electronic device, and the method comprises the steps: generating a target signal parameter matched with a current target operation mode of a switching chip when the operation mode of the switching chip is detected to be changed, the target signal parameter can indicate that the switching chip expects the offset of the clock signal output by the target clock chip relative to the reference frequency in the target operation mode, and the success rate of the switching chip processing service according to the clock signal meeting the target signal parameter in the target operation mode is greater than a preset threshold value; and then the target clock chip is controlled to output the clock signal to the switching chip according to the current signal parameter of the target clock chip and the target signal parameter, and by adopting the technical scheme, the problems of poor service processing stability in different operation modes and the like caused by the fact that the fixed clock mode of the switch cannot adapt to the operation mode in the related technology are solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication networks, in particular to a control method and device of a switch, a storage medium and an electronic device. BACKGROUND

[0002] In modern communication networks, as the core equipment of data transmission, the adaptation ability of the clock signal of the switch directly affects the stability and reliability of service processing. The traditional switch can only fixedly select one clock mode in design, and cannot simultaneously adapt to multiple requirements such as reference clock, positive bias clock, and specific frequency offset clock. When the network scene needs the switch to switch from the reference clock mode to the positive bias clock or other clock modes, due to the fixed clock mode of the switch, the switch cannot be switched to other clock modes, which will cause the arrival timing of the data packet to mismatch the receiving window, and further cause the problem of packet loss. This not only significantly reduces the success rate of service processing, but also causes the switch to fail to pass the 100% line speed test under all working conditions, which seriously affects the network transmission efficiency. In related technologies, the clock line is usually manually plugged or the hardware configuration is modified to change the clock mode of the switch. This processing method not only has a complicated operation process and a long time-consuming, but also causes the service link to be interrupted during the configuration change, resulting in the problem of long-time stagnation of data transmission.

[0003] In related technologies, the fixed clock mode of the switch cannot adapt to the running mode, which causes poor service processing stability under different running modes, and an effective solution has not been proposed. SUMMARY

[0004] Embodiments of the present application provide a control method and device of a switch, a storage medium and an electronic device to at least solve the problem in related technologies that the fixed clock mode of the switch cannot adapt to the running mode, which causes poor service processing stability under different running modes.

[0005] According to an embodiment of the present application, a control method of a switch is provided, a switch control system includes: a control end and a switch, a switching chip and a target clock chip are deployed on the switch, the control end is connected with the switching chip and the target clock chip respectively, the switching chip and the target clock chip are connected, the switching chip is used for processing services of the switch according to a clock signal output by the target clock chip, the method is applied to the control end, and the method includes:

[0006] detecting whether a running mode of the switching chip is changed;

[0007] In a case where it is detected that the operation mode of the switch chip changes, a target signal parameter matched with a target operation mode in which the switch chip currently stays is generated, wherein the target signal parameter is used to indicate an offset amount of a clock signal output by the target clock chip relative to a reference frequency expected by the switch chip in the target operation mode, and a success rate of processing a service by the switch chip in the target operation mode according to the clock signal satisfying the target signal parameter is greater than a preset threshold value.

[0008] The target clock chip outputs a clock signal to the switch chip according to the current signal parameter of the target clock chip and the target signal parameter, wherein the current signal parameter is used to indicate an offset amount of a clock signal currently output by the target clock chip relative to a reference frequency.

[0009] Optionally, the switch control system further comprises a user terminal, the control end is connected with the user terminal, and the control end further comprises a storage space used to store operation modes and signal parameters having a corresponding relationship. The generation of the target signal parameter matched with the target operation mode in which the switch chip currently stays comprises:

[0010] acquiring the operation modes and the signal parameters having the corresponding relationship from the storage space;

[0011] matching the target signal parameter corresponding to the target operation mode from the operation modes and the signal parameters having the corresponding relationship;

[0012] In a case where the target clock parameter corresponding to the target operation mode is not matched from the operation modes and the clock parameters having the corresponding relationship, the target signal parameter corresponding to the target operation mode is acquired from the user terminal.

[0013] Optionally, the acquisition of the target signal parameter corresponding to the target operation mode from the user terminal comprises:

[0014] sending a parameter request carrying the target operation mode to the user terminal, wherein the parameter request is used to request to acquire the signal parameter corresponding to the target operation mode;

[0015] receiving the target signal parameter sent by the user terminal in response to the parameter request, and adding the target operation mode and the target signal parameter having the corresponding relationship to the storage space.

[0016] Optionally, the control of the target clock chip to output a clock signal to the switch chip according to the current signal parameter of the target clock chip and the target signal parameter comprises:

[0017] performing a subtraction operation on the current signal parameter of the target clock chip and the target signal parameter to obtain a first difference value, wherein the first difference value is used to indicate an offset of a clock signal currently output by the target clock chip relative to a clock signal expected to be output by the target clock chip in the target operation mode of the switch chip;

[0018] adjusting a frequency of the clock signal output by the target clock chip to the switch chip according to the first difference value.

[0019] Optionally, the adjusting of the frequency of the clock signal output by the target clock chip to the switch chip according to the first difference value comprises:

[0020] detecting a component type of the target clock chip to obtain a target type;

[0021] in a case where the target type is a first type, generating a frequency control instruction carrying the first difference value, wherein the clock chip belonging to the first type is a clock chip allowed to configure a frequency of an output clock signal, and the frequency control instruction is used to control the target clock chip to adjust the frequency of the output clock signal according to the first difference value; and controlling the target clock chip to execute the frequency control instruction.

[0022] in a case where the target type is a second type, generating a signal switching instruction carrying the first difference value, wherein the clock chip belonging to the second type is a clock chip not allowed to configure the frequency of the output clock signal, and the signal switching instruction is used to control the target clock chip to output a clock signal after switching the clock signal to a clock signal matched with the first difference value; and controlling the target clock chip to execute the signal switching instruction.

[0023] Optionally, after the adjusting of the frequency of the clock signal output by the target clock chip to the switch chip according to the first difference value, the method further comprises:

[0024] detecting whether a second difference value between a reference signal parameter of the clock signal currently output by the target clock chip and the target signal parameter is greater than a preset difference value;

[0025] in a case where the second difference value is greater than the preset difference value, controlling the target clock chip to output the clock signal to the switch chip according to the reference signal parameter and the target signal parameter.

[0026] According to another embodiment of the embodiment of the application, a switch control system is further provided, comprising: a control end and a switch, wherein the switch is deployed with a switch chip and a target clock chip, the control end is connected with the switch chip and the target clock chip respectively, and the switch chip and the target clock chip are connected.

[0027] the control terminal, configured to detect whether a running mode of the switch chip changes, and generate a target signal parameter matched with a target running mode in which the switch chip currently locates, in a case where it is detected that the running mode of the switch chip changes, wherein the target signal parameter is used to indicate an offset amount of a clock signal output by the target clock chip relative to a reference frequency, which is expected by the switch chip in the target running mode, and a success rate of processing a service by the switch chip in the target running mode according to the clock signal satisfying the target signal parameter is greater than a preset threshold; and control the target clock chip to output the clock signal to the switch chip according to a current signal parameter of the target clock chip and the target signal parameter, wherein the current signal parameter is used to indicate an offset amount of a clock signal currently output by the target clock chip relative to the reference frequency.

[0028] the target clock chip, configured to output the clock signal to the switch chip according to the control of the control terminal.

[0029] the switch chip, configured to process the service of the switch according to the clock signal output by the target clock chip.

[0030] According to another embodiment of the embodiment of the present application, a control device of a switch is further provided, and a switch control system includes a control terminal and a switch, the switch is deployed with a switch chip and a target clock chip, the control terminal is connected with the switch chip and the target clock chip respectively, the switch chip is connected with the target clock chip, the switch chip is used to process a service of the switch according to a clock signal output by the target clock chip, the device is applied to the control terminal, and the device includes:

[0031] a first detection module, configured to detect whether a running mode of the switch chip changes;

[0032] a generation module, configured to generate a target signal parameter matched with a target running mode in which the switch chip currently locates, in a case where it is detected that the running mode of the switch chip changes, wherein the target signal parameter is used to indicate an offset amount of a clock signal output by the target clock chip relative to a reference frequency, which is expected by the switch chip in the target running mode, and a success rate of processing a service by the switch chip in the target running mode according to the clock signal satisfying the target signal parameter is greater than a preset threshold;

[0033] a first control module, configured to control the target clock chip to output the clock signal to the switch chip according to a current signal parameter of the target clock chip and the target signal parameter, wherein the current signal parameter is used to indicate an offset amount of a clock signal currently output by the target clock chip relative to the reference frequency.

[0034] According to a further aspect of the embodiments of the present application, a computer readable storage medium is also provided, in which a computer program is stored, and the computer program is configured to execute the control method of the switch when running.

[0035] According to a further aspect of the embodiments of the present application, an electronic device is also provided, which comprises a memory, a processor, and a computer program stored in the memory and capable of running on the processor, and the processor executes the control method of the switch by the computer program.

[0036] In the embodiments of the present application, a control method of a switch is provided, and the switch control system comprises a control end and a switch, and a switching chip and a target clock chip are deployed on the switch, the control end is connected with the switching chip and the target clock chip respectively, the switching chip and the target clock chip are connected, the switching chip can process the service of the switch according to the clock signal output by the target clock chip, the control end first detects whether the running mode of the switching chip changes, generates a target signal parameter matched with the target running mode in which the switching chip currently locates when detecting that the running mode of the switching chip changes, the target signal parameter can indicate the offset of the clock signal output by the target clock chip relative to a reference frequency in the target running mode, and the success rate of the switching chip processing the service according to the clock signal meeting the target signal parameter in the target running mode is greater than a preset threshold; and then the target clock chip is controlled to output the clock signal to the switching chip according to the current signal parameter and the target signal parameter of the target clock chip, and the current signal parameter can indicate the offset of the clock signal currently output by the target clock chip relative to the reference frequency.

[0037] In the above manner, the control end can generate the target signal parameter matched with the target running mode in which the switching chip currently locates in real time, and the parameter indicates the offset of the clock signal output by the target clock chip relative to the reference frequency in the target running mode, and then the target clock chip is controlled to output the clock signal in combination with the offset of the clock signal currently output by the target clock chip relative to the reference frequency, so that the switching chip can obtain the matched clock signal in different running modes, and the success rate of service processing is maintained at a high level, thereby avoiding the risk that the running mode switching occurs data packet loss and the success rate of service processing is significantly reduced due to the fixed clock signal of the switch failing to adapt to the change of the running mode. By using the above technical scheme, the problem that the fixed clock mode of the switch fails to adapt to the running mode in the related art, resulting in poor service processing stability in different running modes, is solved, and the technical effect of improving the service processing stability of the switch in different running modes is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0038] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0039] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of the hardware environment for a switch control method according to an embodiment of this application;

[0041] Figure 2 This is a flowchart of a switch control method according to an embodiment of this application;

[0042] Figure 3 This is a structural block diagram of the first switch control system according to an embodiment of this application;

[0043] Figure 4 This is a structural block diagram of the second switch control system according to an embodiment of this application;

[0044] Figure 5 This is a flowchart of a clock signal control method for a target clock chip according to an embodiment of this application;

[0045] Figure 6 This is a structural block diagram of a control device for a switch according to an embodiment of this application. Detailed Implementation

[0046] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0047] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0048] The methods and embodiments provided in this application can be executed on a computer terminal, device terminal, or similar computing device. Taking running on a computer terminal as an example, Figure 1 This is a schematic diagram of the hardware environment for a switch control method according to an embodiment of this application. Figure 1 As shown, a computer terminal may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. In one exemplary embodiment, the computer terminal may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the computer terminal described above. For example, the computer terminal may also include components that are more complex than those described above. Figure 1 The more or fewer components shown, or having the same Figure 1 Equivalent functions or ratios shown Figure 1 The functions shown have more different configurations.

[0049] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the message push sending method in this embodiment of the invention. The processor 102 executes various functional applications and data processing by running the computer programs stored in the memory 104, thereby implementing the above-described method. The memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to a computer terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0050] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider for the computer terminal. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0051] This embodiment provides a control method for a switch. The switch control system includes a control terminal and a switch. A switching chip and a target clock chip are deployed on the switch. The control terminal is connected to both the switching chip and the target clock chip. The switching chip is connected to the target clock chip. The switching chip processes the switch's services according to the clock signal output by the target clock chip. The method is applied to the control terminal. Figure 2 This is a flowchart of a switch control method according to an embodiment of this application, such as... Figure 2 As shown, the process includes the following steps:

[0052] Step S202: Detect whether the operating mode of the switching chip has changed;

[0053] Step S204: When a change in the operating mode of the switching chip is detected, a target signal parameter matching the target operating mode currently in which the switching chip is located is generated. The target signal parameter is used to indicate the offset of the clock signal output by the target clock chip relative to the reference frequency that the switching chip expects in the target operating mode. The success rate of the switching chip in processing services according to the clock signal that satisfies the target signal parameter in the target operating mode is greater than a preset threshold.

[0054] Step S206: Control the target clock chip to output a clock signal to the switching chip according to the current signal parameters of the target clock chip and the target signal parameters, wherein the current signal parameters are used to indicate the offset of the clock signal currently output by the target clock chip relative to the reference frequency.

[0055] Through the above steps, the control terminal can generate target signal parameters in real time that match the target operating mode currently in which the switching chip is operating. These parameters represent the expected offset of the clock signal output by the target clock chip relative to the reference frequency in the target operating mode. Combined with the offset of the target clock chip's current output clock signal relative to the reference frequency, the control terminal controls the target clock chip to output its clock signal. This ensures that the switching chip can obtain a matching clock signal in different operating modes, maintaining a high success rate for service processing. This avoids the risk of packet loss and a significant decrease in service processing success rate during mode switching caused by the inability of a fixed clock signal to adapt to changes in operating modes, as seen in existing technologies. By adopting this technical solution, the problem of poor service processing stability in different operating modes due to the inability of a fixed clock mode to adapt to operating modes is solved, achieving the technical effect of improving the stability of service processing in different operating modes.

[0056] Optionally, in this embodiment, Figure 3 This is a structural block diagram of the first switch control system according to an embodiment of this application, as shown below. Figure 3 As shown, the switch control system may be, but is not limited to, the first switch control system, wherein the first switch control system includes a control terminal and a switch, on which a switching chip and a target clock chip are deployed, and the control terminal is connected to the switching chip and the target clock chip respectively through a communication link (such as an I2C / SPI bus), and the switching chip and the target clock chip are connected.

[0057] Optionally, in this embodiment, the switch control system may further include a control terminal and multiple switches. Each of the multiple switches is equipped with a switching chip and a target clock chip. The control terminal is connected to the switching chip and the target clock chip on each switch respectively. The control terminal can detect changes in the operating mode of each switching chip in real time through the communication link with each switching chip, and perform regulation on the clock signal output by each target clock chip.

[0058] Optionally, in this embodiment, the control terminal may be, but is not limited to, software running on the terminal device for managing the switch, such as a network management system (NMS) and switch configuration tools. After startup, it can automatically execute control methods for the switch, including detecting changes in the operating mode of the switching chip and regulating the clock signal output by the target clock chip. The switch may be, but is not limited to, an Ethernet switch, a data center switch, or other device capable of high-speed forwarding of data frames, routing switching, and service traffic management. The switching chip is the core integrated circuit in the switch responsible for data processing, used to handle services such as packet forwarding, filtering, and VLAN segmentation. The target clock chip may be, but is not limited to, a hardware chip integrating clock signal generation and regulation functions, such as a digital phase-locked loop (DPLL), an oven-controlled crystal oscillator (OCXO), and a voltage-controlled crystal oscillator (VCXO). By outputting a stable high-frequency pulse signal, it provides a unified timing reference for the internal logic circuits of the switching chip (such as data buffers and forwarding engines), ensuring that the switching chip processes services according to a fixed cycle.

[0059] Optionally, in this embodiment, the operating mode of the switching chip may be, but is not limited to, the working mode adopted by the switching chip when processing services, such as: high-speed mode, low-latency mode, Synchronization Ethernet (SyncE) function mode, specific port rate mode, etc.

[0060] In the technical solution provided in step S202 above, the control terminal can detect whether the operating mode of the switching chip has changed in the following ways, but not limited to: sending a read request to the switching chip via the I2C / SPI bus, the read request being used to request the reading of operating mode parameters related to the operating mode in the switching chip; receiving the operating mode parameters returned by the switching chip in response to the read request; and determining that the operating mode of the switching chip has changed when it is detected that the received operating mode parameters are inconsistent with the previously received operating mode parameters. For example, the controller can request to read the register configuration of the switching chip, such as the port rate register and the function mode control bit, and determine whether the operating mode has changed by detecting whether the read parameters have changed.

[0061] Optionally, in this embodiment, the control terminal may also detect whether the operating mode of the switching chip has changed in the following ways, but not limited to: monitoring specific events or instructions that cause a change in operating mode, and determining whether the operating mode has changed by whether specific events or instructions are detected. For example, parsing configuration change instructions issued by the network management system, and determining that the operating mode will change when an instruction to modify the port rate or enable a specific function (such as SyncE) is detected; or monitoring flow table rule updates issued by the Software-Defined Networking (SDN) controller through the OpenFlow protocol, and inferring that the switch needs to switch to low-latency operating mode if a new flow table entry related to low-latency forwarding is detected, that is, the operating mode will change.

[0062] In the technical solution provided in step S204 above, before generating target signal parameters matching the target operating mode currently in which the switching chip is located, when a change in the operating mode is detected by reading operating mode parameters related to the operating mode in the switching chip, the following steps may be included: based on the received operating mode parameters, and combined with a predefined mode mapping table that records specific operating mode parameters and corresponding operating modes, the changed operating mode of the switching chip (equivalent to the target operating mode) is parsed. For example, if the operating mode parameter read is a register configuration parameter indicating that the SyncE function is activated, then the target operating mode is determined to be "SyncE enabled mode".

[0063] In the technical solution provided in step S204 above, before generating the target signal parameters that match the target operating mode currently in which the switching chip is located, if the change in operating mode is detected by monitoring specific events or instructions that cause the change in operating mode, the control terminal may directly extract the changed operating mode of the switching chip (equivalent to the target operating mode) from the detected configuration change instructions or flow table entries. For example, the "queue_properties" field in the OpenFlow message carries the low-latency queue configuration and is mapped to "low-latency mode".

[0064] In one exemplary embodiment, the switch control system further includes: a user terminal, the control terminal being connected to the user terminal, the control terminal further including a storage space, the storage space being used to store corresponding operating modes and signal parameters, and may generate target signal parameters matching the target operating mode currently in which the switch chip is located in the following ways, but not limited to: obtaining corresponding operating modes and signal parameters from the storage space; matching the target signal parameters corresponding to the target operating mode from the corresponding operating modes and signal parameters; and, if no target clock parameter corresponding to the target operating mode is matched from the corresponding operating modes and clock parameters, obtaining the target signal parameters corresponding to the target operating mode from the user terminal.

[0065] Optionally, in this embodiment, Figure 4 This is a structural block diagram of the second switch control system according to an embodiment of this application, as shown below. Figure 4 As shown, the switch control system may be, but is not limited to, a second switch control system. The second switch control system includes a control terminal, a switch, and a user terminal. The switch is equipped with a switching chip and a target clock chip. The control terminal is connected to the switching chip and the target clock chip respectively through a communication link (such as an I2C / SPI bus). The switching chip and the target clock chip are connected. The control terminal is also connected to the user terminal. The control terminal also includes a storage space, which can store corresponding operating modes and signal parameters.

[0066] Optionally, in this embodiment, the corresponding operating modes and signal parameters may be, but are not limited to, pre-stored in the storage space in the form of a mapping table, which stores the parameter requirements of multiple pre-configured operating modes for the clock signal.

[0067] Optionally, in this embodiment, the information recorded in the mapping table may include the frequency offset of the clock signal relative to the reference frequency required by different operating modes, such as 0ppm frequency offset for standard mode, +50ppm frequency offset for low latency mode, +10ppm frequency offset for SyncE mode, or specific clock frequency offset corresponding to specific port rates (such as 10G / 100G) (such as +20ppm for 10G port and +40ppm for 100G port).

[0068] Optionally, in this embodiment, the information recorded in the mapping table may also include clock frequency values ​​required for different operating modes, such as 125MHz for standard mode, 125.00625MHz (125MHz+50ppm) for low latency mode, 125.00125MHz (125MHz+10ppm) for SyncE mode, or clock frequency values ​​corresponding to specific port rates (such as 10G / 100G) (125.0025MHz for 10G port and 125.005MHz for 100G port).

[0069] Optionally, in this embodiment, after determining that the operating mode after the change of the switching chip is the target operating mode, the control terminal retrieves a mapping table from the storage space that records the operating mode and the corresponding frequency offset value (equivalent to signal parameter). If the mapping table records the frequency offset value corresponding to the target operating mode, the corresponding frequency offset value is determined as the target signal parameter. If the mapping table does not record the frequency offset value corresponding to the target operating mode, the target signal parameter corresponding to the target operating mode is retrieved from the user terminal.

[0070] Optionally, in this embodiment, the user terminal may be, but is not limited to, a terminal device or mobile device running network management software. After receiving a parameter request carrying the target operating mode, it may display detailed information about the target operating mode (such as the current port rate and service type) and provide a parameter input interface to prompt the user to input the signal parameters corresponding to the target operating mode. After the user completes the input, the input result is returned to the control terminal.

[0071] In one exemplary embodiment, the target signal parameters corresponding to the target operating mode can be obtained from the user terminal in the following manner, but not limited to: sending a parameter request carrying the target operating mode to the user terminal, wherein the parameter request is used to request the acquisition of signal parameters corresponding to the target operating mode; receiving the target signal parameters sent by the user terminal in response to the parameter request, and adding the corresponding target operating mode and the target signal parameters to the storage space.

[0072] Optionally, in this embodiment, after obtaining the parameters returned by the user terminal, it can also be verified whether the parameters are within the range supported by the clock chip (e.g., ±100ppm) to avoid invalid input causing the clock frequency to exceed the physical capability of the clock chip and leading to system crash. After successful verification, the valid input is determined as the target signal parameter, and the new target operating mode and the corresponding target signal parameter are written into the mapping table to achieve dynamic updating of the mapping table.

[0073] In the technical solution provided in step S206 above, the control terminal adjusts the clock signal output by the target clock chip according to the frequency offset value (i.e., the offset relative to the reference frequency) of the current output clock signal of the target clock chip and the frequency offset value of the clock signal expected by the switching chip in the target operating mode as indicated by the target signal parameters, so as to meet the clock signal requirements required by the switching chip to maintain a high service processing success rate in the target operating mode.

[0074] In an exemplary embodiment, the target clock chip can be controlled to output a clock signal to the switching chip through, but is not limited to, the following steps, based on the current signal parameters of the target clock chip and the target signal parameters: performing a subtraction operation on the current signal parameters of the target clock chip and the target signal parameters to obtain a first difference, wherein the first difference is used to indicate the offset of the clock signal currently output by the target clock chip relative to the clock signal that the switching chip expects the target clock chip to output in the target operating mode; and adjusting the frequency of the clock signal output by the target clock chip to the switching chip based on the first difference.

[0075] Optionally, in this embodiment, Figure 5 This is a flowchart of a clock signal control method for a target clock chip according to an embodiment of this application, as shown below. Figure 5 As shown, when the control terminal detects whether the operating mode of the switching chip has changed, it also reads the frequency offset (or frequency value) of the clock signal output by the target clock chip. For example, when it detects that the operating mode of the switching chip is about to change from the standard mode (the initial reference frequency output by the DPLL upon power-on) to the target operating mode, the frequency offset value of the clock signal output by the DPLL (i.e., the target clock chip) is read as Xppm. The control terminal, combined with the target signal parameters indicating the expected clock signal frequency offset value Zppm of the switching chip in the target operating mode, calculates the required frequency offset Yppm (i.e., the first difference, Y = ZX). By adjusting the configuration parameters of the target clock chip, the frequency of the clock signal output to the switching chip is increased (or decreased) by the frequency offset corresponding to the first difference Yppm. This achieves automatic adjustment of the frequency of the clock signal output by the target clock chip to the switching chip, matching its operating mode. This eliminates the need for manual adjustment of the target clock chip, effectively preventing service interruptions.

[0076] In one exemplary embodiment, the frequency of the clock signal output by the target clock chip to the switching chip can be adjusted according to the first difference in the following manner, but not limited to: detecting the component type of the target clock chip to obtain a target type; if the target type is a first type, generating a frequency adjustment instruction carrying the first difference, wherein the clock chip belonging to the first type is a clock chip that is allowed to configure the frequency of the output clock signal, and the frequency adjustment instruction is used to control the target clock chip to adjust the frequency of the output clock signal according to the first difference; controlling the target clock chip to execute the frequency adjustment instruction; if the target type is a second type, generating a signal switching instruction carrying the first difference, wherein the clock chip belonging to the second type is a clock chip that is not allowed to configure the frequency of the output clock signal, and the signal switching instruction is used to control the target clock chip to switch the clock signal to a clock signal that matches the first difference before outputting it; controlling the target clock chip to execute the signal switching instruction.

[0077] Optionally, in this embodiment, as Figure 5 As shown, for a target clock chip that supports dynamic configuration of the output clock signal frequency (i.e., belongs to the first type), the control terminal generates a frequency adjustment command carrying a first difference value, which is sent to the target clock chip via the I2C / SPI bus. By adjusting the frequency control word (FCW) or phase-locked loop (PLL) parameters inside the target clock chip, the frequency offset value of the output of the target clock chip is matched with the clock signal of the target signal parameters.

[0078] Optionally, in this embodiment, as Figure 5As shown, for target clock chips that do not support dynamic configuration of the output clock signal frequency (i.e., belong to the second type), the control terminal, based on multiple pre-configured fixed-frequency offset clock sources, such as clock source Clock1 providing a +0ppm frequency offset and clock source Clock2 providing a +20ppm frequency offset, performs the following operations: Based on the frequency offset value required by the target operating mode (e.g., +20ppm), it selects the clock source (e.g., Clock2) from the candidate clock sources that is closest to the frequency offset value indicated by the target signal parameters. Then, it converts the digital instructions into physical level signals (e.g., 3.3V / 0V) via the I2C / SPI bus to the General Purpose Input / Output (GPIO) controller and outputs them to the control pins of the target clock chip. The multiplexer (MUX) inside the clock chip switches the reference clock source to Clock2 based on the binary value of the GPIO input, thereby outputting a clock signal with a +20ppm frequency offset, thus adjusting the output clock signal frequency. This method of directly switching fixed-frequency offset clock sources via a hardware multiplexer eliminates the need for dynamic configuration of the clock chip and enables rapid response to changes in operating modes.

[0079] Optionally, in this embodiment, after the target clock chip executes the frequency adjustment instruction or signal switching instruction, it outputs a clock signal that conforms to the target signal parameters, and transmits it to the forwarding engine, data buffer and other functional modules of the switching chip via the clock distribution network.

[0080] In an exemplary embodiment, after adjusting the frequency of the clock signal output by the target clock chip to the switching chip according to the first difference, the method further includes: detecting whether a second difference between a reference signal parameter and a target signal parameter of the clock signal currently output by the target clock chip is greater than a preset difference; if the second difference is greater than the preset difference, controlling the target clock chip to output a clock signal to the switching chip according to the reference signal parameter and the target signal parameter.

[0081] Optionally, in this embodiment, as Figure 5 As shown, after the target clock chip executes the frequency adjustment command or signal switching command, the control terminal will also detect whether the deviation (i.e., the second difference) between the actual frequency deviation value (i.e., the reference signal parameter) and the expected frequency deviation value (i.e., the target signal parameter) of the clock signal currently output by the target clock chip is greater than a preset threshold (e.g., ±2ppm). If the deviation is greater than the preset difference, the control terminal will again generate a correction command (including the adjustment command or the signal switching command) based on the deviation between the reference signal parameter and the target signal parameter and send it to the target clock chip to further adjust its output clock signal until the second difference converges to the preset range.

[0082] Optionally, in this embodiment, the control terminal can confirm whether the clock signal has been output according to the target signal parameters by: reading the status register (such as the lock status bit, current frequency register) of the target clock chip via the I2C / SPI bus to verify whether the parameters have been updated to the target value; and using the clock jitter monitoring module built into the switching chip to measure the jitter index of the clock signal in real time to ensure that it meets the accuracy requirements of the target operating mode (e.g., the low latency mode requires clock jitter <50ps). Through continuous monitoring and dynamic adjustment by the control terminal, it is ensured that the clock signal output by the target clock chip to the switching chip can maintain high-precision output in various operating modes, effectively improving system stability and business processing success rate.

[0083] This embodiment also provides a switch control system, including: a control terminal and a switch, wherein a switching chip and a target clock chip are deployed on the switch, the control terminal is connected to the switching chip and the target clock chip respectively, and the switching chip and the target clock chip are connected; the control terminal is used to detect whether the operating mode of the switching chip has changed; when a change in the operating mode of the switching chip is detected, it generates target signal parameters matching the target operating mode currently in which the switching chip is located, wherein the target signal parameters are used to indicate the offset of the clock signal output by the target clock chip relative to a reference frequency that the switching chip expects in the target operating mode, and the success rate of the switching chip processing services according to the clock signal satisfying the target signal parameters in the target operating mode is greater than a preset threshold; it controls the target clock chip to output a clock signal to the switching chip according to the current signal parameters of the target clock chip and the target signal parameters, wherein the current signal parameters are used to indicate the offset of the clock signal currently output by the target clock chip relative to a reference frequency; the target clock chip is used to output a clock signal to the switching chip according to the control of the control terminal; the switching chip is used to process the services of the switch according to the clock signal output by the target clock chip.

[0084] Optionally, in this embodiment, such as Figure 3 As shown, the control terminal detects whether the operating mode of the switching chip has changed. When a change in the operating mode of the switching chip is detected, it generates target signal parameters that match the target operating mode of the switching chip. Based on the current signal parameters of the target clock chip and the target signal parameters, it controls the target clock chip to output a clock signal to the switching chip. The target clock chip outputs a clock signal to the switching chip according to the control of the control terminal. The switching chip processes the switch's services according to the clock signal output by the target clock chip.

[0085] To better understand the process of the above-described switch control method, the flow of the switch control method performing switch control tasks will be described below in conjunction with optional embodiments, but this is not intended to limit the technical solutions of the embodiments of this application.

[0086] This embodiment provides a control method for a switch, mainly including the following steps: After the switch is powered on, the DPLL first outputs the initial operating state, such as the reference frequency in standard mode, to ensure the initial operation of the switch is stable. When the switch settings change (e.g., enabling or disabling the SyncE function, configuring port speed, etc.), the software (equivalent to the control terminal) reads the frequency offset status Xppm of the current DPLL output clock according to the pre-set configuration table. Taking enabling SyncE as an example, if the switching chip in the switch was previously in standard mode (frequency offset X = 0ppm), while the SyncE mode requires a target frequency offset Z = +10ppm, then the compensation value Y = ZX = +10ppm is calculated through an algorithm. Subsequently, the software adjusts the DPLL output in two ways according to the target operating mode requirements: for DPLLs that support dynamic configuration, the CPU directly sends an instruction via the I2C bus to request an increase of 10ppm frequency offset; for types that do not support dynamic configuration, the GPIO control module is driven to switch to the clock input source with the corresponding frequency offset. After adjustment, the software reads the frequency offset value of the DPLL output again. If it meets the requirements, the configuration ends; if there is an error (e.g., not reaching +10ppm), the compensation value is recalculated and the configuration process is repeated until the frequency offset value meets the target operating condition requirements, forming a closed-loop control mechanism to ensure clock signal accuracy. Using this method, dynamic configuration and fine-tuning of the target clock chip's output are achieved, enabling the switching chip in the switch to meet the requirement of 100% line-speed packet throughput under various operating conditions (running modes). It also achieves adaptive port rate configuration dynamic switching, ensuring that the target clock chip outputs a clock signal to the switching chip that meets the requirements of both normal and overclocked port rates.

[0087] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0088] This embodiment also provides a control device for a switch, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0089] Figure 6 This is a structural block diagram of a control device for a switch according to an embodiment of this application, such as... Figure 6 As shown, the switch control system includes: a control terminal and a switch. A switching chip and a target clock chip are deployed on the switch. The control terminal is connected to both the switching chip and the target clock chip. The switching chip is connected to the target clock chip. The switching chip processes the switch's services according to the clock signal output by the target clock chip. The device is applied to the control terminal and includes:

[0090] The first detection module 602 is used to detect whether the operating mode of the switching chip has changed;

[0091] The generation module 604 is used to generate target signal parameters that match the target operating mode of the switching chip when a change in the operating mode of the switching chip is detected. The target signal parameters are used to indicate the offset of the clock signal output by the target clock chip from the reference frequency that the switching chip expects in the target operating mode. The success rate of the switching chip in processing services according to the clock signal that satisfies the target signal parameters in the target operating mode is greater than a preset threshold.

[0092] The first control module 606 is used to control the target clock chip to output a clock signal to the switching chip according to the current signal parameters of the target clock chip and the target signal parameters, wherein the current signal parameters are used to indicate the offset of the clock signal currently output by the target clock chip relative to the reference frequency.

[0093] Through the above embodiments, the control terminal can generate target signal parameters in real time that match the target operating mode currently in which the switching chip is operating. These parameters represent the expected offset of the clock signal output by the target clock chip relative to the reference frequency in the target operating mode. Combined with the offset of the current output clock signal of the target clock chip relative to the reference frequency, the control terminal controls the output clock signal of the target clock chip. This ensures that the switching chip can obtain a matching clock signal in different operating modes, maintaining a high service processing success rate. This avoids the risk of packet loss and a significant decrease in service processing success rate during mode switching caused by the fixed clock signal of the switch failing to adapt to changes in operating mode, as seen in existing technologies. By adopting the above technical solution, the problem of poor service processing stability in different operating modes due to the fixed clock mode of the switch failing to adapt to the operating mode is solved, achieving the technical effect of improving the service processing stability of the switch in different operating modes.

[0094] In an exemplary embodiment, the switch control system further includes: a user terminal, the control terminal being connected to the user terminal, the control terminal further including a storage space for storing corresponding operating modes and signal parameters; the generation module includes: a first acquisition unit for acquiring corresponding operating modes and signal parameters from the storage space; a matching unit for matching the target signal parameter corresponding to the target operating mode from the corresponding operating modes and signal parameters; and a second acquisition unit for acquiring the target signal parameter corresponding to the target operating mode from the user terminal when no target clock parameter corresponding to the target operating mode is matched from the corresponding operating modes and clock parameters.

[0095] In an exemplary embodiment, the second acquisition unit is further configured to: send a parameter request carrying the target operating mode to the user terminal, wherein the parameter request is used to request the acquisition of signal parameters corresponding to the target operating mode; receive the target signal parameters sent by the user terminal in response to the parameter request; and add the corresponding target operating mode and the target signal parameters to the storage space.

[0096] In an exemplary embodiment, the first control module includes: an execution unit, configured to perform a subtraction operation on the current signal parameter of the target clock chip and the target signal parameter to obtain a first difference, wherein the first difference is used to indicate the offset of the clock signal currently output by the target clock chip relative to the clock signal expected to be output by the target clock chip in the target operating mode by the switching chip; and an output unit, configured to adjust the frequency of the clock signal output by the target clock chip to the switching chip according to the first difference.

[0097] In an exemplary embodiment, the output unit is configured to: detect the component type of the target clock chip to obtain a target type; if the target type is a first type, generate a frequency adjustment instruction carrying the first difference, wherein the clock chip of the first type is a clock chip that is allowed to configure the frequency of the output clock signal, and the frequency adjustment instruction is used to control the target clock chip to adjust the frequency of the output clock signal according to the first difference; control the target clock chip to execute the frequency adjustment instruction; if the target type is a second type, generate a signal switching instruction carrying the first difference, wherein the clock chip of the second type is a clock chip that is not allowed to configure the frequency of the output clock signal, and the signal switching instruction is used to control the target clock chip to switch the clock signal to a clock signal that matches the first difference before outputting it; control the target clock chip to execute the signal switching instruction.

[0098] In one exemplary embodiment, the apparatus further includes: a second detection module, configured to, after adjusting the frequency of the clock signal output by the target clock chip to the switching chip according to the first difference, detect whether a second difference between a reference signal parameter and a target signal parameter of the clock signal currently output by the target clock chip is greater than a preset difference; and a second control module, configured to, if the second difference is greater than the preset difference, control the target clock chip to output a clock signal to the switching chip according to the reference signal parameter and the target signal parameter.

[0099] Embodiments of this application also provide a storage medium including a stored program, wherein the program executes any of the methods described above when it is run.

[0100] Optionally, in this embodiment, the storage medium may be configured to store program code for performing the following steps:

[0101] S1, Detect whether the operating mode of the switching chip has changed;

[0102] S2, when a change in the operating mode of the switching chip is detected, a target signal parameter matching the target operating mode currently in which the switching chip is located is generated, wherein the target signal parameter is used to indicate the offset of the clock signal output by the target clock chip relative to the reference frequency that the switching chip expects in the target operating mode, and the success rate of the switching chip in processing services according to the clock signal satisfying the target signal parameter in the target operating mode is greater than a preset threshold.

[0103] S3, based on the current signal parameters of the target clock chip and the target signal parameters, control the target clock chip to output a clock signal to the switching chip, wherein the current signal parameters are used to indicate the offset of the clock signal currently output by the target clock chip relative to the reference frequency.

[0104] Embodiments of this application also provide an electronic device including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0105] Optionally, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0106] Optionally, in this embodiment, the processor can be configured to perform the following steps via a computer program:

[0107] S1, Detect whether the operating mode of the switching chip has changed;

[0108] S2, when a change in the operating mode of the switching chip is detected, a target signal parameter matching the target operating mode currently in which the switching chip is located is generated, wherein the target signal parameter is used to indicate the offset of the clock signal output by the target clock chip relative to the reference frequency that the switching chip expects in the target operating mode, and the success rate of the switching chip in processing services according to the clock signal satisfying the target signal parameter in the target operating mode is greater than a preset threshold.

[0109] S3, based on the current signal parameters of the target clock chip and the target signal parameters, control the target clock chip to output a clock signal to the switching chip, wherein the current signal parameters are used to indicate the offset of the clock signal currently output by the target clock chip relative to the reference frequency.

[0110] Optionally, in this embodiment, the storage medium may include, but is not limited to, various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0111] Optionally, specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementations, and will not be repeated here.

[0112] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using computer-executable program code, thereby storing them in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0113] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A control method for a switch, characterized in that, The switch control system includes a control terminal and a switch. A switching chip and a target clock chip are deployed on the switch. The control terminal is connected to both the switching chip and the target clock chip. The switching chip and the target clock chip are connected. The switching chip processes the switch's services according to the clock signal output by the target clock chip. The method is applied to the control terminal, and the method includes: Detect whether the operating mode of the switching chip has changed; When a change in the operating mode of the switching chip is detected, a target signal parameter matching the target operating mode currently in which the switching chip is located is generated. The target signal parameter is used to indicate the offset of the clock signal output by the target clock chip relative to the reference frequency that the switching chip expects in the target operating mode. The success rate of the switching chip in processing services according to the clock signal that satisfies the target signal parameter in the target operating mode is greater than a preset threshold. The target clock chip is controlled to output a clock signal to the switching chip based on the current signal parameters of the target clock chip and the target signal parameters, wherein the current signal parameters are used to indicate the offset of the clock signal currently output by the target clock chip relative to the reference frequency.

2. The method according to claim 1, characterized in that, The switch control system further includes: a user terminal, the control terminal being connected to the user terminal, and the control terminal further including a storage space for storing corresponding operating modes and signal parameters. Generating target signal parameters that match the target operating mode currently in which the switch chip is located includes: Retrieve the corresponding operating modes and signal parameters from the storage space; The target signal parameter corresponding to the target operating mode is matched from the corresponding operating modes and signal parameters; If no target clock parameter corresponding to the target operating mode is found from the corresponding operating modes and clock parameters, the target signal parameter corresponding to the target operating mode is obtained from the user terminal.

3. The method according to claim 2, characterized in that, The step of obtaining the target signal parameters corresponding to the target operating mode from the user terminal includes: Send a parameter request carrying the target operating mode to the user terminal, wherein the parameter request is used to request the acquisition of signal parameters corresponding to the target operating mode; The system receives the target signal parameters sent by the user terminal in response to the parameter request, and adds the corresponding target operating mode and the target signal parameters to the storage space.

4. The method according to claim 1, characterized in that, The step of controlling the target clock chip to output a clock signal to the switching chip based on the current signal parameters of the target clock chip and the target signal parameters includes: A first difference is obtained by subtracting the current signal parameters of the target clock chip from the target signal parameters. The first difference is used to indicate the offset of the clock signal currently output by the target clock chip relative to the clock signal that the switching chip expects the target clock chip to output in the target operating mode. The frequency of the clock signal output by the target clock chip to the switching chip is adjusted based on the first difference.

5. The method according to claim 4, characterized in that, The step of adjusting the frequency of the clock signal output by the target clock chip to the switching chip based on the first difference includes: The component type of the target clock chip is detected to obtain the target type; When the target type is the first type, a frequency adjustment instruction carrying the first difference is generated, wherein the clock chip belonging to the first type is a clock chip that allows configuration of the frequency of the output clock signal, and the frequency adjustment instruction is used to control the target clock chip to adjust the frequency of the output clock signal according to the first difference; and to control the target clock chip to execute the frequency adjustment instruction; When the target type is the second type, a signal switching instruction carrying the first difference is generated. The clock chip belonging to the second type is a clock chip that is not allowed to configure the frequency of the output clock signal. The signal switching instruction is used to control the target clock chip to switch the clock signal to a clock signal that matches the first difference and then output it; and to control the target clock chip to execute the signal switching instruction.

6. The method according to claim 4, characterized in that, After adjusting the frequency of the clock signal output by the target clock chip to the switching chip based on the first difference, the process includes: Detect whether the second difference between the reference signal parameter and the target signal parameter of the clock signal currently output by the target clock chip is greater than a preset difference; If the second difference is greater than the preset difference, the target clock chip is controlled to output a clock signal to the switching chip according to the reference signal parameters and the target signal parameters.

7. A switch control system, characterized in that, include: The system includes a control terminal and a switch, on which a switching chip and a target clock chip are deployed. The control terminal is connected to both the switching chip and the target clock chip. The control terminal is used to detect whether the operating mode of the switching chip has changed; When a change in the operating mode of the switching chip is detected, target signal parameters matching the current target operating mode of the switching chip are generated. These target signal parameters indicate the offset of the clock signal output by the target clock chip relative to a reference frequency that the switching chip expects in the target operating mode. The success rate of the switching chip processing services with a clock signal satisfying the target signal parameters in the target operating mode is greater than a preset threshold. Based on the current signal parameters of the target clock chip and the target signal parameters, the target clock chip is controlled to output a clock signal to the switching chip. The current signal parameters indicate the offset of the clock signal currently output by the target clock chip relative to a reference frequency. The target clock chip is used to output a clock signal to the switching chip according to the control of the control terminal; The switching chip is used to process the services of the switch according to the clock signal output by the target clock chip.

8. A control device for a switch, characterized in that, The switch control system includes: a control terminal and a switch, on which a switching chip and a target clock chip are deployed. The control terminal is connected to both the switching chip and the target clock chip. The switching chip and the target clock chip are connected. The switching chip processes the services of the switch according to the clock signal output by the target clock chip. The device is applied to the control terminal and includes: The first detection module is used to detect whether the operating mode of the switching chip has changed; The generation module is used to generate target signal parameters that match the target operating mode of the switching chip when a change in the operating mode of the switching chip is detected. The target signal parameters are used to indicate the offset of the clock signal output by the target clock chip from the reference frequency that the switching chip expects in the target operating mode. The success rate of the switching chip in processing services according to the clock signal that satisfies the target signal parameters in the target operating mode is greater than a preset threshold. The first control module is used to control the target clock chip to output a clock signal to the switching chip according to the current signal parameters of the target clock chip and the target signal parameters, wherein the current signal parameters are used to indicate the offset of the clock signal currently output by the target clock chip relative to the reference frequency.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored program, wherein the program, when executed, performs the method of any one of claims 1 to 6.

10. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to execute the method of any one of claims 1 to 6 through the computer program.

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