LED chip

Abstract

This invention provides a light-emitting diode (LED) chip, comprising a substrate, a plurality of LEDs, a first electrode, and a second electrode. The second electrode is at least partially embedded in the substrate, such that the bottom end of the second electrode is lower than the bottom ends of the plurality of LEDs. In this invention, because the second electrode is at least partially embedded in the chip's substrate, the space occupied by the second electrode between adjacent LEDs is reduced, and the gap between adjacent LEDs can be adaptively reduced, thereby reducing the overall size of the chip. This allows for compatibility with thinner and more portable electronic devices and adaptability to a wider range of applications. This invention also provides an LED chip in which the top surface of the top semiconductor layer of the LED's light-emitting body is configured as a non-planar structure with optical microstructures, which enhances light emission, increases diffuse reflection, improves light extraction efficiency, and optimizes the performance of the LED chip.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more specifically to a light-emitting diode chip. Background Technology

[0002] Light-emitting diode (LED) technology is a planar display technology that uses LEDs as pixel units. Micro LED technology, in particular, is a high-pixel-density LED planar display technology that uses micrometer-scale LEDs as pixels, assembled on a control backplane at micrometer-scale intervals. The core structure of a micro LED is a PN junction diode, which is made of a direct bandgap semiconductor material. When a forward bias voltage is applied to the upper and lower electrodes of the micro LED, causing current to flow, electrons and holes recombine in the active region, simultaneously emitting a single-color photon.

[0003] Compared to traditional LEDs, Micro LEDs offer better strain relaxation, higher light extraction efficiency, more uniform current diffusion, and superior output performance. Micro LEDs also boast advantages such as improved thermal performance, faster response times, a wider operating temperature range, higher resolution, a broader color gamut, higher contrast, lower power consumption, and higher current density. Micro LEDs are hailed as the next generation of display technology and are receiving increasing attention.

[0004] In existing micro-LED chips, some electrodes are positioned between adjacent LEDs to conductively connect the semiconductor structure layer of the LEDs to an external power source. However, these electrodes are typically located directly between adjacent LEDs, meaning there is horizontal overlap between the LEDs and the electrodes. To provide sufficient space between the LEDs to accommodate these electrodes, the spacing between adjacent LEDs must be large, resulting in a large overall size for the micro-LED chip, which fails to meet the requirements of electronic devices.

[0005] For example, the top surface of the light-emitting body of a light-emitting diode is usually flat, which cannot effectively diffuse the emitted light, and the light extraction efficiency needs to be improved. For another example, if the thickness of the top semiconductor structure of the light-emitting body is large, it will block the light from the light-emitting layer below the semiconductor structure, which will also have an adverse effect on the overall light extraction efficiency.

[0006] Therefore, there is a need to provide a light-emitting diode chip to at least partially solve the above problems. Summary of the Invention

[0007] According to one aspect of the present invention, a light-emitting diode (LED) chip is provided, wherein an electrode for conductively connecting with the top semiconductor layer of the diode is at least partially embedded in the substrate of the chip, thereby reducing the space occupied by the electrode between adjacent LEDs and adaptively reducing the gap between adjacent LEDs, thereby reducing the overall size of the chip, which can be matched with thinner and more portable electronic devices and adapted to more application scenarios.

[0008] Another aspect of the present invention provides a light-emitting diode, wherein a second electrode between two adjacent light-emitting diodes having another kind of adjacency is electrically isolated from the pair of light-emitting diodes. Since this part does not need to be in direct conductive contact, the size of this part can be made as small as possible, which is beneficial to the miniaturization of the chip as a whole.

[0009] According to another aspect of the present invention, the top surface of the top semiconductor layer of the diode light-emitting body of the chip is configured as a non-planar surface with optical microstructure, thereby increasing diffuse reflection and improving light extraction efficiency.

[0010] According to another aspect of the invention, the top semiconductor layer of the diode light-emitting body of the chip is adaptively thinned to improve the light extraction efficiency of the light-emitting layer below the thinned portion.

[0011] Specifically, according to one aspect of the present invention, a light-emitting diode chip is provided, comprising:

[0012] Substrate;

[0013] A plurality of light-emitting diodes are arranged in an array on the substrate. Each light-emitting diode includes a light-emitting layer, a first type of semiconductor located on the bottom side of the light-emitting layer, and a second type of semiconductor located on the top side of the light-emitting layer.

[0014] A first electrode is disposed on the substrate and positioned at the bottom of each of the light-emitting diodes, and the first electrode is electrically connected to the first type of semiconductor; and

[0015] A second electrode, a portion of which is disposed on the substrate and positioned between a pair of light-emitting diodes having a first adjacent relationship, wherein the portion of the second electrode is conductively connected to the second type of semiconductor.

[0016] In this embodiment, a portion of the second electrode is at least partially embedded in the substrate, such that the bottom end of the portion of the second electrode is lower than the bottom end of the plurality of light-emitting diodes.

[0017] In one embodiment, the second electrode is disposed around each of the light-emitting diodes to form between the light-emitting diodes having a first adjacent relationship, and / or

[0018] On a predetermined cross section taken from the plane containing the axis of the light-emitting diode, the second electrode is formed as a trapezoidal cross section with radial dimensions gradually increasing or decreasing from bottom to top.

[0019] In one embodiment, each of the light-emitting diodes forms a columnar structure with a radial dimension that gradually decreases from bottom to top, such that the cross-section of the light-emitting diode is also trapezoidal at the predetermined cross-section, and the angle between the lower base and the waist of the trapezoid coincides with the corresponding angle of the trapezoidal cross-section of the second electrode; or

[0020] The angle between the lower base and the waist of the trapezoid is smaller than the corresponding angle of the trapezoidal cross-section of the second electrode; or

[0021] The angle between the lower base and the waist of the trapezoid is greater than the corresponding angle of the trapezoidal cross section of the second electrode.

[0022] In one embodiment, the top end of the second electrode is lower than the bottom end of the plurality of light-emitting diodes, and the distance between the top end of the second electrode and the bottom end of the plurality of light-emitting diodes is 10 nm-2 μm; or

[0023] The top of the second electrode is flush with the bottom of the plurality of light-emitting diodes.

[0024] In one embodiment, the light-emitting diode further includes:

[0025] The bottom conductive layer located on the bottom side of the first type of semiconductor;

[0026] The bonding layer located on the bottom side of the bottom conductive layer; and

[0027] At least partially coated on the top conductive layer on top of the second type of semiconductor,

[0028] The first electrode is electrically connected via the bottom conductive layer, the bonding layer and the first type of semiconductor, and the second electrode is electrically connected via the top conductive layer and the second type of semiconductor.

[0029] In one embodiment, the second electrode is located below the top conductive layer, which extends from the top of the second type of semiconductor to the top of the second electrode.

[0030] Furthermore, the first type of semiconductor, the light-emitting layer, and the second type of semiconductor together constitute the light-emitting body. An insulating layer is provided between the sidewall of the light-emitting body and the top conductive layer. The insulating layer extends from the top of the second type of semiconductor and terminates near the top of the second electrode without reaching the top of the second electrode, so as to allow the top conductive layer and the second electrode to be in direct contact.

[0031] In one embodiment, the bottom surface of the bonding layer is higher than the top surface of the second electrode, and the height difference is 10 nm-2 μm; or

[0032] The bottom surface of the bonding layer is flush with the top surface of the second electrode.

[0033] In one embodiment, the second electrode includes a first conductive layer and a second conductive layer on top of the first conductive layer, wherein the side surfaces of the first conductive layer and the second conductive layer are smoothly connected and transitioned, thereby giving the second electrode a smooth side surface; and / or

[0034] A step is formed between the sidewalls of the first conductive layer and the second conductive layer of the electrode.

[0035] In one embodiment, the material of the second electrode is one or more of Cr, Pt, Au, Ti, Al, Ag, and Sn.

[0036] In one embodiment, the second conductive layer of the electrode is made of Cr or Ti, and the first conductive layer of the electrode is made of one or more of Cr, Pt, Au, Ti, Al, Ag, and Sn; and / or

[0037] The thickness of the first conductive layer of the electrode is greater than the thickness of the second conductive layer of the electrode.

[0038] In one embodiment, the first electrode includes a top segment and a bottom segment, at least one of the top segment and the bottom segment being formed as a columnar structure perpendicular to the substrate, the radial dimension of the top segment being smaller than the radial dimension of the bottom segment, and the second electrode being located between the top segments of adjacent first electrodes.

[0039] In one embodiment, the bottom surface of the top segment of the first electrode is flush with the bottom surface of the second electrode; and / or

[0040] At least one of the top segment and the bottom segment gradually increases in radial dimension from bottom to top.

[0041] In one embodiment, the second type of semiconductor includes a thinned region, the thickness of which is less than the thickness of other regions of the second type of semiconductor.

[0042] In one embodiment, the thinned region is positioned at the top circumferential edge of the second type of semiconductor to surround the other regions; and / or

[0043] The thinned region is constructed to have a thickness of zero.

[0044] In one embodiment, on a predetermined cross-section taken from the plane containing the axis of the light-emitting diode, the inclination angle of the sidewalls of the other regions of the second type of semiconductor is the same as the inclination angle of the sidewalls formed by the light-emitting layer and the first type of semiconductor; and / or

[0045] The included angle of inclination of the sidewalls of the other regions of the second type of semiconductor is smaller than the included angle of inclination of the sidewalls formed by the light-emitting layer and the first type of semiconductor; and / or

[0046] The angle of inclination of the sidewalls of the other regions of the second type of semiconductor is greater than the angle of inclination of the sidewalls formed by the light-emitting layer and the first type of semiconductor.

[0047] In one embodiment, the thinning region extends continuously in the circumferential direction.

[0048] In one embodiment, the bonding interface between the first type of semiconductor and the bottom conductive layer is flat, and the bonding interface between the bottom conductive layer and the bonding layer is flat.

[0049] In one embodiment, the roughness of the interface between the first type of semiconductor and the bottom conductive layer, and the interface between the bottom conductive layer and the bonding layer, are both less than 10 nm.

[0050] In one embodiment, a gap exists between the pair of light-emitting diodes having a first adjacent relationship, and a portion of the second electrode is partially positioned at or directly below the gap.

[0051] Furthermore, the bottom ends of the pair of light-emitting diodes having a second adjacent relationship are close together without any gap.

[0052] In one embodiment, the top conductive layer includes at the interval:

[0053] A horizontally extending section above the top surface of the substrate to cover the top surface of the substrate; and

[0054] The recessed contact section, which is recessed relative to the top surface of the substrate, is configured as a columnar section that is coaxial with the second electrode and has a radial dimension smaller than the radial dimension of the top surface of the second electrode.

[0055] The horizontal section and the sunken contact section together form a rotationally symmetrical structure around the axis of the second electrode.

[0056] In one embodiment, the top conductive layer includes a horizontally extending section at the interval to cover the top surface of the second electrode, the horizontal section being directly connected to a section of the top conductive layer covering the sidewall of the light-emitting diode, wherein the horizontal section is located above or recessed relative to the top surface of the substrate.

[0057] In one embodiment, the top conductive layer has an inverted truncated conical section between the pair of light-emitting diodes having a second adjacent relationship, such that the bottom end of the inverted truncated conical section having a minimum radial dimension is connected to the substrate.

[0058] Furthermore, the bottom end of the truncated conical section and the second electrode are separated by a dielectric material of the substrate.

[0059] In one embodiment, the bonding layer or bottom conductive layer of a pair of light-emitting diodes having a second adjacent relationship at least partially blocks the second electrode between the pair of light-emitting diodes in the vertical direction.

[0060] In one embodiment, a semiconductor interconnect layer with a radial dimension smaller than that of the top surface of the second type semiconductor is disposed on the top of the second type semiconductor.

[0061] In one embodiment, the semiconductor interconnect layer is made of at least one of Au, Ge, Ni, Cr, Br, and Ti, wherein the content of Au is greater than, less than, or equal to the content of Ge; and / or

[0062] The semiconductor interconnect layer is made of a semi-transparent material; and / or

[0063] The thickness of the semiconductor interconnect layer is 0.5nm-150nm.

[0064] In one embodiment, the thickness of the bottom conductive layer is 1 / 20 to 2 times the thickness of the bonding layer; and / or

[0065] The total thickness of the bottom conductive layer and the bonding layer is 50nm-4000nm; and / or

[0066] The thickness of the bottom conductive layer is less than 1000 nm; and / or

[0067] The thickness of the bonding layer is 50nm-3000nm.

[0068] In one embodiment, the bonding layer includes a mirror layer on top of it, the mirror layer being made of pure silver, pure gold, a silver-copper alloy, or a gold-chromium alloy; or

[0069] The mirror layer is made of gold and trace elements, with gold being the main component and the trace elements including at least one of chromium, titanium, and nickel.

[0070] In one embodiment, the light-emitting diode chip is a micro light-emitting diode chip that uses micron-scale LEDs as light-emitting diodes.

[0071] In one embodiment, the light-emitting diode chip further includes:

[0072] Multiple microlenses, each corresponding to a light-emitting diode;

[0073] A light-transmitting gap is disposed between the microlens and the light-emitting diode. The light-transmitting gap has a gap between two adjacent light-emitting diodes. The gap is a narrow slit with a closed top. The top of the gap is higher than the light-emitting layer of the light-emitting diode, and the bottom of the gap is lower than the light-emitting layer of the light-emitting diode.

[0074] According to one aspect of the present invention, a light-emitting diode chip is provided, comprising:

[0075] Substrate;

[0076] A plurality of light-emitting diodes are arranged in an array on the substrate, each of the light-emitting diodes comprising a light-emitting layer, a first type semiconductor located on the bottom side of the light-emitting layer, and a second type semiconductor located on the top side of the light-emitting layer;

[0077] A first electrode, a portion of which is disposed on the substrate and positioned at the bottom of the light-emitting diode, is electrically connected to the first type of semiconductor; and

[0078] A second electrode, a portion of which is disposed on the substrate and positioned between a pair of light-emitting diodes having a second adjacent relationship,

[0079] In this embodiment, a portion of the second electrode is embedded in the substrate, such that the bottom end of the portion of the second electrode is lower than the bottom end of the plurality of light-emitting diodes, and the portion of the second electrode and the light-emitting diodes are separated by a dielectric material of the substrate.

[0080] In one embodiment, the bottom ends of a pair of light-emitting diodes having a second adjacent relationship are close together without any gap.

[0081] In one embodiment, another portion of the second electrode is disposed on the substrate and positioned between a pair of light-emitting diodes having a first adjacency relationship, the other portion of the second electrode being electrically connected to the second type of semiconductor, wherein the other portion of the second electrode is at least partially embedded in the substrate such that the bottom end of the other portion of the second electrode is lower than the bottom end of the plurality of light-emitting diodes.

[0082] In one embodiment, the light-emitting diode chip is a micro light-emitting diode chip that uses micron-scale LEDs as light-emitting diodes.

[0083] According to another aspect of the present invention, a light-emitting diode chip is provided, comprising:

[0084] Substrate;

[0085] A plurality of light-emitting diodes are arranged in an array on the substrate, and each light-emitting diode includes a first type of semiconductor, a light-emitting layer, and a second type of semiconductor stacked sequentially from bottom to top.

[0086] The top surface of the second type of semiconductor includes a first region, which is configured as a non-planar region with optical microstructures.

[0087] In one embodiment, the top surface of the second type semiconductor further includes a second region on which a semiconductor interconnect layer is disposed. The top surface of the semiconductor interconnect layer is planar, and the light-emitting diode includes a top conductive layer covering only the second region on the top surface of the second type semiconductor. The semiconductor interconnect layer is configured to conductively connect the second type semiconductor and the top conductive layer.

[0088] In one embodiment, for each of the light-emitting diodes, the first regions on the top surface of its second type semiconductor are interconnected and surround a unique second region, and / or

[0089] The second region is located near the edge of the top surface of the second type of semiconductor; and / or

[0090] The first region is in direct contact with the dielectric material; and / or

[0091] The second region is located at the edge of the top surface of the second type of semiconductor; and / or

[0092] The area of ​​the second region is less than 1 / 2 of the area of ​​the top surface of the second type of semiconductor.

[0093] In one embodiment, the top surface of the second type of semiconductor further includes a third region different from the first region and the second region.

[0094] In one embodiment, the non-planar surface is a surface with irregularly shaped particles.

[0095] In one embodiment, the surface with the irregular particles is a serrated surface.

[0096] In one embodiment, each tooth of the serrated surface is formed as a spherical particle or a particle with a sharp tip; and / or

[0097] The bottom radial dimension of each tooth of the serrated surface is 50nm-500nm, and the height is 50nm-500nm; and / or

[0098] The ratio of the bottom radial dimension of each tooth to the top radial dimension of each tooth on the serrated surface is 0.5:1-100:1; and / or

[0099] The ratio of the bottom radial dimension of each tooth of the serrated surface to the radial dimension of the top surface of the second type of semiconductor is 1:5-1:100; and / or

[0100] The ratio of the height of each serration on the serrated surface to the radial dimension of the top surface of the second type of semiconductor is 1:5-1:100; and / or

[0101] The first type of semiconductor, the second type of semiconductor, and the light-emitting layer together constitute the light-emitting body, and the ratio of the height of each serration of the serrated surface to the height of the light-emitting body is 1:3-1:30.

[0102] In one embodiment, the uneven particles include spherical particles, wherein the diameter at the junction of the bottom end and the top surface of the spherical particles is smaller than the maximum diameter of the spherical particles.

[0103] In one embodiment, the light-emitting diode chip includes:

[0104] A first electrode is disposed on the substrate and positioned at the bottom of each of the light-emitting diodes, and the first electrode is electrically connected to the first type of semiconductor; and

[0105] A second electrode, a portion of which is disposed on the substrate and positioned between a pair of light-emitting diodes having a first adjacent relationship, wherein the portion of the second electrode is conductively connected to the second type of semiconductor.

[0106] In this embodiment, a portion of the second electrode is at least partially embedded in the substrate, such that the bottom end of the portion of the second electrode is lower than the bottom end of the plurality of light-emitting diodes.

[0107] In one embodiment, the second electrode is disposed around each of the light-emitting diodes to form between the light-emitting diodes having a first adjacent arrangement; and / or

[0108] On a predetermined cross section taken from the plane containing the axis of the light-emitting diode, the second electrode is formed as a trapezoidal cross section with radial dimensions gradually increasing or decreasing from bottom to top.

[0109] In one embodiment, each of the light-emitting diodes forms a columnar structure with its radial dimension gradually decreasing from bottom to top, such that the cross-section of the light-emitting diode is also trapezoidal at the predetermined cross-section, wherein:

[0110] The angle between the lower base and the waist of the trapezoid is the same as the corresponding angle of the trapezoidal cross-section of the second electrode; or

[0111] The angle between the lower base and the waist of the trapezoid is smaller than the corresponding angle of the trapezoidal cross-section of the second electrode; or

[0112] The angle between the lower base and the waist of the trapezoid is greater than the corresponding angle of the trapezoidal cross section of the second electrode.

[0113] In one embodiment, the top end of the second electrode is lower than the bottom end of the plurality of light-emitting diodes, and the distance between the top end of the second electrode and the bottom end of the plurality of light-emitting diodes is 10 nm-2 μm; or

[0114] It is flush with the bottom of the plurality of light-emitting diodes.

[0115] In one embodiment, the light-emitting diode further includes:

[0116] The bottom conductive layer located on the bottom side of the first type of semiconductor;

[0117] The bonding layer located on the bottom side of the bottom conductive layer;

[0118] At least partially coated on the top conductive layer on top of the second type of semiconductor,

[0119] The first electrode is electrically connected via the bottom conductive layer, the bonding layer and the first type of semiconductor, and the second electrode is electrically connected via the top conductive layer and the second type of semiconductor.

[0120] In one embodiment, the second electrode is located below the top conductive layer, which extends from the top of the second type of semiconductor to the top of the second electrode.

[0121] Furthermore, the first type of semiconductor, the light-emitting layer, and the second type of semiconductor together constitute the light-emitting body. An insulating layer is provided between the sidewall of the light-emitting body and the top conductive layer. The insulating layer extends from the top of the light-emitting body and terminates near the top of the second electrode without reaching the top of the second electrode, so as to allow the top conductive layer and the second electrode to contact.

[0122] In one embodiment, the bottom surface of the bonding layer is higher than the top surface of the second electrode, and the height difference is 10 nm-2 μm; or

[0123] The bottom surface of the bonding layer is flush with the top surface of the second electrode.

[0124] In one embodiment, the second electrode includes a first conductive layer and a second conductive layer on top of the first conductive layer, the second conductive layer being configured to prevent metal diffusion from the first conductive layer, wherein the side surfaces of the first and second conductive layers are smoothly connected and transitioned, thereby giving the second electrode a smooth side surface; and / or

[0125] A step is formed between the sidewalls of the first conductive layer and the second conductive layer of the electrode.

[0126] In one embodiment, the material of the second electrode is Cr, Pt, Au, Ti, Al, Ag, or Sn.

[0127] In one embodiment, the material of the second conductive layer of the electrode is Cr or Ti, and the material of the first conductive layer of the electrode is Cr, Pt, Au, Ti, Al, Ag, Sn; and / or

[0128] The thickness of the first conductive layer of the electrode is greater than the thickness of the second conductive layer of the electrode.

[0129] In one embodiment, the first electrode includes a top segment and a bottom segment, at least one of the top segment and the bottom segment being formed as a columnar structure perpendicular to the substrate, the radial dimension of the top segment being smaller than the radial dimension of the bottom segment, and the second electrode being located between the top segments of adjacent first electrodes.

[0130] In one embodiment, the bottom surface of the top segment of the first electrode is flush with the bottom surface of the second electrode; and / or

[0131] At least one of the top segment and the bottom segment gradually increases in radial dimension from bottom to top.

[0132] In one embodiment, the second type of semiconductor includes a thinned region, the thickness of which is less than the thickness of other regions of the second type of semiconductor.

[0133] In one embodiment, the thinned region is positioned at the top circumferential edge of the second type of semiconductor to surround the other regions; and / or

[0134] The thinned region is constructed to have a thickness of zero.

[0135] In one embodiment, on a predetermined cross-section taken from the plane containing the axis of the light-emitting diode, the inclination angle of the sidewall of the central portion of the second type of semiconductor is the same as the inclination angle of the sidewall formed by the light-emitting layer and the first type of semiconductor; and / or

[0136] The included angle of inclination of the sidewalls of the other regions of the second type of semiconductor is smaller than the included angle of inclination of the sidewalls formed by the light-emitting layer and the first type of semiconductor; and / or

[0137] The angle of inclination of the sidewalls of the other regions of the second type of semiconductor is greater than the angle of inclination of the sidewalls formed by the light-emitting layer and the first type of semiconductor.

[0138] In one embodiment, the thinning region extends continuously in the circumferential direction.

[0139] In one embodiment, the bonding interface between the first type of semiconductor and the bottom conductive layer is flat, and the bonding interface between the bottom conductive layer and the bonding layer is flat.

[0140] In one embodiment, the roughness of the interface between the first type of semiconductor and the bottom conductive layer, and the interface between the bottom conductive layer and the bonding layer, are both less than 1 nm.

[0141] In one embodiment, a gap exists between any pair of light-emitting diodes having a first adjacent relationship, and a portion of the second electrode is positioned at or directly below the gap.

[0142] Furthermore, the bottom ends of any pair of light-emitting diodes having a second adjacent relationship are adjacent to each other without any gap.

[0143] In one embodiment, the top conductive layer includes at the interval:

[0144] A horizontally extending section above the top surface of the substrate to cover the top surface of the substrate; and

[0145] The recessed contact section, which is recessed relative to the top surface of the substrate, is configured as a columnar section that is coaxial with the second electrode and has a radial dimension smaller than the radial dimension of the top surface of the second electrode.

[0146] The horizontal section and the sunken contact section together form a rotationally symmetrical structure around the axis of the second electrode.

[0147] In one embodiment, the top conductive layer has an inverted truncated conical section between the light-emitting diodes having a second adjacent relationship, such that the bottom end of the inverted truncated conical section having a minimum radial dimension is connected to the substrate.

[0148] Furthermore, the bottom end of the truncated conical section and another part of the second electrode are separated by a dielectric material of the substrate.

[0149] In one embodiment, a semiconductor interconnect layer with a radial dimension smaller than that of the top surface of the second type semiconductor is disposed on the top of the second type semiconductor.

[0150] In one embodiment, the semiconductor interconnect layer is made of at least one of Au, Ge, Ni, Cr, Br, and Ti, wherein the content of Au is greater than, less than, or equal to the content of Ge; and / or

[0151] The semiconductor interconnect layer is made of a semi-transparent material; and / or

[0152] The thickness of the semiconductor interconnect layer is 0.5nm-150nm.

[0153] In one embodiment, the thickness of the bottom conductive layer is 1 / 20 to 2 times the thickness of the bonding layer; and / or

[0154] The total thickness of the bottom conductive layer and the bonding layer is 50nm-4000nm; and / or

[0155] The thickness of the bottom conductive layer is less than 1000 nm; and / or

[0156] The thickness of the bonding layer is 50nm-3000nm.

[0157] In one embodiment, the bonding layer includes a mirror layer on top of it, the mirror layer being made of pure silver, pure gold, a silver-copper alloy, or a gold-chromium alloy; or

[0158] The mirror layer is made of gold and trace elements, with gold being the main component and the trace elements including at least one of chromium, titanium, and nickel.

[0159] In one embodiment, the top conductive layer includes a horizontally extending section at the interval to cover the top surface of the second electrode, the horizontal section being directly connected to a section of the top conductive layer covering the sidewall of the light-emitting diode, wherein the horizontal section is located above or recessed relative to the top surface of the substrate.

[0160] In one embodiment, the light-emitting diode chip is a micro light-emitting diode chip that uses micron-scale LEDs as light-emitting diodes.

[0161] In one embodiment, the light-emitting diode chip further includes:

[0162] Multiple microlenses, each corresponding to a light-emitting diode;

[0163] A light-transmitting gap is provided between the microlens and the light-emitting diode. The light-transmitting gap has a gap between two adjacent light-emitting diodes. The gap is a narrow slit with a closed top. The top of the gap is higher than the light-emitting layer of the light-emitting diode, and the bottom of the gap is lower than the light-emitting layer of the light-emitting diode. Attached Figure Description

[0164] To better understand the above and other objects, features, advantages, and functions of the present invention, reference can be made to the preferred embodiments shown in the accompanying drawings. The same reference numerals in the drawings refer to the same parts. Those skilled in the art should understand that the drawings are intended to schematically illustrate preferred embodiments of the invention and do not limit the scope of the invention in any way; the parts in the drawings are not drawn to scale.

[0165] Figure 1A A top view of a light-emitting diode chip according to one aspect of the present invention is shown, in which structures such as microlenses are omitted to show the light-emitting diode;

[0166] Figure 1B This is a top view of the second electrode of the LED chip;

[0167] Figure 2 For along Figure 1A A cross-sectional view taken from line AA in the diagram;

[0168] Figure 3 for Figure 2 A magnified view of part E in the image;

[0169] Figure 4 For along Figure 1A A cross-sectional view taken from the BB line in the diagram;

[0170] Figure 5 For relative to Figure 2 A schematic diagram showing the addition of structures such as microlenses;

[0171] Figure 6 for Figure 2 Another possible structure for the light-emitting diode in the image;

[0172] Figure 7 for Figure 2 Another possible structure for a light-emitting diode (LED) in a given configuration;

[0173] Figure 8 for Figure 5 The diagram shows another possible structural schematic.

[0174] Figure 9 for Figure 5 The diagram shows another possible structural schematic.

[0175] Figure 10 for Figure 9 The image shows a general top view of the light-emitting body, which omits some structures to clearly show the top surface of the second type of semiconductor.

[0176] Explanation of reference numerals in the attached figures:

[0177] 100 miniature LED chips

[0178] 1 substrate

[0179] 11 openings

[0180] 12 top substrate layers

[0181] 13 Substrate Layer

[0182] 14. Medium Materials

[0183] 2-pixel unit

[0184] 21 LEDs

[0185] 211 Light-emitting body

[0186] 2111 Type II Semiconductor

[0187] Other regions of 2111a type II semiconductor

[0188] 2111b Thinning region of type II semiconductor

[0189] 2111c First Region

[0190] 2112 Emissive Layer

[0191] 2113 Type I Semiconductor

[0192] 212 bottom conductive layer

[0193] 213 bonded layer

[0194] 214 Top Conductive Layer

[0195] 2141 horizontal section

[0196] 2142 Subsidence Contact Section

[0197] 2143 sidewall coverage section

[0198] 2144 Inverted truncated cone section

[0199] 215 insulation layer

[0200] 2151 Outer wall first section

[0201] 2152 Outer wall second section

[0202] 2153 Outer wall third section

[0203] 216 Additional Insulation Layer

[0204] 217 Semiconductor Interconnect Layer

[0205] 218 Additional Top Conductive Layer

[0206] 22 Light-transmitting partition

[0207] 221 gap section

[0208] 23 microlenses

[0209] 24 Spacing between adjacent LEDs

[0210] 3 First electrode

[0211] 31 Top section of the first electrode

[0212] 32 Bottom section of the second electrode

[0213] 4, 4', 4'' Second Electrode

[0214] 41 Electrode Second Conductive Layer

[0215] 42 Electrode First Conductive Layer

[0216] 43 Hollow section Detailed Implementation

[0217] Now, with reference to the accompanying drawings, specific embodiments of the present invention will be described in detail. The embodiments described herein are merely preferred embodiments of the invention; those skilled in the art can conceive of other ways to implement the invention based on these preferred embodiments, and such other ways also fall within the scope of the invention.

[0218] Figures 1A-10 A miniature light-emitting diode chip according to the present invention is shown. It should first be noted that the directional and positional terms used in this invention should be understood as relative directions and positions, not absolute directions and positions. The directional and positional terms used in this invention can be referred to... Figures 1A-10 The exemplary structure shown is explained.

[0219] Specifically, "axial direction" can be understood as the axial direction of the roughly columnar structure formed by the light-emitting diodes 21 of the micro LED chip 100. Figure 1A The light-emitting diode 21 is indicated by X. It should be noted that the light-emitting diode 21 can be formed into various structures such as a cylinder, a truncated cone, a prism, or other shapes with a height extending along the X direction. For ease of description, these structures are all considered to have an axial direction X. "Radial direction" refers to the radial direction with respect to the axial direction X. Figure 1A The direction is indicated by R; the "circumferential direction" is the circumferential direction around the axial direction X. Figure 1A The symbol C represents the direction of height and thickness, which are parallel to or coincide with the axial direction X.

[0220] Location terminology should also be combined Figures 2-9 Understanding. For example, expressions such as "above," "below," "bottom," and "top" can all be referenced. Figures 2-9 Understand the relative positions of the components shown.

[0221] First refer to Figures 1A-4Some preferred embodiments of the present invention provide a light-emitting diode chip, particularly a micro-light-emitting diode chip 100, i.e., a high pixel density LED formed in micrometer-scale cycles. The micro-light-emitting diode chip 100 includes a substrate 1 and a plurality of light-emitting diodes 21 arranged in an array on the substrate 1. The substrate 1 may be, for example, an IC driver backplane, and includes a dielectric layer and driving circuitry (not shown) housed within the dielectric layer, such as a SiO2 layer. Each light-emitting diode 21 is generally formed in a truncated cone shape, with its radial dimension gradually decreasing from bottom to top. It should be noted that the shapes of the components described in this invention do not necessarily imply that the components have strictly defined geometrical shape characteristics, but only that they visually roughly conform to specific shape characteristics. In some embodiments, the substrate may also contain circuitry other than the IC driver circuitry. In other embodiments, the light-emitting diode chip may be a large-particle LED light-emitting diode chip.

[0222] refer to Figure 2 and Figure 3 Each light-emitting diode 21 includes a light-emitting body 211, which includes a light-emitting layer 2112, a first-type semiconductor 2113 located on the bottom side of the light-emitting layer 2112, and a second-type semiconductor 2111 located on the top side of the light-emitting layer 2112. The light-emitting body 211 is also referred to as an epitaxial layer, and the light-emitting layer 2112 is also referred to as an active layer. The first-type semiconductor 2113 can be either an N-type semiconductor or a P-type semiconductor, and the second-type semiconductor 2111 can be either an N-type semiconductor or a P-type semiconductor.

[0223] The miniature light-emitting diode chip 100 also includes a first electrode 3 and a second electrode 4. The first electrode 3 is disposed on the substrate 1 and positioned at the bottom of each light-emitting diode 21, and is electrically connected to a first-type semiconductor 2113. The second electrode 4 is disposed on the substrate 1 and positioned between adjacent light-emitting diodes 21, and is electrically connected to a second-type semiconductor 2111. The first electrode 3 has the same polarity as the first-type semiconductor 2113, and the second electrode 4 has the same polarity as the second-type semiconductor 2111. In some embodiments, the first-type semiconductor 2113 is a P-type semiconductor, the second-type semiconductor 2111 is an N-type semiconductor, the first electrode 3 is a P-type electrode, and the second electrode 4 is an N-type electrode.

[0224] In this embodiment, the light-emitting diode 21 does not include the first electrode 3 and the second electrode 4, and the light-emitting diode 21 can also be referred to as a light-emitting mesa.

[0225] In some embodiments, the second electrode 4 is at least partially embedded in the substrate 1, such that the bottom end of the second electrode 4 is lower than the bottom ends of the plurality of light-emitting diodes 21. Figure 2 and Figure 4 In the schematic diagram shown, the top of the second electrode 4 is lower than or flush with the bottom of the plurality of light-emitting diodes 21, meaning that the second electrode 4 is completely embedded in the dielectric layer of the substrate 1. However, in other embodiments not shown, the second electrode 4 may only have its bottom embedded in the dielectric layer of the substrate 1, while its top protrudes from the substrate 1 and is located directly between adjacent light-emitting diodes 21. That is, the top of the second electrode 4 may overlap with the light-emitting diodes 21 to a certain extent in the height direction. It is understood that "between the second electrode and the light-emitting diodes" does not mean that there is an overlap with the light-emitting diodes 21 in the horizontal direction. For example, the second electrode 4 being completely below the light-emitting diodes 21 is also referred to as the second electrode 4 being located between the light-emitting diodes 21.

[0226] Continue to refer to Figures 2-4 Each light-emitting diode 21 further includes a bottom conductive layer 212 located on the bottom side of the first type semiconductor 2113, a bonding layer 213 located on the bottom side of the bottom conductive layer 212, and a top conductive layer 214 at least partially covering the top of the second type semiconductor 2111. The first electrode 3 is electrically connected via the bottom conductive layer 212, the bonding layer 213 and the first type semiconductor 2113, and the second electrode 4 is electrically connected via the top conductive layer 214 and the second type semiconductor 2111.

[0227] In some embodiments, both the bottom conductive layer 212 and the top conductive layer 214 can be transparent conductive layers made of, for example, ITO. The bonding layer 213 is used to bond the light-emitting body 211 to the substrate 1, and the material of the bonding layer 213 can be selected from at least one of Ag, Pt, Au, Sn, Cr, and Ti. Specifically, the bonding layer 213 includes a mirror layer (e.g., P-mirror) on top of it, and the mirror layer is made of pure silver, pure gold, a gold-chromium alloy, or a silver-copper alloy. Alternatively, the mirror layer may contain gold and trace elements, with gold as the main component and the trace elements including at least one of chromium, titanium, and nickel. Specifically, different metals have different reflectivities for red, green, and blue wavelengths, and specific materials can be selected for different colors. Pure silver and silver-copper alloys are particularly suitable for yellow-green LEDs. Pure silver, pure gold, and gold-chromium alloys are particularly suitable for red LEDs.

[0228] Preferably, in some embodiments, the bonding layer 213 may further include multiple bonding metal layers (not shown), and the materials of each bonding metal layer may be different. For example, the bonding metal layer in direct contact with the bottom conductive layer 212 may be made of a metal material that is not easily diffused, will not cause serious consequences even if it diffuses, or has low contact resistance with the bottom conductive layer 212. The bottom conductive layer 212 and the metal bonding layer 213 enhance reflectivity. Reflectivity can be further improved by adjusting the interface between the two and the aforementioned interface. The bottom conductive layer 212 may be made of a transparent material to achieve an optimized ODR (Optical Derivative Reflector) mirror effect. The bonding metal layer located in the middle of the bonding layer 213 may be made of a metal material with good conductivity; the bottom bonding metal layer of the bonding layer 213 may be made of a metal material with good bonding to the substrate 1.

[0229] Specifically, the thickness of the bottom conductive layer 212 is 1 / 20 to 2 times the thickness of the bonding layer 213. The total thickness of the bottom conductive layer 212 and the bonding layer 213 is 50nm-4000nm. The thickness of the bottom conductive layer 212 is less than 1000nm, specifically 0nm-500nm, or 10nm-1000nm. The thickness of the bonding layer 213 is 50nm-3000nm, specifically 100nm-700nm, or 50nm-3000nm. The above parameters of the bottom conductive layer 212 have practical engineering significance because the bottom conductive layer 212 itself has light absorption properties; the thicker it is, the stronger its light absorption capacity. Conversely, the thinner the bottom conductive layer 212, the weaker the light distribution and refraction effect, and the lower the light extraction efficiency.

[0230] Figure 2 and Figure 4 The diagram illustrates the connection relationships between adjacent light-emitting diodes 21 and their connection relationships with the second electrode 4 from different cross-sectional viewpoints. Specifically, it shows... Figure 2 The adjacent LEDs 21 shown are referred to as a pair of LEDs with a first adjacent relationship. Figure 4 The adjacent LEDs 21 shown are referred to as a pair of LEDs with a second adjacent relationship. Among them, as... Figure 2 As shown, a gap 24 exists between a pair of light-emitting diodes 21 that have a first adjacent relationship, and the second electrode 4 is partially positioned at or directly below the gap 24, while as Figure 4The bottom ends (the portion above the substrate 1) of the pair of light-emitting diodes 21 with the second adjacent relationship shown are close together without any gap (for example, the presence of only the top conductive layer within this gap is also considered "without gap"). Here, "close together without gap" means that the outer structural layers of the pair of light-emitting diodes 21 (in this embodiment, the top conductive layer 214) converge at the bottom ends of the pair of light-emitting diodes 21, forming an angle, rather than a distinct horizontal transition region. It should be noted that in actual manufacturing processes, this angle may be chamfered or sharpened, but this is different from the presence of a horizontal transition region.

[0231] Furthermore, the top conductive layer 214 extends from the top of the second type semiconductor 2111 to the top of the second electrode 4, and an insulating layer 215 is provided between the sidewall of the light-emitting body 211 and the top conductive layer 214. In a conventional structure where the second electrode is located above the substrate, the second electrode can be directly positioned above the top conductive layer and in direct contact with it. However, in this invention, since the second electrode 4 is partially embedded in the substrate 1, the second electrode 4 is located below the top conductive layer 214. In order to enable the second electrode 4 to contact the top conductive layer 214 and avoid short-circuit problems, in some embodiments, the insulating layer 215 extends downward from the top of the light-emitting diode 21 and terminates above the second electrode 4 near the first adjacent light-emitting diodes 21 without reaching the top of the second electrode 4. That is, the insulating layer 215 forms an opening on the top of the second electrode 4, thereby allowing the bottommost end 2141 of the top conductive layer 214 and the second electrode 4 to contact each other at the opening.

[0232] refer to Figure 3 The top conductive layer 214 includes a sidewall covering section 2143 covering the sidewall of the light-emitting diode 21, a horizontal section 2141 at a spacing 24, and a recessed contact section 2142. The horizontal section 2141 extends horizontally above the top surface of the substrate 1 to cover the top surface of the substrate 1. The recessed contact section 2142 is recessed relative to the top surface of the substrate 1 and is configured as a columnar section coaxial with the second electrode 4 and having a radial dimension smaller than the radial dimension of the top surface of the second electrode 4. The horizontal section 2141 connects the sidewall covering section 2143 and the recessed contact section 2142. The horizontal section 2141 and the recessed contact section 2142 together form a rotationally symmetrical structure about the axis of the second electrode 4.

[0233] This arrangement enables point-to-point conductive contact between the second electrode 4 and the top conductive layer 214, achieving a more precise conductive connection and helping to reduce the size of their electrical connection point, thus allowing the spacing 24 between the first adjacent LEDs 21 to be made sufficiently small. Furthermore, as... Figure 4 As shown, the light-emitting diodes 21 with the second adjacent relationship have no gap between them and are closely connected. The space here can be further reduced, which is more conducive to chip miniaturization.

[0234] The connection between the top conductive layer 214 and the second electrode 4 also brings a host of other advantages. For example, the simultaneous provision of the horizontal section 2141 and the sunken contact section 2142 makes the current conduction at the interval 24 between the first adjacent light-emitting diodes 21 smoother. Imagine if either section were omitted, it would lead to problems such as incomplete structure of the top conductive layer 214 at this point, increased resistance, and current loss.

[0235] In other embodiments, the top conductive layer may include horizontal sections extending in a horizontal direction to cover the top surface of the second electrode at intervals, without having recessed contact sections. The horizontal sections are directly connected to the sections of the top conductive layer that cover the sidewalls of the light-emitting diode. The horizontal sections are located above or recessed relative to the top surface of the substrate. Being located on the top surface facilitates molding, reduces manufacturing difficulty, and lowers cost; while being recessed relative to the top surface of the substrate increases structural rigidity and provides tighter contact.

[0236] In particular, such as Figure 4 As shown, the top conductive layer 214 has an inverted truncated conical section 2144 between any pair of light-emitting diodes 21 having a second adjacent relationship, such that the bottom end of the inverted truncated conical section 2144 with the smallest radial dimension is connected to the substrate 1, and the bottom end of the inverted truncated conical section 2144 and the second electrode 4 are separated by the dielectric material 14 of the substrate. The bonding layer 213 or the bottom conductive layer 212 of the pair of light-emitting diodes 21 having a second adjacent relationship at least partially blocks the second electrode 4 between the pair of light-emitting diodes 21 in the vertical direction, that is, the pair of light-emitting diodes 21 having a second adjacent relationship overlaps with the second electrode 4 in the vertical direction. This arrangement can ensure that the light-emitting diodes 21 are made as large as possible (when the overall chip is small), resulting in better optical performance of the chip.

[0237] In fact, the second electrode 4 is disposed around almost every light-emitting diode 21, thus forming between any adjacent light-emitting diodes 21. Specifically, in a micro light-emitting diode chip 100, the second electrode 4 is integrally connected and formed in a grid shape, with each light-emitting diode 21 positioned within the grid. This part can be referred to... Figure 1B The top view of the second electrode 4 shown. Figure 1B As shown, the mesh-like structure formed by the second electrode 4 includes an array of hollow portions 43, with each light-emitting diode 21 positioned correspondingly in one of the hollow portions 43. However, each light-emitting diode 21 is not directly placed within its corresponding hollow portion 43, but may be located directly above it. For the integrated second electrode 4, a portion of its structure contacts the top conductive layer 214 (e.g., located in...). Figure 2 The light-emitting diodes shown are adjacent to each other, while a portion of the section is spaced apart from the top conductive layer 214 (e.g., located in...). Figure 4 The diagram shows the second adjacent LEDs. Figure 1A As shown, an opening 11 is formed at a specific location on the substrate 1 to expose the second electrode 4 or the top conductive layer 214 on top of the second electrode 4, etc.

[0238] In this invention, the second electrode 4 is at least partially embedded in the dielectric layer of the substrate 1, thereby reducing the space occupied by the second electrode 4 between adjacent light-emitting diodes 21 and adaptively reducing the gap between adjacent light-emitting diodes 21. This results in a relatively smaller overall size of the chip 100, which can be matched with thinner and more portable electronic devices and adapt to more application scenarios.

[0239] In some embodiments, the light-emitting diode 21 may also be provided with an additional insulating layer 216, which is formed radially inside the insulating layer 215 and surrounds only the light-emitting body 211. The insulating layer 215 and the additional insulating layer 216 can be made of the same material, such as SiN. The insulating layer 215 can be formed by physical vapor deposition, and the additional insulating layer 216 can be formed by chemical vapor deposition, or the insulating layer 215 and the additional insulating layer 216 can be integrally formed using the same process.

[0240] refer to Figure 4 and Figure 2The outer wall of the insulating layer 215 comprises three sequentially connected segments: a first segment 2151, a second segment 2152, and a third segment 2153. The transition between the first and second segments 2151 and 2152 is a sharp corner rather than a smooth transition; similarly, the transition between the second and third segments is also a sharp corner rather than a smooth transition. In other words, the second segment 2152 forms a distinct stepped surface with sharp inflection points at both ends. This design facilitates photolithography and is crucial for ensuring the integrity of the light-emitting diode 21, making it particularly suitable for light-emitting diode chips with an embedded second electrode 4. The three sections, namely the first section 2151 of the side wall, the second section 2152 of the outer side wall, and the third section 2153 of the outer side wall, along with the two connecting inflection points in between, constitute the outer contour of the insulating layer 215 that completely protects the light-emitting diode 21. If this design is removed or deformed (e.g., a section or an inflection point is removed), the performance of the insulating layer 215 may be poor, thereby reducing the performance of the light-emitting diode 21.

[0241] A semiconductor interconnect layer 217 may be disposed on the top surface of the second type semiconductor 2111. The top surface of the second type semiconductor 2111 and the semiconductor interconnect layer 217 may be directly covered by an additional top conductive layer 218, and the top conductive layer 214 and the additional top conductive layer 218 are electrically connected. That is, the second type semiconductor 2111 may be indirectly electrically connected to the top conductive layer 214. In some embodiments, the additional top conductive layer 218 may be integrally formed with the top conductive layer 214.

[0242] The semiconductor interconnect layer 217 can be integrally formed with the second type semiconductor 2111, and can be directly processed on the top surface of the second type semiconductor 2111 to form the semiconductor interconnect layer 217. Alternatively, the semiconductor interconnect layer 217 can be made of a different material than the second type semiconductor 2111, and the semiconductor interconnect layer 217 can be constructed to be semi-transparent to improve its light transmittance. For example, the thickness of the semiconductor interconnect layer 217 can be 0.5 nm-150 nm, specifically 2.5 nm, with a light transmittance of 65%. The aforementioned smaller thickness of the semiconductor interconnect layer 217 optimizes its performance; specifically, the thinner the semiconductor interconnect layer 217, the higher its top light transmittance, the higher its light extraction efficiency, and the better its divergence angle. The material of the semiconductor interconnect layer 217 can contain at least one of Au, Ge, Ni, Cr, Br, and Ti, preferably with a greater Au content than the Ge and Ni content. The Au content can also be less than or equal to the Ge content. More preferably, the Au content is more than three times the total amount of all other elements. This material makes the molding process of the semiconductor interconnect layer 217 more stable and the pixel voltage more stable. The radial dimension of the semiconductor interconnect layer 217 can be 1 / 4 to 1 of the top radial dimension of the light-emitting body 211 (when this value is 1, the semiconductor interconnect layer 217 covers the entire top side of the light-emitting body 211).

[0243] As mentioned above, each light-emitting diode 21 forms a columnar structure with its radial dimension gradually decreasing from bottom to top, specifically a truncated cone, on a predetermined cross-section (e.g., on the plane containing the axis X of the light-emitting diode 21). Figure 2 and Figure 4 The interface shown has a trapezoidal cross-section for the light-emitting diode 21. Further, in, for example... Figure 2 and Figure 4 On the predetermined cross-section shown, the second electrode 4 is formed as a trapezoidal cross-section with radial dimensions gradually increasing or decreasing from bottom to top. Setting the second electrode 4 to have a trapezoidal cross-section makes it more suitable for its process characteristics. The trapezoidal cross-section of the second electrode 4 is particularly suitable for the manufacture of electrodes of chips with electrodes embedded in the substrate, and it is easy to implement in the process and easy to mass produce.

[0244] Furthermore, the angle α between the lower base and the waist of the trapezoidal cross-section of the light-emitting diode 21 and the angle β between the lower base and the waist of the trapezoidal cross-section of the second electrode 4 are the same (i.e., equal or approximately equal). In other words, the shapes of the light-emitting diode 21 and the second electrode 4 have a certain similarity, which is particularly beneficial for current conduction, especially for improving the effectiveness of the second electrode 4 in receiving current when at least a portion of it is embedded in the substrate 1. Specifically, α can be 50°-90°, more preferably 85°. In other embodiments, α can be greater than or less than β.

[0245] refer to Figure 4To avoid contact between the bonding layer 213 and the second electrode 4, the embedding position of the second electrode 4 can be lowered, making the bottom surface of the bonding layer 213 higher than the top surface of the second electrode 4, with a height difference of 10nm-2μm. This arrangement has been verified in engineering to simultaneously avoid the risk of short circuits and ensure the effectiveness of current conduction. Specifically, through engineering verification, if the height difference is too small, the dielectric layer of the substrate 1 contributing to the height difference will be easily broken down by current, causing a short circuit between the bonding layer 213 and the second electrode 4. If the height difference is too large, the second electrode 4 will be embedded in the substrate 1 at a greater depth, resulting in an excessively long top conductive layer used to conduct current from the second type semiconductor 2111 to the second electrode 4, leading to greater current loss and affecting the effectiveness of current conduction. The 10nm-2μm size difference can simultaneously avoid short circuits and ensure the effectiveness of the top conductive layer 214. Meanwhile, it can be understood that since there is already a dielectric layer of appropriate size in the height direction between the second electrode 4 and the bonding layer 213, the horizontal distance between them can be made smaller, which is beneficial to the overall miniaturization of the chip.

[0246] In other embodiments, the bottom surface of the bonding layer 213 may also be flush with the top surface of the second electrode 4, and insulation between the two is ensured by maintaining a dielectric material of sufficient thickness between the bonding layer 213 and the second electrode 4 (understandably, this dielectric material is approximately flush with the bonding layer 213 and the second electrode 4 in the height direction). In such embodiments, the size or shape of the second electrode 4 needs to be appropriately adjusted. This arrangement facilitates compressing the chip size in the height direction.

[0247] Besides its location, the second electrode 4 can also have some preferred structural configurations. For example, the material of the second electrode 4 can be one or more of Cr, Pt, Au, Ti, Al, Ag, and Sn. As another example, see reference... Figure 3 The second electrode 4 includes a first conductive layer 42 and a second conductive layer 41 on top of the first conductive layer 42. The second conductive layer 41 is configured to prevent metal diffusion from the first conductive layer 42. More preferably, the second conductive layer 41 is made of Cr or Ti, and the first conductive layer 42 is made of one or more of Cr, Pt, Au, Ti, Al, Ag, and Sn. These materials have unique advantages in manufacturing the second electrode 4 in this invention. For example, Cr, Ti, and Sn have high reflectivity and good adhesion, making them particularly suitable as the bottom structure of the electrode; Pt, Au, and Ag have low resistivity and excellent conductivity, enabling them to function as the contact or top portion of the electrode; and Al, due to its low cost and ease of processing, is suitable for use as an electrode material in mass production. On the other hand, the thickness of the first conductive layer 42 is greater than the thickness of the second conductive layer 41.

[0248] It should be noted that, in order to optimize the performance of electrode 4, the first conductive layer 42 of electrode should serve as the main medium for the spread of current (e.g., N current) throughout the active region. Therefore, it is necessary to select a metal with high conductivity as much as possible. In addition, it is necessary to ensure a certain volume (achieved by setting the thickness, width, and height) to minimize the resistance of the first conductive layer of electrode. The main function of the second conductive layer 41 of electrode is etching barrier / adhesion. In addition, the conductivity of barrier materials such as Cr and Ti (preferred materials for the second conductive layer 41 of electrode) is not as high as that of metals such as Au and Cu (the first conductive layer 42 of electrode). Therefore, the second conductive layer 41 of electrode must be made relatively thin. The material and dimensional characteristics of the first conductive layer 42 and the second conductive layer 41 of electrode described above meet the above requirements.

[0249] from Figure 3 As can be clearly seen, the side surfaces of the first conductive layer 42 and the second conductive layer 41 are smoothly connected and transitioned, giving the second electrode 4 a smooth side surface. This configuration gives the second electrode 4 a complete and smooth contour shape, allowing the first conductive layer 42 and the second conductive layer 41 to work together to perform the function of the second electrode 4, including making current conduction smoother and avoiding adverse factors such as tip discharge caused by rough contours. In other embodiments, a step is formed between the sidewalls of the first conductive layer 42 and the second conductive layer 41. This implementation is easier to achieve in terms of manufacturing process and is more conducive to the mass production of chips.

[0250] In some embodiments, the first electrode 3 may also have certain preferred configurations. For example, such as... Figure 2 and Figure 4 As shown, the first electrode 3 includes a top segment 31 and a bottom segment 32, both of which are formed as columnar structures perpendicular to the substrate 1. The radial dimension of the top segment 31 is smaller than that of the bottom segment 32. The second electrode 4 is located between the top segments 31 of adjacent first electrodes 3. Setting the radial dimension of the top segments 31 of the first electrode 3 to be relatively small facilitates the alignment between the first electrode 3 and the light-emitting diode 21, while also allowing for more space between adjacent first electrodes 3 to accommodate the corresponding second electrode 4. The first electrode 3 can be made of Cu.

[0251] Preferably, the bottom surface of the top segment 31 of the first electrode 3 is flush with the bottom surface of the second electrode 4. Also preferably, the radial dimensions of both the top segment 31 and the bottom segment 32 gradually increase from bottom to top. This arrangement improves current distribution (e.g., a larger top contact area results in stronger current conduction), enhances mechanical and thermal stability, optimizes light extraction efficiency, simplifies manufacturing processes, and supports high-density integration, thus contributing to improved overall performance, reliability, and application range of Micro-LEDs.

[0252] Corresponding to the top segment 31 and bottom segment 32 of the first electrode 3, the substrate 1 also includes a top substrate layer 12 that accommodates the top segment 31 of the first electrode 3 and a bottom substrate layer 13 that accommodates the bottom segment 32 of the first electrode 3. The top substrate layer 12 and the bottom substrate layer 13 can be integrally formed without obvious boundaries.

[0253] The bottom segment 32 is located at the bottom surface layer of the substrate 1. No special manufacturing process is required for the bottom surface layer of the substrate 1 during the manufacturing process. The top substrate layer 12 serves as a redistribution layer, being higher than the bottom substrate layer 13, facilitating the processing of its top surface during manufacturing. Preferably, the interface between the first type semiconductor 2113 and the bottom conductive layer 212 is flat, and the interface between the bottom conductive layer 212 and the bonding layer 213 is also flat. This arrangement increases light reflection from the bottom side of the light-emitting layer 2112, thereby increasing light emission. Furthermore, the roughness of both the interface between the first type semiconductor 2113 and the bottom conductive layer 212, and the interface between the bottom conductive layer 212 and the bonding layer 213, is less than 10 nm. It should be noted that "roughness" in this paper refers to the maximum height difference of the contact surfaces, such as the height difference between the lowest and highest points of a particle.

[0254] In some implementations, the arrangement of the microlens 23 is also optimized. See details... Figure 5 Each light-emitting diode (LED) 21 has a corresponding microlens 23 positioned above it, and the microlens 23 has an upwardly convex curvature. A light-transmitting spacer 22 is provided between the LED 21 and the microlens 23, and the light-transmitting spacer 22 circumferentially surrounds the LED 21, so that the LED 21 is entirely embedded within the light-transmitting spacer 22. For any given LED 21, the LED 21, the microlens 23 directly above it, and the light-transmitting spacer 22 connecting the LED 21 and the microlens 23 together constitute a pixel unit 2. It should be noted that the term "constituent" in this invention does not imply a closed inclusion relationship. For example, the pixel unit 2 may include other parts besides the microlens 23, the light-transmitting spacer 22, and the LED 21.

[0255] Adjacent pixel units 2 can be adjacent to each other or, for example, Figure 5The light-transmitting gaps 22 of adjacent pixel units 2 are connected by light-transmitting gap connecting segments. In some embodiments, the light-transmitting gaps 22 of all pixel units 2 of the micro-light-emitting diode chip 100 and all the light-transmitting gap connecting segments are integrally formed and made of the same material. In some embodiments, the microlens 23 and the light-transmitting gaps 22 of the micro-light-emitting diode chip 100 are integrally formed and made of the same material.

[0256] A gap 221 is present at the connection section of the light-transmitting interval (i.e., between adjacent pixel units 2). The gap 221 is a narrow slit with a closed top. The top of the gap 221 is higher than the light-emitting layer 2112 of the light-emitting diode 21, and the bottom of the gap 221 is lower than the light-emitting layer 2112 of the light-emitting diode 21. The light-transmitting interval 22 and the gap 221 can be generated simultaneously by a self-growth process. The function of the gap 221 is to optimize the light emission angle, isolate the light emission interference of each light-emitting diode 21, and increase the overall light emission.

[0257] Next, go to Figure 6 and Figure 7 The following describes some preferred configurations of another aspect of the present invention. Figure 6 and Figure 7 Some optional settings for the luminous body 211 are shown.

[0258] First refer to Figure 6 The second type semiconductor 2111 includes a thinned region 2111b, the thickness of which is less than the thickness of other regions 2111a of the second type semiconductor 2111. The thinned region 2111b is, for example, a cut or recess formed on the second type semiconductor 2111. Preferably, the thinned region 2111b is positioned at the top circumferential edge of the second type semiconductor 2111 to surround other regions 2111a. More preferably, the thinned region 2111b extends continuously along the circumferential direction C. This arrangement ensures the symmetry of the light-emitting body 211, and the light emission distribution can be symmetrical. Also preferably, on a predetermined cross-section (e.g., on the plane containing the axis X of the light-emitting diode 21)... Figure 6 As shown in the interface), the tilt angle γ of the sidewalls of other regions 2111a of the second type semiconductor 2111 is consistent with the tilt angle θ of the sidewalls formed by the light-emitting layer 2112 and the first type semiconductor 2113. This arrangement ensures that the light-emitting body 211, even with a thinned region, still maintains good structural consistency, facilitating manufacturing. The top radial dimension of the thinned region 2111b can be 0%-75% of the overall top radial dimension of the light-emitting body 211. In other embodiments, γ can be greater than or less than θ.

[0259] Next, go to Figure 7In some embodiments, the thinned region 2111b is constructed to have a thickness of zero, that is, the circumferential edge of the second type semiconductor 2111 is completely removed, leaving only the central region (other regions 2111a), and the light emitted from the circumferential top wall of the light-emitting layer 2112 can be emitted directly upward without passing through the second type semiconductor 2111. Figure 7 Other aspects of settings and Figure 6 The same applies, so I won't repeat it here.

[0260] Figure 6 and Figure 7 In the structure shown, the light extraction efficiency of the light-emitting layer 2112 below the thinned portion is improved due to the presence of the thinned region 2111b, thereby optimizing the light extraction performance of the light-emitting diode 21. The zero thickness of the thinned region 2111b further enhances the light extraction efficiency and saves semiconductor material.

[0261] Figure 6 and Figure 7 The light-emitting body 211 shown can be applied to Figures 1A-5 The implementation shown, in other words, Figure 6 and Figure 7 The structure shown should be considered as Figures 1A-5 This is a part of the implementation shown. Figure 6 and Figure 7 Other regions 2111a of the second type semiconductor 2111 can be directly constructed as follows: Figure 2 The semiconductor interconnect layer 217 is shown.

[0262] The following is for reference. Figures 8 to 10 A preferred embodiment of another aspect of the invention will now be described. First, refer to… Figure 8 The top surface of the second type semiconductor 2111 is roughened to form a first region 2111c. The first region 2111c is a non-planar surface with optical microstructures. A non-planar surface with optical microstructures can increase light emission and diffuse reflection. For example, it can be an uneven surface with jagged grains. A non-planar surface with jagged grains can increase diffuse reflection and improve light extraction efficiency, thereby enhancing light extraction performance. Figure 8 In the structure shown, the second electrode 4 is located between adjacent light-emitting diodes 21, and the second electrode 4 is in direct contact with the top conductive layer 214. Although not shown in the figure, it can be understood that the top conductive layer 214 has a portion that is electrically connected to the second type semiconductor 2111.

[0263] Continue to refer to Figure 9 and Figure 10The top surface of the second type semiconductor 2111 further includes a second region, on which a semiconductor interconnect layer 217 is disposed. The micro-light-emitting diode 21 includes a top conductive layer 214 partially coated on the top of the second type semiconductor 2111. The top conductive layer 214 covers only the second region on the top surface of the second type semiconductor 2111. The semiconductor interconnect layer 217 is configured to electrically connect the second type semiconductor 2111 and the top conductive layer 214. The top surface of the semiconductor interconnect layer 217 is planar. The dimensions and material settings of the semiconductor interconnect layer 217 can be configured to... Figure 2 The semiconductor interconnect layer 217 is the same as in the previous one, and for the sake of simplicity, it will not be described again here. It should be noted that... Figure 9 and Figure 10 It can be corresponding, that is Figure 9 and Figure 10 These can be sectional views and top views of the same structure; in this case, it can be understood that... Figure 9 and Figure 10 Some structures have been omitted or their positions appropriately adjusted; or, Figure 9 and Figure 10 Different implementation methods are also possible.

[0264] In this embodiment, the second region with optical microstructures directly contacts the dielectric material. The non-planar plane with uneven particle size is partially covered by a dielectric layer (the spacer portion of the microlens), while another part is covered by a conductive structure, enabling both effective cooperation with the microlens and outward transmission of current.

[0265] Preferably, such as Figure 10 As shown, for each micro LED 21, the first regions 2111c on the top surface of its second type semiconductor 2111 are interconnected and surround a unique second region (which can be understood as...). Figure 10 The top conductive layer 214 directly above the semiconductor interconnect layer 217 has been removed. In other embodiments not shown, the top surface of the second type semiconductor 2111 includes at least two first regions 2111c spaced apart from each other, and the top surface of the second type semiconductor 2111 may also include at least two second regions spaced apart from each other. The top surface of the second type semiconductor also includes a third region different from the first and second regions. The second regions may be located near the edge of the second type semiconductor 2111 to avoid blocking the light emitted by the light-emitting diode 21. Preferably, the area of ​​the second region may be less than half the area of ​​the top surface of the second type semiconductor 2111.

[0266] The portion of the top conductive layer 214 covering the semiconductor interconnect layer 217 may have the same or similar shape as the semiconductor interconnect layer 217.

[0267] Figure 8 and Figure 9 The first region 2111c shown as being formed as a non-planar surface with uneven granularity can have further optional configurations. For example, the non-planar surface can be a serrated surface. The serrated surface can include a uniform serrated surface where each serration is identical, or it can include an irregular serrated surface. The serrated surface may include irregular particles (which may be regular or irregular), which may be spherical or have sharp tips. Sharp-tipped particles may be pyramidal or conical. The bottom radial dimension of each serration of the serrated surface is 50nm-500nm, and the height is 50nm-500nm. The ratio of the bottom radial dimension of the serrated surface to the radial dimension of the top surface of the second type semiconductor 2111 is 1:5-1:100. The ratio of the height of each serration of the serrated surface to the radial dimension of the top surface of the second type semiconductor 2111 is 1:5-1:100. The first type semiconductor 2113, the second type semiconductor 2111, and the light-emitting layer 2112 together constitute the light-emitting body 211. The ratio of the height of each serration of the serrated surface to the height of the light-emitting body 211 is 1:3-1:30. The ratio of the bottom radial dimension of each serration of the serrated surface to the top radial dimension of each serration is 0.5:1-100:1.

[0268] In some embodiments, the second region on top of the second type semiconductor 2111 also has a certain degree of granularity. The second region on top of the second type semiconductor 2111 may be higher than the first region, meaning that the first and second regions may not be located on the same plane. As mentioned above, in some embodiments, the optical microstructures on top of the first and second regions may be composed of or include several spherical particles (which may be near-spherical particles, such as ellipsoids, etc.). The bottom ends of these spherical particles are connected to the top reference surface of the second type semiconductor 2111, and the diameter at the junction of the bottom end of the spherical particle and the top surface of the second type semiconductor 2111 is smaller than the maximum diameter of the spherical particle. That is, for a spherical particle, its bottom diameter is smaller, while the diameter at the middle position in the height direction is larger. These spherical particles maximize the light-emitting area. To achieve this structural feature, the present invention employs a dry etching process. This process is also compatible with the fabrication process of ultra-miniature light-emitting diode chips, achieving the desired effect.

[0269] It should be noted that, although Figure 8 and Figure 9 Although the second electrodes 44' and 4'' shown are not embedded in the substrate 1, Figure 8 and Figure 9 The structural features related to the light-emitting diode 21 can be combined with Figures 1A-7The embodiments shown are combined. That is, Figure 8 and Figure 9 The structural features related to the light-emitting diode 21 should be considered as... Figures 1A-7 As shown in the embodiments, for example, the present invention includes embodiments in which the embodiments simultaneously have the following features: Figure 8 and Figure 9 The top surface of the second type of semiconductor shown and Figures 1A-7 The second electrode 4 shown is embedded in the substrate 1 and other structures.

[0270] In this invention, the electrode of the micro light-emitting diode chip, which is conductively connected to the top semiconductor layer of the diode, is at least partially embedded in the substrate of the chip. This reduces the space occupied by the electrode between adjacent light-emitting diodes, and the gap between adjacent light-emitting diodes can be adaptively reduced, thereby reducing the overall size of the chip. This allows it to be matched with thinner and more portable electronic devices and adapt to more application scenarios.

[0271] The present invention also sets the top surface of the top semiconductor layer of the diode light-emitting body of the chip to be non-planar with uneven particle size, thereby increasing diffuse reflection and improving light extraction efficiency.

[0272] The present invention further adaptively thins a portion of the top semiconductor layer of the diode light-emitting body of the chip to improve the light extraction efficiency of the light-emitting layer below the thinned portion.

[0273] From the above, those skilled in the art will readily recognize that alternative structures to the structures disclosed in this invention can be used as feasible alternative implementations, and that the implementations disclosed in this invention can be combined to produce new implementations, which also fall within the scope of the appended claims.

Claims

1. A light-emitting diode chip (100), characterized in that, include: Substrate (1); Multiple light-emitting diodes (21) are arranged in an array on the substrate. Each light-emitting diode includes a first type semiconductor (2113), a light-emitting layer (2112), and a second type semiconductor (2111) stacked from bottom to top. The first electrode (3) is disposed on the substrate and positioned at the bottom of the light-emitting diode, and the first electrode and the first type of semiconductor (2113) are electrically connected. A second electrode (4) is disposed on the substrate and positioned between a pair of light-emitting diodes having a first adjacent relationship. The portion of the second electrode is electrically connected to the second type of semiconductor (2111). Wherein, a portion of the second electrode is at least partially embedded in the substrate (1), such that the bottom end of the portion of the second electrode is lower than the bottom end of the plurality of light-emitting diodes (21); The light-emitting diode chip also includes: Multiple microlenses (23), each microlens corresponding to a light-emitting diode; and A light-transmitting spacer (22) is disposed between the microlens and the light-emitting diode. The light-transmitting spacer has a gap (221) between two adjacent light-emitting diodes. The gap is a narrow slit with a closed top. The top of the gap (221) is higher than the light-emitting layer (2112) of the light-emitting diode, and the bottom of the gap (221) is lower than the light-emitting layer (2112) of the light-emitting diode.

2. The light-emitting diode chip according to claim 1, characterized in that, The second electrode (4) is disposed around each of the light-emitting diodes to form between the light-emitting diodes having a first adjacent relationship, and / or On a predetermined cross section taken from the plane containing the axis (X) of the light-emitting diode, the second electrode is formed as a trapezoidal cross section with radial dimensions gradually increasing or decreasing from bottom to top.

3. The light-emitting diode chip according to claim 2, characterized in that, Each of the light-emitting diodes forms a columnar structure with its radial dimension gradually decreasing from bottom to top, such that the cross-section of the light-emitting diode at the predetermined cross-section is also trapezoidal, wherein: The angle (α) between the lower base and the leg of the trapezoid is the same as the corresponding angle (β) of the trapezoidal cross-section of the second electrode; or The angle (α) between the lower base and the leg of the trapezoid is smaller than the corresponding angle (β) of the trapezoidal cross-section of the second electrode; or The angle (α) between the lower base and the waist of the trapezoid is greater than the corresponding angle (β) of the trapezoidal cross section of the second electrode.

4. The light-emitting diode chip according to claim 1, characterized in that, The top of the second electrode is lower than the bottom of the plurality of light-emitting diodes, and the distance between the top of the second electrode and the bottom of the plurality of light-emitting diodes is 10 nm-2 μm; or The top of the second electrode is flush with the bottom of the plurality of light-emitting diodes.

5. The light-emitting diode chip according to claim 1, characterized in that, The light-emitting diode (21) also includes: The bottom conductive layer (212) is located on the bottom side of the first type of semiconductor (2113). The bonding layer (213) located on the bottom side of the bottom conductive layer; and A top conductive layer (214) is at least partially coated on top of the second type semiconductor (2111). The first electrode is electrically connected via the bottom conductive layer, the bonding layer and the first type of semiconductor, and the second electrode is electrically connected via the top conductive layer and the second type of semiconductor.

6. The light-emitting diode chip according to claim 5, characterized in that, The second electrode is located below the top conductive layer (214), which extends from the top of the second type semiconductor (2111) to the top of the second electrode (4). Furthermore, the first type of semiconductor, the light-emitting layer, and the second type of semiconductor together constitute a light-emitting body (211). An insulating layer (215) is provided between the sidewall of the light-emitting body and the top conductive layer. The insulating layer extends from the top of the second type of semiconductor and terminates near the top of the second electrode without reaching the top of the second electrode, so as to allow the top conductive layer and the second electrode to be in direct contact.

7. The light-emitting diode chip according to claim 5, characterized in that, The bottom surface of the bonding layer is higher than the top surface of the second electrode, and the height difference is 10 nm-2 μm; or The bottom surface of the bonding layer is flush with the top surface of the second electrode.

8. The light-emitting diode chip according to any one of claims 1-7, characterized in that, The second electrode includes a first conductive layer (42) and a second conductive layer (41) on top of the first conductive layer, wherein the side surfaces of the first conductive layer and the second conductive layer are smoothly connected and transitioned, thereby giving the second electrode a smooth side surface; and / or A step is formed between the sidewalls of the first conductive layer and the second conductive layer of the electrode.

9. The light-emitting diode chip according to claim 8, characterized in that, The material of the second electrode is one or more of Cr, Pt, Au, Ti, Al, Ag, and Sn.

10. The light-emitting diode chip according to claim 8, characterized in that, The second conductive layer of the electrode is made of Cr or Ti, and the first conductive layer of the electrode is made of one or more of Cr, Pt, Au, Ti, Al, Ag, and Sn; and / or The thickness of the first conductive layer of the electrode is greater than the thickness of the second conductive layer of the electrode.

11. The light-emitting diode chip according to any one of claims 1-7, characterized in that, The first electrode (3) includes a top segment (31) and a bottom segment (32), at least one of the top segment and the bottom segment being formed as a columnar structure perpendicular to the substrate, the radial dimension of the top segment being smaller than the radial dimension of the bottom segment, and the second electrode (4) being located between the top segments (31) of adjacent first electrodes.

12. The light-emitting diode chip according to claim 11, characterized in that, The bottom surface of the top segment of the first electrode is flush with the bottom surface of the second electrode; and / or At least one of the top segment and the bottom segment gradually increases in radial dimension from bottom to top.

13. The light-emitting diode chip according to any one of claims 1-7, characterized in that, The second type of semiconductor (2111) includes a thinned region (2111b) whose thickness is less than that of other regions (2111a) of the second type of semiconductor.

14. The light-emitting diode chip according to claim 13, characterized in that, The thinning region is positioned at the top circumferential edge of the second type of semiconductor to surround the other regions; and / or The thinned region is constructed to have a thickness of zero.

15. The light-emitting diode chip according to claim 13, characterized in that, On a predetermined cross-section taken from the plane containing the axis (X) of the light-emitting diode, wherein, The tilt angle (γ) of the sidewalls of the other regions of the second type of semiconductor is consistent with the tilt angle (θ) of the sidewalls formed by the light-emitting layer and the first type of semiconductor; and / or The tilt angle (γ) of the sidewalls of the other regions of the second type of semiconductor is smaller than the tilt angle (θ) of the sidewalls formed by the light-emitting layer and the first type of semiconductor; and / or The tilt angle (γ) of the sidewalls of the other regions of the second type of semiconductor is greater than the tilt angle (θ) of the sidewalls formed by the light-emitting layer and the first type of semiconductor.

16. The light-emitting diode chip according to claim 13, characterized in that, The thinning region extends continuously along the circumferential direction (C).

17. The light-emitting diode chip according to claim 5, characterized in that, The interface between the first type of semiconductor and the bottom conductive layer is flat, and the interface between the bottom conductive layer and the bonding layer is flat.

18. The light-emitting diode chip according to claim 17, characterized in that, The roughness of the interface between the first type of semiconductor and the bottom conductive layer, and the interface between the bottom conductive layer and the bonding layer, are both less than 10 nm.

19. The light-emitting diode chip according to claim 5, characterized in that, There is a gap (24) between the pair of light-emitting diodes having a first adjacent relationship, and a portion of the second electrode (4) is partially located at the gap or directly below the gap. Furthermore, the bottom ends of the pair of light-emitting diodes having a second adjacent relationship are close together without any gap.

20. The light-emitting diode chip according to claim 19, characterized in that, The top conductive layer (214) includes at the interval (24): A horizontal section (2141) extending horizontally above the top surface of the substrate (1) to cover the top surface of the substrate; and The recessed contact section (2142) that is recessed relative to the top surface of the substrate (1) is configured as a columnar section that is coaxial with the second electrode (4) and has a radial dimension smaller than the radial dimension of the top surface of the second electrode. The horizontal section (2141) and the sunken contact section (2142) together form a rotationally symmetrical structure around the axis of the second electrode.

21. The light-emitting diode chip according to claim 19, characterized in that, The top conductive layer includes a horizontal segment extending in a horizontal direction at the interval to cover the top surface of the second electrode. The horizontal segment is directly connected to a segment of the top conductive layer (214) that covers the sidewall of the light-emitting diode. The horizontal segment is located above or below the top surface of the substrate.

22. The light-emitting diode chip according to claim 19, characterized in that, The top conductive layer (214) has an inverted truncated conical section (2144) between the pair of light-emitting diodes (21) having a second adjacent relationship, such that the bottom end of the inverted truncated conical section having a minimum radial dimension is connected to the substrate. Furthermore, the bottom end of the truncated cone section and the second electrode are separated by a dielectric material (14) of the substrate.

23. The light-emitting diode chip according to claim 19, characterized in that, The bonding layer or bottom conductive layer of a pair of light-emitting diodes having a second adjacent relationship at least partially blocks the second electrode between the pair of light-emitting diodes in the vertical direction.

24. The light-emitting diode chip according to claim 1, characterized in that, The top of the second type semiconductor (2111) is provided with a semiconductor interconnect layer (217) with a radial dimension smaller than the top surface of the second type semiconductor.

25. The light-emitting diode chip according to claim 24, characterized in that, The semiconductor interconnect layer is made of at least one of Au, Ge, Ni, Cr, Br, and Ti, wherein the content of Au is greater than or less than or equal to the content of Ge; and / or The semiconductor interconnect layer is made of a semi-transparent material; and / or The thickness of the semiconductor interconnect layer is 0.5nm-150nm.

26. The light-emitting diode chip according to claim 5, characterized in that, The thickness of the bottom conductive layer (212) is 1 / 20 to 2 times the thickness of the bonding layer; and / or The total thickness of the bottom conductive layer and the bonding layer (213) is 50nm-4000nm; and / or The thickness of the bottom conductive layer is less than 1000 nm; and / or The thickness of the bonding layer is 50nm-3000nm.

27. The light-emitting diode chip according to claim 5, characterized in that, The bonding layer includes a mirror layer on top of it, the mirror layer being made of pure silver, pure gold, a silver-copper alloy, or a gold-chromium alloy; or The mirror layer is made of gold and trace elements, with gold being the main component and the trace elements including at least one of chromium, titanium, and nickel.

28. The light-emitting diode chip according to any one of claims 1-7, characterized in that, The light-emitting diode chip is a miniature light-emitting diode chip that uses micron-sized LEDs as light-emitting diodes.

29. A light-emitting diode chip (100), characterized in that, include: Substrate (1); Multiple light-emitting diodes (21) are arranged in an array on the substrate. Each light-emitting diode includes a first type semiconductor (2113), a light-emitting layer (2112), and a second type semiconductor (2111) stacked from bottom to top. A first electrode (3) is disposed on the substrate and positioned at the bottom of the light-emitting diode. The first electrode and the first type semiconductor (2113) are electrically connected. The second electrode (4) is disposed on the substrate and positioned between a pair of light-emitting diodes having a second adjacent relationship; Multiple microlenses (23), each microlens corresponding to a light-emitting diode; as well as A light-transmitting spacer (22) is disposed between the microlens and the light-emitting diode. The light-transmitting spacer has a gap (221) between two adjacent light-emitting diodes. The gap is a narrow slit with a closed top. The top of the gap (221) is higher than the light-emitting layer (2112) of the light-emitting diode, and the bottom of the gap (221) is lower than the light-emitting layer (2112) of the light-emitting diode. In this embodiment, a portion of the second electrode is embedded in the substrate (1), such that the bottom end of the portion of the second electrode is lower than the bottom end of the plurality of light-emitting diodes (21), and the portion of the second electrode and the light-emitting diodes are separated by a dielectric material of the substrate.

30. The light-emitting diode chip according to claim 29, characterized in that, The bottom ends of the pair of light-emitting diodes having a second adjacent relationship are close together without any gap.

31. The light-emitting diode chip according to claim 29, characterized in that, Another portion of the second electrode is disposed on the substrate and positioned between a pair of light-emitting diodes having a first adjacent relationship. The other portion of the second electrode is electrically connected to the second type semiconductor (2111). The other portion of the second electrode is at least partially embedded in the substrate (1), such that the bottom end of the other portion of the second electrode is lower than the bottom end of the plurality of light-emitting diodes (21).

32. The light-emitting diode chip according to any one of claims 29-31, characterized in that, The light-emitting diode chip is a miniature light-emitting diode chip that uses micron-sized LEDs as light-emitting diodes.

33. A light-emitting diode chip (100), characterized in that, include: Substrate (1); Multiple light-emitting diodes (21) are arranged in an array on the substrate. Each light-emitting diode includes a first type semiconductor (2113), a light-emitting layer (2112), and a second type semiconductor (2111) stacked from bottom to top. The top surface of the second type of semiconductor includes a first region (2111c), which is configured as a non-planar region with optical microstructures. The top surface of the second type semiconductor further includes a second region, on which a semiconductor interconnect layer (217) is disposed. The top surface of the semiconductor interconnect layer is planar. The light-emitting diode includes a top conductive layer (214) covering only the second region on the top surface of the second type semiconductor. The semiconductor interconnect layer (217) is configured to electrically connect the second type semiconductor (2111) and the top conductive layer (214).

34. The light-emitting diode chip according to claim 33, characterized in that, For each of the aforementioned light-emitting diodes, the first regions (2111c) on the top surface of the second type of semiconductor are interconnected and surround the unique second region, and / or The second region is located near the edge of the top surface of the second type of semiconductor; and / or The first region is in direct contact with the dielectric material; And / or The second region is located at the edge of the top surface of the second type of semiconductor; and / or The area of ​​the second region is less than 1 / 2 of the area of ​​the top surface of the second type of semiconductor.

35. The light-emitting diode chip according to claim 33, characterized in that, The top surface of the second type of semiconductor also includes a third region that is different from the first region and the second region.

36. The light-emitting diode chip according to any one of claims 33-35, characterized in that, The non-planar surface is a surface with uneven particles.

37. The light-emitting diode chip according to claim 36, characterized in that, The surface with uneven particles is a serrated surface.

38. The light-emitting diode chip according to claim 37, characterized in that, Each tooth of the serrated surface is formed as a spherical particle or a particle with a sharp tip; and / or The bottom radial dimension of each tooth of the serrated surface is 50nm-500nm, and the height is 50nm-500nm; and / or The ratio of the bottom radial dimension of each tooth to the top radial dimension of each tooth on the serrated surface is 0.5:1-100:1; and / or The ratio of the bottom radial dimension of each tooth of the serrated surface to the radial dimension of the top surface of the second type of semiconductor is 1:5-1:100; and / or The ratio of the height of each serration on the serrated surface to the radial dimension of the top surface of the second type of semiconductor is 1:5-1:100; and / or The first type of semiconductor, the second type of semiconductor, and the light-emitting layer together constitute the light-emitting body, and the ratio of the height of each serration of the serrated surface to the height of the light-emitting body is 1:3-1:

30.

39. The light-emitting diode chip according to claim 36, characterized in that, The uneven particles include spherical particles, wherein the diameter at the junction of the bottom end and the top surface of the spherical particles is smaller than the maximum diameter of the spherical particles.

40. The light-emitting diode chip according to any one of claims 33-35, characterized in that, The light-emitting diode chip (100) includes: A first electrode (3) is disposed on the substrate and positioned at the bottom of each of the light-emitting diodes, and the first electrode is electrically connected to the first type of semiconductor (2113); and A second electrode (4) is disposed on the substrate and positioned between a pair of light-emitting diodes having a first adjacent relationship. The portion of the second electrode is electrically connected to the second type of semiconductor (2111). In this embodiment, a portion of the second electrode is at least partially embedded in the substrate (1), such that the bottom end of the portion of the second electrode is lower than the bottom end of the plurality of light-emitting diodes.

41. The light-emitting diode chip according to claim 40, characterized in that, The second electrode (4) is disposed around each of the light-emitting diodes, thereby forming between the light-emitting diodes having a first adjacent arrangement; and / or On a predetermined cross section taken from the plane containing the axis (X) of the light-emitting diode, the second electrode is formed as a trapezoidal cross section with radial dimensions gradually increasing or decreasing from bottom to top.

42. The light-emitting diode chip according to claim 41, characterized in that, Each of the light-emitting diodes forms a columnar structure with its radial dimension gradually decreasing from bottom to top, such that the cross-section of the light-emitting diode is also trapezoidal, wherein: The angle (α) between the lower base and the leg of the trapezoid is the same as the corresponding angle of the trapezoidal cross-section of the second electrode; or The angle (α) between the lower base and the leg of the trapezoid is smaller than the corresponding angle (β) of the trapezoidal cross-section of the second electrode; or The angle (α) between the lower base and the waist of the trapezoid is greater than the corresponding angle (β) of the trapezoidal cross section of the second electrode.

43. The light-emitting diode chip according to claim 40, characterized in that, The top of the second electrode is lower than the bottom of the plurality of light-emitting diodes, and the distance between the top of the second electrode and the bottom of the plurality of light-emitting diodes is 10 nm-2 μm; or The top of the second electrode is flush with the bottom of the plurality of light-emitting diodes.

44. The light-emitting diode chip according to claim 40, characterized in that, The light-emitting diode (21) also includes: The bottom conductive layer (212) is located on the bottom side of the first type of semiconductor (2113). Bonding layer (213) located on the bottom side of the bottom conductive layer; A top conductive layer (214) is at least partially coated on top of the second type semiconductor (2111). The first electrode is electrically connected via the bottom conductive layer, the bonding layer and the first type of semiconductor, and the second electrode is electrically connected via the top conductive layer and the second type of semiconductor.

45. The light-emitting diode chip according to claim 44, characterized in that, The second electrode is located below the top conductive layer (214), which extends from the top of the second type semiconductor (2111) to the top of the second electrode (4). Furthermore, the first type of semiconductor, the light-emitting layer, and the second type of semiconductor together constitute a light-emitting body (211). An insulating layer (215) is provided between the sidewall of the light-emitting body and the top conductive layer. The insulating layer extends from the top of the light-emitting body and terminates near the top of the second electrode without reaching the top of the second electrode, so as to allow the top conductive layer and the second electrode to contact.

46. ​​The light-emitting diode chip according to claim 44, characterized in that, The bottom surface of the bonding layer is higher than the top surface of the second electrode, and the height difference is 10 nm-2 μm; or The bottom surface of the bonding layer is flush with the top surface of the second electrode.

47. The light-emitting diode chip according to claim 40, characterized in that, The second electrode includes a first conductive layer (42) and a second conductive layer (41) on top of the first conductive layer, wherein the side surfaces of the first conductive layer and the second conductive layer are smoothly connected and transitioned, thereby giving the second electrode a smooth side surface; and / or A step is formed between the sidewalls of the first conductive layer and the second conductive layer of the electrode.

48. The light-emitting diode chip according to claim 47, characterized in that, The material of the second electrode is one or more of Cr, Pt, Au, Ti, Al, Ag, and Sn.

49. The light-emitting diode chip according to claim 47, characterized in that, The second conductive layer of the electrode is made of Cr or Ti, and the first conductive layer of the electrode is made of one or more of Cr, Pt, Au, Ti, Al, Ag, and Sn; and / or The thickness of the first conductive layer of the electrode is greater than the thickness of the second conductive layer of the electrode.

50. The light-emitting diode chip according to claim 40, characterized in that, The first electrode (3) includes a top segment (31) and a bottom segment (32), at least one of the top segment and the bottom segment being formed as a columnar structure perpendicular to the substrate, the radial dimension of the top segment being smaller than the radial dimension of the bottom segment, and the second electrode being located between the top segments (31) of adjacent first electrodes.

51. The light-emitting diode chip according to claim 50, characterized in that, The bottom surface of the top segment of the first electrode is flush with the bottom surface of the second electrode; and / or At least one of the top segment and the bottom segment gradually increases in radial dimension from bottom to top.

52. The light-emitting diode chip according to claim 38, characterized in that, The second type of semiconductor (2111) includes a thinned region (2111b) with a thickness less than that of other regions (2111a) of the second type of semiconductor.

53. The light-emitting diode chip according to claim 52, characterized in that, The thinning region is positioned at the top circumferential edge of the second type of semiconductor to surround the other regions; and / or The thinned region is constructed to have a thickness of zero.

54. The light-emitting diode chip according to claim 52, characterized in that, On a predetermined cross-section taken from the plane containing the axis (X) of the light-emitting diode, wherein, The tilt angle (γ) of the sidewalls of the other regions (2111a) of the second type of semiconductor is consistent with the tilt angle (θ) of the sidewalls formed by the light-emitting layer and the first type of semiconductor; and / or The tilt angle (γ) of the sidewalls of the other regions of the second type of semiconductor is smaller than the tilt angle (θ) of the sidewalls formed by the light-emitting layer and the first type of semiconductor; and / or The tilt angle (γ) of the sidewalls of the other regions of the second type of semiconductor is greater than the tilt angle (θ) of the sidewalls formed by the light-emitting layer and the first type of semiconductor.

55. The light-emitting diode chip according to claim 52, characterized in that, The thinning region extends continuously along the circumferential direction (C).

56. The light-emitting diode chip according to claim 44, characterized in that, The interface between the first type of semiconductor and the bottom conductive layer is flat, and the interface between the bottom conductive layer and the bonding layer is flat.

57. The light-emitting diode chip according to claim 56, characterized in that, The roughness of the interface between the first type of semiconductor and the bottom conductive layer, and the interface between the bottom conductive layer and the bonding layer, are both less than 10 nm.

58. The light-emitting diode chip according to claim 40, characterized in that, There is a gap (24) between the pairs of light-emitting diodes having a first adjacent relationship, and a portion of the second electrode (4) is located at or directly below the gap. Furthermore, the bottom ends of the light-emitting diodes having a second adjacent relationship are adjacent to each other without any gap.

59. The light-emitting diode chip according to claim 58, characterized in that, The top conductive layer (214) includes at the interval (24): A horizontal section (2141) extending horizontally above the top surface of the substrate (1) to cover the top surface of the substrate; and The recessed contact section (2142) that is recessed relative to the top surface of the substrate (1) is configured as a columnar section that is coaxial with the second electrode (4) and has a radial dimension smaller than the radial dimension of the top surface of the second electrode. The horizontal section (2141) and the sunken contact section (2142) together form a rotationally symmetrical structure around the axis of the second electrode.

60. The light-emitting diode chip according to claim 58, characterized in that, The top conductive layer (214) has an inverted truncated conical section (2144) between the light-emitting diodes (21) having a second adjacent relationship, such that the bottom end of the inverted truncated conical section having a minimum radial dimension is connected to the substrate. Furthermore, the bottom end of the truncated cone section and another part of the second electrode are separated by a dielectric material (14) of the substrate.

61. The light-emitting diode chip according to claim 58, characterized in that, The bonding layer or bottom conductive layer of a pair of light-emitting diodes having a second adjacent relationship at least partially blocks the second electrode between the pair of light-emitting diodes in the vertical direction.

62. The light-emitting diode chip according to claim 33, characterized in that, The top of the second type semiconductor (2111) is provided with a semiconductor interconnect layer (217) with a radial dimension smaller than the top surface of the second type semiconductor.

63. The light-emitting diode chip according to claim 62, characterized in that, The semiconductor interconnect layer is made of at least one of Au, Ge, Ni, Cr, Br, and Ti, wherein the content of Au is greater than, less than, or equal to the content of Ge; and / or The semiconductor interconnect layer is made of a semi-transparent material; and / or The thickness of the semiconductor interconnect layer is 0.5nm-150nm.

64. The light-emitting diode chip according to claim 44, characterized in that, The thickness of the bottom conductive layer (212) is 1 / 20 to 2 times the thickness of the bonding layer; and / or The total thickness of the bottom conductive layer and the bonding layer (213) is 50nm-4000nm; and / or The thickness of the bottom conductive layer is less than 1000 nm; and / or The thickness of the bonding layer is 50nm-3000nm.

65. The light-emitting diode chip according to claim 44, characterized in that, The bonding layer includes a mirror layer on top of it, the mirror layer being made of pure silver, pure gold, a silver-copper alloy, or a gold-chromium alloy; or The mirror layer is made of gold and trace elements, with gold being the main component and the trace elements including at least one of chromium, titanium, and nickel.

66. The light-emitting diode chip according to claim 58, characterized in that, The top conductive layer (214) includes a horizontal section at the interval (24) extending in a horizontal direction to cover the top surface of the second electrode. The horizontal section is directly connected to a section of the top conductive layer (214) that covers the sidewall of the light-emitting diode. The horizontal section is located above or below the top surface of the substrate.

67. The light-emitting diode chip according to any one of claims 33-35, characterized in that, The light-emitting diode chip is a miniature light-emitting diode chip that uses micron-sized LEDs as light-emitting diodes.

68. The light-emitting diode chip according to claim 33, characterized in that, Also includes: Multiple microlenses (23), each microlens corresponding to a light-emitting diode; A light-transmitting spacer (22) is disposed between the microlens and the light-emitting diode. The light-transmitting spacer has a gap (221) between two adjacent light-emitting diodes. The gap is a narrow slit with a closed top. The top of the gap (221) is higher than the light-emitting layer (2112) of the light-emitting diode, and the bottom of the gap (221) is lower than the light-emitting layer (2112) of the light-emitting diode.

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