A method for eliminating interference of a camera on a Beidou positioning and navigation signal

Abstract

This invention relates to the field of power communication technology, and in particular to a method for eliminating interference from cameras to BeiDou positioning and navigation signals. The method includes the following steps: detecting the frequency relationship between the MIPI interface clock signal of the camera in a power supply service recorder and the BeiDou navigation signal, determining the degree of overlap between the clock signal after frequency multiplication and the BeiDou frequency point, and identifying the characteristics of the interference source; based on the characteristics of the interference source, transferring the generation location of the clock signal from the external main control chip to the inside of the camera module, obtaining an oscillator circuit design scheme; cutting off the original external clock trace according to the oscillator circuit design scheme, switching the camera's clock input to the internal oscillator supply, and collecting the internal clock radiation from the internal oscillator; and setting a metal shield around the camera module to form an electromagnetic shielding space to counteract the internal clock radiation. This invention can effectively identify and suppress interference from cameras to BeiDou positioning and navigation signals.

Description

Technical Field

[0001] This invention relates to the field of power communication technology, and in particular to a method for eliminating interference from cameras on BeiDou positioning and navigation signals. Background Technology

[0002] In the design of miniaturized electronic devices (such as power supply service recorders), camera modules and BeiDou positioning and navigation modules often need to be integrated within a limited space. Due to the need for product miniaturization, the camera and positioning antenna are usually placed on the top of the device, very close to each other. In existing technology, because the frequency of the clock signal in the camera's MIPI interface signal, after frequency multiplication, is close to the frequency of satellite navigation, when the camera is working, the clock signal will affect the satellite navigation signal in the transmission space. Specifically, this manifests as a decrease in satellite signal strength, longer positioning time, or failure to locate. However, in the design of recorders and other products with miniaturization requirements, the spatial distance between the camera and positioning antenna cannot often be solved by structural design, and the camera and positioning antenna are usually required to be placed on the top of the device, so traditional solutions are often difficult to implement or have limited effectiveness. Summary of the Invention

[0003] Therefore, it is necessary for the present invention to provide a method for eliminating the interference of cameras on BeiDou positioning and navigation signals, so as to solve at least one of the above-mentioned technical problems.

[0004] To achieve the above objective, a method for eliminating interference from cameras on BeiDou positioning and navigation signals includes the following steps:

[0005] Step S1: Detect the frequency relationship between the MIPI interface clock signal of the camera in the power supply service recorder and the Beidou navigation signal, determine the degree of overlap between the clock signal after frequency multiplication and the Beidou frequency point, and identify the characteristics of the interference source;

[0006] Step S2: Based on the characteristics of the interference source, the generation location of the clock signal is transferred from the external main control chip to the inside of the camera module to obtain the oscillator circuit design scheme.

[0007] Step S3: According to the oscillator circuit design, cut off the original external clock line, switch the camera's clock input to the internal oscillator supply, and collect the internal clock radiation from the internal oscillator.

[0008] Step S4: To address the internal clock radiation, a metal shielding cover is installed around the camera module to form an electromagnetic shielding space;

[0009] Step S5: Measure the BeiDou positioning signal strength and positioning time under electromagnetic shielding to verify the effectiveness of eliminating external clock signal interference and confirm that the system is working normally.

[0010] This invention accurately identifies harmonic components that may interfere with the BeiDou L1 band by measuring the fundamental frequency and harmonic spectrum of the MIPI interface clock signal, providing a basis for subsequent oscillator design. By transferring the external clock signal to the inside of the camera module and designing the crystal oscillator and its peripheral circuitry based on interference characteristics, not only is direct radiation interference from the external clock eliminated, but the stability and purity of the clock signal are also ensured through load capacitors, decoupling capacitors, and low-pass filter circuits, ensuring normal camera operation while reducing high-order harmonic radiation. By setting a metal shielding cover for the camera module and combining it with precise grounding spring connections, not only is internal clock radiation shielded, but a stable electromagnetic shielding space is also formed, allowing the BeiDou receiver to obtain higher signal strength and signal-to-noise ratio in a shielded environment. By actually measuring the L1 band signal strength after shielding and comparing the positioning time with the data before the improvement, the interference suppression effect and the improvement in positioning efficiency can be quantitatively verified. During the overall implementation, the signal recovery rate of the Beidou positioning module after shielding reached more than 90% of the benchmark value, and the initial positioning time was reduced by more than 70%. At the same time, the camera image output remained normal, indicating that the camera interference was effectively eliminated. The system's positioning accuracy and response speed were significantly improved, ensuring the reliability and stability of the navigation system in complex electromagnetic environments. This provides a feasible signal interference protection solution for power service recorders and similar equipment in practical applications. Attached Figure Description

[0011] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0012] Figure 1 This is a flowchart illustrating the steps of the method for eliminating interference from cameras to BeiDou positioning and navigation signals according to the present invention.

[0013] Figure 2 This is a comparative diagram of the architecture of the method for eliminating interference from cameras to BeiDou positioning and navigation signals according to the present invention;

[0014] Figure 3 This is a partial top view of a PCB according to an embodiment of the present invention. Detailed Implementation

[0015] The technical method of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0016] Furthermore, the accompanying drawings are merely illustrative of the invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor methods and / or microcontroller methods.

[0017] It should be understood that although the terms "first," "second," etc., may be used herein to describe various units, these units should not be limited by these terms. These terms are used merely to distinguish one unit from another. For example, without departing from the scope of the exemplary embodiments, a first unit may be referred to as a second unit, and similarly, a second unit may be referred to as a first unit. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0018] To achieve the above objectives, please refer to Figures 1 to 3 This invention provides a method for eliminating interference from cameras on BeiDou positioning and navigation signals, the method comprising the following steps:

[0019] Step S1: Detect the frequency relationship between the MIPI interface clock signal of the camera in the power supply service recorder and the Beidou navigation signal, determine the degree of overlap between the clock signal after frequency multiplication and the Beidou frequency point, and identify the characteristics of the interference source;

[0020] Further, step S1 includes:

[0021] With the camera on, measure the fundamental frequency of the MIPI interface clock signal, calculate the frequency values ​​of each harmonic, and generate a harmonic spectrum list.

[0022] In one embodiment, the camera is activated under normal power supply recorder conditions, causing the MIPI interface to enter image data transmission state. At this time, a spectrum analyzer or high-bandwidth oscilloscope can be connected to the MIPI clock pin of the camera module to obtain its output clock waveform, and the fundamental frequency of the clock signal can be directly measured using Fourier transform or a spectrum analyzer. In one embodiment, the fundamental frequency of the MIPI clock is measured to be 192MHz, which is the reference value for subsequent harmonic calculations. A series of harmonic frequency values, fi, are obtained through frequency multiplication. n= n × f0 (where f0 is the fundamental frequency and n is the harmonic order). Continuing with the above example, if the fundamental frequency is 192MHz, then its second harmonic is 384MHz, its third harmonic is 576MHz, and so on. For easy comparison, harmonic frequencies within a certain range (e.g., up to 2GHz and above) need to be listed in a table to form a harmonic spectrum list. While generating the harmonic spectrum list, the amplitude values ​​of each harmonic displayed on the spectrum analyzer also need to be recorded to establish a "frequency-amplitude" correspondence.

[0023] Each frequency in the harmonic spectrum list is compared with the BeiDou L1 band. When the nth harmonic frequency falls into the passband of the BeiDou receiver, the harmonic is marked as an interference source.

[0024] In one embodiment, the generated harmonic spectrum list is compared with the BeiDou system L1 band (center frequency 1575.42MHz, typical receiver passband ±2MHz). If a harmonic frequency is found to fall within this passband range, it can be determined that it will interfere with the BeiDou receiver.

[0025] In the above embodiment, 192MHz×8=1536MHz, 192MHz×9=1728MHz, where the 8th harmonic is only 39MHz away from the center frequency of Beidou L1 and is not within the passband; however, if the fundamental frequency is slightly offset (e.g., 193.4MHz), the frequency of its 8th harmonic is 1547.2MHz, which may overlap with the edge of the receiver passband, thus becoming a potential source of interference.

[0026] Record the harmonic order, harmonic frequency value, and amplitude value of the harmonics marked as interference sources to form interference source characteristics.

[0027] In one embodiment, when a harmonic is identified as an interference source, its key information needs to be saved, including the harmonic order n, the actual measured frequency value, and the amplitude value (usually expressed in dBm or dBμV).

[0028] In the above embodiment, if the frequency of the 8th harmonic is measured to be 1547.2MHz and the amplitude is -45dBm, then "n=8, frequency 1547.2MHz, amplitude -45dBm" is recorded in the interference source characteristic table.

[0029] Step S2: Based on the characteristics of the interference source, the generation location of the clock signal is transferred from the external main control chip to the inside of the camera module to obtain the oscillator circuit design scheme.

[0030] Further, step S2 includes the following steps:

[0031] Step S21: Determine the oscillator device model based on the characteristics of the interference source, and determine the device layout reference point based on the remaining space on the camera module PCB board;

[0032] In one embodiment, the fundamental frequency marked as the interference source in the interference source characteristics is read as the target frequency f0. Combined with the nominal clock requirements of the camera module (voltage, drive method, jitter, and stability), a crystal oscillator model with a matching output frequency and frequency stability better than ±50ppm is selected from the parts library. Simultaneously, constraints are placed on the supply voltage (e.g., 1.8V / 2.8V / 3.3V), package (e.g., 2.0×1.6mm / 2.5×2.0mm), and operating temperature range. Subsequently, the remaining available space on the camera module PCB (including device height and surrounding clearance areas) is measured. Using this as a constraint, the shortest connection point is searched near the clock input pin (CLK_IN) of the MIPI processor, and the center coordinates of its pads are used as the device layout reference point.

[0033] In the above embodiment, the target frequency given by the interference source characteristics is 24.000MHz. A crystal resonator + on-chip inverting amplifier scheme with a 24MHz, ±20ppm, 1.8V power supply and 2.0×1.6mm package is selected. After measurement, the 3.2mm×2.4mm empty area on the left side of the MIPI processor CLK_IN meets the requirements of the device and vias, and this is determined as the layout reference point.

[0034] Step S22: Starting from the device layout reference point, design the shortest trace path from the crystal oscillator output signal to the MIPI processor clock input pin, and measure the trace length;

[0035] In one embodiment, starting from the layout reference point, the shortest single-ended path from the crystal oscillator output (XOUT) to the MIPI processor CLK_IN is planned: prioritizing straight runs on the same layer, minimizing or eliminating vias, and laying a reference ground plane throughout the path to avoid parallel, close-range, long-distance coupling with the MIPI-PHY differential data lines (a spacing of ≥10 mil can be maintained and isolated with ground copper). The trace width is locked in ECAD to meet the target impedance / current requirements (MCLK is typically a single-ended CMOS, so the recommended trace width for the device is sufficient). After completion, the CAD automatically marks the actual trace length L and exports a routing report for subsequent parasitic parameter evaluation.

[0036] In the above embodiment, a direct connection on the same layer is adopted, and after avoiding two vias, a single layer trace of 11.8mm can still be maintained. The entire trace has a continuous ground plane above it. Near the end, a series resistor is added near the pin for reserved space (not installed) to perform micro-damping compensation if necessary.

[0037] Step S23: Calculate the required load capacitance value for the crystal oscillator based on the trace length and the input capacitance specification of the MIPI processor;

[0038] In one embodiment, the input capacitance of the MIPI processor clock input pin (given in the datasheet) is read. The parasitic capacitance of this trace is measured using an LCR meter at the target operating frequency (the measuring fixture is short and fixture error is deducted). The nominal load capacitance is then consulted from the crystal resonator datasheet. The equivalent value of the external capacitor is calculated according to specifications as 2 × (nominal load capacitance - input capacitance - parasitic capacitance). The value closest to the nominal external capacitance from the E12 series is selected as the external equivalent value. Since this scheme uses a symmetrical series connection of two capacitors with the midpoint grounded, to ensure the series equivalent is equal to the external capacitance, each series capacitor is valued at twice the external capacitance.

[0039] Step S24: Design the peripheral circuit of the crystal oscillator according to the load capacitance value, including the load capacitance, decoupling capacitor and power supply filter circuit;

[0040] In one embodiment, a symmetrical load capacitor circuit is constructed based on the external capacitor value: a 30pF capacitor is connected in series at each of the two crystal pins, and the midpoint of the two capacitors is connected to the ground plane through a via (multiple vias are recommended, placed close to the midpoint), forming a symmetrical grounding structure with the shortest return path; for power integrity, a 100μF tantalum capacitor is placed at the oscillator / driver power input for main decoupling, and a 0.1μF ceramic capacitor is placed near the chip power pin for high-frequency decoupling; when the power supply line is introduced into this branch, a 10Ω ferrite bead (selected according to the nominal impedance of 100MHz) is connected in series, and a 10μF capacitor is connected in parallel to the rear end of the ferrite bead to ground to form a low-pass filter. The ferrite bead and the decoupling capacitor are placed as close as possible to the device power pin. During layout, ensure that: the crystal loop area is minimized, the traces are as short as possible, the midpoint grounding via is connected to the ground plane with low inductance; the crystal is isolated from high swing / high speed differential lines (MIPIHS), and ground copper is used for shielding isolation where necessary.

[0041] In the above embodiment, 30pF×2 C0G / NP0 dielectric capacitors are used as series capacitors, and dual vias are placed at the midpoint to ground; a 100μF tantalum is placed at the VDD terminal entrance, and a 0.1μF is placed within 0.8mm of the chip pin; a 600Ω@100MHz equivalent ferrite bead (DC resistance <0.2Ω) is connected in series at the power supply branch entrance, and a 10μF is connected in parallel to ground after the ferrite bead. The actual measured loop is only 6.5mm×4.0mm.

[0042] Step S25: Verify whether the timing parameters of the output signal of the peripheral circuit meet the requirements of the MIPI interface, and integrate the verified circuit parameters to form an oscillator circuit design scheme.

[0043] In one embodiment, after assembly, the actual output frequency after applying the load capacitor is measured using a spectrum analyzer / frequency counter, and the deviation is compared with the nominal value to confirm that it is ≤ ±50ppm. The ripple voltage at the VDD pin of the device is measured using an oscilloscope, and the ripple is confirmed to be <50mV at the actual working frame rate / resolution. The high-order harmonic suppression at the output terminal is observed using a spectrum analyzer, verifying that the third harmonic attenuation is >20dB. Simultaneously, the duty cycle (45–55%) and rise / fall time of the clock waveform are checked to ensure they meet the input timing requirements of the MIPI processor (refer to the processor manual thresholds). After connecting the camera, the stable video link output is confirmed without frame drops / screen distortion. The verified actual values ​​of the load capacitor, decoupling configuration, and power supply filtering parameters, along with the wiring length, device coordinates, and test records, are then solidified into the final version of the oscillator circuit design scheme.

[0044] In the above embodiment, the measured frequency was 24.000026MHz (+1.1ppm), VDD ripple was 21mV (pp), tri-harmonic rejection was 27dB, duty cycle was 49.2%, and the camera ran stably for 2 hours at 1080p@30fps without any abnormalities. Based on this, the mass production parameters were archived and marked.

[0045] It should be noted that:

[0046] (1) The “10Ω” in “10Ω ferrite bead” refers to the nominal value of AC impedance (usually nominally 100MHz), not DC resistance; the selection of the device should be based on the impedance curve of the target interference frequency band.

[0047] (2) When there is no accurate value for the E12 series, after taking the nearest value, be sure to retest the frequency deviation and jitter; if the frequency deviation is critical, the parasitic capacitance can be compensated by fine-tuning the series capacitor or shortening / optimizing the circuit.

[0048] (3) If a shield is subsequently installed in step S4, the crystal circuit and the midpoint via should be connected to the grounding network of the shield with equipotential and low inductance to avoid introducing new parasitic resonances.

[0049] Further, step S21 includes the following steps:

[0050] Read the characteristics of the interference source and extract the fundamental frequency value marked as the interference source as the target frequency;

[0051] In one embodiment, the interference source characteristic table obtained in the previous steps is invoked. This table contains harmonic orders, frequency values, and amplitude values. Entries marked as interference sources are located within this table, and the fundamental frequency of these entries is extracted as the target frequency for design reference. The reason for this is that harmonic interference essentially originates from the fundamental frequency signal, and the output frequency of the crystal oscillator should be locked to this fundamental frequency to replace the original oscillation source and prevent harmonics from falling into sensitive frequency bands.

[0052] In the above embodiment, the interference source characteristic table shows that the 8th harmonic (1547.2MHz) falls within the passband of the Beidou L1 receiver, with an amplitude of -45dBm. The corresponding fundamental frequency is 193.4MHz, therefore the target frequency is determined to be 193.4MHz.

[0053] Select crystal oscillator models with output frequency matching and frequency stability better than ±50ppm based on the target frequency.

[0054] In one embodiment, after determining the target frequency, it is necessary to screen for crystal oscillator models that match that frequency from a component database or supplier directory. Simultaneously, their frequency stability should be checked, requiring a value better than ±50ppm to ensure that the output clock does not drift into interference-sensitive areas due to temperature or power supply changes. During the screening process, parameters such as power supply voltage range (e.g., 1.8V / 2.8V / 3.3V), drive capability, and operating temperature rating should also be considered.

[0055] In the above embodiment, for the target frequency of 193.4MHz, a certain type of CMOS output crystal oscillator was selected, with a voltage of 1.8V, a stability of ±25ppm, and a temperature range of -40℃ to +85℃.

[0056] The remaining space dimensions of the power supply service recorder camera module PCB board are measured, and the space dimensions are used as constraints to match the package dimensions of the selected crystal oscillators.

[0057] In one embodiment, the available space dimensions of the camera module's clock area are measured using PCB design tools or directly on a physical prototype, typically including length, width, and height limitations. The measured available dimensions are then compared to the package dimensions of a shortlisted crystal oscillator model. If a device package exceeds the available space, it must be rejected to avoid affecting the installation of other components or shielding.

[0058] In the above embodiment, the remaining space on the side of the camera module PCB closest to the MIPI processor is measured to be 3.5mm × 2.5mm, with a height not exceeding 1.2mm. The selected crystal oscillator model has a package size of 2.5mm × 2.0mm and a height of 0.9mm, which fully meets the installation constraints.

[0059] After determining the crystal oscillator model that meets the space constraints, locate the mounting position on the camera module PCB that is closest to the MIPI processor clock input pin, and record the coordinates of this position as the device layout reference point.

[0060] In one embodiment, the optimal solution is selected from the remaining qualified models, and the location on the PCB closest to the MIPI processor clock input pin is found as the mounting point. This location can be determined using the "Component Positioning" function in PCBCAD software or by calculating the Manhattan distance of the trace. The coordinates of this location are recorded as the starting reference point for subsequent routing and peripheral circuit design.

[0061] In the above embodiment, the coordinates of the MIPI processor clock input pin were measured in Altium Designer as (x = 45.3 mm, y = 28.7 mm). The Manhattan distance between this pin and the oscillator landing point was only 1.1 mm. Therefore, this landing point was determined as the device layout reference point.

[0062] It should be noted that the target frequency is not necessarily exactly the same as the interference frequency; it originates from the fundamental frequency corresponding to the interference harmonics. Therefore, in actual circuits, a standard frequency point (such as 192MHz instead of 193.4MHz) may need to be selected, and the harmonic impact should be reduced through system design. Spatial dimension measurements must consider subsequent shielding, filtering components, heat sinks, and other structural components, avoiding focusing solely on planar space while ignoring height limitations.

[0063] Of particular importance, step S23 includes:

[0064] Obtain the input capacitance value of the clock input pin in the MIPI processor;

[0065] In one embodiment, before designing the oscillator peripheral circuitry, it is necessary to consult the MIPI processor's hardware datasheet or design manual to obtain the input capacitance value of its clock input pin. This capacitance value is typically specified in the datasheet as "Input Capacitance (C)". in The value is indicated by "(" or "Clock Pin Capacitance")", and is generally between 2pF and 8pF. If the datasheet does not provide a specific value, it can be extracted through simulation using the IBIS / SPICE model provided by the component manufacturer.

[0066] In the above embodiment, according to the datasheet of a certain MIPI processor model, the input capacitance value of the clock input pin is 5pF.

[0067] The parasitic capacitance formed by the trace path on the PCB is measured using an LCR meter at the oscillator operating frequency.

[0068] In one embodiment, parasitic capacitance inevitably forms on the PCB along the trace from the clock output to the processor input. This parasitic capacitance can be measured by disconnecting the oscillator output on the PCB prototype and then measuring the trace path to ground using a precision LCR meter. The measurement frequency should be as close as possible to the oscillator operating frequency (e.g., 192MHz) to ensure accurate readings.

[0069] In the above embodiment, the parasitic capacitance of the oscillator output trace to the processor input pin was measured to be 1.5pF on the PCB prototype.

[0070] Find the nominal load capacitance of the crystal oscillator;

[0071] In one embodiment, crystal oscillator manufacturers typically provide recommended load capacitance values ​​(C) in their product specifications. l This is the design parameter for a crystal oscillator to oscillate stably and ensure frequency accuracy. The nominal load capacitance of different models of crystal oscillators is usually 12pF, 16pF, or 18pF.

[0072] In the above embodiment, the nominal load capacitance of the selected crystal oscillator is 16pF, as specified in the datasheet.

[0073] The external capacitance value is calculated as 2 × (nominal load capacitance - input capacitance value - parasitic capacitance value);

[0074] In one embodiment, given the input capacitance, parasitic capacitance, and nominal load capacitance, the required external capacitance value can be calculated using a formula. This formula is derived from the symmetrical configuration of the equivalent circuits at both ends of the crystal resonator, and the calculated capacitance value represents the size of the capacitance that needs to be connected in parallel at each end.

[0075] In the above embodiment, given a nominal load capacitance of 16pF, an input capacitance of 5pF, and a parasitic capacitance of 1.5pF, then: external capacitance value = 2 × (16 - 5 - 1.5) = 2 × 9.5 = 19pF.

[0076] Select the capacitance value from the E12 series capacitors that is closest to the external capacitor value as the load capacitance value required for the crystal oscillator.

[0077] In one embodiment, since the actual capacitance value must be from a standard series (such as E12 or E24 series), it is necessary to select the capacitance value closest to the calculated value from the available capacitors. More precise matching can be achieved by connecting capacitors in parallel or series if necessary.

[0078] In the above embodiment, the calculated value was 19pF, but this value is not available in the E12 series; the closest values ​​are 18pF or 20pF. Based on component inventory, 18pF was ultimately selected as the external load capacitor in the actual design.

[0079] It should be noted that due to differences in PCB manufacturing processes, parasitic capacitance values ​​may deviate from theoretical estimates. It is recommended to use calculated values ​​during the design phase and then adjust the capacitance values ​​appropriately during the prototype stage through frequency testing. External load capacitance typically consists of two identical capacitors, each connected from the crystal to ground; therefore, two equivalent capacitors should be listed in the BOM.

[0080] Further, step S24 includes the following steps:

[0081] The load capacitance is decomposed into two series capacitors of equal value, each with a capacitance twice that of the load capacitance.

[0082] In one embodiment, based on the equivalent relationship of crystal load capacitance, when an equivalent capacitor is connected to ground at each end of the crystal, its equivalent series capacitance is: To obtain the target external load capacitance C ext Each capacitor should be set to a value of 2C. ext During implementation, two capacitors of equal value should be included in the BOM (preferably C0G / NP0 dielectric to achieve low temperature drift and low dissipation factor).

[0083] In the above embodiments, after the above calculations, C is obtained. ext =15pF. Then each capacitor should be 30pF (E12 nominal), and the two capacitors of equal value should be connected to the two pins of the crystal respectively.

[0084] On the camera module PCB, a series capacitor is placed at each of the two crystal oscillator pins of the crystal oscillator. The midpoint of the connection between the two capacitors is connected to the ground plane through a via, forming a symmetrical load capacitor circuit.

[0085] In one embodiment, during layout, the two capacitors are placed as close as possible to the crystal pins (preferably ≤1mm), and the trace lengths and via numbers on both sides are kept symmetrical to reduce loop area and unbalanced coupling. The connection midpoint of the two capacitors is directly grounded to the ground plane through multiple vias (≥2 recommended, placed nearby) to reduce grounding inductance; the midpoint is isolated from any high-speed differential line (MIPIHS), and ground copper is used for shielding where necessary.

[0086] In the above embodiment, two 30pF / 0402 / C0G transistors are placed close to the X1 and X2 pins of the crystal, respectively, with a connection length of 0.8mm / 0.8mm, which is symmetrical; a double via is arranged at the midpoint and falls directly to the GND plane, with a copper thickness of ≥1oz from the via to the ground plane, and a loop size of approximately 6.2mm×3.8mm.

[0087] In the power supply terminal of the symmetrical load capacitor circuit, a tantalum capacitor with a capacitance of 100 microfarads is selected as the main decoupling capacitor, and a ceramic capacitor with a capacitance of 0.1 microfarads is placed at the power supply pin of the crystal oscillator as the high-frequency decoupling capacitor to obtain the decoupling capacitor circuit.

[0088] In one embodiment, to reduce low-frequency and mid-to-high-frequency ripple at the oscillator / inverter power supply terminals, a two-stage decoupling is implemented near the device on the power supply branch: ① A 100μF tantalum capacitor (with a withstand voltage ≥ rated voltage × 2) is placed near the power supply branch inlet or near the device to suppress low-frequency drops and transients; ② A 0.1μF / 0402 / ceramic capacitor (X7R or better, preferably multiple capacitors in parallel with varying differential values) is placed as close as possible (≤1mm) to the oscillator power supply pins to reduce high-frequency impedance. The pads are also connected to the ground plane using multiple vias to reduce ESL.

[0089] In the above embodiment, a 100μF tantalum / 6.3V capacitor is placed at the 1.8V power supply branch input; a 0.1μF / 0402 capacitor is placed 0.7mm from the VDD pin edge of the oscillator, and its ground terminal is connected to the ground plane via two vias; the measured ripple upon power-on (camera operating state) is <25mV. p―p .

[0090] Starting from the power input terminal of the decoupling capacitor circuit, a 10-ohm ferrite bead is connected in series on the power supply line, and a 10-microfarad capacitor is connected in parallel to ground after the ferrite bead to form a low-pass filter circuit.

[0091] In one embodiment, when the clock branch is drawn from the main power supply line, a ferrite bead with a nominal impedance of 10Ω (@100MHz) is connected in series to improve the impedance to mid-to-high frequency noise and harmonics. A 10μF / ceramic capacitor is connected in parallel to ground at the rear end of the ferrite bead, forming a first-order low-pass filter. The ferrite bead should be located close to the branch bifurcation point, and the 10μF capacitor should be on the same side as the ferrite bead and grounded nearby, ensuring the shortest return path is closed. When selecting a ferrite bead, pay attention to its DC resistance (DCR) and rated current to avoid voltage drop and saturation.

[0092] In the above embodiment, a 600Ω@100MHz equivalent curve and a DCR of 0.15Ω ferrite bead are used, and a 10μF / 0603 / X5R is connected after the ferrite bead; this combination has a significant suppression of noise in the 100MHz–1GHz range, and with the aforementioned decoupling, the VDD high-frequency noise is reduced by about 10–15dB.

[0093] The symmetrical load capacitor circuit, decoupling capacitor circuit, and low-pass filter circuit are arranged on the PCB with the shortest possible interconnection traces and minimal mutual interference to form the peripheral circuit of the crystal oscillator.

[0094] In one embodiment, the "symmetrical load capacitor circuit, decoupling capacitor circuit, and low-pass filter circuit" are arranged as a whole according to the principles of signal priority and shortest return current: the small loop of crystal-capacitor-midpoint grounding is centered; the power supply enters this branch from the main line via the ferrite bead, first encountering a 10μF, then a 100μF tantalum and a 0.1μF near-end decoupling, and finally reaching the oscillator VDD; all intersections with MIPI differential lines are orthogonally crossed or isolated with ground copper, maintaining a spacing of ≥10mil; long coupling segments parallel and close to the camera traces are avoided. After completion, the assembly space of the via ground loop and shield (if any) is verified using 3D / EM view, and the assembly drawing and coordinate file are output.

[0095] In the above embodiment, the final trace is 11.8mm long from the oscillator output to MIPI CLK_IN, running straight in a single layer; the power branch is connected to a ferrite bead 1.2mm after the main line, with a 10μF amplifier 0.6mm after the bead, and then runs along the line for 2.3mm to the device VDD; after completing the DRC and EMI pre-checks, the prototype's measured third harmonic suppression is >20dB, and the camera link works stably.

[0096] It should be noted that:

[0097] The term "series capacitor" refers to a classic load network where each capacitor is connected to ground at both ends, and their values ​​are added together to form an equivalent series connection to the crystal; therefore, "each capacitor = 2 × C". ext The calculation premise is that the two capacitors have equal values ​​and the midpoint is grounded with low inductance.

[0098] It is recommended to select C0G / NP0 load capacitor to avoid frequency deviation caused by capacitor drift under bias voltage and temperature changes in X7R; if space is limited, a second choice can be made, but the frequency difference needs to be retested and the value finely adjusted during the prototype stage.

[0099] "10Ω ferrite bead" refers to the nominal AC impedance (usually nominally 100MHz), not the DC resistance; the specific selection should be based on the impedance curve of the target interference frequency band.

[0100] If a shield is subsequently added, it is necessary to ensure that the midpoint grounding and the shield grounding are on the same low-impedance grounding grid to avoid introducing parasitic resonance; and to reserve creepage / assembly gaps for the shield to avoid affecting the position of the above-mentioned components and the landing of vias.

[0101] Of particular importance is that the timing parameters of the peripheral circuit are verified in step S25 as follows:

[0102] After measuring the applied load capacitance, the deviation between the actual output frequency and the nominal frequency of the crystal oscillator was confirmed to be within 50 parts per million.

[0103] In one embodiment, the installed prototype is powered on under normal operating conditions (e.g., the camera is on and continuously transmitting video), and the frequency value f at the oscillator output is directly measured using a frequency meter or a spectrum analyzer + frequency meter mode. meas (It is recommended to use a frequency meter with a time reference accuracy better than 1 ppm to reduce measurement error.) Compare with the nominal frequency f nom Compared with the measured frequency f meas Calculate the deviation Δf = f meas -f nom And convert to ppm: Deviation (ppm) = (Δf / f nom )×10 6 If the absolute value of the deviation is ≤50ppm, then it passes.

[0104] In the above embodiments, the nominal f nom =24000000Hz; measured f meas =24000800Hz; then Δf = 800Hz; the calculation process is 800 ÷ 24000000 = 0.0000333333……, multiplied by 10 6 The result is 33.3333 ppm, therefore 33.33 ppm < 50 ppm, which meets the requirements. During measurement, the measuring instrument model, time reference source, ambient temperature, and power supply voltage should be recorded for traceability.

[0105] Verify the filtering effect of the decoupling capacitor circuit, measure the ripple voltage of the oscillator power supply pin, and confirm that it is less than fifty millivolts;

[0106] In one embodiment, the ripple voltage on the oscillator's VDD pin is measured using an oscilloscope. An oscilloscope with appropriate bandwidth (≥100MHz) and a low-inductance measurement probe (such as a probe with a grounding spring or a differential probe) are recommended to reduce loop noise introduced by the probe. During measurement, the voltage waveform is acquired over a stable period under camera operating load (typical frame rate / resolution), and the peak-to-peak value (pp) is recorded. For greater accuracy, an FFT can be performed on the acquired time-domain waveform to distinguish between switching noise and power frequency noise. A pass is considered achieved if the VDD peak-to-peak ripple is <50mV.

[0107] In the above embodiment, the VDD ripple was measured to be 21mV using an oscilloscope (with a differential probe) while the prototype was in operation. p―p The measurement report should meet the <50mV requirement and include information such as oscilloscope probe type, bandwidth setting, time base, and sampling rate.

[0108] The effect of the low-pass filter circuit on suppressing higher harmonics of the clock signal was tested, and it was confirmed that the attenuation of the third harmonic was greater than 20 decibels.

[0109] In one embodiment, a spectrum analyzer is used to set the measurement point at the crystal oscillator output or at a radiation measurement point near the camera module housing (or a near-field probe if evaluating radiation). The center frequency is set as the fundamental frequency, and the scanning bandwidth covers at least three times the fundamental frequency (to include the third harmonic) or measures point-by-point at the corresponding frequency. The power P1 (dBm) at the fundamental frequency and the power P3 (dBm) at the third harmonic are recorded, and the attenuation Δ (dB) = P1 - P3 is calculated. If Δ ≥ 20dB, the requirement is met. During measurement, care is taken to select an appropriate RBW / VBW (e.g., RBW 100kHz, VBW ≥ RBW is a common starting point), and the measurement connection and probe position are recorded.

[0110] In the above embodiment, the power of the fundamental frequency P1 = -3dBm and the power of the third harmonic P3 = -30dBm are measured on the spectrum analyzer. Then the attenuation Δ = (-3) - (-30) = 27dB, which meets the requirement of >20dB.

[0111] The actual values ​​of the load capacitor, the configuration of the decoupling capacitor, and the parameters of the filter circuit that meet the above conditions are recorded as the final output of the oscillator circuit design scheme.

[0112] In one embodiment, after all three verifications above are passed, the actual nominal values ​​of the two load capacitors to be used (e.g., 30pF per end), the list of decoupling devices (e.g., specific packages and placement coordinates of 100μF tantalum and 0.1μF ceramic), the filter devices (magnetic bead model, rated AC impedance and placement position), the trace length and device layout coordinates, and all measurement records (frequency measurement table, ripple sampling file, spectrum scan screenshot, test environment and test equipment list) are summarized into an oscillator circuit design scheme.

[0113] In another embodiment, if any one of the following is not met, please first check: the actual value and selection of the load capacitance, the layout of the decoupling / filtering device, the actual frequency characteristics of the ferrite bead and the ground loop impedance. If necessary, correct it by fine-tuning the load capacitance or optimizing the decoupling / filtering layout, then retest and record the modification history.

[0114] It is important to note that sources of measurement error (instrument time base error, probe capacitive load, grounding loop) can affect the results. It is recommended to use calibrated equipment and record the instrument uncertainty. Frequency deviation should be assessed considering the instrument's inherent ppm error. When measuring ripple, a probe grounding loop significantly increases low-frequency false noise; differential probes or the shortest grounding spring should be used to minimize this error. Third harmonic suppression measurements performed in a near-field environment (using a probe to measure the outer casing surface) will be affected by the probe coupling position; multiple measurements are recommended, and the worst value should be used as a conservative assessment.

[0115] Step S3: According to the oscillator circuit design, cut off the original external clock line, switch the camera's clock input to the internal oscillator supply, and collect the internal clock radiation from the internal oscillator.

[0116] Further, step S3 includes:

[0117] Identify the PCB traces between the clock output pin of the main control chip and the clock input pin of the camera's MIPI interface on the motherboard of the power supply service recorder.

[0118] In one embodiment, when locating the PCB trace between the clock output pin of the main control chip and the clock input pin of the camera MIPI interface on the motherboard of the power supply service recorder, the corresponding net name (e.g., CLK_CAM or MCLK) is first searched in PCBCAD (such as Altium) to obtain the precise coordinates of the starting and ending components and the trace path. If the CAD information is incomplete, a multimeter in continuity mode, an oscilloscope, or a logic probe is used on the prototype to probe point by point from the clock output pin of the main control chip to the camera connector (confirming the presence and direction of the signal at each pin / via), and the oscilloscope is used to confirm that the trace outputs a stable square wave / clock waveform when the camera is turned on.

[0119] In the above embodiment, the main controller U1.PA7 (clock output) was located in Altium and connected to the camera socket J2.P5 (CLK_IN). The CAD showed that the trace passed through 3 vias and a 0.3mm wide trace. On the prototype, a square wave of 24.000MHz was observed at J2.P5 with an oscilloscope, confirming that the target trace was correct.

[0120] Measure the path along the PCB traces to determine the cut point as the location closest to and easiest to operate the camera interface, and record the coordinates of the cut point.

[0121] In one embodiment, when measuring the PCB trace path and determining the cut point, the geometric path and relative coordinates of the entire trace should be marked in CAD. A location close to the camera interface and easily accessible for maintenance should be selected as the cut point based on a physical prototype (avoiding multiple dense traces, via clusters, and ground plane cracks). Simultaneously, the distance from the cut point to the camera connector should be as short as possible to facilitate subsequent internal oscillator connection. After selecting the location, the PCB coordinates (e.g., in mm) of that point should be exported from CAD and verified on the prototype using a distance measuring tool or micrometer ruler. These coordinates should then be recorded as the cut point coordinates.

[0122] In the above embodiment, the CAD showed that there was an exposed trace that could be operated 4.6mm outward from J2.P5. The point (x=45.3mm, y=28.7mm) was selected as the cut-off point and recorded in the work order.

[0123] The copper foil of the original external clock trace is physically cut at the cut point coordinates, with a cut width of not less than 0.5 mm.

[0124] In one embodiment, when physically cutting the copper foil of the original external clock trace at the cutting point, an appropriate process (such as a PCB-specific engraving cutter / micro-milling machine, a Dremel precision milling head, or using a needle knife under a microscope to separate the copper foil) is used to remove the copper foil, ensuring that the cut width is not less than 0.5 mm (to prevent residual copper from causing short circuits or connections through thin layers). After cutting, the cut is checked under a microscope to ensure it is completely severed, and the trace is confirmed to be open (infinite impedance / no waveform) using a multimeter in resistance mode or an oscilloscope. If necessary, the solder and copper plating layer should be removed at the cutting point, and the surface should be cleaned with a cleaning agent to avoid minor conductive residues.

[0125] In the above embodiment, a 0.8 mm wide copper foil was milled off at a selected point using a micro-milling cutter and then cleaned. Under a microscope, it was confirmed that there was no residual copper on the fracture surface. An open circuit was measured using a multimeter, and the image and test results were recorded.

[0126] Furthermore, step S3 also includes:

[0127] Read the output frequency parameters of the oscillator circuit design scheme, measure the actual installed internal oscillator output frequency, and the deviation is within 50 parts per million to pass the verification.

[0128] In one embodiment, when reading the output frequency parameters of the oscillator circuit design and measuring the output frequency of the actually installed internal oscillator, the center frequency f at the oscillator output should be measured using a frequency counter with a time reference or a spectrum / frequency counter after the internal oscillator is installed and powered on (under normal power supply and operating temperature). meas Record the accuracy of the measuring equipment and its time reference. The measured f... meas With the design nominal frequency f nom Compare and calculate the deviation ppm = (f meas -f nom ) / f nom ×10 6 If the absolute value of the deviation is ≤50ppm, the measurement is considered passed; otherwise, the load capacitance needs to be adjusted or the component selection corrected before retesting. Measurements should be performed under the camera's operating load conditions to reflect the true working state.

[0129] In the above embodiments, the nominal design f nom =24.000000MHz, measured f meas =24.000800MHz, deviation =33.3ppm (<50ppm), record the instrument model and measurement time.

[0130] Connect the verified internal clock signal to the camera. After confirming that the video output is normal, use a spectrum analyzer to measure around the camera module. Set the center frequency to the Beidou L1 band and record the radiated power spectral density in that band.

[0131] In one embodiment, after physically connecting the verified internal clock signal to the camera and confirming normal video output, the radiated power spectral density (PSD) within the BeiDou L1 band (center 1575.42MHz) should be measured around the camera module using a spectrum analyzer with a near-field probe or a calibrated antenna. The center frequency should be set to 1575.42MHz, a suitable scanning bandwidth (at least ±5MHz or according to receiver passband requirements), RBW / VBW (e.g., RBW 100kHz), and the measurement distance (5mm from the housing at the near-field probe or far-field measurement using an antenna at the specified distance). The power spectrum curve within this band should be acquired and saved (units dBm or dBμV / m; if using an antenna, antenna calibration is required to obtain the absolute field strength). The same measurement conditions should be maintained before and after connection for comparison. Video output confirmation items include: clear image, no dropped frames, frame rate and resolution meeting expectations and remaining stable (it is recommended to observe continuously for at least 1–2 minutes or run a standard test sequence).

[0132] In the above embodiment, when the camera is running at 1080p@30, the maximum spectral line in the L1 band is measured to be -72dBm at a distance of 5mm from the shield using a near-field probe, and the spectrum screenshot is saved.

[0133] Harmonic components related to the measured output frequency of the internal oscillator are identified from the radiated power spectral density, and the frequency and amplitude values ​​of the harmonics are recorded as internal clock radiation.

[0134] In one embodiment, when identifying harmonic components related to the measured output frequency of the internal oscillator from the recorded radiated power spectral density, the harmonic index n ≈ round(f) that may fall into the L1 region is first calculated using mathematical methods. L1 / f meas Then, find the peak value near the corresponding frequency point on the spectrum (or measure the power at that nth harmonic point point by point on the spectrum analyzer); record each identified harmonic as "harmonic number n, harmonic frequency f". n (Hz), amplitude value A n (dBm or dBμV / m)”, and archive these values ​​as “Internal Clock Radiation” output entries for reference in subsequent shielding / filtering designs. If no significant peaks related to the oscillator are found in the spectrum (below the criterion threshold or below the reference noise), “No L1 band harmonics related to the internal oscillator detected” should also be recorded and the original data saved.

[0135] In the above embodiments, f meas=24.0008MHz, then n = round(1575.42 / 24.0008) = 66, calculate f 66 =24.0008×66=1584.05MHz; no significant peak was observed at this point on the spectrum (<-85dBm), but no peak caused by the oscillator was observed near 1575.42MHz either, which was recorded as "no L1 band harmonics".

[0136] Step S4: To address the internal clock radiation, a metal shielding cover is installed around the camera module to form an electromagnetic shielding space;

[0137] Further, step S4 includes the following steps:

[0138] Step S41: Calculate the interference intensity of each harmonic component on the BeiDou L1 band based on the frequency and amplitude values ​​of the internal clock radiation.

[0139] In one embodiment, based on the frequency and amplitude of the internal clock radiation, harmonic components falling into or near the BeiDou L1 (1575.42MHz) band are first identified, and then their interference intensity is calculated using the power superposition formula. For example, if the 66th harmonic appears at 1575.4MHz and has an amplitude of -70dBm, it can be directly regarded as the interference power to the L1 band.

[0140] In the above embodiment, the measured amplitude of the internal oscillator harmonics near L1 is -68dBm, and the recorded interference intensity is -68dBm.

[0141] Step S42: Determine the required shielding effectiveness of not less than 40 decibels based on the interference intensity, and select a copper alloy material with a thickness of not less than 0.2 mm as the shielding material accordingly, and output the material specifications.

[0142] In one embodiment, based on the calculated interference intensity, the design requires a shielding effectiveness of no less than 40dB. To ensure sufficient attenuation, a copper alloy with a thickness ≥0.2mm is selected as the shielding material, and its specifications are output (e.g., CuSn6, thickness 0.25mm).

[0143] In the above embodiment, if it is required to reduce the interference from -68dBm to below -108dBm, a 40dB attenuation is needed, and a copper-tin alloy plate with a thickness of 0.25mm is selected.

[0144] Step S43: Measure the maximum external dimensions of the camera module, including the internal oscillator circuit, based on the material specifications. Leave a 1 mm gap in each of the length, width, and height directions, and calculate the internal space dimensions required for the shielding cover.

[0145] In one embodiment, the external dimensions of the camera module, including the internal oscillator circuit, are measured, with a 1mm margin added in each of the length, width, and height directions, to calculate the internal space of the shielding cover.

[0146] In the above embodiment, the module is 22mm long, 18mm wide, and 5mm high, so the internal space of the shielding cover is designed to be 23×19×6mm.

[0147] Step S44: Design the shielding structure based on the internal space dimensions, including the dimensions of the base plate, the height of the side walls, and the dimensions of the top cover. Make corresponding rectangular openings on the base plate according to the camera interface positions to obtain the shielding structure design drawing.

[0148] In one embodiment, a shielding structure is designed according to the internal space dimensions, including a base plate, four side walls and a top cover, and a rectangular opening is designed on the base plate according to the location of the camera interface to ensure that the ribbon cable or socket can pass through.

[0149] In the above embodiment, the base plate is designed to be 23×19mm, the side wall height is 6mm, and a 5×2mm rectangular hole is opened on the left edge for the MIPI interface to be brought out.

[0150] Step S45: Based on the opening positions in the shielding cover structural design drawing, set a copper grounding spring with a width of three millimeters at the edge of each opening. The overlap length between the spring and the edge of the opening is not less than one millimeter, thus obtaining the processed shielding cover.

[0151] In one embodiment, a 3mm wide copper grounding spring is arranged at the edge of the opening to ensure that it has an overlap length of ≥1mm with the edge of the opening, so as to ensure reliable grounding.

[0152] In the above embodiment, 3mm wide copper springs are arranged around the MIPI interface opening, with each spring overlapping the edge of the opening by 1.5mm.

[0153] Furthermore, step S4 also includes the following steps:

[0154] Step S46: Install the processed shielding cover onto the camera module, use conductive silver paste to firmly fix the grounding spring to the ground plane of the camera module PCB, and record the installation position coordinates;

[0155] In one embodiment, a shielding cover is placed over the camera module, each grounding spring is fixed to the PCB ground plane with conductive silver paste, and the installation position coordinates are recorded in the CAD coordinate system.

[0156] In the above embodiment, after the shielding cover is installed, the coordinates of the four grounding points are recorded as (x1, y1)...(x4, y4).

[0157] Step S47: Measure the DC resistance between each grounding spring and the ground plane of the camera module based on the installation location coordinates. When the resistance value at all measurement points is less than 0.1 ohms, the electrical connection is confirmed to be qualified, and the resistance measurement data table is output.

[0158] In one embodiment, a milliohm meter is used to measure the DC resistance from each grounding spring to the PCB ground plane. If all resistances are less than 0.1Ω, the connection is deemed qualified, and a resistance table is output.

[0159] In the above embodiment, the resistances at the four measuring points are 0.02, 0.03, 0.05, and 0.04 Ω, respectively, all of which meet the requirements.

[0160] Step S48: Using the qualified connection points confirmed by the resistance measurement data sheet, use a near-field probe to measure the radiation intensity of the Beidou L1 band at a distance of 5 mm from the outer surface of the shield. Compare the measured value with the recorded internal clock radiation amplitude value to calculate the actual shielding effectiveness value.

[0161] In one embodiment, the radiation intensity of the L1 band is measured at a distance of 5 mm from the outer surface of the shield using a near-field probe, and compared with the original internal harmonic amplitude value to calculate the shielding effectiveness (difference).

[0162] In the above embodiment, the original radiation was -68dBm, and after shielding it was measured to be -112dBm, so the shielding effectiveness was 44dB.

[0163] Step S49: When the actual shielding effectiveness reaches 40 decibels or more, confirm that the electromagnetic shielding space has been formed.

[0164] In the above embodiment, the measured value was 44dB > 40dB, and the verification was successful.

[0165] Step S5: Measure the BeiDou positioning signal strength and positioning time under electromagnetic shielding to verify the effectiveness of eliminating external clock signal interference and confirm that the system is working normally.

[0166] Further, step S5 includes:

[0167] With the power supply service recorder powered on, the camera and Beidou positioning module are activated simultaneously to measure the L1 band signal strength under electromagnetic shielding space and record the signal strength value as the signal strength after shielding.

[0168] In one embodiment, while the power supply recorder is powered on, the camera and the BeiDou positioning module are simultaneously activated. A spectrum analyzer or the built-in receiver is used to measure the L1 band signal strength after the camera is shielded, and the value is recorded. For example, after the shielding is installed, the measured L1 signal power is -90dBm, which is taken as the signal strength after shielding.

[0169] It should be noted that during measurement, the BeiDou module should be under the same antenna and environmental conditions to avoid external signal fluctuations affecting the results.

[0170] The interference suppression effect is confirmed to be up to standard when the signal strength after shielding is compared with the reference carrier-to-noise ratio measured before the camera is turned on in step S1.

[0171] In one embodiment, the signal strength after shielding is compared with the reference carrier-to-noise ratio (C / N0) measured before the camera is turned on in step S1, and the recovery percentage is calculated. For example, if the reference carrier-to-noise ratio is 45 dB-Hz and the measured value after shielding is 42 dB-Hz, the recovery rate is approximately 93%, confirming that the interference suppression effect meets the standard. The recovery rate calculation should use the same units and measurement time window to avoid misjudgment due to transient fluctuations.

[0172] It should be noted that during measurement, the BeiDou module should be under the same antenna and environmental conditions to avoid external signal fluctuations affecting the results.

[0173] Under the condition that the interference suppression effect meets the standard, the Beidou positioning system is started to conduct the first positioning test, and the time interval from the start of positioning to obtaining effective location information is recorded as the improved positioning time.

[0174] In one embodiment, after confirming that the interference suppression effect meets the standard, the BeiDou positioning system is activated for the first positioning test, and the time interval from the start of positioning to obtaining effective location information (positioning solution) is recorded. For example, if effective coordinates are obtained 12 seconds after the positioning is activated, the improved positioning time is 12 seconds.

[0175] By comparing the improved positioning time with the pre-acquired positioning time, when the positioning time is reduced by more than 70% and the camera image output is normal, it is confirmed that the interference of the camera on the BeiDou positioning and navigation signal has been eliminated.

[0176] In one embodiment, the improved positioning time is compared with the pre-acquired positioning time before the improvement. When the positioning time is reduced by ≥70% and the camera image output is normal, it is confirmed that the interference of the camera on the BeiDou positioning signal has been eliminated. For example, the positioning time before the improvement was 40 seconds, and after the improvement it is 12 seconds, a reduction of about 70%. The image output is normal, verifying that the interference has been eliminated.

[0177] It should be noted that confirming normal image output includes not only displaying the image, but also ensuring that the image has no dropped frames, no color abnormalities, or no interface communication abnormalities.

[0178] See Figure 2 , Figure 2 The original design is on the left. Figure 2 The right side shows the improved design of this invention.

[0179] See Figure 3 This diagram details the cutting operation of the external clock trace on the motherboard of the power service recorder, clearly indicating the key technical parameters and location information of the cutting operation. As shown, the microcontroller chip on the green PCB substrate is connected to the USB connector on the right side via a yellow trace. During the trace cutting operation in step S3, a precise cut must be made at a distance of 4.6mm from the USB connector, clearly marked with a red X symbol. The cutting operation requires a complete gap of 0.8mm in width to ensure the original clock signal transmission path is completely broken. The enlarged detail in the lower right corner further illustrates the microstructure of the cutting point. The cutting gap must completely penetrate the copper foil layer of the PCB trace, and the cutting width should be strictly controlled within the range of 0.8mm ± 0.1mm to prevent signal leakage or short circuits caused by residual copper foil. The blue dashed line represents the connection path of the internal oscillator in subsequent steps. This new trace will replace the cut external clock trace, realizing the architectural transformation from an external clock source to an internal clock source. By comparing the layout differences between the original trace (yellow solid line) and the new trace (blue dashed line), the technical essence of clock signal path reconstruction in this invention can be clearly understood. like Figure 3 As indicated by the dimensions, the 4.6mm cut position ensures sufficient operating space while maximizing the integrity of the wiring near the camera interface, thus reserving reasonable wiring space for the subsequent installation and connection of the internal oscillator.

[0180] Therefore, the embodiments should be considered as exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of the equivalents of the application be incorporated into the invention.

[0181] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features of the invention herein.

Claims

1. A method for eliminating interference from cameras on BeiDou positioning and navigation signals, characterized in that, When applied to a power supply service recorder, the following steps are included: Step S1: Detect the frequency relationship between the MIPI interface clock signal of the camera in the power supply service recorder and the Beidou navigation signal, determine the degree of overlap between the clock signal after frequency multiplication and the Beidou frequency point, and identify the characteristics of the interference source; Step S2: Based on the characteristics of the interference source, the generation location of the clock signal is transferred from the external main control chip to the inside of the camera module, resulting in the oscillator circuit design scheme. Step S2 specifically involves: Step S21: Determine the oscillator device model based on the characteristics of the interference source, and determine the device layout reference point based on the remaining space on the camera module PCB board; Step S22: Starting from the device layout reference point, design the shortest trace path from the crystal oscillator output signal to the MIPI processor clock input pin, and measure the trace length; Step S23: Calculate the required load capacitance value for the crystal oscillator based on the trace length and the input capacitance specification of the MIPI processor; Step S24: Design the peripheral circuit of the crystal oscillator according to the load capacitance value, including the load capacitance, decoupling capacitor and power supply filter circuit; Step S25: Verify whether the timing parameters of the output signal of the peripheral circuit meet the requirements of the MIPI interface, and integrate the verified circuit parameters to form an oscillator circuit design scheme; Step S3: According to the oscillator circuit design, cut off the original external clock line, switch the camera's clock input to the internal oscillator supply, and collect the internal clock radiation from the internal oscillator. Step S4: To address the internal clock radiation, a metal shielding cover is installed around the camera module to form an electromagnetic shielding space; Step S5: Measure the BeiDou positioning signal strength and positioning time under electromagnetic shielding to verify the effectiveness of eliminating external clock signal interference and confirm that the system is working normally.

2. The method for eliminating interference from cameras to BeiDou positioning and navigation signals according to claim 1, characterized in that, Step S1 includes: With the camera on, measure the fundamental frequency of the MIPI interface clock signal, calculate the frequency values ​​of each harmonic, and generate a harmonic spectrum list. Each frequency in the harmonic spectrum list is compared with the BeiDou L1 band. When the nth harmonic frequency falls into the passband of the BeiDou receiver, the harmonic is marked as an interference source. Record the harmonic order, harmonic frequency value, and amplitude value of the harmonics marked as interference sources to form interference source characteristics.

3. The method for eliminating interference from cameras to BeiDou positioning and navigation signals according to claim 2, characterized in that, Step S21 includes the following steps: Read the characteristics of the interference source and extract the fundamental frequency value marked as the interference source as the target frequency; Select crystal oscillator models with output frequency matching and frequency stability better than ±50ppm based on the target frequency. The remaining space dimensions of the power supply service recorder camera module PCB board are measured, and the space dimensions are used as constraints to match the package dimensions of the selected crystal oscillators. After determining the crystal oscillator model that meets the space constraints, locate the mounting position on the camera module PCB that is closest to the MIPI processor clock input pin, and record the coordinates of this position as the device layout reference point.

4. The method for eliminating interference from cameras to BeiDou positioning and navigation signals according to claim 3, characterized in that, Step S24 includes the following steps: The load capacitance is decomposed into two series capacitors of equal value, each with a capacitance twice that of the load capacitance. On the camera module PCB, a series capacitor is placed at each of the two crystal oscillator pins of the crystal oscillator. The midpoint of the connection between the two capacitors is connected to the ground plane through a via, forming a symmetrical load capacitor circuit. In the power supply terminal of the symmetrical load capacitor circuit, a tantalum capacitor with a capacitance of 100 microfarads is selected as the main decoupling capacitor, and a ceramic capacitor with a capacitance of 0.1 microfarads is placed at the power supply pin of the crystal oscillator as the high-frequency decoupling capacitor to obtain the decoupling capacitor circuit. Starting from the power input terminal of the decoupling capacitor circuit, a 10-ohm ferrite bead is connected in series on the power supply line, and a 10-microfarad capacitor is connected in parallel to ground after the ferrite bead to form a low-pass filter circuit. The symmetrical load capacitor circuit, decoupling capacitor circuit, and low-pass filter circuit are arranged on the PCB with the shortest possible interconnection traces and minimal mutual interference to form the peripheral circuit of the crystal oscillator.

5. The method for eliminating interference from cameras to BeiDou positioning and navigation signals according to claim 4, characterized in that, Step S3 includes: Identify the PCB traces between the clock output pin of the main control chip and the clock input pin of the camera's MIPI interface on the motherboard of the power supply service recorder. Measure the path along the PCB traces to determine the cut point as the location closest to and easiest to operate the camera interface, and record the coordinates of the cut point. The copper foil of the original external clock trace is physically cut at the cut point coordinates, with a cut width of not less than 0.5 mm.

6. The method for eliminating interference from cameras to BeiDou positioning and navigation signals according to claim 5, characterized in that, Step S3 also includes: Read the output frequency parameters of the oscillator circuit design scheme, measure the actual installed internal oscillator output frequency, and the deviation is within 50 parts per million to pass the verification. Connect the verified internal clock signal to the camera. After confirming that the video output is normal, use a spectrum analyzer to measure around the camera module. Set the center frequency to the Beidou L1 band and record the radiated power spectral density in that band. Harmonic components related to the measured output frequency of the internal oscillator are identified from the radiated power spectral density, and the frequency and amplitude values ​​of the harmonics are recorded as internal clock radiation.

7. The method for eliminating interference from cameras to BeiDou positioning and navigation signals according to claim 6, characterized in that, Step S4 includes the following steps: Step S41: Calculate the interference intensity of each harmonic component on the BeiDou L1 band based on the frequency and amplitude values ​​radiated by the internal clock. Step S42: Determine the required shielding effectiveness of not less than 40 decibels based on the interference intensity, and select a copper alloy material with a thickness of not less than 0.2 mm as the shielding material accordingly, and output the material specifications. Step S43: Measure the maximum external dimensions of the camera module, including the internal oscillator circuit, based on the material specifications. Leave a 1 mm gap in each of the length, width, and height directions, and calculate the internal space dimensions required for the shielding cover. Step S44: Design the shielding structure based on the internal space dimensions, including the dimensions of the base plate, the height of the side walls, and the dimensions of the top cover. Make corresponding rectangular openings on the base plate according to the camera interface positions to obtain the shielding structure design drawing. Step S45: Based on the opening positions in the shielding cover structural design drawing, set a copper grounding spring with a width of three millimeters at the edge of each opening. The overlap length between the spring and the edge of the opening is not less than one millimeter, thus obtaining the processed shielding cover.

8. The method for eliminating interference from cameras to BeiDou positioning and navigation signals according to claim 7, characterized in that, Step S4 also includes the following steps: Step S46: Install the processed shielding cover onto the camera module, use conductive silver paste to firmly fix the grounding spring to the ground plane of the camera module PCB, and record the installation position coordinates; Step S47: Measure the DC resistance between each grounding spring and the ground plane of the camera module based on the installation location coordinates. When the resistance value at all measurement points is less than 0.1 ohms, the electrical connection is confirmed to be qualified, and the resistance measurement data table is output. Step S48: Using the qualified connection points confirmed by the resistance measurement data sheet, use a near-field probe to measure the radiation intensity of the Beidou L1 band at a distance of 5 mm from the outer surface of the shield. Compare the measured value with the recorded internal clock radiation amplitude value to calculate the actual shielding effectiveness value. Step S49: When the actual shielding effectiveness reaches 40 decibels or more, confirm that the electromagnetic shielding space has been formed.

9. The method for eliminating interference from cameras to BeiDou positioning and navigation signals according to claim 8, characterized in that, Step S5 includes: With the power supply service recorder powered on, the camera and Beidou positioning module are activated simultaneously to measure the L1 band signal strength under electromagnetic shielding space and record the signal strength value as the signal strength after shielding. The interference suppression effect is confirmed to be up to standard when the signal strength after shielding is compared with the reference carrier-to-noise ratio measured before the camera is turned on in step S1. Under the condition that the interference suppression effect meets the standard, the Beidou positioning system is started to conduct the first positioning test, and the time interval from the start of positioning to obtaining effective location information is recorded as the improved positioning time. By comparing the improved positioning time with the pre-acquired positioning time, when the positioning time is reduced by more than 70% and the camera image output is normal, it is confirmed that the interference of the camera on the BeiDou positioning and navigation signal has been eliminated.

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