Inter-chip data transmission method, communication module, computer equipment and medium

Abstract

The embodiment of the invention provides an inter-chip data transmission method, a communication module, computer equipment and a medium, and relates to the technical field of inter-chip serial communication, and the inter-chip data transmission method comprises the steps that a master chip informs slave chips of data transmission events, the selected slave chips feed back a receiving preparation state to the master chip, and two synchronous control lines are arranged between the master chip and the slave chips; if the receiving preparation state is receiving preparation, the master chip sends a data packet to the selected slave chip; the master chip receives a verification result of the selected slave chip based on verification of the data packet; and selecting the next sent data packet according to the verification result. The method is suitable for a bidirectional real-time interaction system, a synchronization control line is newly added to control data transmission, the boundary of a data packet is clearly identified, it is ensured that a receiving end can accurately identify the initial position of the data packet, the influence of clock jitter on data transmission is reduced, data loss or dislocation is effectively avoided, and the correctness and integrity of data are ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of inter-chip serial communication, and in particular to an inter-chip data transmission method, a communication module, a computer device and a medium. BACKGROUND

[0002] In modern heterogeneous computing system integration, serial interface technology is one of the core channels for chip-level interconnection, and its transmission reliability directly affects the collaborative performance of components such as multi-core processors and intelligent sensors. The SPI bus represented by the four-wire synchronous communication architecture establishes a low-latency data path between microcontrollers and peripheral devices by virtue of its lightweight protocol stack and clock-driven transmission mechanism.

[0003] However, in actual scene transmission that requires interaction between both parties, the master control end can control the data transmission timing through the SCK clock signal, but cannot real-time perceive the state readiness of the controlled device, and there is no effective transmission method to ensure the integrity and reliability of data transmission, which cannot meet the complex data interaction between chips. For example, in an automatic emergency braking warning system, the master controller initiates transmission without knowing the state of the slave end, causing overlapping of effective data windows, resulting in data packet loss, and finally leading to performance degradation or even functional failure. SUMMARY

[0004] Therefore, in order to solve the data packet loss in the chip transmission process of the prior art, the embodiments of the present application provide an inter-chip data transmission method, which adopts double SPI communication, adds a synchronous control line, and determines the normal sending and receiving of data packets through a communication exception handling mechanism, thereby effectively reducing the occurrence of data packet loss.

[0005] In order to achieve the above technical purposes, the present application provides an inter-chip data transmission method, comprising: The master chip notifies the slave chip of a data transmission event through a chip selection signal, and the selected slave chip feeds back a receiving preparation state to the master chip through a first synchronous control line in response to the chip selection signal, wherein two synchronous control lines are arranged between the master chip and the slave chip; If the receiving preparation state is receiving preparation ready, the master chip sends a data packet to the selected slave chip through the first synchronous control line; The master chip receives a verification result fed back by the selected slave chip through MISO based on verification of the data packet; If the check result is a check pass, and the master chip receives the next receiving preparation state of the selected slave chip fed back through the first synchronous control line as receiving preparation ready, the master chip sends a next data packet to the selected slave chip through the first synchronous control line; if the check result is a check fail, and the master chip receives the next receiving preparation state of the selected slave chip fed back through the first synchronous control line as receiving preparation ready, the master chip resends a previous data packet to the selected slave chip through the first synchronous control line.

[0006] The inter-chip data transmission method provided by the application further has the technical features that the master chip sends a data packet to the selected slave chip through the first synchronous control line, including: The master chip completes sending a data packet to the selected slave chip in the first half interval of the receiving preparation ready interval.

[0007] The inter-chip data transmission method provided by the application further has the technical features further including: If the receiving preparation state is receiving preparation ready, and no data is received or the current data packet is received within a preset time length after the receiving preparation state is receiving preparation ready, the selected slave chip controls the receiving preparation state of the first synchronous control line to flip.

[0008] The inter-chip data transmission method provided by the application further has the technical features further including: If the receiving preparation state is non-receiving preparation ready, the duration of the non-receiving preparation ready controlled by the selected slave chip is less than the minimum transmission period of the master chip sending a data packet.

[0009] The inter-chip data transmission method provided by the application further has the technical features that in the transmission method, the time of the receiving chip in the non-preparation ready state when controlling the synchronous control line in the timeout period is less than the minimum period of the sending chip sending a data packet.

[0010] The inter-chip data transmission method provided by the application further has the technical features that the data packet sent by the master chip through the first synchronous control line includes a frame sequence number and a check code.

[0011] The inter-chip data transmission method provided by the application further has the technical features that if the receiving preparation state is receiving preparation ready, the master chip sends a data packet to the selected slave chip through the first synchronous control line, including: If the receiving preparation state is receiving preparation ready, the master chip enters the interrupt setting sendable flag bit valid, the master chip starts to send the data packet in the preset valid sending time when sending the data packet through the first synchronous control line, and the sum of the preset valid sending time and the valid transmission time is less than the data packet sending period, wherein the valid sending time is configured to start timing from setting the sendable valid flag bit, the sendable valid flag bit is cleared if there is no data transmission event in the preset valid sending time, and the next receiving preparation ready state is waited.

[0012] Another purpose of the present application is to provide a communication module for inter-chip data transmission, which is a double-channel independent operation, comprising a serial clock signal pin SCK for data transmission of both chips, a pin CS for the master chip to send a chip selection signal to the slave chip, a pin MOSI for the master chip to send a data packet to the slave chip, a pin MISO for the slave chip to feed back a data check result to the master chip, and a synchronous control line SYNC for the slave chip to inform the master chip of the receiving preparation state.

[0013] A third purpose of the present application is to provide a computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor executes the computer program to implement the inter-chip data transmission method of any one of the preceding embodiments.

[0014] A fourth purpose of the present application is to provide a computer readable storage medium storing an inter-chip data transmission method of any one of the preceding embodiments.

[0015] Compared with the prior art, the above-mentioned at least one technical solution adopted by the embodiments of the present application can achieve the beneficial effects at least including: being applicable to a bidirectional real-time interaction system, improving communication efficiency by deploying a double-channel independent SPI link, adding a synchronous control line to control data sending, explicitly identifying the boundary of a data packet, ensuring that the receiving end can accurately identify the starting position of the data packet, reducing the influence of clock jitter on data transmission, simultaneously increasing ACK feedback through MISO, increasing a retransmission mechanism, effectively avoiding data loss or misplacement, and ensuring the correctness and integrity of data. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0017] Figure 1 is a flowchart of the method provided by the embodiments of the present application. Figure 2 is a structural block diagram of a computer device provided by an embodiment of the present application; Figure 3 is a hardware result schematic diagram of real-time interaction of chip A and chip B provided by an embodiment of the present application; Figure 4 is a flowchart of sending a data packet by a master chip in an embodiment of the present application; Figure 5 is a flowchart of accepting a data packet by a slave chip in an embodiment of the present application. DETAILED DESCRIPTION

[0018] The embodiments of the present application will be described in detail below with reference to the drawings.

[0019] The embodiments of the present application will be described in detail below with reference to the drawings.

[0020] As shown in the drawings, Figures 1-5 in an embodiment of the present application, a chip-to-chip data transmission method is provided, and the method comprises: a master chip informs a slave chip of a data transmission event through a chip select signal, and the selected slave chip feeds back a receiving preparation state to the master chip through a first synchronization control line in response to the chip select signal, wherein two synchronization control lines are arranged between the master chip and the slave chip; if the receiving preparation state is receiving preparation ready, the master chip sends a data packet to the selected slave chip through the first synchronization control line; the master chip receives a verification result fed back by the selected slave chip through MISO based on verification of the data packet; If the check result is a check pass, and the master chip receives the next receiving preparation state of the selected slave chip as receiving preparation ready through the first synchronization control line, the master chip sends a next data packet to the selected slave chip through the first synchronization control line; if the check result is a check fail, and the master chip receives the next receiving preparation state of the selected slave chip as receiving preparation ready through the first synchronization control line, the master chip resends a previous data packet to the selected slave chip through the first synchronization control line.

[0021] In the above embodiments, the master chip and the slave chip can both act as a sending chip or a receiving chip, when the master chip acts as a receiving chip and the slave chip acts as a sending chip, the first synchronization control line is used to judge the preparation ready state; when the master chip acts as a sending chip and the slave chip acts as a receiving chip, the second synchronization control line is used to judge the preparation ready state.

[0022] In some embodiments, the master chip sends a data packet to the selected slave chip through the first synchronization control line, comprising: The master chip completes sending a data packet to the selected slave chip in the first half of the receiving preparation ready time interval.

[0023] In some embodiments, further comprising: After the receiving preparation state is receiving preparation ready, if no data is received or the current data packet is received within a preset time length, the selected slave chip controls the receiving preparation state of the first synchronization control line to flip.

[0024] In some embodiments, further comprising: If the receiving preparation state is non-receiving preparation ready, the duration of the non-receiving preparation ready controlled by the selected slave chip is less than the minimum transmission period of the master chip sending a data packet.

[0025] In some embodiments, the data packet transmitted between chips is also divided into a periodic data packet and an event type data packet, when sending an event type data packet, a reliable communication mechanism is constructed to monitor the data transmission state, to determine that the data packet is normally received and sent, a communication data packet needs to be defined, including a frame header, a frame sequence number, a check sum, a function ID, a data length, and an actual data field.

[0026] Especially in the process of upgrading the vehicle-mounted ECU, the receiving chip checks the received data packet according to the communication protocol, and sends an ACK signal if the check is successful, and the sending chip can send a next data packet, and sends an NCK signal if the check fails, and the sending chip needs to resend the data when receiving the NCK signal, to avoid the upgrade business failure caused by the data packet loss.

[0027] In some embodiments, in the transmission method, the time during which the receiving chip is in a non-ready state when controlling the synchronization control line during the timeout period is less than the minimum period for the transmitting chip to transmit data packets.

[0028] In some embodiments, the data packets sent by the main chip through the first synchronization control line include a frame sequence number and a checksum.

[0029] In some embodiments, if the reception preparation state is reception ready, the master chip sends a data packet to the selected slave chip via the first synchronization control line, including: If the receiving preparation state is "receiving ready", the main chip enters the interrupt setting and the transmit flag is valid. When the main chip sends a data packet through the first synchronization control line, it starts sending the data packet within a preset valid sending time. The sum of the preset valid sending time and the valid transmission time is less than the data packet sending period. The valid sending time is configured to start counting from when the transmit flag is set to be valid. If there is no data transmission event within the preset valid sending time, the transmit flag is cleared, and the chip waits for the next receiving ready state.

[0030] In some embodiments, a simple sum check is used for verification: .

[0031] In some embodiments, such as Figure 4 The diagram shows a flowchart of the sending chip transmitting data packets. Chip A is defined as the master node, and chip B as the slave node. Then, Chip A obtains the data reception readiness feedback signal (Ready signal) through the SPI synchronization control line.

[0032] This can be achieved by interrupting reception to avoid the loss of the ready signal: the receive ready signal is defined to be valid when it is high, and when there is a rising edge transition on the synchronization control line signal, the transmitting chip enters the interrupt setting and the transmit flag is valid.

[0033] When this flag is valid, the sending chip enables DMA and begins sending data cached in the memory pool to the MOSI line, while simultaneously pulling the chip select low. Here, the chip select signal is defined to be valid when it is low.

[0034] The sender's data packets must be assembled strictly according to the communication protocol and must include a frame sequence number and a checksum for valid data packet verification and packet loss detection. The verification method can be to add the data together for verification and check the frame sequence number at the same time.

[0035] After chip A successfully sends a data packet, it needs to clear the sendable flag bit and reset it only after receiving the next valid Ready signal. Chip A also needs to read the verification status signal fed back by chip B.

[0036] If a successful verification is received, wait for the next sendable flag to send a new data packet. If the verification fails, wait for the next sendable flag to resend the failed data packet, while simultaneously counting retransmissions.

[0037] Under normal circumstances, if the verification fails and is retransmitted three times, the fault should be reported and the SPI should be reinitialized.

[0038] Optionally, to avoid data transmission occurring at the edge of the Ready signal's valid transmission time, which could result in data not being received properly, a valid transmission time can be set according to specific circumstances. The valid time starts counting from when the flag is valid. If no data transmission event occurs after the valid time, the valid transmission flag is cleared, and the system waits for the next valid Ready signal.

[0039] The effective transmission time definition needs to be set according to the actual data packet transmission cycle. The effective transmission and data packet sending time must be less than the data packet sending cycle to avoid sending data at the critical point of the slave receiving state, which would cause the slave to be unable to receive the data packet completely.

[0040] The receiving chip performs packet verification on each data packet sent by the sending chip and feeds back the verification result to the master node through MISO. At the same time, it flips the synchronization control line to re-enter the receiving preparation state.

[0041] In some embodiments, such as Figure 5 The diagram shows a flowchart of the receiving chip receiving data packets. Chip A is defined as the master node and chip B as the slave node. Then, Before data transmission, chip B indicates that it is in a receive-ready state by pulling the synchronization control line. Here, it is defined that the receive-ready signal is valid when the synchronization control line is at a high level.

[0042] Synchronization control here requires the addition of timeout logic. When a reception timeout occurs, the synchronization control line needs to be toggled. At the same time, when a data packet is received, the synchronization control line also needs to be toggled in a timely manner to avoid packet loss due to transmission blockage at the sender.

[0043] Chip B determines the presence of a data transmission event by the transition state of the CS chip select signal. When chip B receives a valid chip select signal, it begins DMA data reception and places the data packet in the receive buffer to avoid receive blockage.

[0044] Chip B needs to verify the frame sequence number and checksum of the received data packets: If the frame sequence number is not consecutive or the checksum is inconsistent, the NCK signal is fed back through MISO; if the check passes, the ACK signal is fed back.

[0045] Here, ACK can be defined as high level (1) and NCK as low level (0).

[0046] Optionally, when chip B receives a valid chip select signal, it must keep the synchronization control line outputting a high level until the data transmission is complete, to prevent the receiving chip from exiting the receiving state and causing data reception failure.

[0047] Optionally, the time the synchronization control line is pulled low here must be less than the minimum data packet transmission period to avoid the memory pool overflow caused by chip A being unable to send data packets normally due to prolonged busy receiving state.

[0048] The method provided in any of the foregoing embodiments samples dual SPI between chips, adds a synchronization control line and a data feedback and retransmission mechanism, and establishes a data path for an SPI communication system based on the SPI communication protocol. This ensures that data needs to be processed in real-time and efficiently in application scenarios, while effectively solving the data packet loss problem existing in inter-chip communication and effectively avoiding the risk of data packet conflicts and loss caused by bus contention or response delays. Therefore, compared with the basic SPI protocol, it improves communication stability and reliability, thus alleviating serious problems such as data packet loss in application scenarios with high communication requirements, such as automatic emergency braking warning systems.

[0049] In some embodiments, a computer device is provided, such as... Figure 2 As shown, it includes a memory 201, a processor 202, and a computer program stored on the memory 201 and executable on the processor 202. When the processor 202 executes the computer program, it implements the inter-chip data transfer method of any of the above embodiments.

[0050] Specifically, the computer device can be a computer terminal, a server, or a similar computing device.

[0051] In some embodiments, a computer-readable storage medium is provided, the computer-readable storage medium storing the inter-chip data transfer method described in any of the above embodiments.

[0052] Specifically, computer-readable storage media, including both permanent and non-permanent, removable and non-removable media, can store information using any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer-readable storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable storage media does not include transient media, such as modulated data signals and carrier waves.

[0053] Based on the same inventive concept, this invention also provides a communication module for inter-chip data transmission, as described in the following embodiments. Since the principle of a communication module for inter-chip data transmission is similar to that of an inter-chip data transmission method, the implementation of such a module can refer to the implementation of the inter-chip data transmission method, and repeated details will not be elaborated further. As used below, the terms "unit" or "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0054] A communication module for inter-chip data transmission, the communication module being a dual-channel independent operation, includes a serial clock signal pin SCK for data transmission between the two chips, a pin CS for the master chip to send a chip select signal to the slave chip, a pin MOSI for the master chip to send data packets to the slave chip, a pin MISO for the slave chip to feed back data verification results to the master chip, and a synchronization control line SYNC for the slave chip to notify the master chip of its readiness status.

[0055] Obviously, those skilled in the art should understand that the modules or steps of the above-described embodiments of the present invention can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using computer-executable program code, thereby storing them in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the embodiments of the present invention are not limited to any particular hardware and software combination.

[0056] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, various modifications and variations can be made to the embodiments of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for data transmission between chips, characterized in that, The method includes: The master chip notifies the slave chip of a data transmission event via a chip select signal. The selected slave chip responds to the chip select signal by sending a feedback reception readiness status back to the master chip via a first synchronization control line. There are two synchronization control lines between the master chip and the slave chip. If the receiving preparation state is "receiving ready", then the master chip sends a data packet to the selected slave chip through the first synchronization control line; The master chip receives the verification result fed back by the selected slave chip through MISO based on the verification of the data packet; If the verification result is successful, and the master chip receives feedback from the selected slave chip via the first synchronization control line that the next reception preparation status is ready for reception, the master chip sends the next data packet to the selected slave chip via the first synchronization control line; if the verification result is unsuccessful, and the master chip receives feedback from the selected slave chip via the first synchronization control line that the next reception preparation status is ready for reception, the master chip retransmits the previous data packet to the selected slave chip via the first synchronization control line.

2. The inter-chip data transmission method according to claim 1, characterized in that, The master chip sends a data packet to the selected slave chip via the first synchronization control line, including: The master chip sends a data packet to the selected slave chip during the first half of the receiving ready time interval.

3. The inter-chip data transmission method according to claim 1, characterized in that, Also includes: If no data is received or the current data packet is received within a preset time after the receiving preparation state is completed, the receiving preparation state of the selected slave chip controlling the first synchronization control line will be toggled.

4. The inter-chip data transmission method according to claim 1, characterized in that, Also includes: If the receive preparation state is not ready to receive, the selected slave chip controls the duration of the non-ready state to be less than the minimum transmission period for the master chip to send data packets.

5. The inter-chip data transmission method according to claim 1, characterized in that, In the transmission method, the time during which the receiving chip is in a non-ready state when controlling the synchronization control line during the timeout period is less than the minimum period for the transmitting chip to send data packets.

6. The inter-chip data transmission method according to claim 1, characterized in that, The data packets sent by the main chip through the first synchronization control line include a frame sequence number and a checksum.

7. The inter-chip data transmission method according to claim 1, characterized in that, If the receive preparation state is "receive ready", then the master chip sends a data packet to the selected slave chip via the first synchronization control line, including: If the receiving preparation state is "receiving ready", the main chip enters the interrupt setting and the transmit flag is valid. When the main chip sends a data packet through the first synchronization control line, it starts sending the data packet within a preset valid sending time. The sum of the preset valid sending time and the valid transmission time is less than the data packet sending period. The valid sending time is configured to start counting from when the transmit flag is set to be valid. If there is no data transmission event within the preset valid sending time, the transmit flag is cleared, and the chip waits for the next receiving ready state.

8. A communication module for inter-chip data transmission, characterized in that, The communication module operates independently in two channels, including a serial clock signal pin SCK for data transmission between the two chips, a pin CS for the master chip to send a chip select signal to the slave chip, a pin MOSI for the master chip to send data packets to the slave chip, a pin MISO for the slave chip to feed back data verification results to the master chip, and a synchronization control line SYNC for the slave chip to notify the master chip of the reception readiness status.

9. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the inter-chip data transmission method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores the inter-chip data transfer method according to any one of claims 1 to 7.

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