A table-based automatic logic operation connection simulation method
By using a table-based automatic logic operation simulation method, the problems of manual operation errors and long design cycles in traditional methods are solved. It realizes the automatic construction and optimization of logic models, improves design efficiency and verification coverage, and ensures the credibility of results.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 浙江智行微电子有限公司
- Filing Date
- 2025-09-02
- Publication Date
- 2026-07-07
AI Technical Summary
Traditional logic operation connection simulation methods suffer from problems such as easy configuration errors due to manual operation, high communication costs, chaotic version management, low debugging efficiency, and lengthy design cycles, making it difficult to meet the high efficiency requirements of complex SoCs.
A table-based automatic logic operation connection simulation method is adopted. The system generates a global configuration ID by having the user fill in a structured table, automatically generates a logic model and performs conflict detection, dynamically instantiates storage units, configures interrupt-aware interfaces, executes coverage-driven testing and optimizes timing constraints, and finally outputs the approval result.
It achieves a seamless connection from requirement definition to approval and verification, eliminates manual coding errors, improves design efficiency, reduces resource consumption, increases verification coverage, and ensures the credibility of results through blockchain notarization, thus shortening the design cycle.
Smart Images
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Abstract
Description
Technical Field
[0001] This invention relates to the field of automatic logic operation connection simulation technology, specifically a table-based automatic logic operation connection simulation method. Background Technology
[0002] Logical operations refer to basic operations based on Boolean algebra, including combinations of basic logic gates such as AND, OR, and NOT, used to process the truth value determination and logical relationship derivation of binary signals. In hardware design, logical operations constitute the core functional units of digital circuits, implementing key behaviors such as condition judgment, data selection, and state control through combinational or sequential logic. Essentially, it uses high and low levels of electrical signals to simulate true / false binary states, constructing a circuit behavior model that meets specific functional requirements. Logic operation connection simulation refers to the process of modeling and verifying the interconnection relationships between logic units in chip design, covering the collaborative simulation of signal transmission paths, storage interaction mechanisms, and exception handling logic. Traditional methods require manually configuring the mapping relationship between peripherals and DMA channels, for example, assigning 208 peripheral request signals to 16 channels, and verifying timing and functional correctness through simulation tools. This process not only needs to accurately describe the logical operation behavior but also ensure that the physical connections meet timing constraints and power consumption requirements, ultimately outputting synthesizable hardware code and coverage reports.
[0003] Traditional methods typically rely on designers to manually write RTL code to implement logical connections, defining signal paths, interrupt priorities, and storage interfaces line by line. A typical process includes manually collecting requirements for each module, writing Verilog code, building a test platform, and iteratively debugging. This method has significant drawbacks:
[0004] Manual operation is prone to configuration errors, such as missing signals or priority conflicts; communication costs are high and version management is chaotic when multiple modules collaborate; the debugging phase requires in-depth code location, which is inefficient; when requirements change, a large amount of code needs to be refactored, resulting in poor maintainability. In addition, the discrete design, simulation, and optimization stages are fragmented, leading to a lengthy design cycle and difficulty in meeting the high-efficiency requirements of complex SoCs.
[0005] Based on this, the present invention provides a table-based automatic logic operation connection simulation method to solve the above-mentioned technical problems. Summary of the Invention
[0006] The purpose of this invention is to provide a table-based automatic logical operation connection simulation method to solve the problems mentioned in the background art.
[0007] To achieve the above objectives, the present invention provides the following technical solution:
[0008] This invention proposes a table-based automatic logical operation connection simulation method, comprising the following steps:
[0009] S1. The user fills in a structured table containing core parameters such as storage type, logical operation type, and space mapping rules. The system automatically generates a global configuration ID and initializes the default value, completing template standardization and dependency pre-check.
[0010] S2. The parsing engine loads tabular data, decomposes composite parameters and automatically corrects format errors, generates versioned logical objects and constructs semantic graphs, realizing the conversion of data to structured objects and conflict detection;
[0011] S3. Based on the parameterized flexible logic unit of the logic object, the operation model is simplified to piecewise linear approximation. The hardware mapping of signals to coordinates is realized according to spatial rules, and the truth extraction pipeline is optimized.
[0012] S4. Dynamically instantiate SRAM and MRAM memory cells, configure low-power mode and cooperative bus bandwidth, allocate resources according to timing constraints and integrate interrupt-aware interface;
[0013] S5. Analyze the logic hierarchy and insert pipeline registers, dynamically fill Verilog templates to implement priority encoding and signal merging, inject timing constraints to generate synthesizable code;
[0014] S6. Perform coverage-driven simulation testing, actively inject signal loss anomalies, monitor the error rate in real time and verify the interrupt response logic, and trigger model reconstruction conditions;
[0015] S7. Dynamically adjust the power consumption mode of the storage unit, optimize the timing of critical paths, and iteratively update global configuration parameters to achieve performance balance;
[0016] S8. Generate a multi-dimensional analysis report related to the version, quantify the optimization effect and trigger closed-loop verification, and finally output the approval result or start the re-parsing process.
[0017] Preferably, the implementation steps of step S1 are as follows:
[0018] S1.1. Requirement Field Standardization: Users fill in a structured form, and the mandatory fields include: storage type: mem_type: SRAM / MRAM mixed ratio; logic type: logic_type: AND / OR / custom function name; space mapping rule: space_rule: default "linear" or custom 3D coordinate formula including (x, y, z)=(addr%16, addr / 16, signal); timing constraint: max_delay: unit ns; power mode: power_mode: high / low. Missing fields are automatically filled with default values: space_rule="linear", max_delay=10ns;
[0019] S1.2. Global configuration generation: The system creates a global configuration object cfg_id=GLOBAL_CFG_001 for the current table, stores field constraint rules, including power_mode being forced to high when SRAM percentage is ≥60%, and generates a template file template_v1.xlsx with check bits;
[0020] S1.3. Dependency pre-check: Scan the custom function names in logic_type to verify their existence in the pre-defined library, including lib_function[]={"T-norm", "S-norm"}. If not defined, throw an exception ERR_UNDEF_FUNC@RowX and interrupt the process.
[0021] Preferably, the implementation steps of step S2 are as follows:
[0022] S2.1. Dynamic parsing engine: Calls Pandas to read template_v1.xlsx and uses regular expressions to decompose composite fields: including parsing "AND|SRAM|max_delay=5ns" into a dictionary {"op":"AND", "mem":"SRAM", "delay":5}, and automatically correcting format errors: including correcting max_dely to max_delay;
[0023] S2.2. Encapsulation of logical objects: Generate a versioned logical object LogicObj_v1, whose attributes include obj_id="LOGIC_"+timestamp(), raw data raw_data, and parsed dictionary parsed_dict. The validate() method performs conflict detection: including returning ERR_DELAY_CONFLICT when mem_type="MRAM" is detected and max_delay<3ns.
[0024] S2.3. Semantic Graph Construction: Convert parsed_dict into a directed acyclic graph, with nodes representing logical operations, including AND_node, and edges representing data flow dependencies: input_A→AND_node→output_Z. Store the graph as an adjacency matrix for use in step S3.
[0025] Preferably, the implementation steps of step S3 are as follows:
[0026] S3.1. Flexible Logic Parameterization: Extract the flexibility factor h from logic_type, with a default value of 0.5. When h < 0.3, compile as a hardware lookup table LUT_min to implement strict AND; when h > 0.7, compile as a LUT_max to implement loose OR. Intermediate value generation interpolation module:
[0027] ;
[0028] S3.2. Instantiate the coordinate transformer based on the space_rule parameter:
[0029] If space_rule="linear", then the hardware implementation will have coord=base_addr<<2;
[0030] If the formula is a custom formula (x, y, z) = f(signal), then the Verilog function functioncalc_coord(input[31:0]signal) is generated; ...endfunction;
[0031] S3.3. Truth Extraction Optimization: Design a pipelined truth extraction unit. Input coord and signal strength sig_strength, and output the normalized truth value truth_value=sig_strength>threshold?1:0 through a comparator array. The threshold is set by the global configuration in cfg_id.
[0032] Preferably, the implementation steps of step S4 are as follows:
[0033] S4.1. Memory cell instantiation: Allocate SRAM / MRAM resources according to mem_type: Instantiate an 8T cell in the SRAM module and inject a low-power enable signal: lp_en=cfg_id.power_mode=="low"?1:0; Configure a 2T-1MTJ cell in the MRAM module, and set write_disable=1 for non-volatile mode;
[0034] S4.2. Dynamic bandwidth allocation, calculating the SRAM bandwidth ratio:
[0035] ;
[0036] Generate a memory coordination bus mem_bus[width:0], where the high-order bits of sram_ratio*width are bound to SRAM and the low-order bits are bound to MRAM;
[0037] S4.3. Interrupt Awareness Interface: The priority encoder generates an interrupt number intr_id=901 for memory access conflicts, which is mapped to the high priority group in cfg_id. The exception signal is directly connected to the error handling unit.
[0038] Preferably, the implementation steps of step S5 are as follows:
[0039] S5.1. Logical hierarchy analysis: parse the longest path depth logic_depth in graph_matrix. If depth>3, insert pipeline stage reg_stage=ceil(depth / 3) and generate register configuration table reg_map={nodeA:stage1, nodeB:stage2}.
[0040] S5.2. Dynamic template filling: Input LogicObj_v1.parsed_dict and reg_map into the code template engine to fill Verilog placeholders: use case(intr_id) to implement priority logic, and use assignmerge_out=sig1|sig2 to implement OR merging;
[0041] S5.3. Timing constraint injection: Insert SDC constraints at the beginning of the generated code.
[0042] set_max_delay{max_delay}ns-from[get_pinssrc_reg]-to[get_pinsdst_reg];
[0043] Binding cfg_id ensures version traceability.
[0044] Preferably, the implementation steps of step S6 are as follows:
[0045] S6.1. Coverage-Driven Testing: Generates spatially distributed test vectors based on space_rule: If it is a linear mapping, a uniformly distributed signal is created; if it is a 3D custom mapping, Gaussian distributed point cloud data is generated.
[0046] ;
[0047] S6.2. Active Error Injection: The error handling unit randomly triggers four types of exceptions: signal loss: force signal=0, MRAM write error: flip write enable we=~we, timing violation: shorten clock cycle, priority conflict: duplicate interrupt number;
[0048] S6.3. Real-time monitoring matrix: Construct a monitoring matrix monitor_matrix[error_type][response], count the number of unhandled exceptions, and calculate the dynamic error rate error_rate = (Σ unhandled exceptions / total number of injections) × 100%;
[0049] S6.4. Interrupt Response Verification: Verify whether the interrupt logic responds according to intr_map: High-priority interrupt intr_id=960 should preempt low-priority interrupt intr_id=180 within 3 cycles, otherwise it is marked as ERR_INTR_TIMEOUT.
[0050] Preferably, the implementation steps of step S7 are as follows:
[0051] S7.1. Dynamic power consumption control: Real-time acquisition of SRAM activity rate sram_activity: If the continuous idle period is >100 and power_mode="low", then set lp_en=1 to disable the clock tree; MRAM permanently disables the write driver write_disable=1 in non-volatile mode;
[0052] S7.2. Critical Path Optimization: Extract paths that exceed the max_delay limit from the timing report. If the path involves spatial computation, enable local optimization and add the LOCAL_COMPUTE attribute; if it is combinational logic, insert the parallel submodule parallel_unit.
[0053] S7.3. Configuration version iteration: Generate optimized global configuration cfg_id=GLOBAL_CFG_002, update fields: sram_ratio=new value, power_mode=optimized state, reg_stage=new stage.
[0054] Preferably, the implementation steps of step S8 are as follows:
[0055] S8.1. Multidimensional report generation: Output version-related report: Signal list labeled LogicObj_v1.obj_id, timing curve comparison cfg_id change points, error list location table row number, including ERR_INTR_CONFLICT@Row12: interrupt number 960 repeated;
[0056] S8.2. Quantify the optimization effect and calculate the improvement rate of key indicators: cycle shortening = (cfg_v1.max_delay - cfg_v2.max_delay) / cfg_v1.max_delay;
[0057] Power consumption decrease = (cfg_v1.power - cfg_v2.power) / cfg_v1.power;
[0058] S8.3. Closed-loop verification trigger: If error_rate > 5% or cycle shortening rate < 20%, return to step S2.1 with the parameter tuple: LogicObj_v1.obj_id, cfg_id, error_rate, triggering re-parsing and model reconstruction;
[0059] S8.4. Intelligent Iteration Termination: When error_rate decreases by less than 2% for three consecutive iterations, the final version RTL_final is output and a signing report is generated. The core indicators are written to the blockchain for evidence storage.
[0060] Compared with the prior art, the beneficial effects of the present invention are:
[0061] This invention automates the entire process through structured tables, achieving seamless integration from requirement definition to approval and verification. Users only need to fill in standardized parameter tables, and the system automatically completes logical model construction, hybrid storage configuration, interruption-aware code generation, and closed-loop optimization, completely eliminating manual coding errors. Versioned objects and global configurations ensure data consistency. Lightweight flexible logic units reduce resource consumption compared to traditional generalized logic operations. Dynamic power consumption control and critical path optimization improve energy efficiency. Proactive error injection and real-time monitoring mechanisms increase verification coverage. The closed-loop iterative process of blockchain notarization ensures the credibility of the results, ultimately achieving the advantages of shortened design cycles and near-zero error rates. Detailed Implementation
[0062] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.
[0063] This invention proposes a table-based automatic logical operation connection simulation method, specifically including the following steps:
[0064] S1. The user fills in a structured table containing core parameters such as storage type, logical operation type, and space mapping rules. The system automatically generates a global configuration ID and initializes the default value, completing template standardization and dependency pre-check.
[0065] Furthermore, it should be noted that the implementation steps of step S1 are as follows:
[0066] S1.1. Requirement Field Standardization: Users fill in a structured form, and the mandatory fields include: storage type: mem_type: SRAM / MRAM mixed ratio; logic type: logic_type: AND / OR / custom function name; space mapping rule: space_rule: default "linear" or custom 3D coordinate formula including (x, y, z)=(addr%16, addr / 16, signal); timing constraint: max_delay: unit ns; power mode: power_mode: high / low. Missing fields are automatically filled with default values: space_rule="linear", max_delay=10ns;
[0067] S1.2. Global configuration generation: The system creates a global configuration object cfg_id=GLOBAL_CFG_001 for the current table, stores field constraint rules, including power_mode being forced to high when SRAM percentage is ≥60%, and generates a template file template_v1.xlsx with check bits;
[0068] S1.3. Dependency pre-check: Scan the custom function names in logic_type to verify their existence in the pre-built library, including lib_function[]={"T-norm", "S-norm"}. If not defined, throw an exception ERR_UNDEF_FUNC@RowX and interrupt the process.
[0069] Through this step, users define core parameters (storage type, logical operation type, etc.) through a structured table. The system automatically generates a global configuration ID and initializes the default value, completing template standardization and dependency pre-checking, ensuring input standardization and early error interception.
[0070] S2. The parsing engine loads tabular data, decomposes composite parameters and automatically corrects format errors, generates versioned logical objects and constructs semantic graphs, realizing the conversion of data to structured objects and conflict detection;
[0071] Furthermore, it should be noted that the implementation steps of step S2 are as follows:
[0072] S2.1. Dynamic parsing engine: Calls Pandas to read template_v1.xlsx and uses regular expressions to decompose composite fields: including parsing "AND|SRAM|max_delay=5ns" into a dictionary {"op":"AND", "mem":"SRAM", "delay":5}, and automatically correcting format errors: including correcting max_dely to max_delay;
[0073] S2.2. Encapsulation of logical objects: Generate a versioned logical object LogicObj_v1, whose attributes include obj_id="LOGIC_"+timestamp(), raw data raw_data, and parsed dictionary parsed_dict. The validate() method performs conflict detection: including returning ERR_DELAY_CONFLICT when mem_type="MRAM" is detected and max_delay<3ns.
[0074] S2.3. Semantic Graph Construction: Convert parsed_dict into a directed acyclic graph, where nodes are logical operations, including AND_node, and edges are data flow dependencies: input_A→AND_node→output_Z, stored as an adjacency matrix graph_matrix for use in step S3;
[0075] Through this step, the parsing engine loads table data, intelligently decomposes composite parameters and corrects format errors, encapsulates versioned logical objects and constructs semantic graphs, realizing the conversion of data to a structured model and conflict detection;
[0076] S3. Based on the parameterized flexible logic unit of the logic object, the operation model is simplified to piecewise linear approximation. The hardware mapping of signals to coordinates is realized according to spatial rules, and the truth extraction pipeline is optimized.
[0077] Furthermore, it should be noted that the implementation steps of step S3 are as follows:
[0078] S3.1. Flexible Logic Parameterization: Extract the flexibility factor h from logic_type, with a default value of 0.5. When h < 0.3, compile as a hardware lookup table LUT_min to implement strict AND; when h > 0.7, compile as a LUT_max to implement loose OR. Intermediate value generation interpolation module:
[0079] ;
[0080] S3.2. Instantiate the coordinate transformer based on the space_rule parameter:
[0081] If space_rule="linear", then the hardware implementation will have coord=base_addr<<2;
[0082] If the formula is a custom formula (x, y, z) = f(signal), then the Verilog function functioncalc_coord(input[31:0]signal) is generated; ...endfunction;
[0083] S3.3. Truth extraction optimization: Design a pipelined truth extraction unit. Input coord and signal strength sig_strength, and output normalized truth value truth_value=sig_strength>threshold?1:0 through comparator array. The threshold is set by the global configuration in cfg_id.
[0084] Through this step, a flexible logic unit based on logical object parameterization is used, a piecewise linear approximation simplifies the operation model, the mapping of signals to hardware coordinates is realized according to spatial rules, and the truth extraction pipeline is optimized to reduce latency.
[0085] S4. Dynamically instantiate SRAM and MRAM memory cells, configure low-power mode and cooperative bus bandwidth, allocate resources according to timing constraints and integrate interrupt-aware interface;
[0086] Furthermore, it should be noted that the implementation steps of step S4 are as follows:
[0087] S4.1. Memory cell instantiation: Allocate SRAM / MRAM resources according to mem_type: Instantiate an 8T cell in the SRAM module and inject a low-power enable signal: lp_en=cfg_id.power_mode=="low"?1:0; Configure a 2T-1MTJ cell in the MRAM module, and set write_disable=1 for non-volatile mode;
[0088] S4.2. Dynamic bandwidth allocation, calculating the SRAM bandwidth ratio:
[0089] ;
[0090] Generate a memory coordination bus mem_bus[width:0], where the high-order bits of sram_ratio*width are bound to SRAM and the low-order bits are bound to MRAM;
[0091] S4.3. Interrupt-aware interface: The priority encoder generates an interrupt number intr_id=901 for memory access conflicts, which is mapped to the high priority group in cfg_id. The exception signal is directly connected to the error handling unit.
[0092] This step dynamically instantiates SRAM and MRAM memory cells, configures low-power mode and cooperative bus bandwidth, allocates resources according to timing constraints, and integrates high-priority interrupt interfaces to improve energy efficiency and error response speed.
[0093] S5. Analyze the logic hierarchy and insert pipeline registers, dynamically fill Verilog templates to implement priority encoding and signal merging, inject timing constraints to generate synthesizable code;
[0094] Furthermore, it should be noted that the implementation steps of step S5 are as follows:
[0095] S5.1. Logical hierarchy analysis: parse the longest path depth logic_depth in graph_matrix. If depth>3, insert pipeline stage reg_stage=ceil(depth / 3) and generate register configuration table reg_map={nodeA:stage1, nodeB:stage2}.
[0096] S5.2. Dynamic template filling: Input LogicObj_v1.parsed_dict and reg_map into the code template engine to fill Verilog placeholders: use case(intr_id) to implement priority logic, and use assignmerge_out=sig1|sig2 to implement OR merging;
[0097] S5.3. Timing constraint injection: Insert SDC constraints at the beginning of the generated code.
[0098] set_max_delay{max_delay}ns-from[get_pinssrc_reg]-to[get_pinsdst_reg];
[0099] Binding cfg_id ensures version traceability;
[0100] This step analyzes the logic hierarchy depth and automatically inserts pipeline registers, dynamically fills Verilog templates to implement priority encoding and signal merging, injects timing constraints to generate synthesizable code, and ensures timing convergence.
[0101] S6. Perform coverage-driven simulation testing, actively inject signal loss anomalies, monitor the error rate in real time and verify the interrupt response logic, and trigger model reconstruction conditions;
[0102] Furthermore, it should be noted that the implementation steps of step S6 are as follows:
[0103] S6.1. Coverage-Driven Testing: Generates spatially distributed test vectors based on space_rule: If it is a linear mapping, a uniformly distributed signal is created; if it is a 3D custom mapping, Gaussian distributed point cloud data is generated.
[0104] ;
[0105] S6.2. Active Error Injection: The error handling unit randomly triggers four types of exceptions: signal loss: force signal=0, MRAM write error: flip write enable we=~we, timing violation: shorten clock cycle, priority conflict: duplicate interrupt number;
[0106] S6.3. Real-time monitoring matrix: Construct a monitoring matrix monitor_matrix[error_type][response], count the number of unhandled exceptions, and calculate the dynamic error rate error_rate = (Σ unhandled exceptions / total number of injections) × 100%;
[0107] S6.4. Interrupt response verification: Verify whether the interrupt logic responds according to intr_map: High-priority interrupt intr_id=960 should preempt low-priority interrupt intr_id=180 within 3 cycles, otherwise it is marked as ERR_INTR_TIMEOUT;
[0108] This step involves performing coverage-driven spatial distribution testing, proactively injecting four types of hardware anomalies and monitoring the error rate in real time, verifying the real-time performance of interrupt response, and providing quantitative indicators for optimization.
[0109] S7. Dynamically adjust the power consumption mode of the storage unit, optimize the timing of critical paths, and iteratively update global configuration parameters to achieve performance balance;
[0110] Furthermore, it should be noted that the implementation steps of step S7 are as follows:
[0111] S7.1. Dynamic power consumption control: Real-time acquisition of SRAM activity rate sram_activity: If the continuous idle period is >100 and power_mode="low", then set lp_en=1 to disable the clock tree; MRAM permanently disables the write driver write_disable=1 in non-volatile mode;
[0112] S7.2. Critical Path Optimization: Extract paths that exceed the max_delay limit from the timing report. If the path involves spatial computation, enable local optimization and add the LOCAL_COMPUTE attribute; if it is combinational logic, insert the parallel submodule parallel_unit.
[0113] S7.3. Configuration version iteration: Generate optimized global configuration cfg_id=GLOBAL_CFG_002, update fields: sram_ratio=new value, power_mode=optimized status, reg_stage=new stage;
[0114] S8. Generate a multi-dimensional analysis report related to the version, quantify the optimization effect and trigger closed-loop verification, and finally output the approval result or start the re-parsing process;
[0115] This step dynamically adjusts the power consumption of storage units, enables localized computing or parallel optimization for critical paths, and iteratively updates global configuration parameters to balance performance and energy efficiency.
[0116] Furthermore, it should be noted that the implementation steps of step S8 are as follows:
[0117] S8.1. Multidimensional report generation: Output version-related report: Signal list labeled LogicObj_v1.obj_id, timing curve comparison cfg_id change points, error list location table row number, including ERR_INTR_CONFLICT@Row12: interrupt number 960 repeated;
[0118] S8.2. Quantify the optimization effect and calculate the improvement rate of key indicators: cycle shortening = (cfg_v1.max_delay - cfg_v2.max_delay) / cfg_v1.max_delay;
[0119] Power consumption decrease = (cfg_v1.power - cfg_v2.power) / cfg_v1.power;
[0120] S8.3. Closed-loop verification trigger: If error_rate > 5% or cycle shortening rate < 20%, return to step S2.1 with the parameter tuple: LogicObj_v1.obj_id, cfg_id, error_rate, triggering re-parsing and model reconstruction;
[0121] S8.4. Intelligent Iteration Termination: When error_rate decreases by less than 2% for three consecutive iterations, the final version RTL_final is output and a signing report is generated. The core indicators are written to the blockchain for evidence storage.
[0122] This step generates a multi-dimensional analysis report on version association and quantifies the optimization effect. Based on the error rate and performance indicators, a closed-loop verification cycle is triggered, and finally, the blockchain notarization signature result is output or the re-parse process is initiated.
[0123] Through the above steps, this invention achieves seamless integration from requirement definition to approval and verification by driving full-process automation through structured tables. Users only need to fill in standardized parameter tables, and the system automatically completes logical model construction, hybrid storage configuration, interruption-aware code generation, and closed-loop optimization, completely eliminating manual coding errors. Versioned objects and global configurations ensure data consistency. Lightweight flexible logic units reduce resource consumption compared to traditional general logic operations. Dynamic power consumption control and critical path optimization improve energy efficiency. Proactive error injection and real-time monitoring mechanisms improve verification coverage. The closed-loop iterative process of blockchain notarization ensures the credibility of the results, ultimately achieving the advantages of shortened design cycle and near-zero error rate.
[0124] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0125] The preferred embodiments of the present invention disclosed above are merely illustrative of the invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims
1. A table-based automatic logical operation connection simulation method, characterized in that, Includes the following steps: S1. The user fills in a structured table containing core parameters such as storage type, logical operation type, and space mapping rules. The system automatically generates a global configuration ID and initializes the default value, completing template standardization and dependency pre-check. S2. The parsing engine loads tabular data, decomposes composite parameters and automatically corrects format errors, generates versioned logical objects and constructs semantic graphs, realizing the conversion of data to structured objects and conflict detection; S3. Based on the parameterized flexible logic unit of the logic object, the operation model is simplified to piecewise linear approximation. The hardware mapping of signals to coordinates is realized according to spatial rules, and the truth extraction pipeline is optimized. S4. Dynamically instantiate SRAM and MRAM memory cells, configure low-power mode and cooperative bus bandwidth, allocate resources according to timing constraints and integrate interrupt-aware interface; S5. Analyze the logic hierarchy and insert pipeline registers, dynamically fill Verilog templates to implement priority encoding and signal merging, inject timing constraints to generate synthesizable code; S6. Perform coverage-driven simulation testing, actively inject signal loss anomalies, monitor the error rate in real time and verify the interrupt response logic, and trigger model reconstruction conditions; S7. Dynamically adjust the power consumption mode of the storage unit, optimize the timing of critical paths, and iteratively update global configuration parameters to achieve performance balance; S8. Generate a multi-dimensional analysis report related to the version, quantify the optimization effect and trigger closed-loop verification, and finally output the approval result or start the re-parsing process.
2. The table-based automatic logical operation connection simulation method according to claim 1, characterized in that, The implementation steps of step S1 are as follows: S1.
1. Requirement Field Standardization: Users fill in a structured form, and the mandatory fields include: storage type: mem_type: SRAM / MRAM mixed ratio; logic type: logic_type: AND / OR / custom function name; space mapping rule: space_rule: default "linear" or custom 3D coordinate formula including (x, y, z)=(addr%16, addr / 16, signal); timing constraint: max_delay: unit ns; power mode: power_mode: high / low. Missing fields are automatically filled with default values: space_rule="linear", max_delay=10ns; S1.
2. Global configuration generation: The system creates a global configuration object cfg_id=GLOBAL_CFG_001 for the current table, stores field constraint rules, including power_mode being forced to high when SRAM percentage is ≥60%, and generates a template file template_v1.xlsx with check bits; S1.
3. Dependency pre-check: Scan the custom function names in logic_type to verify their existence in the pre-defined library, including lib_function[]={"T-norm", "S-norm"}. If not defined, throw an exception ERR_UNDEF_FUNC@RowX and interrupt the process.
3. The table-based automatic logical operation connection simulation method according to claim 2, characterized in that, The implementation steps of step S2 are as follows: S2.
1. Dynamic parsing engine: Calls Pandas to read template_v1.xlsx and uses regular expressions to decompose composite fields: including parsing "AND|SRAM|max_delay=5ns" into a dictionary {"op":"AND", "mem":"SRAM", "delay":5}, and automatically correcting format errors: including correcting max_dely to max_delay; S2.
2. Encapsulation of logical objects: Generate a versioned logical object LogicObj_v1, whose attributes include obj_id="LOGIC_"+timestamp(), raw data raw_data, and parsed dictionary parsed_dict. The validate() method performs conflict detection: including returning ERR_DELAY_CONFLICT when mem_type="MRAM" is detected and max_delay<3ns. S2.
3. Semantic Graph Construction: Convert parsed_dict into a directed acyclic graph, with nodes representing logical operations, including AND_node, and edges representing data flow dependencies: input_A→AND_node→output_Z. Store the graph as an adjacency matrix for use in step S3.
4. The table-based automatic logical operation connection simulation method according to claim 3, characterized in that, The implementation steps of step S3 are as follows: S3.
1. Flexible Logic Parameterization: Extract the flexibility factor h from logic_type, with a default value of 0.
5. When h < 0.3, compile as a hardware lookup table LUT_min to implement strict AND; when h > 0.7, compile as a LUT_max to implement loose OR. Intermediate value generation interpolation module: ； S3.
2. Instantiate the coordinate transformer based on the space_rule parameter: If space_rule="linear", then the hardware implementation will have coord=base_addr<<2; If the formula is a custom formula (x, y, z) = f(signal), then the Verilog function functioncalc_coord(input[31:0]signal) is generated; ...endfunction; S3.
3. Truth Extraction Optimization: Design a pipelined truth extraction unit. Input coord and signal strength sig_strength, and output the normalized truth value truth_value=sig_strength>threshold?1:0 through a comparator array. The threshold is set by the global configuration in cfg_id.
5. The table-based automatic logical operation connection simulation method according to claim 4, characterized in that, The implementation steps of step S4 are as follows: S4.
1. Memory cell instantiation: Allocate SRAM / MRAM resources according to mem_type: Instantiate an 8T cell in the SRAM module and inject a low-power enable signal: lp_en=cfg_id.power_mode=="low"?1:0; Configure a 2T-1MTJ cell in the MRAM module, and set write_disable=1 for non-volatile mode; S4.
2. Dynamic bandwidth allocation, calculating the SRAM bandwidth ratio: ； Generate a memory coordination bus mem_bus[width:0], where the high-order bits of sram_ratio*width are bound to SRAM and the low-order bits are bound to MRAM; S4.
3. Interrupt Awareness Interface: The priority encoder generates an interrupt number intr_id=901 for memory access conflicts, which is mapped to the high priority group in cfg_id. The exception signal is directly connected to the error handling unit.
6. The table-based automatic logical operation connection simulation method according to claim 5, characterized in that, The implementation steps of step S5 are as follows: S5.
1. Logical hierarchy analysis: parse the longest path depth logic_depth in graph_matrix. If depth>3, insert pipeline stage reg_stage=ceil(depth / 3) and generate register configuration table reg_map={nodeA:stage1, nodeB:stage2}. S5.
2. Dynamic template filling: Input LogicObj_v1.parsed_dict and reg_map into the code template engine to fill Verilog placeholders: use case(intr_id) to implement priority logic, and use assignmerge_out=sig1|sig2 to implement OR merging; S5.
3. Timing constraint injection: Insert SDC constraints at the beginning of the generated code. set_max_delay{max_delay}ns-from[get_pinssrc_reg]-to[get_pinsdst_reg]; Binding cfg_id ensures version traceability.
7. The table-based automatic logical operation connection simulation method according to claim 6, characterized in that, The implementation steps of step S6 are as follows: S6.
1. Coverage-Driven Testing: Generates spatially distributed test vectors based on space_rule: If it is a linear mapping, a uniformly distributed signal is created; if it is a 3D custom mapping, Gaussian distributed point cloud data is generated. ； S6.
2. Active Error Injection: The error handling unit randomly triggers four types of exceptions: signal loss: force signal=0, MRAM write error: flip write enable we=~we, timing violation: shorten clock cycle, priority conflict: duplicate interrupt number; S6.
3. Real-time monitoring matrix: Construct a monitoring matrix monitor_matrix[error_type][response], count the number of unhandled exceptions, and calculate the dynamic error rate error_rate = (Σ unhandled exceptions / total number of injections) × 100%; S6.
4. Interrupt Response Verification: Verify whether the interrupt logic responds according to intr_map: High-priority interrupt intr_id=960 should preempt low-priority interrupt intr_id=180 within 3 cycles, otherwise it is marked as ERR_INTR_TIMEOUT.
8. The table-based automatic logical operation connection simulation method according to claim 7, characterized in that, The implementation steps of step S7 are as follows: S7.
1. Dynamic power consumption control: Real-time acquisition of SRAM activity rate sram_activity: If the continuous idle period is >100 and power_mode="low", then set lp_en=1 to shut down the clock tree; MRAM permanently disables the write driver write_disable=1 in non-volatile mode; S7.
2. Critical Path Optimization: Extract paths that exceed the max_delay limit from the timing report. If the path involves spatial computation, enable local optimization and add the LOCAL_COMPUTE attribute; if it is combinational logic, insert the parallel submodule parallel_unit. S7.
3. Configuration version iteration: Generate optimized global configuration cfg_id=GLOBAL_CFG_002, update fields: sram_ratio=new value, power_mode=optimized state, reg_stage=new stage.
9. The table-based automatic logical operation connection simulation method according to claim 8, characterized in that, The implementation steps of step S8 are as follows: S8.
1. Multidimensional report generation: Output version-related report: Signal list labeled LogicObj_v1.obj_id, timing curve comparison cfg_id change points, error list location table row number, including ERR_INTR_CONFLICT@Row12: interrupt number 960 repeated; S8.
2. Quantify the optimization effect and calculate the improvement rate of key indicators: cycle shortening = (cfg_v1.max_delay - cfg_v2.max_delay) / cfg_v1.max_delay; Power consumption decrease = (cfg_v1.power - cfg_v2.power) / cfg_v1.power; S8.
3. Closed-loop verification trigger: If error_rate > 5% or cycle shortening rate < 20%, return to step S2.1 with the parameter tuple: LogicObj_v1.obj_id, cfg_id, error_rate, triggering re-parsing and model reconstruction; S8.
4. Intelligent Iteration Termination: When error_rate decreases by less than 2% for three consecutive iterations, the final version RTL_final is output and a signing report is generated. The core indicators are written to the blockchain for evidence storage.