Automatic generation method and terminal for FPGA component codes

By defining interfaces for FPGA application components, visual modeling and automated code generation solve the problems of high professional threshold, low efficiency and poor consistency in FPGA component code generation in existing technologies. It enables participation by non-professionals and ensures process consistency, thereby improving development efficiency and reducing error rate.

CN122308812AActive Publication Date: 2026-06-30成都谐盈科技有限公司
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Patent Information

Application Number
CN202610772907.2
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-06-01
Publication Date
2026-06-30
Estimated Expiration
2046-06-01

AI Technical Summary

Technical Problem

Existing FPGA component code generation methods have high professional thresholds, low development efficiency, high error rates, and poor process consistency. Existing visualization tools cannot achieve automated conversion from modeling to code.

Method used

By defining FPGA application components with interfaces, visual modeling is performed, and component instances and port connections are established. Combined with Eclipse PDE technology, a trigger mechanism is configured to automatically generate FPGA component code. The action execution class is used to collect model information and call the generator, replacing the manual writing of traditional hardware description languages.

Benefits of technology

It lowers the professional threshold, enabling non-professionals to participate in development, improving development efficiency, reducing error rates, ensuring consistency in the development process, and optimizing overall process efficiency and collaboration efficiency.

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Abstract

The invention belongs to the technical field of FPGAs, and relates to an FPGA component code automatic generation method and a terminal. According to the method, manual writing of a traditional hardware description language is replaced by a mode of defining an FPGA application component with an interface, creating a component instance for configuring logic information and establishing port connection through a connection line, so that non-professional personnel can participate in development; then, based on an Eclipse PDE configuration triggering mechanism, model information is collected through an action execution class, a generator is called, a project is automatically created, a configuration file is generated, placeholder replacement is completed, automatic conversion from modeling to codes is achieved, careful description burden of manual writing and errors caused by human negligence are avoided, the development efficiency is improved, the debugging cost is reduced, and the development efficiency is improved. Various tools and specifications are replaced by unified modeling specifications and generation processes, development consistency is guaranteed to improve cooperation efficiency, follow-up maintenance iteration is facilitated, and meanwhile the defect that an existing visualization tool can only display and cannot automatically transcode is overcome.
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