Method for calculating distortion degree, chip and electronic device

Abstract

The application discloses a distortion degree calculation method, a chip and an electronic device, and belongs to the field of video coding. The method comprises the following steps: calculating the residual value between each pair of pixel points occupying the same position in an original pixel block and a prediction pixel block, obtaining a residual pixel block, the prediction pixel block being obtained by predicting the original pixel block, the original pixel block comprising N*N pixel points, N being a positive integer; buffering a sub-pixel block in the residual pixel block according to a preset pixel block size, and outputting a pixel block in the sub-pixel block, the preset pixel block size being smaller than the size of the residual pixel block; calculating the distortion degree corresponding to the pixel block in the sub-pixel block; and calculating the distortion degree corresponding to the original pixel block and the prediction pixel block according to the distortion degree corresponding to the pixel block in the sub-pixel block. The application can reduce the hardware resource consumption of distortion degree calculation.

Description

Technical Field

[0001] This application relates to the field of video encoding and decoding, and in particular to a method for calculating distortion, a chip, and an electronic device. Background Technology

[0002] By calculating the distortion corresponding to the original pixel blocks and predicted pixel blocks in a video frame, the encoding strategy for the video can be determined. The predicted pixel blocks are obtained by predicting the original pixel blocks through intra-frame prediction or inter-frame prediction. Intra-frame prediction is used to handle spatial redundancy in video frames, while inter-frame prediction is used to handle temporal redundancy in video frames.

[0003] In related technologies, by determining the residual pixel blocks corresponding to the original and predicted pixel blocks and calculating the sum of absolute transformed differences (SATD) of the residual pixel blocks, the distortion corresponding to the original and predicted pixel blocks can be calculated. The residual pixel blocks include the residual values ​​between each pair of pixels occupying the same position in the original and predicted pixel blocks. During the calculation of SATD, a two-dimensional Hadamard transformation is required. This transformation needs to be performed using a buffer that supports transposing N×N pixel blocks, where N×N is the size of the residual pixel block.

[0004] The above method calculates the distortion corresponding to the original pixel block and the predicted pixel block, but it requires a cache of N×N pixel blocks, which results in high hardware resource consumption. Summary of the Invention

[0005] This application provides a method, chip, and electronic device for calculating distortion, which can reduce the hardware resource consumption of distortion calculation. The technical solution is as follows.

[0006] According to one aspect of this application, a method for calculating distortion is provided, the method comprising:

[0007] The residual value between each pair of pixels occupying the same position in the original pixel block and the predicted pixel block is calculated to obtain the residual pixel block. The predicted pixel block is obtained by predicting the original pixel block, which includes N×N pixels, where N is a positive integer.

[0008] The sub-pixel blocks in the residual pixel block are cached according to a preset pixel block size, and the pixel blocks in the sub-pixel blocks are output. The preset pixel block size is smaller than the size of the residual pixel block.

[0009] Calculate the distortion corresponding to the pixel block in the sub-pixel block;

[0010] The distortion of the original pixel block and the predicted pixel block is calculated based on the distortion of the pixel block in the sub-pixel block.

[0011] According to another aspect of this application, a chip is provided, the chip comprising:

[0012] The first calculation unit is used to calculate the residual value between each pair of pixels occupying the same position in the original pixel block and the predicted pixel block to obtain the residual pixel block. The predicted pixel block is obtained by predicting the original pixel block. The original pixel block includes N×N pixels, where N is a positive integer.

[0013] A caching unit is used to cache sub-pixel blocks in the residual pixel block according to a preset pixel block size, and output the pixel blocks in the sub-pixel block, wherein the preset pixel block size is smaller than the size of the residual pixel block;

[0014] The second calculation unit is used to calculate the distortion corresponding to the pixel block in the sub-pixel block;

[0015] The third calculation unit is used to calculate the distortion corresponding to the original pixel block and the predicted pixel block based on the distortion corresponding to the pixel block in the sub-pixel block.

[0016] According to another aspect of this application, an electronic device is provided, the electronic device comprising the chip described above.

[0017] The beneficial effects of the technical solution provided in this application include at least the following:

[0018] By using a preset pixel block size to cache sub-pixel blocks within the residual pixel block and then outputting the pixel blocks within those sub-pixel blocks, the distortion corresponding to the pixel blocks within those sub-pixel blocks can be calculated. This allows for the calculation of the distortion corresponding to both the original pixel block and the predicted pixel block. Since the preset pixel block size is smaller than the residual pixel block size, distortion calculation can be achieved by supporting the caching of pixel blocks smaller than the residual pixel block size, thereby reducing the hardware resource consumption for distortion calculation. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a hardware architecture diagram for computing an 8×8 SATD provided in an exemplary embodiment of this application;

[0021] Figure 2 This is a schematic diagram of a distortion calculation process provided in an exemplary embodiment of this application;

[0022] Figure 3 This is a flowchart illustrating a method for calculating distortion provided in an exemplary embodiment of this application;

[0023] Figure 4 This is a flowchart illustrating another method for calculating distortion provided in an exemplary embodiment of this application;

[0024] Figure 5 This is a schematic diagram of a cache unit provided in an exemplary embodiment of this application;

[0025] Figure 6 This is another hardware architecture diagram for computing an 8×8 SATD provided in an exemplary embodiment of this application;

[0026] Figure 7 This is a schematic diagram of the chip structure provided in an exemplary embodiment of this application;

[0027] Figure 8 This is a schematic diagram of the structure of another chip provided in an exemplary embodiment of this application;

[0028] Figure 9 This is a structural block diagram of an electronic device provided in an exemplary embodiment of this application.

[0029] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0031] First, the technical background involved in this application will be introduced.

[0032] With the improvement of video resolution and quality, the transmission and storage of digital video have become increasingly important, and the research field of video encoding and decoding has gradually expanded, giving rise to a series of video coding standards. Currently, commonly used video coding standards include H.264 / Advanced Video Coding (AVC) and H.265 / High Efficiency Video Coding (HEVC), both of which offer excellent video compression rates and quality. H.264 / AVC and H.265 / HEVC standards support intra-frame prediction and inter-frame prediction. Intra-frame prediction is used to handle (eliminate) spatial redundancy in a frame, such as repetitive information caused by the continuity of local regions like texture and color within the same frame. Inter-frame prediction is used to handle (eliminate) temporal redundancy in a frame, such as the repetition of background, static objects, etc., between consecutive frames in a video frame sequence. During the prediction process, video frames are divided into pixel blocks of predefined sizes. The core coding unit of the H.264 / AVC standard is the macroblock, with a maximum of 16×16 luma blocks. The H.265 / HEVC standard adopts the concepts of Coding Tree Unit (CTU) and Coding Tree Block (CTB), dividing the coding blocks (CB) downwards in the form of a quadtree, with a maximum of 64×64 luma blocks and a minimum of 4×4 chroma blocks.

[0033] Prediction refers to using a certain method to predict the currently processed pixel block (the original pixel block) using already encoded pixel blocks, and encoding the residual value between the original pixel block and the predicted pixel block. The standard for measuring the residual is distortion, which has a direct impact on video quality and the size of the final generated bitstream. Commonly used methods for calculating distortion include Sum of Absolute Difference (SAD), Sum of Squared Difference (SSD), and Sum of Absolute Transformed Difference (SATD).

[0034] SAD is used to calculate the sum of the absolute values ​​of the differences between each pair of pixels occupying the same position in the N×N predicted pixel block P and the original pixel block O, as shown in formula (1). The calculation is simple and suitable for hardware implementation, but it is sensitive to high-frequency noise and its accuracy is insufficient.

[0035] (1)

[0036] SSD is used to calculate the sum of squares of the differences between each pair of pixels occupying the same position in the predicted pixel block and the original pixel block, as shown in Equation (2). The squaring operation is closer to the peak signal-to-noise ratio (PSNR) index and has high accuracy, but it requires a multiplier, which leads to high hardware overhead.

[0037] (2)

[0038] SATD is used to perform Hadamard Transform on the residual pixel block R, and then the sum of the absolute values ​​of the transform coefficients is calculated, as shown in formula (3).

[0039] (3)

[0040] Where T(·) is the Hadamard transform, calculated by formula (4):

[0041] (4)

[0042] Here, H is an N×N Hadamard matrix consisting of ±1.

[0043] SATD takes into account frequency domain characteristics, making it closer to the true coding distortion than SAD. Furthermore, Hadamard transform only requires addition and subtraction, significantly reducing the hardware overhead of multiplication in SSD. Therefore, SATD has become a commonly used distortion calculation method for H.264 / AVC and H.165 / HEVC coding standards in the hardware design of video codec chips.

[0044] SATD comprises an N×N Hadamard matrix. For coded pixel blocks (residual pixel blocks) of different sizes (4×4, 8×8, 16×16, 32×32, etc.), a corresponding SATD architecture, i.e., a corresponding Hadamard matrix, is typically used. In ultra-high resolution video coding, 8×8 or 16×16 Hadamard transforms are used more frequently to calculate SATD because ultra-high resolution videos are usually divided into larger blocks to achieve better coding efficiency.

[0045] In the current SATD calculation scheme, the size (order) of the Hadamard transform architecture of SATD, i.e., the Hadamard matrix, depends on the size of the residual pixel block. The standard Hadamard transform requires multiple layers of addition / subtraction operations. The computational complexity of Hadamard transforms of 8×8, 16×16 and larger sizes is high. Taking 8×8 SATD as an example, its two-dimensional Hadamard transform calculation is shown in formula (5).

[0046] (5)

[0047] Each one-dimensional transformation must process eight residual pixels (one row or one column of pixels in an 8×8 residual pixel block) to complete its calculation, and this process must be repeated eight times to process a complete 8×8 residual pixel block. Therefore, a two-dimensional transformation requires at least 16 layers of 8 addition / subtraction operations. The larger the size of the Hadamard matrix, the more layers of addition / subtraction operations are required, and the computational complexity increases proportionally, affecting not only hardware timing performance but also increasing hardware area consumption.

[0048] In hardware implementation, the two-dimensional Hadamard transform is typically calculated in two stages. First, a horizontal transformation is performed followed by transpose, then a vertical transformation is performed. The transpose requires N×N pixel-sized memory, such as a Static Random-Access Memory (SRAM) cache that supports transposing N×N pixel blocks. For example, Figure 1 This is a hardware architecture diagram for computing an 8×8 SATD provided in an exemplary embodiment of this application. Figure 1 As shown, the transpose buffer module in this hardware architecture is used to implement the transpose in the two-dimensional Hadamard transform process. As the matrix size of the Hadamard transform increases, the area of ​​the transpose buffer module also increases accordingly.

[0049] In summary, the above method for calculating distortion results in relatively high hardware resource consumption for hardware architectures used to calculate large-size SATDs, which is a significant factor limiting the achievement of high-performance encoders.

[0050] The method provided in this application calculates the distortion corresponding to the original pixel block and the predicted pixel block by using a preset pixel block size. Since the preset pixel block size is smaller than the residual pixel block size, distortion calculation can be achieved by caching pixel blocks smaller than the residual pixel block size, thereby reducing the hardware resource consumption for distortion calculation.

[0051] Taking the method provided in this application as an example, applied to a chip, such as a video codec chip, a chip in a video codec server, or a general-purpose graphics processing unit (GPU), the chip includes a first computing unit, a cache unit, a second computing unit, and a third computing unit. It should be noted that the aforementioned first computing unit, cache unit, second computing unit, and third computing unit are either virtual units or physical units, and this application does not impose any limitations on this. Figure 2 This is a schematic diagram illustrating the distortion calculation process provided in an exemplary embodiment of this application. Figure 2As shown, the first computing unit calculates the residual value between each pair of pixels occupying the same position in the original pixel block 201 and the predicted pixel block 202, resulting in a residual pixel block 203. The predicted pixel block 202 is obtained by predicting the original pixel block 201, for example, by intra-frame prediction and / or inter-frame prediction. The original pixel block 201 includes N×N pixels, where N is a positive integer. A pair of pixels occupying the same position includes the pixel located at a first position in the original pixel block 201 and the pixel also located at a first position in the predicted pixel block 202. The first position can be any position in the original pixel block 201 and the predicted pixel block 202. The residual value between pixels is used to reflect the difference between the pixel values ​​of the pixels. The caching unit caches sub-pixel blocks in the residual pixel block 203 according to a preset pixel block size 204, and outputs the pixel blocks in the sub-pixel blocks. The preset pixel block size 204 is smaller than the size of the residual pixel block 203, and the size of the residual pixel block 203 is the same as the size of the original pixel block 201 and the predicted pixel block 202. The second calculation unit calculates the distortion corresponding to the pixel blocks in the sub-pixel blocks of the residual pixel block 203, for example, calculating the SATD corresponding to the pixel blocks in the sub-pixel blocks of the residual pixel block 203. The third calculation unit calculates the distortion 206 corresponding to the original pixel block 201 and the predicted pixel block 202 based on the distortion corresponding to the pixel blocks in the sub-pixel blocks of the residual pixel block 203, for example, by calculating the sum of the distortion corresponding to all pixel blocks in all sub-pixel blocks of the residual pixel block 203, thereby obtaining the distortion 206 corresponding to the original pixel block 201 and the predicted pixel block 202.

[0052] In some embodiments, the preset pixel block size 204 is related to the size of the residual pixel block 203. For example, if the size of the residual pixel block 203 is equal to M×M, the preset pixel block size 204 is M×M / 2, and the size of the pixel blocks in the output sub-pixel blocks is M / 2×M / 2; if the size of the residual pixel block 203 is greater than M×M, the preset pixel block size 204 is N×M / 2, and the size of the pixel blocks in the output sub-pixel blocks is M / 2×M / 2. For example, for the case where the size of the residual pixel block 203 is 8×8: the preset pixel block size 204 is 8×4, the caching unit caches the sub-pixel blocks in the residual pixel block 203 according to the 8×4 pixel block size, and outputs the pixel blocks in the sub-pixel blocks. In some embodiments, the caching unit outputs the pixel blocks in the sub-pixel blocks according to the 4×4 pixel block size 205. The above process can be executed in a pipeline manner. For example, when the size of the residual pixel block 203 is greater than 8×8: the buffer unit includes a first sub-unit and a second sub-unit, and the preset pixel block size 204 is N×4, for example, the size of the residual pixel block 203 is 16×16, and the preset pixel block size 204 is 16×4. The first sub-unit buffers the first sub-pixel block in the residual pixel block 203 according to the 16×4 pixel block size and outputs the pixel block in the first sub-pixel block. The second sub-unit buffers the second sub-pixel block in the residual pixel block 203 according to the 16×4 pixel block size and outputs the pixel block in the second sub-pixel block. In some embodiments, the first sub-unit outputs the pixel block in the first sub-pixel block according to the 4×4 pixel block size 205, and the second sub-unit outputs the pixel block in the second sub-pixel block according to the 4×4 pixel block size 205. The above process can also be executed in a pipelined manner, and the first sub-unit and the second sub-unit can form a ping-pong buffer.

[0053] By using a preset pixel block size to cache sub-pixel blocks within the residual pixel block and then outputting the pixel blocks within those sub-pixel blocks, the distortion corresponding to the pixel blocks within those sub-pixel blocks can be calculated. This allows for the calculation of the distortion corresponding to both the original pixel block and the predicted pixel block. Since the preset pixel block size is smaller than the residual pixel block size, distortion calculation can be achieved by supporting the caching of pixel blocks smaller than the residual pixel block size, thereby reducing the hardware resource consumption for distortion calculation.

[0054] Figure 3 This is a flowchart illustrating a distortion calculation method provided in an exemplary embodiment of this application. This method can be used in chips, such as those used in video codec chips, chips in video codec servers, or GPUs for general-purpose graphics and video computing. Figure 3 As shown, the method includes:

[0055] Step 302: Calculate the residual value between each pair of pixels occupying the same position in the original pixel block and the predicted pixel block to obtain the residual pixel block.

[0056] In some embodiments, the chip calculates the residual value between each pair of pixels occupying the same position in the original pixel block and the predicted pixel block through a first computing unit to obtain the residual pixel block.

[0057] A raw pixel block is a block of pixels within a video frame. A raw pixel block comprises N×N pixels, where N is a positive integer. For example, a raw pixel block may include 4×4 pixels, 8×8 pixels, 16×16 pixels, 32×32 pixels, or 64×64 pixels.

[0058] Predicted pixel blocks are obtained by predicting original pixel blocks. In some embodiments, predicted pixel blocks are obtained by predicting original pixel blocks through intra-frame prediction and / or inter-frame prediction. Intra-frame prediction is used to process (eliminate) spatial redundancy in video frames, such as eliminating repetitive information caused by the continuity of local regions such as texture and color within the same frame. Inter-frame prediction is used to process (eliminate) temporal redundancy in video frames, such as eliminating the repetition of background, static objects, etc., between consecutive frames in a video frame sequence.

[0059] There is a one-to-one correspondence between pixels in the original pixel block and pixels in the predicted pixel block. A pair of pixels occupying the same position in the original and predicted pixel blocks includes a pixel at a first position in the original pixel block and a pixel at the same first position in the predicted pixel block. The first position can be any position in either the original or predicted pixel block. The residual value between pixels reflects the difference between pixel values, for example, determined by the difference between the pixel values ​​of pixels in the predicted pixel block and pixels in the original pixel block.

[0060] For example, taking the original pixel block as represented by O and the predicted pixel block as represented by P, the residual values ​​included in the residual pixel block can be represented as follows: .in, This represents the pixel value of the pixel in the i-th row and j-th column of the predicted pixel block. This represents the pixel value of the pixel in the i-th row and j-th column of the original pixel block.

[0061] Step 304: Cache the sub-pixel blocks in the residual pixel block according to the preset pixel block size, and output the pixel blocks in the sub-pixel block.

[0062] In some embodiments, the chip caches sub-pixel blocks in the residual pixel block according to a preset pixel block size through a cache unit, and outputs the pixel blocks in the sub-pixel block.

[0063] The preset pixel block size can be understood as the size of the pixel blocks that the cache unit supports caching, or as the number of pixels that the cache unit supports caching. In some embodiments, the preset pixel block size is related to the size of the residual pixel block. For example, if the size of the residual pixel block is equal to M×M, the preset pixel block size is M×M / 2; if the size of the residual pixel block is greater than M×M, the preset pixel block size is N×M / 2. Optionally, M equals 8.

[0064] The size of the preset pixel block is smaller than the size of the residual pixel block, the size of the sub-pixel blocks in the residual pixel block is smaller than the size of the residual pixel block, and the size of the preset pixel block is equal to the size of the sub-pixel blocks in the residual pixel block. In some embodiments, since the size of the preset pixel block is smaller than the size of the residual pixel block, the cache unit in this embodiment is smaller than the target cache in at least one aspect of hardware area, number of components, and hardware complexity. The target cache is a cache that supports storing (transposing) pixel blocks of size N×N.

[0065] In some embodiments, the caching unit includes multiple sub-units. Each sub-unit is used to cache sub-pixel blocks in the residual pixel block according to a preset pixel block size and output the pixel blocks in the sub-pixel block. Different sub-units are responsible for processing different sub-pixel blocks. It should be noted that in this case, the product of the preset pixel block size and the number of sub-units is less than the size of the residual pixel block. For example, if the size of the residual pixel block is 16×16, the caching unit includes 2 sub-units, the preset pixel block size is 16×4, and the product of the preset pixel block size and the number of sub-units, 16×8, is less than the size of the residual pixel block, 16×16.

[0066] In some embodiments, the size of the pixel blocks in a sub-pixel block is the same as the size of the sub-pixel block (i.e., the preset pixel block size), meaning the buffer unit outputs the entire sub-pixel block, thereby outputting the pixel blocks within the sub-pixel block. Alternatively, the size of the pixel blocks in a sub-pixel block is smaller than the size of the sub-pixel block (i.e., the preset pixel block size), meaning the buffer unit outputs multiple partial pixel blocks from the sub-pixel block, thereby outputting the pixel blocks within the sub-pixel block. These multiple partial pixel blocks can form a complete sub-pixel block.

[0067] Step 306: Calculate the distortion of the pixel blocks in the sub-pixel blocks.

[0068] In some embodiments, the chip calculates the distortion corresponding to the pixel block in the sub-pixel block through a second computing unit.

[0069] The distortion of a pixel block within a sub-pixel block reflects the degree of distortion of the pixel block corresponding to the pixel block in the predicted pixel block compared to the pixel block corresponding to the pixel block in the original pixel block.

[0070] In some embodiments, the second computing unit calculates the SATD corresponding to the pixel block in the sub-pixel block, thereby obtaining the distortion corresponding to the pixel block in the sub-pixel block.

[0071] Step 308: Calculate the distortion of the original pixel block and the predicted pixel block based on the distortion of the pixel block in the sub-pixel block.

[0072] In some embodiments, the chip uses a third computing unit to calculate the distortion of the original pixel block and the predicted pixel block based on the distortion of the pixel block in the sub-pixel block.

[0073] The distortion values ​​corresponding to the original pixel block and the predicted pixel block are used to reflect the degree of distortion of the predicted pixel block compared to the original pixel block. In some embodiments, the third calculation unit obtains the distortion values ​​corresponding to the original pixel block and the predicted pixel block by accumulating the distortion values ​​corresponding to each pixel block in each sub-pixel block. For example, the third calculation unit obtains the distortion values ​​corresponding to the original pixel block and the predicted pixel block by calculating the sum of the distortion values ​​corresponding to all pixel blocks in all sub-pixel blocks of the residual pixel block.

[0074] It should be noted that the first computing unit, cache unit, second computing unit and third computing unit mentioned above are virtual units or physical units, and the embodiments of this application do not limit them.

[0075] In some embodiments, when the first computing unit, cache unit, second computing unit, and third computing unit are physical units, the first computing unit is electrically connected to the cache unit, the cache unit is electrically connected to the second computing unit, and the second computing unit is electrically connected to the third computing unit. The first computing unit is equivalent to / can be replaced by a residual calculation unit, the cache unit is equivalent to / can be replaced by a cache remapping buffer unit, the second computing unit is equivalent to / can be replaced by a 4×4 two-dimensional Hadamard 2-D computing unit, and the third computing unit is equivalent to / can be replaced by an Asum unit.

[0076] In summary, the method provided in this embodiment caches sub-pixel blocks in the residual pixel block using a preset pixel block size and outputs the pixel blocks in the sub-pixel block, thereby calculating the distortion corresponding to the pixel blocks in the sub-pixel block, and thus calculating the distortion corresponding to the original pixel block and the predicted pixel block. Since the preset pixel block size is smaller than the size of the residual pixel block, distortion calculation can be achieved by supporting the caching of pixel blocks smaller than the residual pixel block size, thereby reducing the hardware resource consumption of distortion calculation.

[0077] Figure 4This is a flowchart illustrating another method for calculating distortion provided in an exemplary embodiment of this application. This method can be used in chips, such as those used in video codec chips, chips in video codec servers, or GPUs for general-purpose graphics and video computing. Figure 4 As shown, the method includes:

[0078] Step 402: Calculate the residual value between each pair of pixels occupying the same position in the original pixel block and the predicted pixel block to obtain the residual pixel block.

[0079] In some embodiments, the chip calculates the residual value between each pair of pixels occupying the same position in the original pixel block and the predicted pixel block through a first computing unit to obtain the residual pixel block.

[0080] A raw pixel block is a block of pixels within a video frame, comprising N×N pixels, where N is a positive integer. Predicted pixel blocks are obtained by predicting the raw pixel blocks. In some embodiments, predicted pixel blocks are obtained by predicting the raw pixel blocks using intra-frame prediction and / or inter-frame prediction.

[0081] A pair of pixels occupying the same position in the original pixel block and the predicted pixel block includes a pixel located at a first position in the original pixel block and a pixel also located at a first position in the predicted pixel block. The first position can be any position in either the original pixel block or the predicted pixel block. The residual value between pixels is used to reflect the difference between the pixel values ​​of the pixels.

[0082] In some embodiments, the first computing unit divides the process of calculating the residual value into N cycles, using a row-scanning method, to calculate the residual value between each pair of pixels occupying the same position in the original pixel block and the predicted pixel block. For example, in the first cycle, the first computing unit calculates the residual value between each pair of pixels occupying the same position in the first row of pixels in the original pixel block and the predicted pixel block; in the Nth cycle, the first computing unit calculates the residual value between each pair of pixels occupying the same position in the Nth row of pixels in the original pixel block and the predicted pixel block.

[0083] Step 404: Cache the sub-pixel blocks in the residual pixel block according to the pixel block size of M×M / 2, and output the pixel blocks in the sub-pixel block.

[0084] In some embodiments, the chip caches sub-pixel blocks in the residual pixel block according to the pixel block size of M×M / 2 through a cache unit, and outputs the pixel blocks in the sub-pixel block.

[0085] The pixel block size of M×M / 2 is a preset pixel block size. The preset pixel block size can be understood as the size of the pixel blocks that the cache unit supports caching, or as the number of pixels that the cache unit supports caching. In some embodiments, the preset pixel block size is related to the size of the residual pixel block.

[0086] When the size of the residual pixel block is equal to M×M, the cache unit caches the sub-pixel blocks in the residual pixel block according to a pixel block size of M×M / 2, and outputs the pixel blocks in the sub-pixel blocks. Here, M is a positive integer. In some embodiments, M equals 8. In some embodiments, since the preset pixel block size (M×M / 2) is smaller than the size of the residual pixel block (N×N), the cache unit in this embodiment is smaller than the target cache in at least one aspect: hardware area, number of components, and hardware complexity. The target cache is a cache that supports storing pixel blocks of size N×N.

[0087] In some embodiments, the size of the pixel blocks within a sub-pixel block is the same as the size of the sub-pixel block; that is, the buffer unit outputs the entire sub-pixel block, thereby achieving the output of pixel blocks within the sub-pixel block. Alternatively, the size of the pixel blocks within a sub-pixel block is smaller than the size of the sub-pixel block; that is, the buffer unit outputs multiple partial pixel blocks within the sub-pixel block, thereby achieving the output of pixel blocks within the sub-pixel block. These multiple partial pixel blocks can form a complete sub-pixel block.

[0088] Optionally, the buffer unit buffers sub-pixel blocks from the residual pixel block according to a pixel block size of M×M / 2, and outputs pixel blocks from the sub-pixel block according to a pixel block size of M / 2×M / 2. For example, the residual pixel block size is 8×8, and the preset pixel block size is 8×4. The buffer unit buffers sub-pixel blocks from the residual pixel block according to an 8×4 pixel block size, and outputs pixel blocks from the sub-pixel block according to a 4×4 pixel block size. In this case, the buffer unit can output 16 pixels from the residual pixel block per clock cycle.

[0089] In some embodiments, the caching unit employs a pipeline approach, caching sub-pixel blocks within a residual pixel block of size M×M / 2, and outputting pixel blocks within the sub-pixel block of size M / 2×M / 2. For example, the caching unit caches one sub-pixel block from the residual pixel block in the row direction (horizontal direction) of size M×M / 2, and outputs pixel blocks within a sub-pixel block of size M / 2×M / 2. If all pixel blocks within the aforementioned sub-pixel block are output in size M / 2×M / 2, the caching unit continues to cache the next sub-pixel block corresponding to the aforementioned sub-pixel block, and outputs pixel blocks within the next sub-pixel block of size M / 2×M / 2. The aforementioned sub-pixel block can be any pixel block within the residual pixel block, and the next sub-pixel block is either the pixel block adjacent to the aforementioned sub-pixel block in the row direction, or the first pixel block in the next row of sub-pixel blocks of the aforementioned sub-pixel block.

[0090] In some embodiments, the cache unit in this application is SRAM.

[0091] Step 406: Cache the first sub-pixel block in the residual pixel block according to the pixel block size of N×M / 2, and output the pixel block in the first sub-pixel block; and cache the second sub-pixel block in the residual pixel block according to the pixel block size of N×M / 2, and output the pixel block in the second sub-pixel block.

[0092] In some embodiments, the chip caches the first sub-pixel block in the residual pixel block according to the pixel block size of N×M / 2 through the first sub-unit and outputs the pixel block in the first sub-pixel block; and caches the second sub-pixel block in the residual pixel block according to the pixel block size of N×M / 2 through the second sub-unit and outputs the pixel block in the second sub-pixel block.

[0093] The pixel block size of N×M / 2 is the preset pixel block size. The preset pixel block size can be understood as the size of the pixel blocks that the cache unit supports caching, or as the number of pixels that the cache unit supports caching. In some embodiments, the preset pixel block size is related to the size of the residual pixel block.

[0094] When the size of the residual pixel block is greater than M×M, the cache unit includes a first sub-unit and a second sub-unit, where M is a positive integer. The first sub-unit caches the first sub-pixel block in the residual pixel block according to a pixel block size of N×M / 2 and outputs the pixel block in the first sub-pixel block; the second sub-unit caches the second sub-pixel block in the residual pixel block according to a pixel block size of N×M / 2 and outputs the pixel block in the second sub-pixel block. The first sub-pixel block and the second sub-pixel block are different sub-pixel blocks in the residual pixel block. In some embodiments, M equals 8. In some embodiments, since the preset pixel block size (N×M / 2) is smaller than the size of the residual pixel block (N×N), the cache unit (the whole composed of the first and second sub-units) in this embodiment is smaller than the target cache in at least one aspect: hardware area, number of components, and hardware complexity. The target cache is a cache that supports storing pixel blocks of size N×N.

[0095] In some embodiments, the size of the pixel blocks in the first sub-pixel block is the same as the size of the first sub-pixel block, that is, the first sub-unit outputs the entire first sub-pixel block, thereby achieving the output of the pixel blocks in the first sub-pixel block; the size of the pixel blocks in the second sub-pixel block is the same as the size of the second sub-pixel block, that is, the second sub-unit outputs the entire second sub-pixel block, thereby achieving the output of the pixel blocks in the second sub-pixel block. Alternatively, the size of the pixel blocks in the first sub-pixel block is smaller than the size of the first sub-pixel block, that is, the first sub-unit outputs multiple partial pixel blocks in the first sub-pixel block, thereby achieving the output of the pixel blocks in the first sub-pixel block, and the multiple partial pixel blocks in the first sub-pixel block can form a complete first sub-pixel block; the size of the pixel blocks in the second sub-pixel block is smaller than the size of the second sub-pixel block, that is, the second sub-unit outputs multiple partial pixel blocks in the second sub-pixel block, thereby achieving the output of the pixel blocks in the second sub-pixel block, and the multiple partial pixel blocks in the second sub-pixel block can form a complete second sub-pixel block.

[0096] Optionally, the first sub-unit caches the first sub-pixel block in the residual pixel block with a pixel block size of N×M / 2, and outputs the pixel block in the first sub-pixel block with a pixel block size of M / 2×M / 2; the second sub-unit caches the second sub-pixel block in the residual pixel block with a pixel block size of N×M / 2, and outputs the pixel block in the second sub-pixel block with a pixel block size of M / 2×M / 2. For example, the size of the residual pixel block is 16×16, and the preset pixel block size is 16×4. The first sub-unit caches the first sub-pixel block in the residual pixel block with a pixel block size of 16×4, and outputs the pixel block in the first sub-pixel block with a pixel block size of 4×4; the second sub-unit caches the second sub-pixel block in the residual pixel block with a pixel block size of 16×4, and outputs the pixel block in the second sub-pixel block with a pixel block size of 4×4.

[0097] In some embodiments, the first sub-pixel block belongs to a first row of pixel blocks in the residual pixel block, and the second sub-pixel block belongs to a second row of pixel blocks in the residual pixel block. The first and second pixel blocks include a row of sub-pixel blocks in the residual pixel block, the first and second pixel blocks are different, and the first and second pixel blocks are adjacent in the residual pixel block.

[0098] In some embodiments, the first and second sub-units in this application are SRAM. The first and second sub-units can form a ping-pong buffer.

[0099] For example, Figure 5 This is a schematic diagram of a cache unit provided in an exemplary embodiment of this application. Figure 5 As shown, the cache unit 501 includes a first sub-unit (Ping SRAM) 5011 and a second sub-unit (Pong SRAM) 5012. The residual pixel block 502 has a size of 16×16. During the process of caching and outputting the sub-pixel blocks in the residual pixel block 502, the first sub-unit 5011 and the second sub-unit 5012 cache the pixels in the residual pixel block 502 in the row direction. The first sub-unit 5011 remaps the cached pixels (16×4) to 4×4 pixel blocks in the first sub-pixel block in the row direction for output, and the second sub-unit 5012 remaps the cached pixels (16×4) to 4×4 pixel blocks in the second sub-pixel block in the row direction for output. The 4×4 pixel blocks in the first and third rows of the residual pixel block 502 are output by the first sub-unit 5011, and the 4×4 pixel blocks in the second and fourth rows of the residual pixel block 502 are output by the second sub-unit 5012.

[0100] In some embodiments, the first and second sub-units employ a pipelined approach, caching sub-pixel blocks from the residual pixel block in a pixel block size of N×M / 2, and outputting pixel blocks from the sub-pixel block in a pixel block size of M / 2×M / 2. For example, the first sub-unit caches a first sub-pixel block from the residual pixel block in the row direction in a pixel block size of N×M / 2, and outputs pixel blocks from the first sub-pixel block in a pixel block size of M / 2×M / 2. After outputting all pixel blocks from the aforementioned first sub-pixel block in a pixel block size of M / 2×M / 2, the first sub-unit continues to cache the next first sub-pixel block corresponding to the aforementioned first sub-pixel block. The second sub-unit caches a second sub-pixel block from the residual pixel block in the row direction in a pixel block size of N×M / 2, and outputs pixel blocks from the second sub-pixel block in a pixel block size of M / 2×M / 2. When outputting all pixels in a second sub-pixel block of size M / 2×M / 2, the second sub-unit continues to cache the next second sub-pixel block corresponding to the aforementioned second sub-pixel block. The first and second sub-units can synchronously cache sub-pixel blocks and output pixels within sub-pixel blocks. Alternatively, when the first sub-unit caches the first sub-pixel block, the second sub-unit outputs pixels within the second sub-pixel block, and when the first sub-unit outputs pixels within the first sub-pixel block, the second sub-unit caches the second sub-pixel block.

[0101] It should be noted that steps 404 and 406 are parallel steps, meaning that when implementing the method provided in this application embodiment, one of steps 404 and 406 can be selected for execution. Furthermore, the hardware architectures corresponding to steps 404 and 406 can be different, as shown in the relevant accompanying drawings.

[0102] Step 408: Calculate the distortion of the pixel blocks in the sub-pixel blocks.

[0103] In some embodiments, the chip calculates the distortion corresponding to the pixel block in the sub-pixel block through a second computing unit.

[0104] The distortion of a pixel block within a sub-pixel block reflects the degree of distortion of the pixel block corresponding to the pixel block in the predicted pixel block compared to the pixel block corresponding to the pixel block in the original pixel block.

[0105] In some embodiments, the second computing unit calculates the SATD corresponding to the pixel block in the sub-pixel block, thereby obtaining the distortion corresponding to the pixel block in the sub-pixel block.

[0106] Step 410: Calculate the distortion of the original pixel block and the predicted pixel block based on the distortion of the pixel block in the sub-pixel block.

[0107] In some embodiments, the chip uses a third computing unit to calculate the distortion of the original pixel block and the predicted pixel block based on the distortion of the pixel block in the sub-pixel block.

[0108] The distortion values ​​corresponding to the original pixel block and the predicted pixel block are used to reflect the degree of distortion of the predicted pixel block compared to the original pixel block. In some embodiments, the third calculation unit obtains the distortion values ​​corresponding to the original pixel block and the predicted pixel block by accumulating the distortion values ​​corresponding to each pixel block in each sub-pixel block. For example, the third calculation unit obtains the distortion values ​​corresponding to the original pixel block and the predicted pixel block by calculating the sum of the distortion values ​​corresponding to all pixel blocks in all sub-pixel blocks of the residual pixel block.

[0109] Taking a residual pixel block size of 8×8 and a preset pixel block size of 8×4 as an example. Figure 6 This is another hardware architecture diagram for computing an 8×8 SATD, provided as an exemplary embodiment of this application. Figure 6 As shown, the first calculation unit 601 calculates the residual value between each pair of pixels occupying the same position in the original pixel block and the predicted pixel block, obtaining the residual pixel block. The caching unit 602 caches the sub-pixel blocks in the residual pixel block according to an 8×4 pixel block size, and outputs the pixel blocks in the sub-pixel blocks according to a 4×4 pixel block size. The second calculation unit 603 calculates the SATD corresponding to the pixel blocks in the sub-pixel blocks. The third calculation unit 604 calculates the sum of the SATD corresponding to all pixel blocks in all sub-pixel blocks, obtaining the distortion corresponding to the original pixel block and the predicted pixel block.

[0110] It should be noted that the first computing unit, cache unit, second computing unit and third computing unit mentioned above are virtual units or physical units, and the embodiments of this application do not limit them.

[0111] In summary, the method provided in this embodiment caches sub-pixel blocks in the residual pixel block using a preset pixel block size and outputs the pixel blocks in the sub-pixel block, thereby calculating the distortion corresponding to the pixel blocks in the sub-pixel block, and thus calculating the distortion corresponding to the original pixel block and the predicted pixel block. Since the preset pixel block size is smaller than the size of the residual pixel block, distortion calculation can be achieved by supporting the caching of pixel blocks smaller than the residual pixel block size, thereby reducing the hardware resource consumption of distortion calculation.

[0112] The method provided in this embodiment further reduces the hardware resource consumption for distortion calculation by caching sub-pixel blocks in the residual pixel block according to an M×M / 2 pixel block size to calculate the distortion corresponding to the original pixel block and the predicted pixel block. This reduces the hardware resource consumption for distortion calculation even for smaller residual pixel blocks. By caching sub-pixel blocks in the residual pixel block according to an N×M / 2 pixel block size to calculate the distortion corresponding to the original pixel block and the predicted pixel block, this reduces the hardware resource consumption for distortion calculation while maintaining computational efficiency even for larger residual pixel blocks. By outputting pixel blocks in the sub-pixel block according to an M / 2×M / 2 pixel block size to calculate the distortion, the distortion calculation process becomes more flexible, simpler, and has lower latency.

[0113] The method provided in this application proposes a hardware-based method for calculating video encoding / decoding distortion. It mainly includes two points: first, for residual pixel blocks of various sizes, different registers (buffer units) are used to buffer remapping, and output in a pipelined manner in 4×4 pixel blocks; second, regardless of the size of the residual pixel blocks, a 4×4 Hadamard transform SATD architecture is used. The distortion calculation process is described below.

[0114] The first step is residual calculation: the calculation unit is the input original pixel block and the predicted pixel block. Due to throughput limitations, the two pixel blocks are split into N cycles for processing in a row scanning manner, and the residual value between each pixel point of the two is calculated to obtain the residual pixel block.

[0115] The second step is cache remapping: the residual values ​​(pixels in the residual pixel blocks) arranged in an N×N row-scanning manner are rearranged, and SRAM (Simplified Chinese RAM) is used to cache the residual values. The data is then output in 4×4 pixel blocks, with 16 pixels from each residual pixel block output per clock cycle. For 8×8 residual pixel blocks, only 8×4 pixel SRAM is needed. When the SRAM is full of output data, the remaining residual pixels are stored in empty SRAM slots, increasing SRAM utilization and reducing hardware area usage. Compared to the 8×8 pixel SRAM used in the commonly used SATD method, this saves nearly half the hardware area. For residual pixel blocks larger than 8×8, a ping-pong cache composed of two N×4 pixel SRAMs is used to achieve seamless continuous data processing, avoid read / write conflicts, and reduce pipeline stalls. Taking a 16×16 residual pixel block as an example, only two 16×4 pixel SRAMs are needed to complete the pipeline output of converting row-arranged pixel blocks into 4×4 pixel blocks. Compared with the 16×16 pixel SRAM used in the commonly used SATD method, it saves about half the area. Moreover, when the residual pixel block is increased to 32×32, the SRAM area used is only 1 / 4 of that of a 32×32 pixel SRAM. The larger the residual pixel block, the more significant the hardware area optimization advantage becomes.

[0116] The third step is the 4×4 Hadamard transform: The calculation of the 4×4 two-dimensional Hadamard transform is shown in formula (6):

[0117] (6)

[0118] The 4×4 two-dimensional transformation is broken down into two levels of one-dimensional operations, row-first and column-second. Since the data in the coefficient matrix are all positive and negative 1, they are simplified to addition and subtraction. Performing four transformations on each row in parallel horizontally yields the row transformation matrix HT, as shown in formula (7):

[0119] (7)

[0120] in , The calculations for the remaining data will not be elaborated here. Furthermore, each column of HT is transformed four times in parallel along the vertical direction to obtain the column transformation matrix VT, as shown in formula (8):

[0121] (8)

[0122] in , The calculations for the remaining data will not be elaborated here. Finally, the absolute values ​​of each element in the VT matrix are summed to obtain the SATD value of a 4×4 pixel block. The values ​​of each element in the row transformation matrix HT and the column transformation matrix VT are calculated in parallel. The entire 4×4 SATD calculation process can be completed within one clock cycle, which is simpler, requires fewer computational resources, and offers better performance compared to 8×8 and 16×16 Hadamard transform calculations.

[0123] The fourth step is SATD value accumulation: The SATD value of the 4×4 pixel block output by the pipeline is obtained in the third step. The SATD values ​​of all 4×4 pixel blocks divided by the N×N residual pixel block need to be accumulated to obtain the final SATD value of the current N×N residual pixel block. This step only requires one clock cycle.

[0124] The method provided in this application has at least the following beneficial effects:

[0125] 1. For residual pixel blocks of various sizes, the 4×4 Hadamard architecture SATD is adopted, which is more flexible, simple to calculate, has low latency, and requires less computing resources;

[0126] 2. Compared with the current N×N pixel size memory buffer module, the buffer module required in this application has a smaller memory area and adopts ping-pong buffer to realize pipelined processing, resulting in low latency and good performance;

[0127] In summary, this application achieves both computational accuracy and low hardware resource consumption, enabling faster calculation of SATD distortion for residual pixel blocks of different sizes.

[0128] It should be noted that this application may display prompt interfaces, pop-ups, or output voice prompts before and during the collection of user data. These prompt interfaces, pop-ups, or voice prompts are used to inform the user that their data is being collected. This ensures that the application only begins the steps for collecting user data after receiving confirmation from the user regarding the prompt interface or pop-up; otherwise (i.e., without user confirmation), the steps for collecting user data end, meaning no user data is collected. In other words, all user data collected in this application is collected with the user's consent and authorization, and the collection, use, and processing of related user data must comply with the relevant laws, regulations, and standards of the relevant countries and regions.

[0129] It should be noted that the order of the method steps provided in the embodiments of this application can be appropriately adjusted, and the steps can also be added or removed as appropriate. Any method variations that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application, and therefore will not be elaborated further.

[0130] Figure 7 This is a schematic diagram of the structure of a chip 700 provided in an exemplary embodiment of this application. The chip 700 includes a first computing unit 701, a cache unit 702, a second computing unit 703, and a third computing unit 704.

[0131] The first calculation unit 701 is used to calculate the residual value between each pair of pixels occupying the same position in the original pixel block and the predicted pixel block to obtain the residual pixel block. The predicted pixel block is obtained by predicting the original pixel block. The original pixel block includes N×N pixels, where N is a positive integer.

[0132] The cache unit 702 is used to cache the sub-pixel blocks in the residual pixel block according to a preset pixel block size, and output the pixel blocks in the sub-pixel blocks, wherein the preset pixel block size is smaller than the size of the residual pixel block;

[0133] The second calculation unit 703 is used to calculate the distortion corresponding to the pixel block in the sub-pixel block;

[0134] The third calculation unit 704 is used to calculate the distortion corresponding to the original pixel block and the predicted pixel block based on the distortion corresponding to the pixel block in the sub-pixel block.

[0135] In an optional design, the size of the residual pixel block is equal to M×M, where M is a positive integer;

[0136] The cache unit 702 is used to cache the sub-pixel blocks in the residual pixel block according to the pixel block size of M×M / 2, and output the pixel blocks in the sub-pixel block.

[0137] In an optional design, the cache unit 702 is used to cache sub-pixel blocks in the residual pixel block according to a pixel block size of M×M / 2, and output pixel blocks in the sub-pixel block according to a pixel block size of M / 2×M / 2.

[0138] In an optional design, the caching unit 702 is configured to cache one sub-pixel block of the residual pixel block according to the row direction with a pixel block size of M×M / 2, and output the pixel blocks in the sub-pixel block according to the pixel block size of M / 2×M / 2; and if all the pixel blocks in the sub-pixel block are output, continue to cache the next sub-pixel block corresponding to the sub-pixel block.

[0139] In an optional design, the size of the residual pixel block is greater than M×M, such as... Figure 8 As shown, the cache unit 702 includes a first subunit 7021 and a second subunit 7022, where M is a positive integer;

[0140] The first sub-unit 7021 is configured to cache the first sub-pixel block in the residual pixel block according to a pixel block size of N×M / 2, and output the pixel block in the first sub-pixel block; the second sub-unit 7022 is configured to cache the second sub-pixel block in the residual pixel block according to a pixel block size of N×M / 2, and output the pixel block in the second sub-pixel block.

[0141] In an optional design, the first sub-unit 7021 is configured to cache the first sub-pixel block in the residual pixel block according to a pixel block size of N×M / 2, and output the pixel block in the first sub-pixel block according to a pixel block size of M / 2×M / 2; the second sub-unit 7022 is configured to cache the second sub-pixel block in the residual pixel block according to a pixel block size of N×M / 2, and output the pixel block in the second sub-pixel block according to a pixel block size of M / 2×M / 2.

[0142] In an optional design, the first sub-pixel block belongs to the first pixel block row in the residual pixel block, and the second sub-pixel block belongs to the second pixel block row in the residual pixel block;

[0143] The first pixel block row and the second pixel block row include a row of sub-pixel blocks in the residual pixel block, and the first pixel block row and the second pixel block row are adjacent in the residual pixel block.

[0144] In an optional design, the second calculation unit 703 is used to calculate the SATD corresponding to the pixel block in the sub-pixel block to obtain the distortion corresponding to the pixel block in the sub-pixel block.

[0145] In an optional design, the third calculation unit 704 is used to calculate the sum of the distortions corresponding to all pixel blocks in all sub-pixel blocks, to obtain the distortions corresponding to the original pixel block and the predicted pixel block.

[0146] It should be noted that the chip provided in the above embodiments is only an example of the division of the above functional modules. In practical applications, the above functions can be assigned to different units as needed, that is, the internal structure of the chip can be divided into different units to complete all or part of the functions described above. In addition, the chip provided in the above embodiments and the distortion calculation method embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0147] Embodiments of this application also provide an electronic device, the electronic device comprising, as follows: Figure 7 or Figure 8 The chip shown. For example, Figure 9 This is a structural block diagram of an electronic device 900 provided in an exemplary embodiment of this application.

[0148] Typically, electronic device 900 includes a processor 910 and a memory 920.

[0149] Processor 910 may include one or more processing cores, such as a quad-core processor or a nine-core processor. Processor 910 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field Programmable Gate Array), and PLA (Programmable Logic Array). Processor 910 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 910 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 910 may also include an Artificial Intelligence (AI) processor, which is used to handle computational operations related to machine learning.

[0150] The memory 920 may include one or more computer-readable storage media, which may be non-transitory. The memory 920 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 920 are used to store a computer program configured to be executed by one or more processors to implement the above-described distortion calculation method.

[0151] Those skilled in the art will understand that Figure 9 The structure shown does not constitute a limitation on the electronic device 900, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0152] It should be understood that "multiple" as used herein refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship. "Greater than or equal to" as used herein can mean greater than or equal to, or greater than; "less than or equal to" can mean less than or equal to. Furthermore, the step numbers described herein are merely illustrative of one possible execution order. In some other embodiments, the steps may not be executed in the order shown in the numbers, such as two steps with different numbers being executed simultaneously, or two steps with different numbers being executed in the reverse order of the illustration. This application does not limit this.

[0153] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent switching, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for calculating distortion, characterized in that, The method includes: The residual value between each pair of pixels occupying the same position in the original pixel block and the predicted pixel block is calculated to obtain the residual pixel block. The predicted pixel block is obtained by predicting the original pixel block, which includes N×N pixels, where N is a positive integer. When the size of the residual pixel block is equal to M×M, the sub-pixel blocks in the residual pixel block are cached according to the pixel block size of M×M / 2, and the pixel blocks in the sub-pixel blocks are output. The pixel block size of M×M / 2 is the size of the pixel blocks that the cache unit supports caching, and M is a positive integer. When the size of the residual pixel block is greater than M×M, the first sub-pixel block in the residual pixel block is cached according to a pixel block size of N×M / 2, and the pixel block in the first sub-pixel block is output; and the second sub-pixel block in the residual pixel block is cached according to a pixel block size of N×M / 2, and the pixel block in the second sub-pixel block is output, where the pixel block size of N×M / 2 is the size of the pixel block that the sub-unit of the cache unit supports caching; Calculate the distortion corresponding to the pixel block in the sub-pixel block; The distortion of the original pixel block and the predicted pixel block is calculated based on the distortion of the pixel block in the sub-pixel block.

2. The method according to claim 1, characterized in that, The step of caching sub-pixel blocks in the residual pixel block according to a pixel block size of M×M / 2 and outputting the pixel blocks in the sub-pixel block includes: The sub-pixel blocks in the residual pixel block are cached according to a pixel block size of M×M / 2, and the pixel blocks in the sub-pixel block are output according to a pixel block size of M / 2×M / 2.

3. The method according to claim 2, characterized in that, The step of caching sub-pixel blocks in the residual pixel block according to a pixel block size of M×M / 2, and outputting pixel blocks in the sub-pixel block according to a pixel block size of M / 2×M / 2, includes: Based on a pixel block size of M×M / 2, a sub-pixel block is cached in the row direction of the residual pixel block, and the pixel block in the sub-pixel block is output according to a pixel block size of M / 2×M / 2. If all pixels in a sub-pixel block are output, the next sub-pixel block corresponding to that sub-pixel block is cached.

4. The method according to claim 1, characterized in that, The first sub-pixel block in the residual pixel block is cached according to a pixel block size of N×M / 2, and the pixel block in the first sub-pixel block is output. And, according to a pixel block size of N×M / 2, cache the second sub-pixel block in the residual pixel block, and output the pixel block in the second sub-pixel block, including: The first sub-pixel block in the residual pixel block is cached according to a pixel block size of N×M / 2, and the pixel block in the first sub-pixel block is output according to a pixel block size of M / 2×M / 2; And cache the second sub-pixel block in the residual pixel block according to the pixel block size of N×M / 2, and output the pixel block in the second sub-pixel block according to the pixel block size of M / 2×M / 2.

5. The method according to claim 1, characterized in that, The first sub-pixel block belongs to the first pixel block row in the residual pixel block, and the second sub-pixel block belongs to the second pixel block row in the residual pixel block; The first pixel block row and the second pixel block row include a row of sub-pixel blocks in the residual pixel block, and the first pixel block row and the second pixel block row are adjacent in the residual pixel block.

6. The method according to any one of claims 1 to 5, characterized in that, The calculation of the distortion corresponding to the pixel block in the sub-pixel block includes: Calculate the transformed absolute difference and SATD corresponding to the pixel blocks in the sub-pixel block to obtain the distortion corresponding to the pixel blocks in the sub-pixel block.

7. The method according to any one of claims 1 to 5, characterized in that, The step of calculating the distortion corresponding to the original pixel block and the predicted pixel block based on the distortion corresponding to the pixel block in the sub-pixel block includes: The sum of the distortion values ​​corresponding to all pixel blocks in all sub-pixel blocks is calculated to obtain the distortion values ​​corresponding to the original pixel block and the predicted pixel block.

8. A chip, characterized in that, The chip includes: The first calculation unit is used to calculate the residual value between each pair of pixels occupying the same position in the original pixel block and the predicted pixel block to obtain the residual pixel block. The predicted pixel block is obtained by predicting the original pixel block. The original pixel block includes N×N pixels, where N is a positive integer. A caching unit is used to cache sub-pixel blocks in the residual pixel block with a pixel block size of M×M / 2 when the size of the residual pixel block is equal to M×M, and output the pixel blocks in the sub-pixel block. The pixel block size of M×M / 2 is the size of the pixel block that the caching unit supports caching, and M is a positive integer. When the size of the residual pixel block is greater than M×M, the caching unit includes a first sub-unit and a second sub-unit; the first sub-unit is used to cache a first sub-pixel block in the residual pixel block according to a pixel block size of N×M / 2, and output the pixel block in the first sub-pixel block; the second sub-unit is used to cache a second sub-pixel block in the residual pixel block according to a pixel block size of N×M / 2, and output the pixel block in the second sub-pixel block, where the pixel block size of N×M / 2 is the size of the pixel block that the first sub-unit and the second sub-unit support caching; The second calculation unit is used to calculate the distortion corresponding to the pixel block in the sub-pixel block; The third calculation unit is used to calculate the distortion corresponding to the original pixel block and the predicted pixel block based on the distortion corresponding to the pixel block in the sub-pixel block.

9. The chip according to claim 8, characterized in that, The buffer unit is used to buffer the sub-pixel blocks in the residual pixel block according to a pixel block size of M×M / 2, and output the pixel blocks in the sub-pixel block according to a pixel block size of M / 2×M / 2.

10. The chip according to claim 9, characterized in that, The caching unit is configured to cache one sub-pixel block of the residual pixel block according to the row direction with a pixel block size of M×M / 2, and output the pixel blocks in the sub-pixel block according to the pixel block size of M / 2×M / 2; when all pixel blocks in the sub-pixel block are output, the next sub-pixel block corresponding to the sub-pixel block is cached.

11. The chip according to claim 8, characterized in that, The first sub-unit is configured to cache the first sub-pixel block in the residual pixel block according to a pixel block size of N×M / 2, and output the pixel block in the first sub-pixel block according to a pixel block size of M / 2×M / 2; The second sub-unit is used to cache the second sub-pixel block in the residual pixel block according to a pixel block size of N×M / 2, and output the pixel block in the second sub-pixel block according to a pixel block size of M / 2×M / 2.

12. The chip according to claim 8, characterized in that, The first sub-pixel block belongs to the first pixel block row in the residual pixel block, and the second sub-pixel block belongs to the second pixel block row in the residual pixel block; The first pixel block row and the second pixel block row include a row of sub-pixel blocks in the residual pixel block, and the first pixel block row and the second pixel block row are adjacent in the residual pixel block.

13. The chip according to any one of claims 8 to 12, characterized in that, The second calculation unit is used to calculate the SATD corresponding to the pixel block in the sub-pixel block, and obtain the distortion corresponding to the pixel block in the sub-pixel block.

14. The chip according to any one of claims 8 to 12, characterized in that, The third calculation unit is used to calculate the sum of the distortion values ​​corresponding to all pixel blocks in all sub-pixel blocks, and obtain the distortion values ​​corresponding to the original pixel block and the predicted pixel block.

15. An electronic device, characterized in that, The electronic device includes the chip as described in any one of claims 8 to 14.

Images