Electron beam deflection scanning driver system

Abstract

The application discloses an electron beam deflection scanning driver system, which comprises a master control system, an FPGA, a precision reference source, a multi-stage DAC circuit, a power amplification module, an upper deflection coil and a lower deflection coil; the master control system is connected to an input port of the FPGA and transmits scanning control instructions and coordinate data; the FPGA is connected to a digital input port of the multi-stage DAC circuit and outputs digitized voltage setting values; an analog output port of the multi-stage DAC circuit is connected to an input terminal of the power amplification module and transmits a precision voltage signal to be amplified; one output end of the power amplification module is connected to the upper deflection coil, and the other output end of the power amplification module is connected to the lower deflection coil; the precision reference source is directly connected to the multi-stage DAC circuit and provides a high-stability voltage reference. The application can reduce aberration of a focused electron beam and obtain higher scanning accuracy.

Description

Technical Field

[0001] This invention relates to an electron beam scanning driver, and more specifically to an electron beam deflection scanning driver system. Background Technology

[0002] CDSEM is based on scanning electron microscopy (SEM) technology. It uses a focused electron beam to bombard the surface of a sample in a planar scanning manner. After the electron beam bombards the sample, it excites secondary electrons and backscattered electrons. These signals are received by a specific detector and converted into a grayscale image, displaying the surface morphology of the sample. Image processing algorithms are used to extract key parameters such as linewidth to achieve the detection function. During CDSEM operation, the focused electron beam needs to be scanned uniformly and smoothly onto the sample surface. The degree of electron beam aberration and the accuracy of the scan greatly affect the electron beam deflection, thus affecting the final detection results. Therefore, a high-precision electron beam deflection scanning driver that can reduce aberrations is needed to obtain accurate detection results.

[0003] An electron beam scanning driver uses current excitation to drive a pair of magnetic coils perpendicular to each other. The current passing through the magnetic coils causes the focused electron beam to deflect. In the prior art, the low operating frequency of the electron beam scanning driver leads to low scanning efficiency, and it is difficult to achieve precise control of the electron beam deflection, which cannot reduce the aberrations of the focused electron beam and will lead to deviations in the measurement results. Summary of the Invention

[0004] In view of the technical problems existing in the prior art, the present invention provides an electron beam deflection scanning driver system that reduces the aberrations of the focused electron beam and obtains higher scanning accuracy.

[0005] To solve the above-mentioned technical problems, the technical solution proposed by this invention is as follows:

[0006] An electron beam deflection scanning driver system includes a main control system, an FPGA, a precision reference source, a multi-stage DAC circuit, a power amplifier module, an upper deflection coil, and a lower deflection coil;

[0007] The main control system is connected to the input port of the FPGA to transmit scan control commands and coordinate data; the FPGA is connected to the digital input port of the multi-stage DAC circuit to output digitized voltage setpoints; the analog output port of the multi-stage DAC circuit is connected to the input terminal of the power amplifier module to transmit the precision voltage signal to be amplified; one output terminal of the power amplifier module is connected to the upper deflection coil, and the other output terminal of the power amplifier module is connected to the lower deflection coil; the precision reference source is directly connected to the multi-stage DAC circuit to provide a highly stable voltage reference.

[0008] As a further improvement to the above technical solution:

[0009] The power amplification module includes a first power amplification module that drives the upper coil and a second power amplification module that drives the lower coil.

[0010] Both the first power amplification module and the second power amplification module include a pre-processing circuit, a power amplifier, a loop parameter adjustment module, a scanning coil, and a scanning accuracy switching module;

[0011] The output of the pre-processing circuit is connected to the input of the power amplifier to transmit the pre-processed scan control signal;

[0012] The output of the power amplifier is connected to the input of the scanning precision switching module, delivering a maximum drive current of 2A.

[0013] The output of the scanning precision switching module is connected to the input terminal of the scanning coil, and the drive signal path is selected according to the mode;

[0014] The precision sampling wire-wound resistor is connected in series in the drive circuit, and the voltage sampling points at its two ends are connected to the loop parameter adjustment module.

[0015] The multi-stage DAC circuit includes a main DAC circuit, a bias DAC circuit, a gain DAC circuit, and a dual-channel output DAC circuit;

[0016] The precision reference source is connected to the reference voltage input pin of the main DAC circuit, providing a highly stable voltage reference;

[0017] The analog output of the main DAC circuit is buffered by an operational amplifier and then connected to the reference voltage input pin of the bias DAC circuit as its voltage reference source.

[0018] The analog output of the bias DAC circuit is buffered by an operational amplifier and then connected to the reference voltage input pin of the gain DAC circuit to provide it with an adjustable voltage reference source.

[0019] The analog output of the gain DAC circuit is buffered by an operational amplifier and then connected to the reference voltage input pin of the dual-channel output DAC circuit to set the final output range.

[0020] In the dual-channel output DAC circuit, the two independent analog outputs are: Channel A is connected to the input terminal of the first power amplifier module; and Channel B is connected to the input terminal of the second power amplifier module.

[0021] The output of the first power amplifier module drives the upper deflection coil; the output of the second power amplifier module drives the lower deflection coil.

[0022] It also includes an automatic scan linearity compensation module, which is used to collect the scan linearity of the first power amplifier module and the second power amplifier module in the X / Y direction and feed it back to the FPGA.

[0023] The automatic scanning linearity compensation module includes a first X-direction linearity ADC sampling module, a first Y-direction linearity ADC sampling module, a second X-direction linearity ADC sampling module, and a second Y-direction linearity ADC sampling module.

[0024] The input terminals of the first X-direction linearity ADC sampling module and the first Y-direction linearity ADC sampling module are connected to the first power amplifier module, and the output terminals are connected to the FPGA. They are used to collect the scanning linearity of the upper coil in the X / Y directions and feed it back to the FPGA, respectively. The input terminals of the second X-direction linearity ADC sampling module and the second Y-direction linearity ADC sampling module are connected to the second power amplifier module, and the output terminals are connected to the FPGA, respectively. They are used to collect the scanning linearity of the lower coil in the X / Y directions and feed it back to the FPGA, respectively.

[0025] Preferably, the gain correction formula is:

[0026]

[0027] Where DAC_Inputcode is the input to the DAC; To determine the maximum output value of the DAC, the N-bit DAC... for ; This represents the maximum voltage output range of the DAC. This represents the voltage value output by the DAC. This is the minimum output voltage value of the DAC;

[0028] Gain correction: Set the DAC input to 20% of its maximum value, record the ideal system output voltage value as DATA1, use the ADC to acquire the voltage, and record the actual system output voltage value as DATA11; set the DAC input to 80% of its maximum value, record the ideal system output voltage value as DATA2, use the ADC to acquire the voltage, and record the actual system output voltage value as DATA22.

[0029] Implement bias correction: Set the DAC to zero input, record the ideal voltage value as DATA3, use the ADC to acquire the voltage, and record the actual voltage value as DATA33; bias value offset = DATA33 - DATA3;

[0030] The formula for the total gain and bias correction is:

[0031] .

[0032] Preferably, the scanning accuracy switching module includes multiple parallel resistor branches, and each resistor branch has a switching switch and a resistor connected in series.

[0033] Preferably, the loop parameter adjustment module includes multiple parallel resistor-capacitor branches, each of which is parallel to the scanning coil; each of the resistor-capacitor branches includes an adjustment switch, an adjustment resistor, and a capacitor connected in series.

[0034] Preferably, each of the RC branches corresponds to each resistor branch, and the resistance of each resistor branch corresponds to the adjusting resistor and capacitor in the corresponding RC branch.

[0035] Preferably, the number of resistor branches and RC branches are both three.

[0036] Compared with the prior art, the advantages of the present invention are as follows:

[0037] This invention adjusts the resolution of the current flowing through the magnetic coil by switching the sampling resistor, increasing the resolution in a small field of view or decreasing the resolution to obtain a larger field of view. During scanning, if the linearity of the current increase or decrease is not optimal, it will cause image misalignment. To compensate for the lack of linearity, an ADC sampling linearity is added in the subsequent stage. The linearity sampling technology is returned to the FPGA, and the linearity compensation is performed by the FPGA controlling the gain DAC circuit and the deflection DAC circuit to obtain better linearity parameters. During the electron beam focusing process, aberrations will occur. The influence of aberrations can be eliminated by deflection through the upper and lower coils.

[0038] The electron beam deflection scanning driver system of this invention can achieve high-speed and precise deflection of the electron beam, automatically compensate for linearity errors, achieve a scanning frequency at the MHz level, and a positioning accuracy at the nanometer level, while effectively reducing aberrations caused by the focused electron beam. This invention can reduce aberrations of the focused electron beam and obtain high scanning accuracy to meet the resolution requirements of CDSEM linewidth measurement functions. Attached Figure Description

[0039] Figure 1 This is a diagram illustrating an embodiment of the electron beam scanning driver system of the present invention in a specific application.

[0040] Figure 2 This is a block diagram of the electron beam scanning driver system in an embodiment of the present invention.

[0041] Figure 3 This is a circuit diagram of the power amplifier module in an embodiment of the present invention.

[0042] Figure 4 This is a diagram illustrating an embodiment of the automatic scanning linearity compensation module of the present invention in a specific application.

[0043] Figure 5 (a) is a diagram of the deviation coil arrangement structure in the prior art; (b) is a diagram of the deviation coil arrangement structure in the present invention.

[0044] Legend: 1. Main control system; 2. FPGA; 3. Precision reference source; 4. Multi-stage DAC circuit; 401. Main DAC circuit; 402. Bias DAC circuit; 403. Gain DAC circuit; 404. Dual-channel output DAC circuit; 5. Power amplifier module; 501. First power amplifier module; 502. Second power amplifier module; 5011. Pre-processing circuit; 5012. Power amplifier; 5013. Loop parameter adjustment module; 5014. Scanning coil; 5015. Scanning accuracy switching module; 5016. Precision sampling winding resistor; 6. Upper deflection coil; 7. Lower deflection coil; 8. Automatic scanning linearity compensation module; 801. First X-direction linearity ADC sampling module; 802. First Y-direction linearity ADC sampling module; 803. Second X-direction linearity ADC sampling module; 804. Second Y-direction linearity ADC sampling module; 9. Lens. Detailed Implementation

[0045] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0046] like Figure 1 As shown, the electron beam deflection scanning driver system provided in this embodiment of the invention includes a main control system 1, an FPGA 2, a precision reference source 3, a multi-stage DAC circuit 4, a power amplifier module 5, an upper deflection coil 6, and a lower deflection coil 7.

[0047] The main control system 1 is connected to the input port of FPGA2 via a digital control bus to transmit scan control commands and coordinate data; FPGA2 is connected to the digital input port of the multi-stage DAC circuit 4 via a digital signal interface to output digitized voltage setpoints; the analog output port of the multi-stage DAC circuit 4 is connected to the input terminal of the power amplifier module 5 to transmit the precision voltage signal to be amplified; one output terminal of the power amplifier module 5 is connected to the upper deflection coil 6 to drive the forward deflection current; the other output terminal of the power amplifier module 5 is connected to the lower deflection coil 7 to drive the reverse deflection current; the precision reference source 3 is directly connected to the reference voltage input pin (Vref) of the multi-stage DAC circuit 4 to provide a highly stable voltage reference.

[0048] The specific working process is as follows: the main control system 1 transmits the control scanning data to FPGA2, FPGA2 controls the multi-stage DAC circuit 4, and the analog signal output by the multi-stage DAC circuit 4 is amplified by the power amplifier module 5 to drive the upper deflection coil 6 and the lower deflection coil 7 to control the scanning deflection of the electron beam.

[0049] FPGA2, model XC7A200T, features high-performance transceiver line speed, DSP processing capabilities, and AMS integration, making it suitable for communication and control within a CDSEM. The multi-stage DAC circuit 4 utilizes high-precision 16-bit LTC1668 and LTC2754. The LTC1668 boasts extremely high SFDR (spurious-free dynamic range), enabling ultra-high linearity output. The LTC2754 exhibits integral nonlinearity (INL) and differential nonlinearity (DNL) errors both less than 1 LSB, achieving high-precision correction.

[0050] like Figure 2 As shown, the multi-stage DAC circuit 4 includes a main DAC circuit 401 and corresponding operational amplifiers, a bias DAC circuit 402 and corresponding operational amplifiers, a gain DAC circuit 403 and corresponding operational amplifiers, and a dual-channel output DAC circuit 404 and corresponding operational amplifiers; the power amplifier module 5 includes a first power amplifier module 501 that drives the upper coil and a second power amplifier module 502 that drives the lower coil.

[0051] The precision reference source 3 is connected to the reference voltage input pin (Vref) of the main DAC circuit 401 to provide a highly stable reference.

[0052] The analog output of the main DAC circuit 401 is buffered by an operational amplifier and then connected to the reference voltage input pin (Vref) of the bias DAC circuit 402 as its reference source.

[0053] The analog output of the bias DAC circuit 402 is buffered by an operational amplifier and then connected to the reference voltage input pin (Vref) of the gain DAC circuit 403 to provide it with an adjustable reference source.

[0054] The analog output of the gain DAC circuit 403 is buffered by an operational amplifier and then connected to the reference voltage input pin (Vref) of the dual-channel DAC circuit to set the final output range.

[0055] In the dual-channel DAC circuit, the two independent analog outputs (buffered by operational amplifiers) are connected as follows: Channel A output is connected to the input terminal of the first power amplifier module 501; Channel B output is connected to the input terminal of the second power amplifier module 502.

[0056] The output of the first power amplifier module 501 drives the upper deflection coil 6; the output of the second power amplifier module 502 drives the lower deflection coil 7.

[0057] The specific working process is as follows: using the high-precision ADR130BUJZ with a deviation of less than 0.35% as the reference, FPGA2 controls the main DAC circuit 401, which, after passing through the subsequent operational amplifier, serves as the reference source for the bias DAC circuit 402; FPGA2 controls the bias DAC circuit 402, which, after passing through the subsequent operational amplifier, serves as the reference source for the gain DAC circuit 403; FPGA2 controls the gain DAC circuit 403, which, after passing through the subsequent operational amplifier, serves as the reference source for the dual-channel output DAC circuit 404; the dual-channel output DAC circuit 404, after passing through the subsequent operational amplifier, forms two inputs, which drive the first power amplifier module 501 and the second power amplifier module 502 respectively, thus completing the scanning control.

[0058] like Figure 3 As shown, the power amplification module 5 includes a pre-processing circuit 5011, a power amplifier 5012, a loop parameter adjustment module 5013, a scanning coil 5014, and a scanning accuracy switching module 5015.

[0059] The output of the pre-processing circuit 5011 is connected to the input of the power amplifier 5012 to transmit the pre-processed scan control signal;

[0060] The output of the power amplifier 5012 is connected to the input of the scanning accuracy switching module 5015, delivering a maximum drive current of 2A.

[0061] The output of the scanning precision switching module 5015 is connected to the input terminal of the scanning coil 5014, and the drive signal path is selected according to the mode;

[0062] Precision sampling wire-wound resistor 5016 ( Figure 3 Resistors R1 and R2 are connected in series in the drive circuit, for example at the output of power amplifier 5012 or the output of scan precision switching module 5015, and the voltage sampling points at both ends are connected to the loop parameter adjustment unit.

[0063] Specifically, the scanning accuracy switching module 5015 includes three parallel resistor branches, each with a switching switch and a resistor connected in series. The loop parameter adjustment module 5013 includes three parallel RC branches, each parallel to the scanning coil 5014; each RC branch includes an adjustment switch, an adjustment resistor, and a capacitor connected in series. Each RC branch corresponds to each resistor branch, and the resistance of each resistor branch corresponds to the adjustment resistor and capacitor in the corresponding RC branch. Of course, in other embodiments, the number of resistor branches and RC branches may be four, five, or more.

[0064] The specific working process is as follows: After passing through the pre-processing circuit 5011, the power is amplified by the power amplifier 5012, which can output a current of 2A. The current resolution is switched by the scanning accuracy switching module 5015. When switch K11 is closed and a large-value resistor R11 is used as the sampling resistor, the output range of the current flowing through coil 5014 is reduced, and the resolution of the output current is improved under the same DAC step. When switch K12 is closed and a medium-value resistor R12 is used as the sampling resistor, the output range of the current flowing through coil 5014 is increased, and the resolution of the output current is reduced under the same DAC step. When switch K13 is closed and a small-value resistor R13 is used as the sampling resistor, the output range of the current flowing through coil 5014 is increased, and the resolution of the output current is further reduced under the same DAC step. The current magnitude is controlled by switching the precision sampling winding resistor 5016. Using a large-value resistor reduces the current output range and shrinks the field of view; using a small-value resistor increases the current output range and expands the field of view. This allows for achieving high resolution in a small field of view and reducing resolution to achieve a larger field of view. Of course, in other embodiments, four, five, or more resistors can be used to switch the current resolution, or adjustable resistors can be used to achieve stepless adjustment of the current resolution.

[0065] This invention uses a scanning precision switching module 5015 to switch the resistance value, flexibly switching the resolution. When the field of view is reduced, a higher resolution can be used, or the resolution can be reduced to achieve a larger field of view.

[0066] However, selecting different resistor values ​​in the scanning accuracy switching module 5015 as the sampling resistor may cause instability in the entire circuit system, leading to output current oscillations. For example, when K11 is closed, i.e., R11 is switched to be used as the sampling resistor, the change in the sampling resistor value alters the phase difference between the input and output of the entire system, potentially generating an additional pole, reducing the phase margin, and causing the system to enter an unstable state. To stabilize the system, the loop parameter adjustment module 5013 closes the corresponding switches (K21-K23), using the corresponding loop resistors and capacitors to match the sampling resistor, generating a zero to offset the effect of a pole, thus increasing the phase margin and ensuring stable operation of the entire circuit. For example, when K11 is closed, the loop parameter adjustment module 5013 closes K21, using R21 and C21 to match the sampling resistor R11, generating a zero to offset the effect of the additional pole.

[0067] like Figure 4As shown, the automatic scanning linearity compensation module 8 includes a first X-direction linearity ADC sampling module 801, a first Y-direction linearity ADC sampling module 802, a second X-direction linearity ADC sampling module 803, and a second Y-direction linearity ADC sampling module 804.

[0068] The input terminals of the first X-direction linearity ADC sampling module 801 and the first Y-direction linearity ADC sampling module 802 are connected to the first power amplifier module 501, and their output terminals are connected to the FPGA2. These modules are used to acquire the X / Y direction scanning linearity of the upper coil and feed it back to the FPGA2. Similarly, the input terminals of the second X-direction linearity ADC sampling module 803 and the second Y-direction linearity ADC sampling module 804 are connected to the first power amplifier module 501, and their output terminals are connected to the FPGA2. These modules are used to acquire the X / Y direction scanning linearity of the lower coil and feed it back to the FPGA2.

[0069] The specific working process is as follows: FPGA2 controls the bias DAC circuit 402 and the gain DAC circuit 403 to drive the first power amplifier module 501 and the second power amplifier module 502. The first X-direction linearity ADC circuit collects the scanning linearity of the upper coil in the X direction, the first Y-direction linearity ADC circuit collects the scanning linearity of the upper coil in the Y direction, the second X-direction linearity ADC circuit collects the scanning linearity of the lower coil in the X direction, and the second Y-direction linearity ADC circuit collects the scanning linearity of the lower coil in the Y direction. The collected linearity data is fed back to FPGA2. In engineering practice, the collected linearity data differs from the ideal situation. After receiving the sampled data, FPGA2 analyzes and compares it with the ideal data. The results of the analysis and comparison are used to control and adjust the bias DAC circuit 402 and the gain DAC circuit 403.

[0070] Specifically, the output of the DAC (bias DAC or gain DAC) is shown in the following formula:

[0071]

[0072] Where DAC_Inputcode is the input to the DAC; To determine the maximum output value of the DAC, the N-bit DAC... for ; This represents the maximum voltage output range of the DAC. This represents the voltage value output by the DAC. This is the minimum output voltage value of the DAC.

[0073] Implement gain correction: Set the DAC input to 20% of its maximum value, record the ideal system output voltage value as DATA1, use the ADC to acquire the voltage, and record the actual system output voltage value as DATA11; set the DAC input to 80% of its maximum value, record the ideal system output voltage value as DATA2, use the ADC to acquire the voltage, and record the actual system output voltage value as DATA22.

[0074] The gain correction formula is:

[0075]

[0076] Implement bias correction: Set the DAC to zero input, record the ideal voltage value as DATA3, use the ADC to acquire the voltage, and record the actual voltage value as DATA33; the bias value offset = DATA33 - DATA3.

[0077] The formula for the total gain and bias correction is:

[0078]

[0079] This formula enables automatic compensation for linearity.

[0080] like Figure 5 As shown, where Figure 5 (a) indicates a common coil arrangement, including lens 9 and a pair of deflection coils. The focusing and deflection of the electron beam are controlled by lens 9 and a pair of deflection coils. This method of focusing with a lens and then deflecting the beam will produce a large aberration. Figure 5 (b) indicates an improved scanning coil arrangement, in which the deflection and focusing of the electron beam are controlled by two pairs of upper and lower deflection coils and lens 9. Using two-stage deflection allows the electron beam to be focused at the center of the lens before scanning begins, thus obtaining smaller aberrations.

[0081] This invention adjusts the resolution of the current flowing through the magnetic coil by switching the sampling resistor, increasing the resolution in a small field of view or decreasing the resolution to obtain a larger field of view. During scanning, if the linearity of the current increase or decrease is not optimal, it will cause image misalignment. To compensate for the lack of linearity, an ADC sampling linearity is added in the subsequent stage. The linearity sampling technology is returned to FPGA2, and the linearity compensation is performed by controlling the gain DAC circuit 403 and the deflection DAC circuit through FPGA2 to obtain better linearity parameters. During the electron beam focusing process, aberrations will occur. The influence of aberrations can be eliminated by deflection through the upper and lower coils.

[0082] The electron beam deflection scanning driver system of this invention can achieve high-speed and precise deflection of the electron beam, automatically compensate for linearity errors, achieve a scanning frequency at the MHz level, and a positioning accuracy at the nanometer level, while effectively reducing aberrations caused by the focused electron beam. This invention can reduce aberrations of the focused electron beam and obtain high scanning accuracy to meet the resolution requirements of CDSEM linewidth measurement functions.

[0083] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. An electron beam deflection scanning driver system, characterized in that, It includes a main control system (1), an FPGA (2), a precision reference source (3), a multi-stage DAC circuit (4), a power amplifier module (5), an upper deflection coil (6), and a lower deflection coil (7); The main control system (1) is connected to the input port of the FPGA (2) to transmit scanning control commands and coordinate data; the FPGA (2) is connected to the digital input port of the multi-stage DAC circuit (4) to output the digitized voltage setting value; the analog output port of the multi-stage DAC circuit (4) is connected to the input terminal of the power amplifier module (5) to transmit the precision voltage signal to be amplified; one output terminal of the power amplifier module (5) is connected to the upper deflection coil (6), and the other output terminal of the power amplifier module (5) is connected to the lower deflection coil (7); the precision reference source (3) is directly connected to the multi-stage DAC circuit (4) to provide a highly stable voltage reference; The power amplification module (5) includes a first power amplification module (501) that drives the upper coil and a second power amplification module (502) that drives the lower coil; The first power amplification module (501) and the second power amplification module (502) both include a pre-processing circuit (5011), a power amplifier (5012), a loop parameter adjustment module (5013), a scanning coil (5014), a scanning accuracy switching module (5015), and a precision sampling wire-wound resistor (5016). The output of the pre-processing circuit (5011) is connected to the input of the power amplifier (5012) to transmit the pre-processed scan control signal; The output of the power amplifier (5012) is connected to the input of the scanning accuracy switching module (5015) to deliver a maximum drive current of 2A. The output of the scanning precision switching module (5015) is connected to the input terminal of the scanning coil (5014) to select the drive signal path according to the mode; The precision sampling wire-wound resistor (5016) is connected in series in the drive circuit, and the voltage sampling points at its two ends are connected to the loop parameter adjustment module (5013). The multi-stage DAC circuit (4) includes a main DAC circuit (401), a bias DAC circuit (402), a gain DAC circuit (403), and a dual-channel output DAC circuit (404); The precision reference source (3) is connected to the reference voltage input pin of the main DAC circuit (401) to provide a highly stable voltage reference; The analog output terminal of the main DAC circuit (401) is buffered by an operational amplifier and then connected to the reference voltage input pin of the bias DAC circuit (402) as its voltage reference source. The analog output of the bias DAC circuit (402) is buffered by an operational amplifier and then connected to the reference voltage input pin of the gain DAC circuit (403) to provide it with an adjustable voltage reference source. The analog output of the gain DAC circuit (403) is buffered by an operational amplifier and then connected to the reference voltage input pin of the dual-channel output DAC circuit (404) to set the final output range. In the two independent analog outputs of the dual-channel output DAC circuit (404), channel A is connected to the input terminal of the first power amplifier module (501); channel B is connected to the input terminal of the second power amplifier module (502). The output of the first power amplifier module (501) drives the upper deflection coil (6); the output of the second power amplifier module (502) drives the lower deflection coil (7).

2. The electron beam deflection scanning driver system according to claim 1, characterized in that, It also includes an automatic scan linearity compensation module (8), which is used to collect the scan linearity of the first power amplifier module (501) and the second power amplifier module (502) in the X / Y direction and feed it back to the FPGA (2).

3. The electron beam deflection scanning driver system according to claim 2, characterized in that, The automatic scanning linearity compensation module (8) includes a first X-direction linearity ADC sampling module (801), a first Y-direction linearity ADC sampling module (802), a second X-direction linearity ADC sampling module (803), and a second Y-direction linearity ADC sampling module (804). The input terminals of the first X-direction linearity ADC sampling module (801) and the first Y-direction linearity ADC sampling module (802) are connected to the first power amplifier module (501), and the output terminals are connected to the FPGA (2), which are used to collect the scanning linearity of the upper coil in the X / Y directions and feed it back to the FPGA (2); the input terminals of the second X-direction linearity ADC sampling module (803) and the second Y-direction linearity ADC sampling module (804) are connected to the second power amplifier module (502), and the output terminals are connected to the FPGA (2), which are used to collect the scanning linearity of the lower coil in the X / Y directions and feed it back to the FPGA (2).

4. The electron beam deflection scanning driver system according to claim 3, characterized in that, The gain correction formula is: Where DAC_Inputcode is the input to the DAC; To determine the maximum output value of the DAC, the N-bit DAC... for ; This represents the maximum voltage output range of the DAC. This represents the voltage value output by the DAC. This is the minimum output voltage value of the DAC; Gain correction: Set the DAC input to 20% of its maximum value, record the ideal system output voltage value as DATA1, use the ADC to acquire the voltage, and record the actual system output voltage value as DATA11; set the DAC input to 80% of its maximum value, record the ideal system output voltage value as DATA2, use the ADC to acquire the voltage, and record the actual system output voltage value as DATA22. Implement bias correction: Set the DAC to zero input, record the ideal voltage value as DATA3, use the ADC to acquire the voltage, and record the actual voltage value as DATA33; bias value offset = DATA33 - DATA3; The formula for the total gain and bias correction is: 。 5. The electron beam deflection scanning driver system according to claim 1, characterized in that, The scanning accuracy switching module (5015) includes multiple parallel resistor branches, each of which has a switching switch and a resistor connected in series.

6. The electron beam deflection scanning driver system according to claim 5, characterized in that, The loop parameter adjustment module (5013) includes multiple parallel resistor-capacitor branches, each of which is parallel to the scanning coil (5014); each of the resistor-capacitor branches includes an adjustment switch, an adjustment resistor, and a capacitor connected in series.

7. The electron beam deflection scanning driver system according to claim 6, characterized in that, Each of the aforementioned RC branches corresponds to each resistor branch, and the resistance of each resistor branch corresponds to the adjusting resistor and capacitor in the corresponding RC branch.

8. The electron beam deflection scanning driver system according to claim 7, characterized in that, The number of resistor branches and RC branches is three each.

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