A NumPy numerical calculation optimization method, system and application based on RISC-V vector extension

Abstract

The application relates to a NumPy numerical calculation optimization method, system and application based on a RISC-V vector extension, and belongs to the technical field of computer science and high-performance computing application, wherein a core calculation part not calling a BLAS library is subjected to high-performance optimization, such as vector element-by-element operation and matrix element-by-element calculation. On the basis of analyzing a calculation step, the performance of NumPy in a broadcast operation and an element-by-element operation scene is improved through technologies such as bottom code replacement, loop optimization, data loading and memory alignment optimization, so as to provide support for scientific calculation and high-performance calculation based on a RISC-V architecture.

Description

Technical Field

[0001] This invention relates to a RISC-V Vector Extension (RVV)-based optimization method and system for NumPy numerical computation, and its application in the open-source numerical computation library NumPy, belonging to the fields of computer science and high-performance computing application technology. Background Technology

[0002] NumPy is a fundamental tool in the field of Python scientific computing, widely used in scenarios such as artificial intelligence, data analysis, and numerical computation. Its efficiency heavily relies on the optimization of the underlying hardware. However, currently, on the RISC-V architecture, NumPy's element-wise operations still lack a systematic optimization scheme based on RISC-V vector extensions, which significantly limits its computational performance.

[0003] Existing work includes NumPy optimization schemes for the ARM architecture, which identify key modules by scanning the code and achieve optimization through SIMD instructions and loop unrolling. While this approach improves performance to some extent, it is limited to simple parallelization of low-level instructions, lacking global optimization design for the algorithm itself and data flow. Furthermore, it is deeply tied to the ARM architecture, making direct adaptation to the RISC-V architecture difficult. In addition, existing RISC-V-based computing devices mostly focus on hardware design and system architecture, accelerating specific types of computing tasks by designing dedicated AI processors, multi-precision vector operation devices, or coprocessors. These solutions aim to improve performance by changing or adding hardware, resulting in limited improvements and limited applicability.

[0004] Therefore, optimizing NumPy's computational efficiency by combining RISC-V vector extensions with the RISC-V architecture, and overcoming the limitations of existing work on the underlying hardware, has become an urgent problem to be solved. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a method, system, and application for optimizing NumPy numerical computation based on RISC-V vector extension instructions, aiming to improve the running efficiency of NumPy on the RISC-V platform. Compared with existing technologies, this invention mainly focuses on the computational flow of NumPy, optimizing the data loading, element-wise operations, and data output stages using RISC-V vector extension instructions. Since NumPy typically calls external high-performance computing libraries (such as BLAS) for inner product operations and matrix multiplication, this invention focuses on high-performance optimization of core computational parts that do not call BLAS libraries, such as vector element-wise operations and matrix element-wise calculations. Based on the analysis of computational steps, techniques such as low-level code replacement, loop optimization, and data loading and memory alignment optimization are used to improve the performance of NumPy in broadcast and element-wise operation scenarios, thereby providing support for scientific computing and high-performance computing based on the RISC-V architecture.

[0006] This invention proposes a design framework for computational process decomposition and optimization based on the original computational flow of NumPy and the characteristics of the RISC-V instruction set architecture. Unlike existing methods that uniformly accelerate computationally intensive code by scanning the entire codebase, this invention starts with the code execution flow and proposes an optimized flow based on RISC-V vector extensions for element-wise operations in specific scenarios. By implementing specific operations (such as element-wise vector addition and element-wise matrix multiplication) using the RISC-V vector extension instruction set, and combining memory access optimization and loop unrolling, this invention can significantly improve the efficiency of operations that do not call the BLAS library.

[0007] The technical solution of the present invention is as follows:

[0008] A method for optimizing NumPy numerical computation based on RISC-V vector extension instructions includes the following steps:

[0009] Step 1: Dynamic hardware detection and RISC-V vector extension support determination;

[0010] After code analysis, this invention designed a hardware environment dynamic detection module to determine whether the target device supports RISC-V vector extension instructions, and then decide whether to enable RISC-V vector extension-related optimization steps.

[0011] Preferred options include:

[0012] RISC-V Vector Extensions Support Detection:

[0013] When the program starts, it reads the processor hardware information and determines whether the target device supports RISC-V vector extension by accessing CSRs (Control and Status Registers).

[0014] The current RISC-V vector extension version features, including the vector register length VLEN and the supported operation bit width, are detected to match the available optimization instructions. Specifically, it is checked whether half-precision floating-point operations (Zvfh) are supported. If the hardware does not support 16-bit floating-point vector instructions, then the corresponding vector instructions cannot be used for optimization of float16 arrays in NumPy.

[0015] Dynamic path selection:

[0016] If the hardware supports RISC-V vector extension and meets the minimum optimization requirements, proceed to step 2; the minimum optimization requirements are that the vector extension specification version is 0.7.1 or higher.

[0017] If the hardware does not support RISC-V vector extensions or does not meet the minimum optimization requirements, it will fall back to the traditional scalar implementation path to ensure that the function works properly in all environments.

[0018] Step 2: Classification and Dynamic Management

[0019] This invention designs a dynamic computation process management method to determine whether to call an external high-efficiency library and select an adaptation strategy:

[0020] Methods for calling external high-efficiency libraries: For computational tasks that call external high-efficiency libraries (such as BLAS) (such as matrix multiplication, matrix inner product operations, etc.), the external library is directly called for execution without enabling the RISC-V vector extension optimization path;

[0021] Element-wise operations without calling external high-efficiency libraries: For core computational tasks that do not call external high-efficiency libraries (such as element-wise addition, subtraction, multiplication and division of vectors or matrices), enable the RISC-V vector extension optimization strategy and proceed to step 3 to achieve efficient computation by combining hardware characteristics.

[0022] Step 3: Optimize the process

[0023] This invention adopts a process-oriented design approach. Based on the NumPy calculation process, the optimization focus is placed on the core calculation part that does not call external BLAS libraries. The overall process is as follows: Analyzing the underlying implementation and execution flow of NumPy, the calculation steps are divided into the following parts:

[0024] 1-1. Data loading and type conversion;

[0025] 1-2. Core calculations, including element-wise operations on vectors or matrices;

[0026] 1-3. Data output and result conversion.

[0027] Step-by-step optimization strategy: Specific algorithms and RISC-V vector extension instructions are used to optimize the process, minimizing changes to the existing NumPy code structure and improving performance.

[0028] Based on a comprehensive analysis of the core operations of NumPy element-wise operations, this invention proposes a series of optimization methods based on RISC-V vector extensions for common element-wise vector and matrix operations. These optimization methods meticulously design each step of the element-wise operation, and combined with the parallel computing capabilities of RISC-V vector extension instructions, significantly improve data processing efficiency and overall performance. Specifically, these methods include the following sub-methods.

[0029] Preferably, 1-1, data loading and type conversion optimization includes the following steps:

[0030] NumPy computations involve loading native Python data structures (such as lists) into NumPy arrays; since data loading and type conversion are typically the initial steps in the computation process, their performance directly impacts subsequent calculations. This invention optimizes the following details:

[0031] Python list dereferencing and value extraction: When the input data is a Python list, first iterate through all elements, dereference each element, and extract the value;

[0032] The RISC-V Vector Extensions instruction set is used to perform batch optimization of pointer dereference operations in the list, and vector registers are used to load values ​​in parallel, avoiding the performance overhead of dereferencing point by point.

[0033] Optimize loading mechanism:

[0034] Uniform data type: When the data types are consistent, such as all integers or floating-point numbers, the RISC-V vector extension vector loading instructions (e.g., VLE) can be used directly. <sew>_v_f <vsew> m <lmul>Batch loading is performed into the vector register to maximize the use of parallel loading capabilities;

[0035] Non-uniform data type: When data types are inconsistent, this invention sets up a boundary recovery module based on RISC-V vector extension optimization to perform individual verification and adaptation on non-uniform data types, ensuring that the data processing is correct and error-free.

[0036] By optimizing RVV parallel processing from serial sequential processing of data loading and type conversion, the data initialization speed is significantly accelerated, providing a foundation for efficient execution of subsequent operations.

[0037] Preferably, steps 1-2 include the following:

[0038] 1) Optimization of element-wise vector operations

[0039] Element-wise vector operations are among the most commonly used operations in NumPy, including but not limited to addition, subtraction, multiplication, division, and multiplication-addition operations (such as a + b, a / b). For this type of operation, this invention designs an efficient parallel implementation method on the RVV platform, with the specific optimization strategy as follows:

[0040] Parallel loading operands:

[0041] Take two vector arrays to be operated on (e.g., array1 and array2), and use RISC-V vector extension vector loading instructions (e.g., VLE) to load the vectors. <sew>_v_f <vsew> m <lmul>This batch loads its elements into the vector register, reducing the number of memory access calls;

[0042] Element-by-element computation optimization:

[0043] Utilizing RISC-V vector extension instructions (e.g., vfadd_vv_f) <vsew> m <lmul>Used for element-wise addition, vfmul_vv_f <vsew> m <lmul>For element-wise multiplication), directly perform element-wise operations in the vector register; at the same time, pipeline the calculation results in the register to maximize the instruction execution efficiency and reduce the complexity of operations between registers;

[0044] Data alignment and memory access optimization:

[0045] When storing the results, directly complete the storage operation in batches in the vector register to avoid frequent memory access operations;

[0046] In the loading and calculation stages, complete the alignment of memory data in advance, optimize the memory access order, and improve the cache hit rate;

[0047] Through the above optimization measures, the processing efficiency of vector element-wise operations has been significantly improved, especially in the case of large data scales.

[0048] 2) Matrix element-wise operation optimization

[0049] Matrix element-wise calculations (including A + B, A - B, A * B, A / B, A > B, A < B, A == B, MAX(A, B)) are another common operation in NumPy calculations. In order to achieve efficient operation by combining the structured parallel mechanism of RVV, the present invention designs the following specific strategies: The optimizations include the following:

[0050] Matrix block processing:

[0051] Decompose the large matrix to be operated into multiple smaller blocks to adapt to the storage capacity of the RISC-V vector register; the size of the blocks is not set arbitrarily, but is dynamically determined according to the vector processing ability of the processor; specifically, the number of elements continuously processed in memory for each block is set based on the key parameters of the RISC-V vector extension, including the vector register length (VLEN), the bit width of the data elements in the current operation (SEW), and the vector register grouping multiplier (LMUL);

[0052] Further preferably, the size of each block is set to an integer multiple of (VLEN / SEW) * LMUL to ensure that when processing in a loop, the vector load instruction can fill the vector register maximally, thereby achieving the highest calculation parallelism. Therefore, the total number of blocks is determined by dividing the total size of the matrix by the size of a single block calculated according to the above parameters, without a preset fixed number.

[0053] Independently perform element-wise calculations on each block, and use RISC-V vector extension instructions (such as vadd.vv or vmul.vv) to implement element-by-element processing between matrix blocks;

[0054] Memory access pattern optimization:

[0055] To address the row and column alignment issues in matrix operations, vector loading instructions (such as VLE) in RVV are used in conjunction with register reordering mechanisms to optimize memory access order and minimize performance loss caused by cross-row or cross-column memory access.

[0056] Output storage optimization:

[0057] After each block of computation is completed, the result is written directly back to memory, using RVV's vector write-back mechanism (such as VSE) to write multiple elements at once. Specifically, in the processing loop, after each block of computation is completed, the result of that block is immediately written from the vector register back to the corresponding location in memory. This process uses RVV's vector storage instructions (such as VSE) to write multiple elements at once, ensuring that the computation result is released from register resources and written to disk in a timely manner, preparing for the computation of the next block. This pipelined mode of alternating "computation-storage" minimizes memory access bottlenecks and intermediate data caching pressure caused by waiting for all computations to complete, and reduces memory access overhead during output.

[0058] By combining block partitioning and memory operation optimization schemes, this invention can efficiently handle matrix element-wise calculation scenarios, especially in high-dimensional matrix operations.

[0059] 3) Broadcast operation optimization

[0060] NumPy supports a broadcast mechanism. When a vector or matrix is ​​broadcast to a scalar value, or a matrix is ​​broadcast to a vector (the method of this invention is applicable to various broadcast operation scenarios, including but not limited to arithmetic operations (such as addition, subtraction, multiplication, and division) and comparison operations (such as greater than, less than, and equal to)), the scalar value must be matched with other elements of the vector or matrix in a broadcast manner. This method has the following optimization design for broadcast scenarios:

[0061] RISC-V Vector Computation Optimization:

[0062] In the RISC-V vector register, a scalar value is loaded as a broadcast vector, and batch operations are performed using RVV vector-scalar computation instructions (such as vfadd_vf_f). <vsew> m <lmul>Used for scalar + vector, vfmul_vf_f <vsew> m <lmul>For scalar * vector, the specific calls to Intrinsic functions include, but are not limited to, floating-point arithmetic operations, integer arithmetic operations, and comparison operations:

[0063] Floating-point arithmetic operations:

[0064] Vector + scalar addition: vfadd_vf_f64m2

[0065] Vector-scalar subtraction: vfsub_vf_f64m2

[0066] Scalar-vector subtraction: vfrsub_vf_f64m2

[0067] Vector * scalar multiplication: vfmul_vf_f64m2

[0068] Vector / scalar division: vfdiv_vf_f64m2

[0069] Integer arithmetic operations:

[0070] Vector + scalar addition: vadd_vx_i64m2

[0071] Vector-scalar subtraction: vsub_vx_i64m2

[0072] Vector * scalar multiplication: vmul_vx_i64m2

[0073] Bitwise AND: vand_vx_i64m2

[0074] Bitwise OR: vor_vx_i64m2

[0075] Comparison operations:

[0076] This type of operation returns a boolean mask vector, which can be used for subsequent conditional execution or logical judgment.

[0077] Equals: vmfeq_vf_f32m1_b32

[0078] Not equal to: vmfne_vf_f32m1_b32

[0079] Greater than: vmfgt_vf_f32m1_b32

[0080] Less than: vmflt_vf_f32m1_b32

[0081] This avoids processing each element individually, thereby improving computational efficiency.

[0082] Preferably, in steps 1-3, the output and data type conversion are optimized.

[0083] After element-wise operations, NumPy typically needs to restore the result from the array to a Python object or return it to an external program; this step optimizes subsequent processing steps, specifically:

[0084] Batch reading and conversion:

[0085] The calculation results in NumPy arrays are read in batches using RISC-V vector loading instructions (such as vle32 or vle64). The number of data read each time is dynamically adjusted by the vector length in the hardware, that is, flexibility is achieved by dynamically setting the VL parameter.

[0086] The read data is converted into Python objects in batches using parallel processing:

[0087] Integers are wrapped as PyLongObjects;

[0088] Floating-point numbers are wrapped as PyFloatObject.

[0089] The above optimizations significantly reduce the operational overhead of the output conversion process and shorten the response time from calculation results to program interaction.

[0090] A NumPy numerical computation optimization system based on RISC-V vector extension includes a function interface and distribution module, a hardware detection module, a dynamic process management module, and an RVV optimization module.

[0091] The function interface and dispatch module is used to receive NumPy function call requests from upper-layer applications (such as Python scripts) at runtime and obtain array data to be processed; this module is the entry point of the entire optimization method, which dispatches the received function call type and data to the dynamic process management module; this corresponds to the starting point of method execution;

[0092] Hardware detection module: Used to detect whether the target device supports RVV extended instructions when the program starts, and to query its specific hardware characteristics;

[0093] Dynamic process management module: used to determine whether a specific computing task calls an external high-efficiency library (BLAS) and select the corresponding computing path;

[0094] RVV Optimization Module: Used to optimize element-wise computation tasks that do not call external libraries using the RVV instruction set, improving performance through vectorized computation.

[0095] A computer-readable storage medium having a program stored thereon that, when executed by a processor, implements the steps in the previously described RISC-V vector extension-based NumPy numerical computation optimization method.

[0096] An electronic device includes a memory, a processor, and a program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps in the NumPy numerical computation optimization method based on RISC-V vector extension as described above.

[0097] This invention belongs to the field of computer software and algorithm optimization, and runs on general-purpose processors conforming to the RISC-V standard. The "computational process decomposition and process optimization" framework proposed in this invention is an effective method that tightly integrates high-level algorithm logic with low-level instruction set characteristics. Through in-depth analysis of NumPy's internal working mechanism, it achieves more efficient and precise performance improvements than general-purpose compiler optimization, especially in scenarios such as broadcasting and element-wise computation. The method of this invention does not rely on any custom coprocessors or non-standard instruction sets. It only utilizes the official standard vector extensions of RISC-V, therefore it can be applied to any RISC-V processor equipped with standard vector extension functionality, resulting in wider applicability and lower implementation costs.

[0098] The beneficial effects of this invention are as follows:

[0099] 1. Significantly improved computational efficiency. This invention optimizes NumPy element-wise computation by introducing RVV vector extension instructions on the RISC-V architecture hardware platform. For example, batch element-wise operations on vectors and matrices convert scalar computation into parallel computation, significantly reducing loop iterations and memory accesses, and greatly improving computational efficiency.

[0100] 2. Improved hardware utilization. This invention fully leverages the hardware parallel computing capabilities of RVV, utilizes vector registers for large-scale batch processing operations, optimizes memory access patterns, avoids the waste of hardware resources in traditional scalar computing, and further reduces the bottleneck impact of memory access latency on computing performance.

[0101] 3. Strong compatibility and adaptability. During the compilation phase, this invention detects whether the target processor supports RVV instruction extensions. When RVV is not supported, it automatically selects to fall back to the NumPy general implementation path, ensuring the integrity and compatibility of the computational logic and adapting to the needs of different hardware platforms.

[0102] 4. Wide range of practical applications. This invention is applicable to scenarios requiring efficient element-wise computation of vectors and matrices, such as scientific computing, artificial intelligence model training, and big data analysis. It offers significant performance improvements and computational advantages, especially in handling large-scale data tasks, expanding the possibilities for NumPy applications on the RISC-V platform. Attached Figure Description

[0103] Figure 1 This is a flowchart of an optimization method for NumPy numerical computation based on RISC-V vector extension. Detailed Implementation

[0104] The present invention will be further described below with reference to the embodiments and accompanying drawings, but is not limited thereto. Example

[0105] A method for optimizing NumPy numerical computation based on RISC-V vector extension instructions, the process is as follows: Figure 1 As shown, the steps are as follows:

[0106] Step 1: Dynamic hardware detection and RISC-V vector extension support determination.

[0107] After code analysis, this invention designed a hardware environment dynamic detection module to determine whether the target device supports RISC-V vector extension instructions, and then decide whether to enable RISC-V vector extension-related optimization steps.

[0108] Specifically, it includes:

[0109] RISC-V Vector Extensions Support Detection:

[0110] When the program starts, it reads the processor hardware information and determines whether the target device supports RISC-V vector extension by accessing CSRs (Control and Status Registers).

[0111] The current RISC-V vector extension version features are detected, including the vector register length VLEN and the supported operation bit width, to match the available optimization instructions. Specifically, it checks whether half-precision floating-point operations (Zvfh) are supported. If the hardware does not support 16-bit floating-point vector instructions, then the corresponding vector instructions cannot be used for optimization of float16 arrays in NumPy.

[0112] Dynamic path selection:

[0113] If the hardware supports RISC-V vector extension and meets the minimum optimization requirements, proceed to step 2; the minimum optimization requirements are that the vector extension specification version is 0.7.1 or higher.

[0114] If the hardware does not support RISC-V vector extensions or does not meet the minimum optimization requirements, it will fall back to the traditional scalar implementation path to ensure that the function works properly in all environments.

[0115] Step 2: Classification and Dynamic Management

[0116] This invention designs a dynamic computation process management method to determine whether to call an external high-efficiency library and select an adaptation strategy:

[0117] Methods for calling external high-efficiency libraries: For computational tasks that call external high-efficiency libraries (such as BLAS) (such as matrix multiplication, matrix inner product operations, etc.), the external library is directly passed for execution without enabling the RISC-V vector extension optimization path.

[0118] Element-wise operations without calling external high-efficiency libraries: For core computational tasks that do not call external high-efficiency libraries (such as element-wise addition, subtraction, multiplication and division of vectors or matrices), enable the RISC-V vector extension optimization strategy and proceed to step 3 to achieve efficient computation by combining hardware characteristics.

[0119] Step 3: Optimize the process

[0120] This invention adopts a process-oriented design approach. Based on the NumPy calculation process, the optimization focus is placed on the core calculation part that does not call external BLAS libraries. The overall process is as follows: Analyzing the underlying implementation and execution flow of NumPy, the calculation steps are divided into the following parts:

[0121] 1-1. Data loading and type conversion;

[0122] 1-2. Core calculations, including element-wise operations on vectors or matrices;

[0123] 1-3. Data output and result conversion.

[0124] Step-by-step optimization strategy: Specific algorithms and RISC-V vector extension instructions are used to optimize the process, minimizing changes to the existing NumPy code structure and improving performance.

[0125] Based on a comprehensive analysis of the core operations of NumPy element-wise operations, this invention proposes a series of optimization methods based on RISC-V vector extensions for common element-wise vector and matrix operations. These optimization methods meticulously design each step of the element-wise operation, and combined with the parallel computing capabilities of RISC-V vector extension instructions, significantly improve data processing efficiency and overall performance. Specifically, these methods include the following sub-methods.

[0126] 1-1. Data loading and type conversion optimization, including the following steps:

[0127] NumPy computations involve loading native Python data structures (such as lists) into NumPy arrays; since data loading and type conversion are typically the initial steps in the computation process, their performance directly impacts subsequent calculations. This invention optimizes the following details:

[0128] Python list dereferencing and value extraction: When the input data is a Python list, first iterate through all elements, dereference each element, and then extract the value.

[0129] The RISC-V Vector Extensions instruction set is used to perform batch optimization of pointer dereference operations in the list, and vector registers are used to load values ​​in parallel, avoiding the performance overhead of dereferencing point by point.

[0130] Optimize loading mechanism:

[0131] Uniform data type: When the data types are consistent, such as all integers or floating-point numbers, the RISC-V vector extension vector loading instructions (e.g., VLE) can be used directly. <sew>_v_f <vsew> m <lmul>Batch loading is performed into the vector register to maximize the use of parallel loading capabilities.

[0132] Non-uniform data types: When data types are inconsistent, this invention sets up a boundary recovery module based on RISC-V vector extension optimization to perform individual verification and adaptation on non-uniform data types, ensuring that the data processing is correct.

[0133] By optimizing RVV parallel processing from serial sequential processing of data loading and type conversion, the data initialization speed is significantly accelerated, providing a foundation for efficient execution of subsequent operations.

[0134] Steps 1-2 include the following:

[0135] 1) Optimization of element-wise vector operations

[0136] Element-wise vector operations are among the most commonly used operations in NumPy, including but not limited to addition, subtraction, multiplication, division, and multiplication-addition operations (such as a + b, a / b). For this type of operation, this invention designs an efficient parallel implementation method on the RVV platform, with the specific optimization strategy as follows:

[0137] Parallel loading operands:

[0138] Take two vector arrays to be operated on (e.g., array1 and array2), and use RISC-V vector extension vector loading instructions (e.g., VLE) to load the vectors. <sew>_v_f <vsew> m <lmul>This batch loads its elements into the vector register, reducing the number of memory access calls.

[0139] Element-by-element computation optimization:

[0140] Utilizing RISC-V vector extension instructions (e.g., vfadd_vv_f) <vsew> m <lmul>Used for element-wise addition, vfmul_vv_f <vsew> m <lmul>For element-wise multiplication), directly perform element-wise operations in the vector register; at the same time, pipeline the calculation results in the register to maximize the instruction execution efficiency and reduce the complexity of operations between registers.

[0141] Data alignment and memory access optimization:

[0142] When storing the results, directly complete the batch storage operation in the vector register to avoid frequent memory access operations.

[0143] In the loading and calculation stages, complete the alignment of memory data in advance, optimize the memory access order, and improve the cache hit rate.

[0144] Through the above optimization measures, the processing efficiency of vector element-wise operations has been significantly improved, especially in the case of large data scales.

[0145] 2) Matrix element-wise operation optimization

[0146] Matrix element-wise calculations (including A + B, A - B, A * B, A / B, A > B, A < B, A == B, MAX(A, B)) are another common operation in NumPy calculations. To achieve efficient operation by combining the structured parallel mechanism of RVV, the present invention designs the following specific strategies: The optimizations include the following:

[0147] Matrix block processing:

[0148] Decompose the large matrix to be operated into multiple smaller blocks to adapt to the storage capacity of the RISC-V vector register; the size of the blocks is not arbitrarily set, but dynamically determined according to the vector processing ability of the processor; specifically, the number of elements continuously processed in memory for each block is set based on the key parameters of the RISC-V vector extension, including the vector register length (VLEN), the bit width of the data elements in the current operation (SEW), and the vector register grouping multiplier (LMUL).

[0149] The size of each block is set to an integer multiple of (VLEN / SEW) * LMUL to ensure that when processing in a loop, the vector load instruction can fill the vector register maximally, thereby achieving the highest calculation parallelism. Therefore, the total number of blocks is determined by dividing the total size of the matrix by the size of a single block calculated according to the above parameters, without presetting a fixed number.

[0150] Independently perform element-wise calculations on each block, and use RISC-V vector extension instructions (such as vadd.vv or vmul.vv) to implement element-by-element processing between matrix blocks;

[0151] Memory access pattern optimization:

[0152] To address the row and column alignment issues in matrix operations, vector loading instructions (such as VLE) in RVV are used in conjunction with register reordering mechanisms to optimize memory access order and minimize performance loss caused by cross-row or cross-column memory access.

[0153] Output storage optimization:

[0154] After each block of computation is completed, the result is written directly back to memory, using RVV's vector write-back mechanism (such as VSE) to write multiple elements at once. Specifically, in the processing loop, after each block of computation is completed, the result of that block is immediately written from the vector register back to the corresponding location in memory. This process uses RVV's vector storage instructions (such as VSE) to write multiple elements at once, ensuring that the computation result is released from register resources and written to disk in a timely manner, preparing for the computation of the next block. This pipelined mode of alternating "computation-storage" minimizes memory access bottlenecks and intermediate data caching pressure caused by waiting for all computations to complete, and reduces memory access overhead during output.

[0155] By combining block partitioning and memory operation optimization schemes, this invention can efficiently handle matrix element-wise calculation scenarios, especially in high-dimensional matrix operations.

[0156] 3) Broadcast operation optimization

[0157] NumPy supports a broadcast mechanism. When a vector or matrix is ​​broadcast to a scalar value, or a matrix is ​​broadcast to a vector (the method of this invention is applicable to various broadcast operation scenarios, including but not limited to arithmetic operations (such as addition, subtraction, multiplication, and division) and comparison operations (such as greater than, less than, and equal to)), the scalar value must be matched with other elements of the vector or matrix in a broadcast manner. This method has the following optimization design for broadcast scenarios:

[0158] RISC-V Vector Computation Optimization:

[0159] In the RISC-V vector register, a scalar value is loaded as a broadcast vector, and batch operations are performed using RVV vector-scalar computation instructions (such as vfadd_vf_f). <vsew> m <lmul>Used for scalar + vector, vfmul_vf_f <vsew> m <lmul>For scalar * vector, the specific calls to Intrinsic functions include, but are not limited to, floating-point arithmetic operations, integer arithmetic operations, and comparison operations:

[0160] Floating-point arithmetic operations:

[0161] Vector + scalar addition: vfadd_vf_f64m2

[0162] Vector-scalar subtraction: vfsub_vf_f64m2

[0163] Scalar-vector subtraction: vfrsub_vf_f64m2

[0164] Vector * scalar multiplication: vfmul_vf_f64m2

[0165] Vector / scalar division: vfdiv_vf_f64m2

[0166] Integer arithmetic operations:

[0167] Vector + scalar addition: vadd_vx_i64m2

[0168] Vector-scalar subtraction: vsub_vx_i64m2

[0169] Vector * scalar multiplication: vmul_vx_i64m2

[0170] Bitwise AND: vand_vx_i64m2

[0171] Bitwise OR: vor_vx_i64m2

[0172] Comparison operations:

[0173] This type of operation returns a boolean mask vector, which can be used for subsequent conditional execution or logical judgment.

[0174] Equals: vmfeq_vf_f32m1_b32

[0175] Not equal to: vmfne_vf_f32m1_b32

[0176] Greater than: vmfgt_vf_f32m1_b32

[0177] Less than: vmflt_vf_f32m1_b32

[0178] This avoids processing each element individually, thereby improving computational efficiency.

[0179] In steps 1-3, output and data type conversion optimization are performed.

[0180] After element-wise operations, NumPy typically needs to restore the result from the array to a Python object or return it to an external program; this step optimizes subsequent processing steps, specifically:

[0181] Batch reading and conversion:

[0182] The calculation results in NumPy arrays are read in batches using RISC-V vector loading instructions (such as vle32 or vle64). The number of data read each time is dynamically adjusted by the hardware vector length, that is, flexibility is achieved by dynamically setting the VL parameter.

[0183] The read data is converted into Python objects in batches using parallel processing:

[0184] Integers are wrapped as PyLongObjects;

[0185] Floating-point numbers are wrapped as PyFloatObject.

[0186] The above optimizations significantly reduce the operational overhead of the output conversion process and shorten the response time from calculation results to program interaction.

[0187] Example 2

[0188] A NumPy numerical computation optimization system based on RISC-V vector extension includes a function interface and distribution module, a hardware detection module, a dynamic process management module, and an RVV optimization module.

[0189] The function interface and dispatch module is used to receive NumPy function call requests from upper-layer applications (such as Python scripts) at runtime and obtain array data to be processed; this module is the entry point of the entire optimization method, which dispatches the received function call type and data to the dynamic process management module; this corresponds to the starting point of method execution.

[0190] Hardware detection module: Used to detect whether the target device supports RVV extended instructions when the program starts, and to query its specific hardware characteristics.

[0191] Dynamic process management module: used to determine whether a specific computing task calls an external high-efficiency library (BLAS) and select the corresponding computing path.

[0192] RVV Optimization Module: Used to optimize element-wise computation tasks that do not call external libraries using the RVV instruction set, improving performance through vectorized computation.

[0193] Example 3

[0194] A computer-readable storage medium having a program stored thereon that, when executed by a processor, implements the steps in the NumPy numerical computation optimization method based on RISC-V vector extension as described in Example 1.

[0195] Example 4

[0196] An electronic device includes a memory, a processor, and a program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps in the NumPy numerical computation optimization method based on RISC-V vector extension as described in Embodiment 1.< / lmul> < / vsew> < / lmul> < / vsew> < / lmul> < / vsew> < / lmul> < / vsew> < / lmul> < / vsew> < / sew> < / lmul> < / vsew> < / sew> < / lmul> < / vsew> < / lmul> < / vsew> < / lmul> < / vsew> < / lmul> < / vsew> < / lmul> < / vsew> < / sew> < / lmul> < / vsew> < / sew>

Claims

1. A NumPy numerical computation optimization method based on RISC-V vector extension, characterized in that, The steps include the following: Step 1: Dynamic hardware detection and RISC-V vector extension support determination; This is used to determine whether the target device supports RISC-V vector extension instructions. If it does not support them, the optimization strategies related to RISC-V vector extension will not be enabled; otherwise, proceed to step 2. Step 2: Categorize and determine whether to call an external high-efficiency library and select an adaptation strategy: Methods for calling external high-efficiency libraries: For computational tasks that call external high-efficiency libraries, the external high-efficiency library is directly called for execution, and the RISC-V vector extension optimization strategy is not enabled; Element-wise operations without calling external high-efficiency libraries: For computation tasks that do not call external high-efficiency libraries, enable the RISC-V vector extension optimization strategy, proceed to step 3, and achieve efficient computation by combining hardware characteristics; Step 3: Optimize the process Analyzing the underlying implementation and execution flow of NumPy, the computation steps are divided into the following parts for optimization: 1-1. Optimization of data loading and type conversion; 1-2. Core computations, including optimization of element-wise operations on vectors or matrices; 1-3. Optimization of data output and result conversion.

2. The NumPy numerical computation optimization method based on RISC-V vector extension according to claim 1, characterized in that, Specifically, it includes: steps 1 includes: RISC-V Vector Extensions Support Detection: When the program starts, it reads the processor hardware information and determines whether the target device supports RISC-V vector extension by using access control and status registers. The current RISC-V vector extension version features, including the vector register length VLEN and the supported operation bit width, are detected to match the available optimization instructions. Specifically, it is checked whether 16-bit floating-point operations are supported. If the hardware does not support 16-bit floating-point vector instructions, then the corresponding vector instructions cannot be used for optimization of float16 arrays in NumPy. Dynamic path selection: If the hardware supports RISC-V vector extension and meets the minimum optimization requirements, proceed to step 2; the minimum optimization requirements are that the vector extension specification version is 0.7.1 or higher. If the hardware does not support RISC-V vector extension or does not meet the minimum optimization requirements, it will fall back to the traditional scalar implementation path.

3. The NumPy numerical computation optimization method based on RISC-V vector extension according to claim 1, characterized in that, Step 1-1, Data loading and type conversion optimization, includes the following steps: NumPy computations involve loading Python's native data structures into NumPy arrays; optimizations include the following: Python list dereferencing and value extraction: When the input data is a Python list, first iterate through all elements, dereference each element, and extract the value; The RISC-V Vector Extensions instruction set is used to batch optimize the dereference operation of pointers in the list, and vector registers are used to load values ​​in parallel. Optimize loading mechanism: Uniform data type: When the data types are consistent, meaning all integers or all floating-point numbers, the vector load instructions of RISC-V vector extension can be used to load them into the vector register in batches. Non-uniform data type: When data types are inconsistent, a boundary recovery module is set up based on RISC-V vector extension optimization to perform individual verification and adaptation on non-uniform data types; By loading and converting data types, the sequential processing is optimized to RVV parallel processing.

4. The NumPy numerical computation optimization method based on RISC-V vector extension according to claim 1, characterized in that, Steps 1-2 include the following: 1) Optimization of element-wise vector operations Vector element-wise operations include addition, subtraction, multiplication, division, and multiply-addition. For this type of operation, an efficient parallel implementation method is designed on the RVV platform. The specific optimization strategy is as follows: Parallel loading operands: The two vector arrays to be operated on are loaded into the vector register in batches using the RISC-V vector extension vector load instruction; Element-by-element computation optimization: The RISC-V vector extension instructions are used to perform element-wise operations directly in the vector register; at the same time, the calculation results in the register are piped. Data alignment and memory access optimization: When storing the results, the storage operation is performed in batches directly in the vector register; Memory data alignment is performed in advance during the loading and computation phases; 2) Optimization of element-wise matrix operations Element-wise matrix calculations include A + B, AB, A * B, A / B, A > B, A < B, A == B, and MAX(A, B). Optimizations include the following: Matrix block processing: The large matrix to be operated on is decomposed into multiple smaller blocks; the size of the blocks is dynamically determined based on the processor's vector processing capability; specifically, the number of elements processed continuously in memory for each block is set based on the key parameters of RISC-V vector extension, including the vector register length VLEN, the current data element bit width SEW, and the vector register grouping ratio LMUL. Each block is computed independently, and the element-by-element processing between matrix blocks is achieved using RISC-V vector extension instructions. Memory access mode optimization: To address the row and column alignment issues in matrix operations, the vector loading instruction in RVV, combined with the register reordering mechanism, is used to optimize the memory access order. Output storage optimization: After each block of computation is completed, the result is written directly back to memory, using the RVV vector write-back mechanism to write multiple elements at once. Specifically: in the processing loop, whenever the computation task of a block is completed, the computation result of that block is immediately written from the vector register back to the corresponding location in memory; this process uses the RVV vector storage instruction to write multiple elements at once. 3) Broadcast operation optimization NumPy supports a broadcast mechanism. When a vector or matrix is ​​broadcast to a scalar value, or vice versa, the scalar value must be matched with other elements of the vector or matrix in a broadcast manner. This method incorporates the following optimizations for broadcast scenarios: RISC-V Vector Computation Optimization: In the RISC-V vector register, the scalar value is loaded as a broadcast vector, and batch operations are performed using RVV vector-scalar calculation instructions, including floating-point arithmetic operations, integer arithmetic operations, and comparison operations. This calculation instruction calls the Intrinsic function.

5. The NumPy numerical computation optimization method based on RISC-V vector extension according to claim 4, characterized in that, In step 2), the size of each block is set to an integer multiple of (VLEN / SEW) * LMUL. During loop processing, the vector loading instruction can maximize the filling of the vector register. Therefore, the total number of blocks is determined by dividing the total size of the matrix by the size of a single block calculated according to the parameters above.

6. The NumPy numerical computation optimization method based on RISC-V vector extension according to claim 1, characterized in that, In steps 1-3, data output and result transformation optimization are performed. After element-wise operations, NumPy needs to restore the result from the array to a Python object or return it to an external program; this step optimizes subsequent processing steps, specifically: Batch reading and conversion: The RISC-V vector loading instruction is used to read the calculation results in NumPy arrays in batches. The number of data read each time is determined by the vector length of the hardware and is dynamically adjusted. In other words, flexibility is achieved by dynamically setting the vector length parameter. The read data is converted into Python objects in batches using parallel processing: Integers are wrapped as PyLongObjects; Floating-point numbers are wrapped as PyFloatObject.

7. A NumPy numerical computation optimization system based on RISC-V vector extension, executing the steps of the NumPy numerical computation optimization method based on RISC-V vector extension as described in claim 1; the system includes a function interface and distribution module, a hardware detection module, a dynamic process management module, and an RVV optimization module; The function interface and dispatch module is used to receive NumPy function call requests from the upper-layer application at runtime and obtain the array data to be processed; this module is the entry point of the entire optimization method, and it dispatches the received function call type and data to the dynamic process management module. Hardware detection module: Used to detect whether the target device supports RVV extended instructions when the program starts, and to query its specific hardware characteristics; Dynamic process management module: used to determine whether a specific computing task calls an external high-efficiency library (BLAS) and select the corresponding computing path; RVV Optimization Module: Used to optimize element-wise computation tasks that do not call external high-efficiency libraries using the RVV instruction set, improving performance through vectorized computation.

8. A computer-readable storage medium, characterized in that, It stores a program that, when executed by a processor, implements the steps in the NumPy numerical computation optimization method based on RISC-V vector extension as described in any one of claims 1-6.

9. An electronic device, characterized in that, It includes a memory, a processor, and a program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps in the NumPy numerical computation optimization method based on RISC-V vector extension as described in any one of claims 1-6.

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