A multi-film local area passivation topcon cell and a preparation method thereof
By using photolithography equipment to cover photoresist on the front side of TOPCon solar cells and performing self-aligned exposure and chemical etching, the problem of cell performance loss caused by multi-segment cutting is solved, thereby achieving increased module power and reduced equipment costs, making it suitable for industrial production.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ANHUI XUHE NEW ENERGY TECH CO LTD
- Filing Date
- 2025-10-31
- Publication Date
- 2026-05-29
AI Technical Summary
Existing TOPCon cells suffer from damage and interface recombination issues caused by laser scribing during multi-segment cutting, resulting in cell performance loss and reduced module power. Existing solutions increase equipment costs and complexity, which is not conducive to industrial production.
Photolithography equipment is used to cover the front of the solar cell with photoresist, and self-aligned exposure or drying and curing are performed. Combined with acid bath and alkaline etching, the exposed area is chemically etched away. Finally, the photoresist is cleaned. Only one photolithography equipment is needed to achieve multi-slice local passivation, avoiding high temperature damage and high costs of laser equipment.
It improves the passivation capability of multi-segment localization, increases component power, reduces equipment investment costs, avoids high-temperature damage to laser equipment, and is suitable for industrial production.
Smart Images
Figure CN121240592B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of photovoltaic cell technology, specifically to a multi-segmented locally passivated TOPCon cell and its fabrication method. Background Technology
[0002] As battery power continues to increase and large-size batteries become more common, the manufacturing of corresponding modules requires cutting and dicing. However, the power loss of the battery cells also increases after dicing. For example, TOPCon batteries need to be cut into two, three, or four pieces in the middle, or shingled batteries, all of which require laser dicing, resulting in power loss and a lower CTM (module power to battery power percentage).
[0003] Currently, TOPCon cell cutting is completed at the module end, using laser scribing. However, this method damages the cut surface and lacks passivation, leading to deep-level recombination due to interface impurities. This can easily result in significant interface recombination, causing performance loss and reduced power. Therefore, to improve the scibing loss problem in modules, there are three main solutions: First, applying passivation materials, as described in patent CN112687763A, involves coating or spin-coating a silicon dioxide passivation slurry onto the cut surface. Second, post-cutting coating, as in CN111430506A, uses PECVD or ALD deposition equipment to deposit an aluminum oxide dielectric film on the sides of stacked cells. Third, some industry practices involve laser scribing on the front side of the silicon wafer after boron diffusion oxidation, using alkaline etching to corrode the scribing areas, and then laser-cleaving the cells at the module end. All three methods require additional equipment besides laser scribing. The first method, applying passivation materials, requires additional coating and annealing equipment, increasing the number of processes and equipment costs. The added equipment also increases the breakage rate, hindering industrial production. The second method, coating after cell cutting, requires PECVD or ALD equipment to coat the cut surface, typically with alumina or silicon dioxide passivation films to reduce minority carrier recombination at the cutting interface and improve overall passivation performance and open-circuit voltage. However, this second method requires an additional coating, increasing process and energy costs, and its complexity hinders cost reduction in industrial applications. The third method, laser scribing on the front of the cell followed by alkaline etching to remove the PN junction at the scribing location to reduce cutting losses, requires additional laser equipment, resulting in high equipment costs. Furthermore, the high temperature of the laser causes significant thermal damage to the front PN junction, limiting module power gain.
[0004] Therefore, there is an urgent need for a multi-segmented local passivation TOPCon cell and its fabrication method to solve the above problems. Summary of the Invention
[0005] The purpose of this invention is to provide a multi-segmented locally passivated TOPCon battery and its fabrication method to overcome the above-mentioned shortcomings in the prior art.
[0006] To achieve the above objectives, the present invention provides the following technical solution:
[0007] A multi-segmented locally passivated TOPCon solar cell and its fabrication method, comprising the following steps:
[0008] S1: Texturing, forming a textured surface on the front side of the silicon wafer to reduce reflection and increase light absorption;
[0009] S2: Boron diffusion forms a boron-doped layer on the front side of the silicon wafer, forming the emitter of the PN junction;
[0010] S3: Oxidation, forming a BSG layer by surface oxidation treatment on the boron diffusion surface;
[0011] S4: Photolithography. After boron diffusion oxidation, the front side of the silicon wafer is covered with multiple layers of photoresist in the photolithography equipment, and then the next station performs self-aligned exposure or drying and curing.
[0012] S5: Alkaline polishing, which involves alkaline etching and polishing on the back side of the silicon wafer, and also etching and polishing the areas on the front side that are not covered with photoresist.
[0013] S6: Poly amorphous silicon doping, which involves in-situ doping of amorphous silicon on the back side of a silicon wafer to form a phosphorus-doped amorphous silicon layer.
[0014] S7: Annealing, phosphorus-doped amorphous silicon layer is annealed to form phosphorus-doped polycrystalline silicon layer;
[0015] S8: RCA cleaning removes the poly silicon layer on the front side of the silicon wafer and cleans and removes the BSG and PSG layers on the front and back sides.
[0016] S9: ALD deposition, performing ALD atomic deposition of aluminum oxide coating on the boron-enlarged front side of the silicon wafer;
[0017] S10: Front-side PECVD coating, multi-layer passivation and anti-reflection passivation film is deposited on the front side of the silicon wafer by PECVD.
[0018] S11: Backside PECVD coating, performing PECVD deposition of multilayer passivation and antireflection passivation film on the backside of the silicon wafer;
[0019] S12: Screen printing, metallization printing on the front and back sides of the silicon wafer to form positive and negative electrodes;
[0020] S13: Testing, sorting TOPCon batteries by testing their electrical performance, EL (electrochemical efficiency), and appearance.
[0021] Preferably, in the S4 photolithography equipment, photoresist is injected into the equipment platform through the injection pipeline, and then multiple photoresist sheets are applied to the silicon wafer made in S3 by means of printing, spin coating, transfer or coating. The processed silicon wafer is then transferred to the next station for self-alignment exposure or drying via a roller platform.
[0022] Preferably, the photoresist has a viscosity of 300-750 mPa*s, a coating thickness of 30-80 μm, and a pattern width of 200-1000 μm.
[0023] Preferably, the photoresist material comprises phenolic resin, acrylate, α-naphthol, phenol, phenylphenol, hydroxyl polydiphenylsiloxane, and propylene glycol methyl ether acetate.
[0024] Preferably, the self-aligned exposure or drying curing time in S4 is 15-60 min, and the temperature is 80℃-200℃.
[0025] Preferably, the equipment platform is divided into a filling area and an overflow area by an internal partition. The photoresist is directly added to the filling area through the dispensing pipeline. When the photoresist level in the filling area is higher than the partition, it automatically enters the overflow area. The partition eliminates air bubbles mixed in with the photoresist through the interceptor set at the upper end. The photoresist in the overflow area is used to coat the silicon wafer.
[0026] Preferably, when the photoresist level in the overflow area is higher than the partition, the lower end of the dispensing pipe is submerged below the liquid level to avoid dripping and generating air bubbles.
[0027] Preferably, after the photoresist level in the overflow area exceeds the partition, the partition can be raised to form a passage gap at the lower end for the photoresist to pass through.
[0028] Preferably, the partition can be removed upwards after the photoresist coating is completed.
[0029] A multi-segmented locally passivated TOPCon solar cell, fabricated based on the above-described preparation method, includes: a silicon wafer substrate, on the front side of the silicon wafer substrate, a P++ layer, an AlOx layer, and a SiNx / SiONx / SiOx composite layer are sequentially disposed from the inside out, the P++ layers are spaced out in segments, and a portion of the AlOx layer is filled in the segmentation gaps of the P++ layers; on the back side of the silicon wafer substrate, a SiOx layer, an N+ploy layer, and a SiNx / SiONx / SiOx composite layer are sequentially disposed from the inside out.
[0030] In the above technical solution, the beneficial effects of the present invention are:
[0031] This multi-segment local passivation TOPCon cell fabrication method involves covering the front side of a silicon wafer with a layer of photoresist through printing, spin coating, transfer, or coating. The mask pattern exposes the location areas of 2, 3, 4, or more segments. Then, self-aligned exposure or drying and curing are performed. Afterward, acid and alkaline etching tanks are used to chemically etch away the exposed areas. Finally, the photoresist is removed with chemical solvents and the wafer is cleaned and dried. This method achieves improved multi-segment local passivation capability and increased module power with only one additional photolithography device, while avoiding the high-temperature damage problem and high cost of laser equipment.
[0032] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative only, and are not intended to limit this disclosure.
[0033] This application provides an overview of various implementations or examples of the technology described in this disclosure, and is not a full disclosure of the entire scope or all features of the disclosed technology. Attached Figure Description
[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this invention. For those skilled in the art, other drawings can be obtained based on these drawings.
[0035] Figure 1 A flowchart of Embodiment 1 provided by the present invention;
[0036] Figure 2 A flowchart of the control group 1 provided by the present invention;
[0037] Figure 3 The flowchart for control group two provided by the present invention;
[0038] Figure 4 This is a schematic cross-sectional view of the battery structure provided by the present invention;
[0039] Figure 5 This is a top view of the battery structure provided by the present invention;
[0040] Figure 6 This is a schematic diagram of the photolithography equipment provided by the present invention;
[0041] Figure 7 Provided by the present invention Figure 6 Enlarged structural diagram at point A;
[0042] Figure 8 A partial structural diagram of the filling area and overflow area after the baffle is raised, provided by the present invention;
[0043] Figure 9 This is a schematic diagram of the device platform structure provided by the present invention;
[0044] Figure 10 Provided by the present invention Figure 9 A magnified structural diagram at point B in the middle.
[0045] Explanation of reference numerals in the attached figures:
[0046] 1. Silicon wafer substrate; 2. P++ layer; 3. AlOx layer; 4. SiNx / SiONx / SiOx composite layer; 5. SiOx layer; 6. N+ploy layer; 7. Injection tubing; 8. Roller platform; 9. Partition; 10. Interceptor; 11. Slot; 12. Block; 13. Bending component; 14. Push rod; 15. Toggle lever; 16. Slot. Detailed Implementation
[0047] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. Example
[0048] A method for fabricating multi-segmented locally passivated TOPCon cells includes the following steps:
[0049] S1: Texturing, forming a textured surface on the front side of the silicon wafer to reduce reflection and increase light absorption;
[0050] S2: Boron diffusion forms a boron-doped layer on the front side of the silicon wafer, forming the emitter of the PN junction of the solar cell;
[0051] S3: Oxidation, forming a BSG layer by surface oxidation treatment on the boron diffusion surface;
[0052] S4: Photolithography. After boron diffusion oxidation, the front side of the silicon wafer is covered with multiple photoresist layers in the photolithography equipment through printing, spin coating, transfer, coating and other methods. Then, the next station performs self-aligned exposure or drying and curing.
[0053] S5: Alkaline polishing, which involves alkaline etching and polishing on the back side of the silicon wafer, and also etching and polishing the areas on the front side that are not covered with photoresist.
[0054] S6: Poly amorphous silicon doping process, which involves in-situ doping of amorphous silicon on the back side of a silicon wafer to form a phosphorus-doped amorphous silicon layer.
[0055] S7: Annealing, phosphorus-doped amorphous silicon layer is annealed to form phosphorus-doped polycrystalline silicon layer;
[0056] S8: RCA cleaning removes the poly silicon layer on the front side of the silicon wafer and cleans and removes the BSG and PSG layers on the front and back sides.
[0057] S9: ALD deposition, performing ALD atomic deposition of aluminum oxide coating on the boron-enlarged front side of the silicon wafer;
[0058] S10: Front-side PECVD coating, multi-layer passivation and anti-reflection passivation film is deposited on the front side of the silicon wafer by PECVD.
[0059] S11: Backside PECVD coating, performing PECVD deposition of multilayer passivation and antireflection passivation film on the backside of the silicon wafer;
[0060] S12: Screen printing, metallization printing on the front and back sides of the silicon wafer to form positive and negative electrodes;
[0061] S13: Testing, sorting TOPCon batteries by testing their electrical performance, EL (electrochemical efficiency), and appearance.
[0062] Furthermore, in the S4 photolithography equipment, photoresist is injected into the equipment platform through the injection pipeline 7, and then covered onto the silicon wafer made in S3 through printing, spin coating, transfer, coating and other methods. The processed silicon wafer is transferred to the next station for self-alignment exposure or drying via the roller platform 8. The photoresist viscosity is 300-750 mPa*s, the coating thickness is 30-80um, and the pattern width is 200-1000um. The photoresist material includes phenolic resin, acrylate, α-naphthol, phenol, phenylphenol, hydroxyl polydiphenylsiloxane, and propylene glycol methyl ether acetate. The self-alignment exposure or drying curing time in S4 is 15-60min, and the temperature is 80℃-200℃.
[0063] Control Group 1
[0064] A method for fabricating multi-segment TOPCon cells includes the following steps:
[0065] S1: Texturing, forming a textured surface on the front side of the silicon wafer to reduce reflection and increase light absorption;
[0066] S2: Boron diffusion forms a boron-doped layer on the front side of the silicon wafer, forming the emitter of the PN junction of the solar cell;
[0067] S3: Oxidation, forming a BSG layer by surface oxidation treatment on the boron diffusion surface;
[0068] S4: Alkaline polishing, which involves alkaline etching and polishing on the back side of the silicon wafer;
[0069] S5: Poly amorphous silicon doping, which involves in-situ doping of amorphous silicon on the back side of a silicon wafer to form a phosphorus-doped amorphous silicon layer.
[0070] S6: Annealing, phosphorus-doped amorphous silicon layer is annealed to form phosphorus-doped polycrystalline silicon layer;
[0071] S7: RCA cleaning removes the poly silicon coating on the front side of the silicon wafer and cleans and removes the BSG and PSG layers on the front and back sides.
[0072] S8: ALD deposition, performing ALD atomic deposition of aluminum oxide coating on the boron-expanded front side of the silicon wafer;
[0073] S9: Front-side PECVD coating, multi-layer passivation and anti-reflection passivation film is deposited on the front side of the silicon wafer by PECVD.
[0074] S10: Backside PECVD coating, multilayer passivation and antireflection passivation film is deposited on the backside of the silicon wafer using PECVD.
[0075] S11: Screen printing, metallization printing on the front and back sides of the silicon wafer to form positive and negative electrodes;
[0076] S12: Testing the electrical performance of the TOPCon battery;
[0077] S13: Laser dicing + edge passivation, the whole TOPCon cell is laser-cut into 2, 3, 4 or more pieces and the edges are passivated with aluminum oxide and silicon nitride.
[0078] S14: Testing, sorting TOPCon batteries by electrical performance, EL and appearance; and IV testing, EL and appearance testing and sorting after edge passivation.
[0079] Control Group 2
[0080] A method for fabricating multi-segment TOPCon cells includes the following steps:
[0081] S1: Texturing, forming a textured surface on the front side of the silicon wafer to reduce reflection and increase light absorption;
[0082] S2: Boron diffusion forms a boron-doped layer on the front side of the silicon wafer, forming the emitter of the PN junction of the solar cell;
[0083] S3: Oxidation, forming a BSG layer by surface oxidation treatment on the boron diffusion surface;
[0084] S4: Laser scribing. After boron diffusion oxidation, laser scribing is performed on the front side of the silicon wafer to divide it into 2, 3, 4, or more sections.
[0085] S5: Alkaline polishing, which involves alkaline etching and polishing on the back of the silicon wafer, and also etching and polishing the area marked on the front.
[0086] S6: Poly amorphous silicon doping, which involves in-situ doping of amorphous silicon on the back side of a silicon wafer to form a phosphorus-doped amorphous silicon layer.
[0087] S7: Annealing, phosphorus-doped amorphous silicon layer is annealed to form phosphorus-doped polycrystalline silicon layer;
[0088] S8: RCA cleaning removes the poly silicon coating on the front side of the silicon wafer and cleans the BSG and PSG layers on the front and back sides, as well as the laser-cut surface.
[0089] S9: ALD deposition, performing ALD atomic deposition of aluminum oxide coating on the boron-enlarged front side of the silicon wafer;
[0090] S10: Front-side PECVD coating, multi-layer passivation and anti-reflection passivation film is deposited on the front side of the silicon wafer by PECVD.
[0091] S11: Backside PECVD coating, performing PECVD deposition of multilayer passivation and antireflection passivation film on the backside of the silicon wafer;
[0092] S12: Screen printing, metallization printing on the front and back sides of the silicon wafer to form positive and negative electrodes;
[0093] S13: Testing, performing electrical performance, EL and appearance tests on TOPCon batteries and sorting them.
[0094] Compared with Control Groups 1 and 2, Example 1 has the following advantages: 1. Low equipment investment, requiring only one additional photolithography device in the normal manufacturing process, while also improving the passivation capability of multi-segment localization and increasing module power; 2. No high-temperature process required, avoiding the high-temperature damage problem of laser equipment and the high-temperature problem of ALD deposition and annealing equipment; 3. Using a photoresist self-alignment process, resulting in high grooving accuracy, low efficiency loss at the cell end, high module power gain, and a manufacturing method that is conducive to industrial production integration.
[0095] Compared to the control group 1, the power of the example was increased by 3.66W, and compared to the control group 2, the power of the example was increased by 8.57W, as shown in Table 1;
[0096]
[0097] (Table 1: Comparison of Electrical Performance Data)
[0098] Since modules require the cutting and dicing of solar cells, which can be divided into 2-segment, 3-segment, or more segments, the power loss of the solar cells increases after dicing, resulting in power loss and a decrease in CTM (module power to cell power percentage). In order to improve the problems of power loss and low CTM, this invention provides a multi-segmented locally passivated TOPCon cell and its preparation method. By optimizing the process at the cell end, the problem of power loss due to multi-segment cutting of modules can be improved.
[0099] This invention provides a method for fabricating multi-segmented localized passivation TOPCon cells. A layer of photoresist is applied to the front side of a silicon wafer by means of printing, spin coating, transfer, or coating. The mask pattern exposes the location areas of 2, 3, 4, or more segments. Then, self-aligned exposure or drying and curing is performed. Afterward, acid and alkaline etching are performed to chemically etch away the exposed areas. Finally, the photoresist is removed by chemical solvents and the wafer is cleaned and dried.
[0100] This invention provides a multi-segment locally passivated TOPCon solar cell and its fabrication method. By adding only one photolithography device, it can improve the multi-segment local passivation capability and increase the module power, while avoiding the high-temperature damage problem and high cost of laser equipment. The multi-segment locally passivated TOPCon solar cell and its fabrication method provided by this invention are a fabrication method with low cost, high module power gain, and ease of industrial production integration.
[0101] As a preferred technical solution in Embodiment 1, please refer to... Figure 6-10 The equipment platform is divided into a filling area and an overflow area by an internal partition 9. The photoresist is directly added to the filling area through the dispensing pipe 7. When the photoresist level in the filling area is higher than that of the partition 9, it automatically enters the overflow area. The partition 9 eliminates air bubbles mixed in with the photoresist through the interceptor 10 set at the upper end. The photoresist in the overflow area is used to coat the silicon wafer. Specifically, multiple interceptors 10 are continuously set along the extension direction of the partition 9. The interceptors 10 are composed of two symmetrical inclined plates, with a larger spacing at the end near the filling area and a smaller spacing at the end near the overflow area. The surface of the interceptor 10 near the filling area is provided with sharp needles or cutting blades. The photoresist overflowing from the filling area and passing through the interceptor 10 flows along the surface of the interceptor 10, causing the air bubbles contained therein to be punctured and eliminated by the action of the needles or cutting blades.
[0102] When the height of the photoresist liquid level in the overflow area is 9 higher than the partition plate, the lower end of the glue injection pipeline 7 is immersed below the liquid level height to avoid the generation of bubbles due to dripping; specifically, as the photoresist is continuously injected in the filling area to raise the liquid level, the outlet of the glue injection pipeline 7 is naturally immersed below the liquid level height. Thus, the glue injection pipeline 7 is directly connected below the liquid surface of the photoresist in the filling area, thereby avoiding the generation of bubbles due to dripping.
[0103] After the height of the photoresist liquid level in the overflow area is higher than the partition plate 9, the partition plate 9 can rise to form a passage gap for the photoresist to pass through at the lower end; specifically, the setting of the intercepting member 10 can prevent bubbles from entering the overflow area. However, after being used for a period of time, the surface of the intercepting member 10 is more likely to adhere to the photoresist, resulting in blockage. Moreover, due to the overflow effect, the photoresist at the bottom layer in the filling area cannot flow upward, causing the photoresist to stagnate and solidify. Based on the above problems, the lifting function of the partition plate 9 is set, specifically including: a support groove 11 is provided on the outer side wall of the equipment platform, a support block 12 is arranged to be lifted in the support groove 11, the support block 12 bypasses the side wall of the equipment platform through a bending member 13 and is fixedly connected to the end of the partition plate 9, and the partition plate 9 can be arranged to be lifted in the equipment platform; a top rod 14 is elastically arranged to be lifted in the support groove 11, and the top rod 14 keeps pushing the support block 12 upward so that the partition plate 9 has a tendency to leave and fit the inner bottom surface of the equipment platform. A limiting component is provided on the support block 12, and the limiting component limits the support block 12 when the partition plate 9 fits the inner bottom surface of the equipment platform; the support block 12 is in a "U" shape, the limiting component includes a lever 15 rotatably arranged inside the support block 12, the support groove 11 is in a U shape, and a clamping groove 16 matching the lever 15 is opened on the side wall of the support groove 11. When the partition plate 9 fits the inner bottom surface of the equipment platform, the support block 12 carries the lever 15 at the height corresponding to the clamping groove 16, and the lever 15 can rotate in and out of the clamping groove 16. In actual use, the support block 12 first presses down the top rod 14, and the lever 15 is embedded in the clamping groove 16. At this time, the partition plate 9 fits the inner bottom surface of the equipment platform to eliminate bubbles during the initial filling of the photoresist. After the liquid level height in the filling area submerges the lower end outlet of the glue injection pipeline 7, the lever 15 can be pushed to disengage from the clamping groove 16, then the top rod 14 elastically pushes the support block 12 to rise. Thus, the partition plate 9 rises to form a passage gap for the photoresist to pass through at the lower end, and the photoresist starts to enter the overflow area through the passage gap. The bubbles will not pass through the passage gap because they float on the liquid surface. On the other hand, it can also prevent the photoresist from stagnating and solidifying at the bottom layer in the filling area.
[0104] After the photoresist coating is completed, the partition plate 9 can be removed upward. Specifically, after the partition plate 9 rises to form a passage gap for the photoresist to pass through at the lower end, the upward movement of the support block 12 in the support groove 11 is not restricted, so the partition plate 9 can be directly moved upward and taken out, which is convenient for cleaning the filling area, the overflow area, and the partition plate 9.
[0105] A multi-segmented locally passivated TOPCon solar cell, fabricated based on the above-described preparation method, includes: a silicon substrate 1, on the front side of the silicon substrate 1, a P++ layer 2, an AlOx layer 3, and a SiNx / SiONx / SiOx composite layer 4 are sequentially disposed from the inside out, the P++ layer 2 is segmented at intervals, and a portion of the AlOx layer 3 is filled in the segmentation intervals of the P++ layer 2; on the back side of the silicon substrate 1, a SiOx layer 5, an N+ploy layer 6, and a SiNx / SiONx / SiOx composite layer 4 are sequentially disposed from the inside out.
[0106] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.
Claims
1. A method for fabricating a multi-segmented locally passivated TOPCon battery, characterized in that, Includes the following steps: S1: Texturing, forming a textured surface on the front side of the silicon wafer to reduce reflection and increase light absorption; S2: Boron diffusion forms a boron-doped layer on the front side of the silicon wafer, forming the emitter of the PN junction; S3: Oxidation, the surface of the boron diffusion surface is oxidized to form a BSG layer (borosilicate glass layer). S4: Photolithography. After boron diffusion oxidation, the front side of the silicon wafer is covered with multiple layers of photoresist in the photolithography equipment. Then, the next station performs self-aligned exposure or drying and curing. In the photolithography equipment of S4, photoresist is injected into the equipment platform through the injection pipeline (7). Then, the photoresist is covered onto the silicon wafer made in S3 by multiple layers through printing, spin coating, transfer or coating. The processed silicon wafer is transferred to the next station for self-aligned exposure or drying through the roller platform (8). S5: Alkaline polishing, which involves alkaline etching and polishing on the back side of the silicon wafer, and also etching and polishing the areas on the front side that are not covered with photoresist. S6: Poly amorphous silicon doping, which involves in-situ doping of amorphous silicon on the back side of a silicon wafer to form a phosphorus-doped amorphous silicon layer. S7: Annealing, phosphorus-doped amorphous silicon layer is annealed to form phosphorus-doped polycrystalline silicon layer; S8: RCA cleaning removes the poly silicon coated on the front side of the silicon wafer and cleans and removes the BSG and PSG (phosphosilicate glass) layers on the front and back sides. S9: ALD deposition, performing ALD atomic deposition of aluminum oxide coating on the boron-enlarged front side of the silicon wafer; S10: Front-side PECVD coating, multi-layer passivation and anti-reflection passivation film is deposited on the front side of the silicon wafer by PECVD. S11: Backside PECVD coating, performing PECVD deposition of multilayer passivation and antireflection passivation film on the backside of the silicon wafer; S12: Screen printing, metallization printing on the front and back sides of the silicon wafer to form positive and negative electrodes; S13: Testing, sorting TOPCon batteries by testing their electrical performance, EL (electrochemical efficiency), and appearance.
2. The method for fabricating a multi-segmented locally passivated TOPCon battery according to claim 1, characterized in that, The photoresist has a viscosity of 300-750 mPa*s, a coating thickness of 30-80 μm, and a pattern width of 200-1000 μm.
3. The method for fabricating a multi-segmented locally passivated TOPCon battery according to claim 1, characterized in that, The photoresist material includes phenolic resin, acrylate, α-naphthol, phenol, phenylphenol, hydroxyl polydiphenylsiloxane, and propylene glycol methyl ether acetate.
4. The method for fabricating a multi-segmented locally passivated TOPCon battery according to claim 1, characterized in that, The self-aligned exposure or drying curing time in S4 is 15-60 minutes, and the temperature is 80℃-200℃.
5. The method for fabricating a multi-segmented locally passivated TOPCon battery according to claim 1, characterized in that, The equipment platform is divided into a filling area and an overflow area by an internal partition (9). The photoresist is directly added to the filling area by the injection pipeline (7). When the photoresist level in the filling area is higher than the partition (9), it automatically enters the overflow area. The partition (9) eliminates the air bubbles mixed in the photoresist by the interceptor (10) set at the upper end. The photoresist in the overflow area is used to coat the silicon wafer.
6. The method for fabricating a multi-segmented locally passivated TOPCon battery according to claim 5, characterized in that, When the photoresist level in the overflow area is higher than the partition (9), the lower end of the dispensing pipe is submerged below the liquid level to avoid dripping and generating bubbles.
7. The method for fabricating a multi-segmented locally passivated TOPCon battery according to claim 5, characterized in that, After the photoresist level in the overflow area is higher than the partition (9), the partition (9) can rise to form a passage gap at the lower end for the photoresist to pass through.
8. The method for fabricating a multi-segmented locally passivated TOPCon battery according to claim 5, characterized in that, After the photoresist coating is completed, the partition (9) can be removed upwards.
9. A multi-segmented locally passivated TOPCon battery, fabricated according to the preparation method described in any one of claims 1 to 8, characterized in that, include: A silicon wafer substrate (1) has a P++ layer (2), an AlOx layer (3) and a SiNx / SiONx / SiOx composite layer (4) arranged sequentially from the inside to the outside on the front side of the silicon wafer substrate (1). The P++ layer (2) is arranged in a spaced-out manner, and part of the AlOx layer (3) is filled in the spaced-out areas of the P++ layer (2). The back side of the silicon substrate (1) is provided with a SiOx layer (5), an N+ploy layer (6) and a SiNx / SiONx / SiOx composite layer (4) from the inside to the outside.