CPU microarchitecture performance evaluation methods, bare-metal performance evaluation tools, electronic devices and computer program products
By using the bare-metal performance evaluation tool L5perf, configuring the events to be monitored and the target test code, controlling the execution of the virtual CPU and collecting data, the gap in pre-silicon CPU microarchitecture performance evaluation is filled, enabling accurate performance evaluation and design optimization.
CN121255596BActive Publication Date: 2026-05-26GUANGDONG LEAPFIVE TECH CO LTD
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Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGDONG LEAPFIVE TECH CO LTD
- Filing Date
- 2025-12-05
- Publication Date
- 2026-05-26
AI Technical Summary
Technical Problem
Existing technologies lack methods for evaluating CPU microarchitecture performance in the pre-silicon stage, making it difficult for chip design engineers to accurately optimize design parameters and predict performance risks.
Method used
L5perf is a bare-metal performance evaluation tool that, by configuring the events to be monitored and the target test code, controls the execution of the virtual CPU and collects event execution data, thereby achieving a quantitative evaluation of CPU microarchitecture performance.
Benefits of technology
Accurately evaluate CPU microarchitecture performance without tape-out, providing quantitative analysis and design decision-making basis, and improving chip design efficiency and accuracy.
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Figure CN121255596B_ABST
Abstract
This application relates to the field of computer technology, providing a CPU microarchitecture performance evaluation method, a bare-metal performance evaluation tool, an electronic device, and a computer program product. The method, applied to the bare-metal performance evaluation tool, includes: configuring at least one event to be monitored and target test code based on the performance evaluation requirements of the CPU microarchitecture to be evaluated; controlling a virtual CPU to execute the target test code and collecting event execution data corresponding to all events to be monitored during code execution; the virtual CPU being created based on the CPU microarchitecture to be evaluated; and determining the performance evaluation information of the CPU microarchitecture based on the event execution data. This solution fills the gap in the lack of CPU microarchitecture performance evaluation methods in the pre-silicon stage, enabling the evaluation of CPU microarchitecture performance without the need for tape-out.
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