Peripheral device startup control method, circuit, device, medium and program product

Abstract

The application relates to the technical field of computer hardware, and provides a peripheral device starting control method, a circuit, equipment, a medium and a program product, wherein the method comprises the following steps: monitoring a power state signal and a received external reset signal; in the case that the power state signal is in a stable state, generating an internal reset control signal for indicating that the reset is released; and according to the internal reset control signal for indicating that the reset is released, controlling internal hardware logic circuit to release the reset, so as to trigger the internal hardware logic circuit to perform an initialization starting operation before the external reset signal is released. According to the application, the initialization starting of the internal hardware logic circuit is triggered in advance by using the stable state of the power state signal before the external reset signal is released, the starting time of the internal core logic of the peripheral device is decoupled from the releasing time of the external reset signal, sufficient time is reserved for the time-consuming initialization operation by starting in advance, and therefore the peripheral device starting reliability is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer hardware, and in particular to a peripheral device startup control method, circuit, device, medium and program product. BACKGROUND

[0002] In a computer system, PCIe (Peripheral Component Interconnect express, a high-speed serial computer expansion bus standard) is a mainstream high-speed bus standard connecting a processor host and a peripheral device. In order to ensure system stability, the startup of a PCIe peripheral device must follow the timing defined in the specification and complete the device startup process within the specified time.

[0003] At present, the startup process of a PCIe peripheral device is generally as follows: a board-level power management chip outputs a power stable signal, and when the signal becomes a valid level (for example, a high level), it indicates that the power supply of the PCIe peripheral device is stable; after the power supply is stable, the system waits for a period of time until it detects that the external reset signal from the system changes from a valid reset level to an invalid reset level, and then the PCIe peripheral device starts to execute its internal initialization startup program.

[0004] However, there is a mandatory time requirement in the PCIe specification, for example, the time consumed from the start of the external reset signal changing to the invalid reset level to the PCIe link entering a specific working state (such as the Detect.Active state of the PCIe link state machine) must be very short (such as less than 20 milliseconds).

[0005] In actual application, it is found that for a high-performance PCIe peripheral device with complex internal logic, its initialization startup process (such as loading firmware, self-checking and repairing, configuring logic, etc.) is very time-consuming, and the required time often far exceeds the 20 millisecond window allowed by the above specification. This results in that the PCIe peripheral device using the traditional startup method is difficult to meet the strict requirements of the PCIe specification, thereby causing problems such as device startup failure, system unable to recognize or unstable operation. Therefore, how to optimize the startup process of the PCIe peripheral device to ensure that the device can complete the startup quickly and reliably under the premise of meeting the PCIe specification is a technical problem to be solved in the field. SUMMARY

[0006] The present application provides a peripheral device startup control method, circuit, device, medium and program product to solve the defect that the startup process of the PCIe peripheral device in the related art is difficult to balance its own complex initialization time-consuming requirement and the strict startup timing limitation of the PCIe specification, thereby reducing the startup reliability.

[0007] The present application provides a peripheral device startup control method, comprising:

[0008] monitoring a power state signal and a received external reset signal;

[0009] generating an internal reset control signal indicating a de-reset in a case where it is monitored that the power state signal is in a stable state;

[0010] controlling an internal hardware logic circuit to de-reset according to the internal reset control signal indicating the de-reset, so as to trigger the internal hardware logic circuit to perform an initialization start operation before the external reset signal de- resets.

[0011] According to the peripheral device start control method provided by the present application, further comprising:

[0012] generating an internal reset control signal indicating a reset in a case where it is monitored that the external reset signal jumps from a reset invalid level to a reset valid level during running;

[0013] controlling the internal hardware logic circuit to enter a reset state according to the internal reset control signal indicating the reset.

[0014] According to the peripheral device start control method provided by the present application, the generating of the internal reset control signal indicating the reset in a case where it is monitored that the external reset signal jumps from a reset invalid level to a reset valid level during running, comprises:

[0015] generating a reset edge detection signal lasting for a preset clock period in a case where it is monitored that the external reset signal jumps from a reset invalid level to a reset valid level;

[0016] generating the internal reset control signal indicating the reset based on an effective state of the reset edge detection signal.

[0017] According to the peripheral device start control method provided by the present application, further comprising:

[0018] establishing a priority determination logic for the internal reset control signal generation, wherein the priority determination logic comprises:

[0019] setting a priority of the internal reset control signal indicating the reset generated based on the reset edge detection signal to be higher than a priority of the internal reset control signal indicating the de-reset generated based on the power state signal;

[0020] generating the internal reset control signal indicating the de-reset in response to the stable state of the power state signal only in a case where the effective state of the reset edge detection signal is not detected.

[0021] According to the peripheral device start control method provided by the present application, further comprising:

[0022] After the internal hardware logic circuit performs the initialization start operation, if it is monitored that the external reset signal is changed from a reset valid level to a reset invalid level, the control link state machine enters a detection state to establish a communication link with the host.

[0023] According to the peripheral device start control method provided by the application, the internal reset control signal indicating the release of reset is generated when the power state signal is in a stable state, and the internal reset control signal includes:

[0024] During the period when the external reset signal is still in the reset valid level, if it is monitored that the power state signal is in a valid level indicating stable power supply, the internal reset control signal indicating the release of reset is generated to make the internal hardware logic circuit start to perform the initialization start operation before the external reset signal is changed to the reset invalid level.

[0025] According to the peripheral device start control method provided by the application, after the steps of monitoring the power state signal and the received external reset signal, the method further includes:

[0026] The power state signal and the external reset signal are respectively subjected to debouncing filtering to filter out signal glitches.

[0027] The application further provides a peripheral device start control circuit, which includes:

[0028] A signal monitoring unit is configured to monitor a power state signal and a received external reset signal.

[0029] A signal generating unit is configured to generate an internal reset control signal indicating the release of reset when it is monitored that the power state signal is in a stable state.

[0030] A control output unit is configured to control the release of reset of an internal hardware logic circuit according to the internal reset control signal indicating the release of reset, so as to trigger the internal hardware logic circuit to perform an initialization start operation before the external reset signal is released from reset.

[0031] The application further provides a peripheral device, which includes:

[0032] An internal hardware logic circuit is configured to perform an initialization start operation and a data processing task.

[0033] The peripheral device start control circuit as described above is connected with the internal hardware logic circuit.

[0034] The application further provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor implements the peripheral device start control method according to any one of the above when executing the computer program.

[0035] The application further provides a non-transitory computer readable storage medium, which stores a computer program, wherein the computer program is executed by a processor to implement the peripheral device start control method according to any one of the above.

[0036] The application further provides a computer program product, comprising a computer program, wherein the computer program is executed by a processor to implement the peripheral device start control method according to any one of the above.

[0037] The peripheral device start control method, circuit, device, medium and program product provided by the application break the inherent logic limitation that internal hardware initialization start must wait for the external reset signal to be removed by introducing an internal reset control mechanism triggered by the power state. Specifically, the application adjusts the start timing of the peripheral device, that is, the peripheral device is no longer passively waiting for the external reset signal to become invalid reset level before starting, but generates an internal reset control signal after monitoring that the power supply is stable, so as to remove the reset of the internal hardware logic circuit in advance. Thus, the waiting time window between the power supply stabilization and the removal of the external reset signal can be used to perform initialization and start operations that would otherwise start after the external reset is removed and take a long time. In this way, when the external reset signal becomes invalid reset level, the core initialization process in the peripheral device is mostly or even completely completed, so that the time consumed from when the external reset signal becomes invalid reset level to when the peripheral device link enters a specific working state can be easily and strictly controlled within the extremely short threshold required by the protocol specification. This fundamentally solves the problem that the initialization takes too long to meet the specification timing requirements, thereby improving the success rate and reliability of peripheral device start and ensuring the compatibility of the device and the system. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the application or the related art, the following will briefly introduce the drawings needed to be used in the embodiments or the related art description. Obviously, the drawings in the following description are some embodiments of the application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0039] Figure 1 is the PCIe peripheral device start timing diagram in the related art;

[0040] Figure 2 is the flowchart of the peripheral device start control method provided by the application;

[0041] Figure 3 is a structural schematic diagram of a peripheral device start control circuit provided by the present application;

[0042] Figure 4 is a structural schematic diagram of a peripheral device provided by the present application;

[0043] Figure 5 is a structural schematic diagram of a PCIe peripheral power-on start optimization system provided by the present application;

[0044] Figure 6 is a structural schematic diagram of an electronic device provided by the present application. DETAILED DESCRIPTION

[0045] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below with reference to the drawings in the present application. Obviously, the described embodiments are some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0046] With the rapid development of computer technology, high-speed serial bus standards (such as PCIe) have become mainstream interface standards for connecting processors and various peripheral devices in computer systems. Common PCIe peripherals include GPU (Graphics Processing Unit, graphics processor) cards, hard drives, sound cards, network cards, etc.

[0047] In order to ensure system stability and device compatibility, the power-on process of any PCIe peripheral needs to strictly follow the standard timing defined by the PCIe specification. Figure 1 is a PCIe peripheral start timing diagram in the related art, as shown in Figure 1 , 3.3V auxiliary power usually refers to standby power, which exists before the main power is turned on, and is used to support some basic management and wake-up functions; 3.3V / 12V main power is the main power supply voltage required for PCIe peripheral operation; Power Stable refers to the state in which the main power voltage reaches its rated value and stabilizes, and the device can be reliably powered; PERST refers to the PCIe reset signal, which is usually a low-active signal, that is, when it is at a low level, the device is in a reset state, and when it becomes high, the reset is released and the device starts to start; REFCLK is the reference clock, which is the reference clock signal used by the PCIe bus for synchronous data transmission; Clock Stable refers to the state in which the frequency and amplitude of the reference clock reach the specification requirements and enter a stable state; PCIe link refers to the physical and logical connection established by the PCIe device between systems.

[0048] Based on the above timing diagram, the start-up procedure of a PCIe device generally includes that a power management chip at board level outputs a power stable signal (e.g., Power Stable signal), when the signal becomes valid (e.g., pulled high), it indicates that the power provided for the PCIe device has been stable. After the power is stable, the system waits for a fixed time (e.g., PCIe specification suggests at least 100ms). During this period, the reference clock REFCLK should also reach a stable state, and the external reset signal (PERST) from the host PCIe slot is always in the valid reset state (e.g., low level). It should be noted that, Figure 1 The hatched area at the beginning of PERST indicates that the signal is in an uncertain state during this period.

[0049] After the waiting time, the host system sets the external reset signal PERST to be invalid (e.g., pulled high from low level) to inform the PCIe device that it can start up, and then the PCIe link enters the active state. In the traditional start-up procedure, the PCIe device will only start to perform its internal initialization start-up procedure after detecting that the PERST signal is set to be invalid.

[0050] However, in addition to the above standard timing of start-up, the PCIe specification also makes mandatory requirements for some key time intervals or states during the start-up procedure. Specifically, the PCIe device must meet the following two specification requirements:

[0051] Specification A: from the time when the external reset signal PERST changes from low level (valid reset level) to high level (invalid reset level) to the time when the link training state machine (LTSSM) of the PCIe device enters the Detect.Active state, the time consumed must be less than a very short threshold, for example, 20ms;

[0052] Specification B: when PERST changes from 1 to 0 in the middle, the PCIe device must be globally reset to the initialization state.

[0053] In practice, it is found that the above-mentioned traditional starting mode has certain defects. Specifically, the internal initialization starting flow of modern high-performance PCIe peripherals, such as GPGPU (General-purpose Graphics Processing Unit), is very complex and time-consuming. After the PERST signal becomes invalid, the peripheral needs to perform a series of operations, which may include: sensing and loading configuration information from eFuse (a kind of non-volatile storage unit), repairing the internal storage unit of the chip, initializing the phase-locked loop, loading the boot firmware from the external flash memory, configuring the internal logic of the PCIe interface, and even performing signature verification on the boot firmware in some high-security chips.

[0054] The total time required for these complex initialization operations often exceeds the 20ms time window strictly defined by the PCIe specification. This results in PCIe peripherals using the traditional starting mode being difficult to meet the requirements of the above-mentioned specification A in actual application, thereby possibly causing device startup failure, the host failing to correctly identify the peripheral, system instability, and a series of other problems, seriously affecting the reliability of the entire system and the performance of the product.

[0055] To this end, the present application provides a peripheral starting control method and circuit, which adjusts the starting timing of the PCIe peripheral, decouples the starting time of the internal core logic of the peripheral from the release time of the external system reset signal, and reserves sufficient time for the time-consuming initialization operation by starting early, so that these peripherals complete the device startup faster and meet the PCIe requirements for starting time, thereby overcoming the above-mentioned defects.

[0056] It should be noted that the peripheral starting control method provided by the present application can be executed by a peripheral starting control circuit. The circuit can be integrated in various peripheral devices that need to communicate with the host system (such as a computer motherboard). The peripheral device here can include devices connected to the host through the PCIe interface, such as GPU graphics cards, sound cards, solid state disks, network cards, or other types of expansion cards. Therefore, the peripheral starting control circuit can be a hardware logic circuit module built into the internal core of these PCIe peripheral device chips. The circuit is responsible for managing and controlling the power-on and reset timing of the internal core hardware logic of the peripheral device to ensure that the peripheral device can quickly and reliably complete the startup process and meet the strict timing requirements of the relevant interface protocol (such as the PCIe specification).

[0057] Figure 2 is a flowchart of the peripheral starting control method provided by the present application, as shown in Figure 2 the method comprises:

[0058] Step S10, monitoring the power state signal and the received external reset signal.

[0059] Specifically, the power state signal is a signal used to represent the state of the power supply system of the peripheral device, which is usually generated by a power management chip or a dedicated power monitoring circuit at the board level. When all the power supply voltages of the peripheral device (for example, 3.3V, 12V, etc. for PCIe devices) have been powered on and reach the stable threshold, the power state signal will become a valid level (for example, from logic 0 to logic 1) representing a stable power supply. In a specific scenario of the present application, the signal can be a Power Stable signal. The so-called stable state means that the power supply voltage has reached the nominal voltage range required by the internal hardware logic circuit of the device for normal operation, and the fluctuation is within the allowable error. Before the power state signal becomes a valid level, the internal logic circuit of the device is in an unreliable working state due to insufficient power supply.

[0060] At the same time, the control circuit also monitors the received external reset signal. This signal is usually provided by the host system through the bus interface (for example, the gold finger of the PCIe slot) to reset the entire peripheral device at the hardware level. For PCIe peripherals, the external reset signal is usually a PERST signal. This signal has two states, a reset valid level (for example, low, logic 0) and a reset invalid level (for example, high, logic 1), where the reset valid level indicates that the peripheral device is required to be in and remain in the reset state; the reset invalid level indicates that the peripheral device is allowed to exit the reset state and start normal operation. In the initial stage of system power-on, the host usually sets the external reset signal to the reset valid level and maintains it for a predetermined time (for example, PCIe specifications usually require at least 100ms after power stabilization), and then sets it to the reset invalid level.

[0061] Step S20, generating an internal reset control signal indicating the release of the reset when it is monitored that the power state signal is in a stable state.

[0062] It should be noted that in the traditional startup process, the internal logic of the peripheral device is completely reset according to the external reset signal, that is, only when the external reset signal becomes a reset invalid level, the internal logic is released. The embodiment of the present application breaks this convention.

[0063] Specifically, in this step, an internal reset control signal (which can be named as Root_reset_n signal) is generated inside the startup control circuit of the peripheral device, which directly controls whether the core hardware logic circuit inside the peripheral device is reset or not. When the startup control circuit monitors that the aforementioned power state signal has been in a stable state (for example, the Power Stable signal becomes high level), it will actively generate an internal reset control signal indicating to release the reset, for example, pull the Root_reset_n signal from the reset state of 0 to the non-reset state (also known as release reset state) of 1.

[0064] It can be understood that the triggering condition of this operation is only the stable power state, and does not depend on the state of the external reset signal. In a typical power-on timing, at this time the external reset signal (such as PERST) is still in the reset active level (such as low level). Therefore, this step realizes that the reset signal is generated and sent internally in advance in the case that the external system still requires the peripheral device to be reset, and creates conditions for subsequent initialization operations.

[0065] Step S30, according to the internal reset control signal indicating to release the reset, control the internal hardware logic circuit to release the reset, so as to trigger the internal hardware logic circuit to perform initialization startup operation before the external reset signal is released.

[0066] Specifically, the internal hardware logic circuit refers to the core circuit part of the peripheral device that performs the main function except the startup control circuit itself. For example, for a GPGPU, the internal hardware logic circuit can include a computing unit, a memory controller, various interface intellectual property (Intellectual Property, IP) cores, a phase-locked loop (Phase Locked Loop, PLL) circuit, etc.

[0067] When these internal hardware logic circuits receive the internal reset control signal indicating to release the reset generated by the above step S20, they will exit the reset state and immediately start performing the preset initialization startup operation. These initialization operations are the preparation work that must be completed before the device can work normally, and usually take a long time. For example, these operations can include reading and loading the configuration information of the chip from eFuse, repairing the storage unit inside the chip, initializing the phase-locked loop, firmware loading, firmware signature verification, PCIe controller initialization, etc.

[0068] Since all the above initialization operations are started at a stage when the external reset signal (such as PERST) is still at a reset valid level (such as low level), the embodiment of the present application is equivalent to using the waiting time of at least 100 ms required by the PCIe specification for the PERST signal to remain at low level. When the subsequent external reset signal finally becomes at a reset invalid level (such as high level), the initialization operation inside the peripheral device can have been mostly or even completely completed.

[0069] In the embodiment of the present application, the time-consuming initialization operation originally performed after the PERST is pulled high is advanced to be performed in parallel with the PERST low level maintaining stage before the PERST is pulled high. In this way, the time between the PERST being pulled high and the peripheral device being ready (for example, the PCIe link state machine entering the Detect.Active state) is shortened, so that the strict requirement of the PCIe specification that this time is less than 20 ms can be easily met, and the problem of violating the protocol specification due to too long startup time in the related art is solved, and the startup speed of the peripheral device and the overall boot efficiency of the system are improved.

[0070] The method provided by the embodiment of the present application breaks the inherent logical limitation that the internal hardware initialization startup must wait for the external reset signal to be released by introducing an internal reset control mechanism triggered by the power state. Specifically, the present application adjusts the startup timing of the peripheral device, that is, the peripheral device no longer passively waits for the external reset signal to become at an invalid reset level before starting, but generates an internal reset control signal after monitoring that the power supply is stable, to release the reset of the internal hardware logic circuit in advance. In this way, the waiting time window between the power supply being stable and the external reset signal being released can be used to perform initialization startup operations that would have been started after the external reset was released and that are time-consuming. In this way, when the external reset signal becomes at an invalid reset level, the core initialization process inside the peripheral device has been mostly or even completely completed, so that the time consumed from when the external reset signal becomes at an invalid reset level to when the peripheral device link enters a specific working state can be easily and strictly controlled within the extremely short threshold required by the protocol specification. This fundamentally solves the problem of not being able to meet the specification timing requirements due to too long initialization time, thereby improving the success rate and reliability of the peripheral device startup and ensuring the compatibility of the device and the system.

[0071] Based on any of the above embodiments, after step S10, the method further comprises:

[0072] The power state signal and the external reset signal are respectively subjected to debouncing filtering processing to filter out signal glitches.

[0073] It should be noted that in the actual physical environment, the signal from outside the chip or the state signal generated by the power supply system is often not an ideal digital signal, which may be accompanied by noise, jitter or glitch. These non-ideal factors may cause misjudgment of the control logic, thereby causing system failure. The embodiment of the present application provides an effective means for processing these non-ideal signals.

[0074] Specifically, this step is usually implemented at the signal input end of the start control circuit, which is a filtering process for the original input signal. Specifically, the de-bouncing filtering process can be implemented by using a variety of techniques commonly used in digital circuit design. A simple and effective method is multi-cycle sampling confirmation.

[0075] For the power state signal (such as Power Stable), since it usually changes slowly, the filtering circuit can be designed as follows: when the change of the signal level is detected, the change is not immediately sampled, but is continuously sampled in the next N clock cycles (for example, N can be 4, 8 or greater). Only when the sampling values of the N cycles are all stable at the new level, the output of the filtering circuit (i.e. the purified internal Power Stable signal) will be updated to the new level. This way can effectively filter out the signal glitches caused by the instantaneous voltage drop or rise during the power establishment process.

[0076] For the external reset signal (such as PERST), its jump is a key trigger event. Filtering it is also crucial, which can prevent noise on the system bus from being misjudged as a reset command. The filtering circuit continuously samples the input PERST signal, and only when the signal is stable at a new level (high or low) for a preset M clock cycles, the change is transmitted to the subsequent logic circuit. This ensures that only clear and stable level changes will be recognized as valid state transitions, thereby filtering out transient interference pulses that may exist on the PERST signal line.

[0077] After this step, all subsequent control logic (such as priority determination logic, edge detection logic, etc.) will no longer use the original external signal that may have noise, but will use the clean and stable signal after filtering.

[0078] The embodiment of the present application effectively prevents logic mis-triggering caused by unstable physical signals by adding a de-bouncing filtering link before digital logic processing, for example, avoids the start logic error caused by power glitch to determine that the power has stabilized, or the system accidental reset caused by bus noise.

[0079] Based on any of the above embodiments, step S20 specifically includes:

[0080] During the period when the external reset signal is still at the reset active level, if the power state signal is monitored to be at the active level representing power stabilization, an internal reset control signal indicating de-reset is generated to make the internal hardware logic circuit start to perform the initialization start operation before the external reset signal turns into the reset inactive level.

[0081] Specifically, the embodiment of the present application more explicitly defines the specific time window and conditions of the early start occurrence. For ease of understanding, the following takes a typical PCIe peripheral cold start timing as an example to illustrate.

[0082] When the system is just powered on, the motherboard provides power to the PCIe slot and at the same time sets the PERST signal to low level (i.e. reset active level). At this time, the power management circuit on the peripheral card starts to work, and each voltage gradually establishes. During this process, the external reset signal PERST is continuously at low level. According to the PCIe specification, after the power is stabilized, the signal needs to remain low for at least 100 ms. The embodiment of the present application takes advantage of this time, when the start control circuit of the peripheral monitors the power state signal (such as Power Stable) of the board to be at the active level representing power stabilization (for example, from 0 to 1), it will immediately judge that the power is ready.

[0083] Unlike the traditional start (the traditional start method will continue to wait for PERST to be high), the start control circuit of the embodiment of the present application generates an internal reset control signal (for example, pulls up Root_reset_n) indicating de-reset at this time (i.e. during the period when PERST is still low). This action will make the internal hardware logic circuit be awakened in advance and immediately start to perform the time-consuming initialization start operation. All of this happens within the low level holding phase of the PERST signal. Therefore, these initialization operations have already started before the external reset signal turns into the reset inactive level (i.e. is pulled up), and may even have been completed.

[0084] The embodiment of the present application fundamentally decouples the internal initialization process from the duration of the external reset signal by explicitly defining the trigger condition (power stabilization) and time window (external reset active period) of the internal reset deactivation. It ingeniously moves the originally serially executed internal initialization into the waiting period of PERST low level and executes it in parallel, thereby gaining valuable hundreds of milliseconds of time for initialization and thus being able to solve the start timeout problem.

[0085] Based on the above embodiment, the method further comprises:

[0086] Step S40, after the internal hardware logic circuit performs the initialization start operation, if it is monitored that the external reset signal is changed from a reset valid level to a reset invalid level, the link state machine is controlled to enter a detection state to establish a communication link with the host.

[0087] Specifically, this step is the key link of the whole start flow from the internal preparation phase to the external communication phase. First, the peripheral has performed and completed most or all of the initialization start operation after the power is stable and the external reset signal PERST is still valid (for example, low level). At this time, the internal peripheral is in a ready state waiting for the host instruction.

[0088] In this state, the start control circuit of the peripheral will continue to monitor the external reset signal PERST. When the host system completes its preparation work and is ready to communicate with the peripheral, it will pull up the PERST signal from the reset valid level (such as low level) to change it to the reset invalid level (such as high level). For the start control circuit, this jump from low to high is a clear instruction to start communication.

[0089] After monitoring the rising edge of PERST, the start control circuit will perform a key action, that is, control the link state machine to enter the detection state. The link state machine here refers to the link training state machine (LTSSM) inside the PCIe controller IP core. LTSSM is the core logic defined in the PCIe specification, which is responsible for managing and controlling all state transitions of the physical layer link, including link detection, configuration, training and entering normal working state, etc. During the period of PERST being low, the LTSSM is usually forced to remain in the disabled or reset state.

[0090] The above detection state is one of the initial states of the LTSSM. Once in this state, the PCIe physical layer of the peripheral will start to detect the termination resistance on its sending and receiving pins to determine whether there is a valid device on the opposite side (i.e. the host side). Therefore, when the start control circuit detects that PERST is pulled up, it will release the forced reset of LTSSM and allow it to start working. LTSSM starts from the Detect state and automatically performs subsequent state transitions according to the PCIe specification, eventually establishing a communication link with the host.

[0091] The embodiment of the present application ensures the timing synchronization between the peripheral device and the host side when starting. It provides that the link establishment process requiring the cooperation of both sides is started only after receiving the explicit reset release signal of the host. Since the peripheral device has performed the initialization and starting in advance, it can start the link training immediately with almost zero delay as soon as the host issues the instruction (i.e. PERST is pulled high), because all time-consuming internal preparations have been completed in advance. This ensures that the time from the pulling of PERST high to the availability of the link is compressed to the shortest, thereby reliably meeting the strict requirements of PCIe and other high-speed bus protocols on the starting time.

[0092] Based on any of the above embodiments, the method further comprises:

[0093] Step S50, during the running process, if the external reset signal is monitored to jump from the reset invalid level to the reset valid level, an internal reset control signal indicating reset is generated;

[0094] Step S60, according to the internal reset control signal indicating reset, the internal hardware logic circuit is controlled to enter the reset state.

[0095] It should be noted that the above embodiment mainly introduces the pre-starting behavior of the peripheral device in the power-on starting process (i.e. cold reset), and the embodiment of the present application further explains how the peripheral device responds to the hot reset or warm reset request issued by the host during the normal running process.

[0096] Specifically, after the device completes the initialization and starting process, the external reset signal (e.g. PERST) will change from the reset valid level (e.g. low level) to the reset invalid level (e.g. high level), and then the device enters the normal working state. In this state, the peripheral device starting control circuit will continue to monitor the external reset signal.

[0097] During the running process, if the external reset signal is monitored to jump from the reset invalid level (e.g. high level) to the reset valid level (e.g. low level), an internal reset control signal indicating reset is generated. This step defines the response logic of the device to the external reset command in the normal working state, so as to meet the requirements of specification B in the PCIe protocol specification.

[0098] Here, the running process refers to that the peripheral device has completed the initial power-on and starting, the connection with the host system may have been established, and it can normally perform its main functions. At this time, the power supply is stable, and the external reset signal is also at the reset invalid level (e.g. PERST is high).

[0099] In some cases, the host system can need to reset the peripheral, for example when updating the driver, when the system wakes up from some low power state, or to recover from some error state. In this case, the host system will pull the external reset signal (e.g. PERST) from the reset inactive level (high) to the reset active level (low). This transition is called a warm reset or hot reset event.

[0100] The peripheral start-up control circuit, during the continuous monitoring process, will make a different decision once it captures the high-to-low transition of the external reset signal. Since the power supply is already stable at this time, the decision basis of the start-up control circuit will change to be dominated by the external reset signal. It will immediately generate an internal reset control signal indicating a reset. For example, the internal reset control signal Root_reset_n, which has been in the non-reset state (high) before, will be reset to the reset state (low).

[0101] When the generated internal reset control signal indicating a reset (e.g. Root_reset_n becomes low) is transmitted to the reset pin of the internal hardware logic circuit (including the computing unit, the memory controller, the PLL, the interface IP core, etc.), these circuits will immediately respond. They will abort all current operations, clear the internal state registers, and return to a predefined initial reset state. This achieves a hardware-level reset of the entire peripheral core function.

[0102] After that, the internal hardware logic circuit will remain in the reset state until the external reset signal PERST is pulled high again by the host. When PERST is pulled high, the entire start-up process will start again, and the start-up behavior can be performed again according to the stable state of the power supply state signal (in this hot reset scenario, since the power supply is already stable, the process from PowerStable active to Root_reset_n pull-up will be very fast), or use the traditional start-up mode following the PERST signal, which can be selected according to actual needs.

[0103] The embodiments of the present application not only solve the problem of long start-up time by performing initialization in advance during cold start, ensuring that the protocol timing is met, but also ensure that the peripheral can correctly and reliably respond to the hot reset command of the host by responding to the external reset signal in real time during operation, ensuring the stability and manageability of the system. This dual logic design enables the peripheral to exhibit optimal start-up and reset behavior in different system scenarios.

[0104] Based on any of the above embodiments, step S50 specifically includes:

[0105] Step S51, when the external reset signal is detected to jump from a reset invalid level to a reset valid level, a reset edge detection signal is generated, which lasts for a preset clock cycle.

[0106] It should be noted that in the design of digital circuits, directly using a level signal as a trigger condition may introduce misjudgment caused by signal noise or glitches, and therefore a more reliable edge detection mechanism is adopted in the embodiments of the present application.

[0107] Specifically, in the above embodiments, it is introduced that the start control circuit monitors the jump of the external reset signal (such as PERST) from high to low. The embodiments of the present application specifically implement this, that is, the start control circuit internally includes an edge detection module, which continuously compares the PERST signal level of the current clock cycle with the PERST signal level of the previous clock cycle. When it is detected that the previous cycle is high (reset invalid) and the current cycle is low (reset valid), the module determines that a valid falling edge jump has occurred.

[0108] Once the falling edge is detected, the edge detection module will immediately generate a reset edge detection signal. The signal is a pulse signal, and its active state (for example, high level) lasts for a preset number of clock cycles. For example, the pulse can last only one system clock cycle. The purpose of this design is to convert a continuous low level state (PERST may remain at low level for a long time) into a transient event pulse, which enables the subsequent logic to clearly respond to the reset event, rather than continuously processing the state of being in reset. In addition, the simple edge detection and pulse generation mechanism can effectively filter out the transient noise or glitches that may exist on the PERST signal line. Only a clear level change lasting at least one clock cycle will be recognized as a valid reset command, thereby improving the reliability of the system.

[0109] Step S52, based on the active state of the reset edge detection signal, an internal reset control signal indicating reset is generated.

[0110] Specifically, the active state of the reset edge detection signal (that is, the appearance of the pulse) is used as a clear trigger. The reset logic (for example, a set / reset flip-flop) inside the start control circuit receives this pulse signal. When the pulse signal becomes active, it will immediately trigger the reset logic, thereby generating an internal reset control signal indicating reset. Specifically, the internal reset control signal (such as Root_reset_n) is forcibly set to a reset valid level (such as logic 0).

[0111] The embodiment of the present application converts the response to the external reset signal from an ambiguous level monitoring process to an accurate event pulse based triggering process, which conforms to the standard practice of synchronous digital circuit design, enhances the reliability and anti-interference ability of the hot reset logic by synchronizing the external asynchronous signal and converting it into a single triggering pulse, and ensures that the peripheral device only performs the reset operation when it receives a clear host reset instruction, thereby avoiding accidental reset caused by unstable signals.

[0112] According to any of the above embodiments, the method further comprises:

[0113] establishing a priority decision logic for the internal reset control signal generation, wherein the priority decision logic comprises:

[0114] setting the priority of the internal reset control signal indicating reset generated based on the reset edge detection signal to be higher than the priority of the internal reset control signal indicating un-reset generated based on the power state signal;

[0115] only in the case where the reset edge detection signal is not detected to be in the valid state, responding to the stable state of the power state signal to generate the internal reset control signal indicating un-reset.

[0116] Specifically, the start control circuit of the peripheral device now has two possible sources of triggering the change of the internal reset signal, one is from the stable state of the power state signal (tending to un-reset), and the other is from the external reset edge signal (tending to apply reset). The embodiment of the present application introduces a priority decision mechanism to arbitrate the two sources.

[0117] In order to ensure that the control logic can make a unique and correct decision in any case, the embodiment of the present application designs a priority decision logic (or called arbiter) in the start control circuit. The responsibility of this logic module is to determine the state of the finally generated internal reset control signal (such as Root_reset_n) according to the preset rules. The inputs of the decision logic at least include the power state signal representing the power state and the reset edge detection signal representing the hot reset event.

[0118] The basic rule of arbitration can be set according to a fundamental system design principle, that is, the reset command from the host has absolute priority. Specifically, the action indicating reset (triggered by the hot reset event) is set to have the highest priority, and the action indicating un-reset (triggered by the attempt to start early after the power is stable) is set to have a lower priority.

[0119] The reason for this priority setting is that, no matter what state the peripheral is in (including trying to start early), as long as the host issues a reset command (i.e. the PERST appears falling edge), the peripheral must enter and remain in the reset state unconditionally and immediately. If the priority of the reset release is higher or equal, it is possible that at the moment when the host issues a hot reset command, the peripheral has been mistakenly released from the internal reset due to power stabilization, which will lead to a serious violation of the bus protocol specification.

[0120] It can be understood that the internal reset control signal indicating the release of the reset is generated in response to the stable state of the power state signal only when it is detected that the reset edge detection signal is in the active state. This step is a specific logical implementation of the above-mentioned priority rule. This means that, in the case of monitoring that the power state signal is in a stable state, the behavior of generating the internal reset control signal indicating the release of the reset now adds a precondition that it must be confirmed that no hot reset event is currently occurring.

[0121] In terms of circuit implementation, the logic path for generating the release of the reset signal is controlled by a gate signal, which comes from the judgment of the reset edge detection signal. Only when the reset edge detection signal is in the inactive state (i.e. no pulse appears), the gate will be opened to allow the power stable state signal to trigger the release of the internal reset. Otherwise, as soon as the reset edge detection signal becomes active (pulse appears), the gate will be closed immediately to prevent any release of the reset behavior and at the same time force the internal reset signal to enter the reset state.

[0122] The embodiment of the present application solves the potential conflict problem between the cold start early start logic and the hot reset logic by introducing an explicit priority determination logic. This ensures that the reset behavior of the peripheral strictly follows the system protocol requirements in all cases, i.e. the host reset command has the highest priority.

[0123] The peripheral start control circuit provided by the present application is described below, and the peripheral start control circuit described below can be referred to each other corresponding to the peripheral start control method described above.

[0124] Based on any of the above embodiments, the embodiment of the present application provides a hardware structure of a peripheral start control circuit, which is a physical carrier of the above-mentioned method embodiments, for realizing the peripheral start control method. The circuit can be integrated into the main chip of the peripheral device as an independent IP core. Figure 3 is a structural schematic diagram of the peripheral start control circuit provided by the present application, as shown in Figure 3 The circuit comprises:

[0125] The signal monitoring unit 310 is configured to monitor the power state signal and the received external reset signal.

[0126] The signal generation unit 320 is configured to generate an internal reset control signal indicating a reset release when it is detected that the power state signal is in a stable state.

[0127] The control output unit 330 is configured to control the internal hardware logic circuit to release the reset according to the internal reset control signal indicating the reset release, so as to trigger the internal hardware logic circuit to perform an initialization start operation before the external reset signal is released.

[0128] Specifically, the main function of the signal monitoring unit is to serve as an interface for the circuit to interact with the external environment, and is responsible for receiving and monitoring key state signals. In hardware implementation, this unit can include an input buffer connected to the chip external pin, used to receive the power state signal (such as the Power Stable signal) from the board-level power management circuit; and an input buffer connected to the bus interface pin such as the PCIe golden finger, used to receive the external reset signal (such as the PERST signal) from the host system.

[0129] Optionally, a digital filter or de-bouncing circuit can also be integrated inside this unit. These filters eliminate glitches and noise that may exist on the signal line by sampling and logically judging the input signal for multiple clock cycles, so as to provide stable and clean signals to the subsequent units and ensure the accuracy of decision-making.

[0130] The signal generation unit is the core decision-making logic part of the control circuit. It receives the processed signals from the signal monitoring unit and generates the core internal reset control signal according to the pre-set logic rules. This unit can be composed of standard combinational logic circuits (such as AND gates, OR gates, NOT gates) and sequential logic circuits (such as flip-flops, latches, state machines). Its specific functions and logic implementation can include: when it receives a signal indicating power stabilization, the unit outputs a level indicating reset release to the internal reset control signal; the unit contains an edge detector inside, which is used to capture the falling edge of the external reset signal (hot reset event), and once captured, it immediately outputs a level indicating reset. In addition, the unit can also contain a priority arbiter inside. The arbiter ensures that the priority of the reset request from the edge detector is always higher than that of the reset release request from the power stabilization detection. For example, this can be implemented as a set / reset flip-flop, in which the hot reset event is connected to the set end with higher priority, and the power stabilization event is connected to the reset end with lower priority.

[0131] A control output unit is configured to reliably deliver the internal reset control signal (e.g., Root_reset_n) generated in the signal generation unit to the downstream circuit to be controlled. It receives a single control signal from the signal generation unit and drives it to the reset port of multiple target flip-flops.

[0132] Through the cooperation of the above-mentioned units, the peripheral device startup control circuit provided by the embodiment of the present application solidifies the innovative logic of early startup at the hardware level. It can intelligently distinguish between cold startup and hot reset scenarios, and use the time window between power stabilization and external reset release to complete internal initialization in advance, thereby greatly shortening the total startup time of the device. At the same time, the structured design and built-in priority arbitration logic of the circuit ensure the correctness and robustness of the circuit behavior under various complex working conditions.

[0133] Based on any of the above embodiments, the signal generation unit is further configured to, during operation, generate an internal reset control signal indicating a reset if it is monitored that the external reset signal jumps from a reset invalid level to a reset valid level;

[0134] The control output unit is further configured to control the internal hardware logic circuit to enter a reset state according to the internal reset control signal indicating a reset.

[0135] Based on any of the above embodiments, the signal generation unit is specifically configured to:

[0136] generate a reset edge detection signal lasting for a preset clock period when it is monitored that the external reset signal jumps from a reset invalid level to a reset valid level;

[0137] generate an internal reset control signal indicating a reset based on the valid state of the reset edge detection signal.

[0138] Based on any of the above embodiments, the circuit further comprises a logic establishment unit, and the logic establishment unit is configured to:

[0139] establish a priority determination logic for the internal reset control signal generation, wherein the priority determination logic comprises:

[0140] set the priority of generating the internal reset control signal indicating a reset based on the reset edge detection signal to be higher than the priority of generating the internal reset control signal indicating a reset release based on the power state signal;

[0141] generate the internal reset control signal indicating a reset release in response to the stable state of the power state signal only when the valid state of the reset edge detection signal is not detected.

[0142] Based on any of the above embodiments, the control output unit is further configured to:

[0143] After the internal hardware logic circuit performs the initialization start operation, if it is monitored that the external reset signal is changed from a reset valid level to a reset invalid level, the control link state machine enters a detection state to establish a communication link with the host.

[0144] Based on any of the above embodiments, the signal generation unit is specifically configured to:

[0145] During the period when the external reset signal is still at the reset valid level, if it is monitored that the power state signal is at a valid level representing stable power supply, an internal reset control signal indicating reset release is generated to make the internal hardware logic circuit start to perform the initialization start operation before the external reset signal is changed to the reset invalid level.

[0146] Based on any of the above embodiments, the circuit further comprises a debounce processing unit, which is configured to:

[0147] The power state signal and the external reset signal are respectively subjected to debounce filtering processing to filter out signal glitches.

[0148] Based on any of the above embodiments, Figure 4 is a structural schematic diagram of a peripheral device provided by the application, as Figure 4 shown, the device comprises:

[0149] an internal hardware logic circuit 410 configured to perform an initialization start operation and a data processing task; and a peripheral start control circuit 420 as described in any of the above embodiments, which is connected with the internal hardware logic circuit 410.

[0150] Specifically, the peripheral device can be any board card level or integrated device that needs to perform high-speed communication with a host system, for example, it can be a GPGPU graphics card, a high-speed solid state disk, a 10-gigabit or higher rate Ethernet card, an acceleration card, etc.

[0151] The peripheral device comprises an internal hardware logic circuit and a peripheral start control circuit as described in any of the above embodiments. The internal hardware logic circuit here is the physical basis for the peripheral device to realize its core value and main function. This part of the circuit occupies the main area and power consumption of the chip, and its specific composition varies with the type of device. For example, in a GPGPU graphics card, it includes hundreds of thousands of computing cores composed of stream processors, a rendering pipeline responsible for graphics rendering, a memory controller for connecting the video memory, and interface IPs such as a PCIe controller and a display controller.

[0152] The internal hardware logic circuit has a dual function. First, it needs to perform a series of initialization and startup operations after power-on to prepare for normal work; second, after initialization is completed, it is responsible for performing the main data processing tasks of the device, such as scientific computing, reading and writing user data, and transmitting network data packets.

[0153] There is a clear connection relationship between the peripheral startup control circuit and the internal hardware logic circuit. Specifically, the control output of the peripheral startup control circuit (i.e. the internal reset control signal Root_reset_n) is connected to the asynchronous or synchronous reset pin of almost all timing logic units in the internal hardware logic circuit. This allows the peripheral startup control circuit to place the entire internal hardware logic circuit in a reset state or wake it up from a reset state at any time.

[0154] The signal monitoring unit of the peripheral startup control circuit has input sources from outside the device (such as the PERST signal provided by the mainboard) and other parts of the device board level (such as the Power Stable signal).

[0155] In a complete device, the two parts of the circuit work together. When powered on, the peripheral startup control circuit works first, and after judging that the power is stable, it releases the reset of the internal hardware logic circuit in advance through the control connection, so that it can start initialization. When the host finally releases the external reset, the internal hardware logic circuit is already ready and can immediately perform link training with the host through its PCIe controller part and quickly enter data processing tasks.

[0156] The embodiment of the present application integrates the peripheral startup control circuit into the device, so that the peripheral device has a significant performance advantage. It is no longer subject to the limitations of traditional startup timing and can complete startup and respond to the host at a faster speed. This not only improves the boot experience of end users, but more importantly, ensures that the device can meet the increasingly stringent timing specifications of high-speed bus protocols.

[0157] Based on any of the above embodiments, Figure 5 is the architecture diagram of the PCIe peripheral power-on startup optimization system provided by the present application, as Figure 5 shown, the system implements the peripheral startup control method described in the above embodiments at the hardware level. Its overall architecture and workflow aim to solve the problem of long peripheral startup time while ensuring correct response to various reset scenarios. The system mainly consists of the following functional modules:

[0158] Firstly, the input signals include a reset signal and a power state signal. The reset signal refers to a hardware reset signal provided by an external host system, such as the PERST signal of a PCIe interface, which is used to indicate that the host requires the peripheral to enter or exit a hardware reset state. The power state signal refers to a signal generated by a power management unit or monitoring circuit at the board level of the peripheral, such as the Power Stable signal, which is used to represent whether the power supply voltage of the peripheral has reached the requirement for stable operation.

[0159] The reset signal debouncing module and the power state signal debouncing module are located at the initial stage of signal input. Their function is to receive the original reset signal and power state signal that may have noise or glitches, and process them through digital filtering algorithms to output stable and clean signals. This ensures the reliability of subsequent logic decisions and prevents false judgments caused by signal interference.

[0160] The falling edge detection module is connected in series after the reset signal debouncing module. Its role is to accurately capture the transition of the filtered reset signal from the reset invalid level (such as high level) to the reset valid level (such as low level), i.e. the falling edge. Once this event is detected (usually in a hot reset scenario), it generates a short pulse signal, i.e. the falling edge detection signal, to inform the core decision logic.

[0161] The signal generation module is the core decision unit of the entire system. It receives two key inputs, i.e. the filtered power state signal and the falling edge detection signal from the falling edge detection module. The module has internal priority arbitration logic that generates the final internal reset signal based on the status of these two input signals. The internal reset signal is the output of the signal generation module and is the final reset signal that directly controls the internal core circuit of the peripheral, such as the Root_reset_n signal.

[0162] The hardware logic circuit is the main functional part of the peripheral, including the CPU core, computation unit, memory controller, interface IP, and all circuits that need to be reset controlled. It receives the internal reset signal and enters the reset or starts working according to the state of the signal.

[0163] The working process of the system will be described in detail as follows: firstly, in a cold start scenario, the device is powered on, the power state signal is in an unstable state (such as low level), and the reset signal (such as PERST) is set to the reset valid state (such as low level) by the host. The internal reset signal output by the signal generation module is reset valid (low level), and the hardware logic circuit is in the reset state.

[0164] After a period of time, the power supply of the peripheral device is stable, and the power state signal becomes a stable state (such as a high level). After being confirmed by the power state signal debouncing module, a stable high level signal is sent to the signal generation module. At this time, since the reset signal PERST is always low, no falling edge jump occurs, and the falling edge detection module does not act, and the falling edge detection signal output by the falling edge detection module is in an invalid state.

[0165] The signal generation module receives the power stable signal and confirms that the falling edge detection signal is invalid. According to the priority logic in it, it judges that the current should perform the pre-start operation. Therefore, it flips the internal reset signal Root_reset_n from reset valid (low level) to reset invalid (high level). After the hardware logic circuit receives the internal reset signal which becomes high level, it immediately exits the reset state and starts to perform the time-consuming initialization start operation. All of this happens at the stage when the reset signal PERST is still low.

[0166] When the host is ready, the PERST signal is pulled high, and the internal initialization of the peripheral device is mostly or completely completed. At this time, the peripheral device can immediately respond to the pull-up of PERST to start its PCIe link state machine (LTSSM) to quickly establish a communication link with the host.

[0167] During normal operation of the device, the power state signal is in a stable state, the reset signal PERST is reset invalid (high level), and the internal reset signal is also reset invalid (high level). When the host needs to reset the peripheral device due to a fault, the reset signal PERST is pulled from high to low. The high-to-low jump is filtered by the reset signal debouncing module and accurately captured by the falling edge detection module. The module immediately generates a valid falling edge detection signal pulse.

[0168] The signal generation module receives this valid falling edge detection signal. According to the internal priority arbitration logic, this signal has the highest priority. Therefore, the signal generation module will unconditionally and immediately force the internal reset signal Root_reset_n to be reset to the valid state (low level). The hardware logic circuit receives the internal reset signal which becomes low level, immediately suspends all current tasks, and enters the hardware reset state, thereby correctly responding to the hot reset command of the host.

[0169] The embodiment of the application completely solves the timeout problem of the PCIe peripheral device start-up by adjusting the traditional PCIe start-up timing and adding part of the circuit design. The added circuit area is small, and the added power consumption and cost can be basically ignored.

[0170] Figure 6 An example of an entity structure schematic diagram of an electronic device is shown in Figure 6As shown, the electronic device can include a processor 610, a communication interface 620, a memory 630, and a communication bus 640, wherein the processor 610, the communication interface 620, and the memory 630 can communicate with each other through the communication bus 640. The processor 610 can invoke the logic instructions in the memory 630 to execute the peripheral device startup control method, which includes monitoring a power state signal and a received external reset signal; generating an internal reset control signal indicating a reset release in a case where the power state signal is monitored to be in a stable state; and controlling an internal hardware logic circuit to release the reset according to the internal reset control signal indicating the reset release, so as to trigger the internal hardware logic circuit to perform an initialization startup operation before the external reset signal releases the reset.

[0171] In addition, the logic instructions in the memory 630 described above can be implemented in the form of a software functional unit and sold or used as an independent product, which can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application or parts of the related art that make essential contributions or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the various embodiments of the present application. The aforementioned storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0172] On the other hand, the present application also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer readable storage medium, and the computer program can be executed by a processor to enable a computer to execute the peripheral device startup control method provided by the above-mentioned methods, which includes monitoring a power state signal and a received external reset signal; generating an internal reset control signal indicating a reset release in a case where the power state signal is monitored to be in a stable state; and controlling an internal hardware logic circuit to release the reset according to the internal reset control signal indicating the reset release, so as to trigger the internal hardware logic circuit to perform an initialization startup operation before the external reset signal releases the reset.

[0173] In yet another aspect, the present application also provides a non-transitory computer readable storage medium having stored thereon a computer program, which, when executed by a processor, implements the peripheral start-up control method provided by any of the above methods, and the method comprises: monitoring a power state signal and a received external reset signal; in a case where it is monitored that the power state signal is in a stable state, generating an internal reset control signal indicating a release of a reset; and controlling, according to the internal reset control signal indicating the release of the reset, an internal hardware logic circuit to release the reset, so as to trigger the internal hardware logic circuit to perform an initialization start-up operation before the external reset signal releases the reset.

[0174] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, i.e., may be located in one place, or may be distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the embodiment scheme according to actual needs. Those skilled in the art can understand and implement without creative labor.

[0175] From the above description of the embodiments, those skilled in the art can clearly understand that the embodiments can be realized by means of software plus necessary universal hardware platforms, and of course can also be realized by hardware. Based on such understanding, the above technical solutions, essentially or in terms of related art, can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments.

[0176] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the above-mentioned embodiments of the present application have been described in detail, those skilled in the art should understand that they can still modify the technical solutions recorded in the above-mentioned embodiments, or make equivalent replacement for some technical features; and these modifications or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A peripheral activation control method, characterized by, The method comprises the following steps: monitoring a power state signal and a received external reset signal; generating an internal reset control signal indicating a reset release in a case where the power state signal is monitored to be in a stable state; controlling an internal hardware logic circuit to release a reset according to the internal reset control signal indicating the reset release, so as to trigger the internal hardware logic circuit to perform an initialization start operation before the external reset signal is released from a reset state; the step of generating the internal reset control signal indicating the reset release in the case where the power state signal is monitored to be in the stable state comprises: generating the internal reset control signal indicating the reset release to make the internal hardware logic circuit start to perform the initialization start operation before the external reset signal is changed from a reset active level to a reset inactive level, if the power state signal is monitored to be in a valid level representing a stable power supply during the external reset signal is still in the reset active level.

2. The peripheral activation control method according to claim 1, wherein The method further comprises the following steps: generating an internal reset control signal indicating a reset in a case where the external reset signal is monitored to jump from a reset inactive level to a reset active level during operation; controlling the internal hardware logic circuit to enter a reset state according to the internal reset control signal indicating the reset.

3. The peripheral activation control method according to claim 2, wherein the step of generating the internal reset control signal indicating the reset in the case where the external reset signal is monitored to jump from the reset inactive level to the reset active level comprises: generating a reset edge detection signal lasting for a preset clock period when the external reset signal is monitored to jump from the reset inactive level to the reset active level; generating the internal reset control signal indicating the reset based on a valid state of the reset edge detection signal.

4. The peripheral activation control method according to claim 3, wherein The method further comprises the following steps: establishing a priority determination logic for the internal reset control signal generation, wherein the priority determination logic comprises: setting a priority of generating the internal reset control signal indicating the reset based on the reset edge detection signal to be higher than a priority of generating the internal reset control signal indicating the reset release based on the power state signal; generating the internal reset control signal indicating the reset release in response to the stable state of the power state signal only when the valid state of the reset edge detection signal is not detected.

5. The peripheral activation control method according to Claim 1, characterized by, The method further comprises the following steps: controlling a link state machine to enter a detection state to establish a communication link with a host if the external reset signal is monitored to change from the reset active level to the reset inactive level after the internal hardware logic circuit performs the initialization start operation.

6. The peripheral activation control method according to any one of claims 1 to 5, wherein After the step of monitoring the power state signal and the received external reset signal, the method further comprises the following steps: respectively performing debouncing filtering processing on the power state signal and the external reset signal to filter out signal glitches.

7. A peripheral start-up control circuit, characterized by comprising: The method comprises the following steps: a signal monitoring unit configured to monitor a power state signal and a received external reset signal; a signal generation unit configured to generate an internal reset control signal indicating a reset release in a case where the power state signal is monitored to be in a stable state; The control output unit is used to control the internal hardware logic circuit to release the reset according to the internal reset control signal indicating that the reset is to be released, so as to trigger the internal hardware logic circuit to perform an initialization start-up operation before the external reset signal releases the reset. The signal generation unit is specifically used for: While the external reset signal is still at the reset active level, if the power status signal is detected to be at an active level indicating power stability, an internal reset control signal indicating release from reset is generated, so that the internal hardware logic circuit begins to execute the initialization startup operation before the external reset signal changes to the reset inactive level.

8. A peripheral device, comprising: include: Internal hardware logic circuitry is used to perform initialization startup operations and data processing tasks; as well as The peripheral device startup control circuit as described in claim 7 is connected to the internal hardware logic circuit.

9. An electronic device comprising a memory, a processor, and a computer program stored on the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the peripheral device startup control method as described in any one of claims 1 to 6. 10.A non-transitory computer-readable storage medium having stored thereon a computer program, characterized in that, When the computer program is executed by the processor, it implements the peripheral device startup control method as described in any one of claims 1 to 6.

11. A computer program product comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the peripheral device startup control method as described in any one of claims 1 to 6.

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