Mainboard network wake-up circuit in low power consumption state, mainboard, electronic equipment and method

Abstract

The invention discloses a mainboard network wake-up circuit in a low-power-consumption state, a mainboard, electronic equipment and a method. A first standing power supply supplies power to a network card when the mainboard is in a low-power-consumption mode; the SIO chip enables the second standing power supply to stop supplying power to the CPU chip in a low-power-consumption mode; the network card receives the wake-up signal in the low power consumption mode and sends a first control signal to the mainboard network wake-up module; the mainboard network wake-up module correspondingly sends a second control signal to the SIO chip; the SIO chip correspondingly sends a third control signal to the main board standing electric control module, and sends a fourth control signal to the CPU chip in a preset waiting duration; the main board standing power control module controls a second standing power supply to supply power to the CPU chip after receiving a third control signal; and the CPU chip is started up after receiving the fourth control signal. According to the embodiment of the invention, when the mainboard is in a low-power-consumption state and the CPU chip is shut down, the wake-up signal received by the network card can realize network wake-up.

Description

Technical Field

[0001] This invention relates to the field of computer equipment technology, and in particular to a motherboard wake-up circuit, motherboard, electronic device, and method under low power conditions. Background Technology

[0002] Computers are widely used in various industries, resulting in a vast number of computer motherboards in use. It is well known that computer motherboards consume energy even when the computer is off; some motherboards maintain a power consumption of 2W even when powered off. Given the sheer number of computer motherboards in use, this means that even when the computer is off, it still consumes a significant amount of energy. Therefore, reducing the power consumption of computer motherboards when powered off is essential for energy conservation and emission reduction.

[0003] Currently, to reduce the power consumption of computer motherboards in the shutdown state, some solutions aim to control the power consumption of the computer motherboard to below 0.5W. The working principle of this solution is as follows: after the computer is shut down, only the power supply required for the normal operation of the CPU (Central Processing Unit) RTC (Real-Time Clock) and the SIO chip (Super Input / Output) is maintained. Other power supplies are shut down by a control signal from the SIO chip, entering a low-power state. The working principle of Wake-on-LAN is that after the CPU or Chipset receives a WAKE signal (wake-up signal) from the network card chip, it triggers the computer to enter normal operation. The CPU or Chipset requires power to perform this function. In the low-power state, the power supply to the CPU or Chipset is completely cut off, and the computer's Wake-on-LAN function cannot be used. However, in industries such as education, computers used in cloud classrooms must use the Wake-on-LAN function, making current solutions unsuitable. Summary of the Invention

[0004] This invention provides a motherboard network wake-up circuit, motherboard, electronic device, and method under low power conditions. It aims to solve the problem in the prior art where, in order to reduce the power consumption of the computer motherboard in the power-off state, only the power supply of the CPU's RTC and the power required for the normal operation of the SIO chip are retained after the computer is powered off, and the CPU's power supply is completely cut off, resulting in the inability to wake up the network card.

[0005] In a first aspect, embodiments of the present invention provide a motherboard wake-up circuit for low-power operation, applied to a motherboard of a computer device. The circuit includes an SIO chip, a CPU chip, a network interface card (NIC), a first standby power supply, a second standby power supply, a motherboard standby power control module, and a motherboard wake-up module, all mounted on the motherboard. The first standby power supply is connected to the motherboard wake-up module, the motherboard standby power control module, the SIO chip, the second standby power supply, and the NIC. The motherboard wake-up module is also connected to the SIO chip and the NIC. The second standby power supply is also connected to the CPU chip and the motherboard standby power control module. The SIO chip is also connected to the CPU chip. The first standby power supply provides power to the NIC and the SIO chip when the motherboard is in a low-power mode. The SIO chip causes the motherboard standby power control module to control the second standby power supply to stop supplying power to the CPU chip when the motherboard is in a low-power mode. When the network card receives an external wake-up signal while the motherboard is in low-power mode, it sends a first control signal to the motherboard's network wake-up module. Upon receiving the first control signal, the motherboard's network wake-up module sends a second control signal to the SIO chip. The SIO chip, upon receiving the second control signal, sends a third control signal to the motherboard's standby power control module, and after waiting for a preset waiting time after sending the third control signal, sends a fourth control signal to the CPU chip. The motherboard's standby power control module, upon receiving the third control signal, controls the second standby power supply to power the CPU chip, causing the motherboard to exit low-power mode. The CPU chip powers on upon receiving the fourth control signal.

[0006] In a second aspect, embodiments of the present invention also provide a motherboard that includes a motherboard network wake-up circuit in a low-power state as described in the first aspect above.

[0007] Thirdly, embodiments of the present invention also provide an electronic device, which includes a motherboard network wake-up circuit in a low-power state as described in the first aspect above, or includes a motherboard as described in the second aspect above.

[0008] Fourthly, embodiments of the present invention also provide a method for waking up a motherboard network in a low-power state, which is applied to a motherboard network wake-up circuit in a low-power state as described in the first aspect above, and the motherboard network wake-up circuit in a low-power state is applied to the motherboard of a computer device; the method for waking up a motherboard network in a low-power state includes: When the network card in the motherboard network wake-up circuit under low power mode receives an external wake-up signal while the motherboard is in low power mode, it sends a first control signal to the motherboard network wake-up module in the motherboard network wake-up circuit under low power mode; wherein, the first standby power supply is used to supply power to the network card when the motherboard is in low power mode, and when the motherboard is in low power mode, the SIO chip in the motherboard network wake-up circuit under low power mode causes the motherboard standby power control module to control the second standby power supply in the motherboard network wake-up circuit under low power mode to stop supplying power to the CPU chip; When the motherboard wake-up module receives the first control signal, it sends a second control signal to the SIO chip. When the SIO chip receives the second control signal, it sends a third control signal to the motherboard standby power control module in the motherboard network wake-up circuit under low power conditions, and sends a fourth control signal to the CPU chip after waiting for a preset waiting time after the third control signal is sent. When the motherboard standby power control module receives the third control signal, it controls the second standby power supply to supply power to the CPU chip in the motherboard network wake-up circuit under low power mode, so that the motherboard exits the low power mode. The CPU chip powers on when it receives the fourth control signal.

[0009] This invention provides a motherboard network wake-up circuit, a motherboard, an electronic device, and a method for low-power operation. The circuit includes an SIO chip, a CPU chip, a network card, a first backup power supply, a second backup power supply, a motherboard backup power control module, and a motherboard network wake-up module, all mounted on the motherboard. The first backup power supply is connected to the motherboard network wake-up module, the motherboard backup power control module, the SIO chip, the second backup power supply, and the network card. The motherboard network wake-up module is also connected to the SIO chip and the network card. The second backup power supply is also connected to the CPU chip and the motherboard backup power control module. The SIO chip is also connected to the CPU chip. The first backup power supply powers the network card when the motherboard is in low-power mode. The SIO chip enables the motherboard to maintain a backup power supply when the motherboard is in low-power mode. The power control module controls the second backup power supply to stop supplying power to the CPU chip; when the network card receives an external wake-up signal while the motherboard is in low-power mode, it sends a first control signal to the motherboard's network wake-up module; the motherboard's network wake-up module, upon receiving the first control signal, sends a second control signal to the SIO chip; the SIO chip, upon receiving the second control signal, sends a third control signal to the motherboard's backup power control module, and after waiting for a preset waiting time after the third control signal is sent, sends a fourth control signal to the CPU chip; the motherboard's backup power control module, upon receiving the third control signal, controls the second backup power supply to supply power to the CPU chip, so that the motherboard exits low-power mode; the CPU chip, upon receiving the fourth control signal, powers on. This embodiment of the invention enables network wake-up when the motherboard is in a low-power state and the CPU chip is powered off, provided the network card receives an external wake-up signal. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic block diagram of the motherboard network wake-up circuit in a low-power state according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the circuit structure of the motherboard standby power control module in the motherboard network wake-up circuit under low power consumption state according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the circuit structure of the motherboard network wake-up module in the motherboard network wake-up circuit under low power consumption conditions according to an embodiment of the present invention; Figure 4 A flowchart illustrating the motherboard network wake-up method under low power conditions provided in an embodiment of the present invention; Figure 5This is a schematic diagram of a sub-process of the motherboard network wake-up method under low power consumption provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of another sub-process of the motherboard network wake-up method under low power conditions provided in an embodiment of the present invention. Detailed Implementation

[0012] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0013] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0014] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0015] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0016] Please see Figure 1 , Figure 1 This is a schematic block diagram of the motherboard network wake-up circuit in a low-power state according to an embodiment of the present invention. Figure 1As shown, this low-power wake-up network circuit is applied to the motherboard of a computer device, and includes an SIO chip 10, a CPU chip 20, a network card 30, a first backup power supply 40, a second backup power supply 50, a motherboard backup power control module 60, and a motherboard wake-up network module 70, all mounted on the motherboard (not shown). The first backup power supply 40 is connected to the motherboard wake-up network module 70, the motherboard backup power control module 60, the SIO chip 10, the second backup power supply 50, and the network card 30. The motherboard wake-up network module 70 is also connected to... The SIO chip 10 and the network card 30 are both connected; the second standby power supply 50 is also connected to the CPU chip 20 and the motherboard standby power control module 60; the SIO chip 10 is also connected to the CPU chip 20; the first standby power supply 40 is used to supply power to the network card 30 and the SIO chip 10 when the motherboard is in a low-power mode; the SIO chip 10 is used to cause the motherboard standby power control module 60 to control the second standby power supply 50 to stop supplying power to the CPU chip 20 when the motherboard is in a low-power mode; When the motherboard receives an external wake-up signal while in low-power mode, the network card 30 sends a first control signal to the motherboard wake-up module 70. Upon receiving the first control signal, the motherboard wake-up module 70 sends a second control signal to the SIO chip 10. The SIO chip 10, upon receiving the second control signal, sends a third control signal to the motherboard standby power control module 60, and after waiting for a preset waiting time after the third control signal is sent, sends a fourth control signal to the CPU chip 20. The motherboard standby power control module 60, upon receiving the third control signal, controls the second standby power supply 50 to supply power to the CPU chip 20, thereby causing the motherboard to exit low-power mode. Upon receiving the fourth control signal, the CPU chip 20 powers on.

[0017] In this embodiment, the first backup power supply 40 supplies power to the network card 30, the motherboard wake-up module 70, and the SIO chip 10 when the motherboard is in low-power mode, while the second backup power supply 50 stops supplying power to the CPU chip 20. When the motherboard is in low-power mode, the second backup power supply 50 not only stops supplying power to the CPU chip 20, but the first backup power supply 40 also maintains only the RTC battery voltage and the +3.3V_STBY voltage required by the network card 30, the motherboard wake-up module 70, and the SIO chip 10, thereby maintaining the motherboard in low-power mode to achieve low power consumption.

[0018] Subsequently, if the network card 30 receives an external wake-up signal while the motherboard is in low-power mode (e.g., when the motherboard is located inside the computer case used in the cloud classroom), and another smart terminal (such as a tablet, laptop, smartphone, or desktop computer) remotely connected to the computer sends a wake-up signal to the network card 30, the network card 30, while in low-power mode, will generate a first control signal and send it to the motherboard's network wake-up module 70. After receiving the first control signal, the motherboard's network wake-up module 70, in order to subsequently wake up and power on the CPU chip 20, also needs to generate a second control signal and send it to the SIO chip 10. Then, upon receiving the second control signal, the SIO chip 10 generates a third control signal and sends it to the motherboard standby power control module 60. After waiting for a preset waiting time (e.g., 100ms, 200ms, 300ms, 400ms, etc., which is not limited to the above example and can be customized according to actual needs) after the third control signal is sent, it sends a fourth control signal to the CPU chip 20. Finally, upon receiving the third control signal, the motherboard standby power control module 60 controls the second standby power supply 50 to supply power to the CPU chip 20 and prepares for the CPU chip 20 to power on, so that the motherboard exits low-power mode. Simultaneously, the CPU chip 20 powers on upon receiving the fourth control signal. Therefore, through the above method, when the motherboard is in a low-power state and the CPU chip is powered off, a wake-up signal received by the network card from an external source can achieve network wake-up.

[0019] In one embodiment, such as Figures 1-2 As shown, the motherboard standby power control module 60 includes a first MOSFET Q1, a second MOSFET Q2, a first capacitor C1, a second capacitor C2, a first resistor R1, and a second resistor R2. The source of the first MOSFET Q1 is connected to the first standby power supply 40, the drain of the first MOSFET Q1 is connected to the second standby power supply 50, and the gate of the first MOSFET Q1 is connected to the SIO chip 10 through the first resistor R1. The gate of the first MOSFET Q1 is also grounded through the first capacitor C1 and the second capacitor C2 connected in parallel. The gate of the second MOSFET Q2 is connected to the first standby power supply through the second resistor R2, the source of the second MOSFET Q2 is grounded, and the drain of the second MOSFET Q2 serves as a connection terminal.

[0020] In this embodiment, the first MOSFET Q1 can be a PMOS transistor, and the second MOSFET Q2 can be an NMOS transistor. When the SIO chip 10 starts working after being connected to the +V3.3_STBY signal provided by the first backup power supply 40, it outputs a 5VSB_CTL_N signal at a high level of 3.3V. At this time, the first MOSFET Q1 and the second MOSFET Q2 are reverse-biased and cut off, causing the motherboard backup power control module 60 to control the second backup power supply 50 to stop supplying power to the CPU chip 20. The motherboard is then in a low-power mode. When the drain of the second MOSFET Q2 is used as a connection terminal, it can be connected to other power supplies on the motherboard (such as other motherboard power supplies besides the first backup power supply 40 and the second backup power supply 50). Using the drain of the second MOSFET Q2 as a connection terminal allows control of the on / off state of these other power supplies on the motherboard.

[0021] Subsequently, since the network card 30 has been powered and working normally by the +3.3V_STBY voltage of the first backup power supply 40, after receiving the wake-up signal from the outside, it will output a low-level WAKE_N signal to the motherboard network wake-up module 70. Under the indirect influence of the motherboard network wake-up module 70 on the motherboard backup power control module 60, the first MOSFET Q1 and the second MOSFET Q2 will be controlled to saturate and conduct, so that the motherboard backup power control module 60 will no longer control the second backup power supply 50 to stop supplying power to the CPU chip 20, and prepares for the subsequent control of the second backup power supply 50 to supply power to the CPU chip so that the CPU chip 20 can be powered on. At this time, the motherboard also exits the low power mode.

[0022] In one embodiment, such as Figures 1-3 As shown, the motherboard network wake-up module 70 includes a third MOSFET Q3, a first diode D1, a first transient voltage suppressor TVS1, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The source of the third MOSFET Q3 is connected to the network card 30 and is also connected to the first standby power supply 40 through the third resistor R3. The gate of the third MOSFET Q3 is connected to the first standby power supply 40 through the fourth resistor R4. The drain of the third MOSFET Q3 is connected to the cathode of the first diode D1. The anode of the first diode D1 is grounded through the first transient voltage suppressor TVS1 and is also connected to the SIO chip 10 through the fifth resistor R5.

[0023] In this embodiment, the motherboard network wake-up module 70 is also powered by the +3.3V_STBY voltage of the first standby power supply 40 and works normally when the motherboard is in low power mode. After the network card 30 receives a wake-up signal from the outside, it will output a low-level WAKE_N signal to the motherboard network wake-up module 70. At this time, the third MOSFET Q3 is saturated and turned on. After its drain outputs a low level, it pulls the PBTNJ_SIO signal output to the SIO chip 10 low through the first diode D1. The PBTNJ_SIO signal is input to the SIO chip 10. After the SIO chip 10 receives the PBTNJ_SIO signal as low, it will pull the 5VSB_CTL_N signal low, thereby making the first MOSFET Q1 and the second MOSFET Q2 in the motherboard standby power control module 60 saturated and turned on.

[0024] As can be seen, the embodiment of this circuit can achieve network wake-up when the motherboard is in a low-power state and the CPU chip is powered off, by receiving a wake-up signal from the outside through the network card.

[0025] This invention also provides a motherboard that includes a motherboard network wake-up circuit in a low-power state as described in any of the preceding embodiments.

[0026] In this embodiment, the motherboard includes a low-power wake-up circuit as described in any of the foregoing embodiments, and therefore possesses at least all the beneficial effects brought about by the technical solutions of the foregoing embodiments, which will not be elaborated upon here. In a specific implementation, the motherboard is a computer motherboard.

[0027] This invention also provides an electronic device, which includes a motherboard network wake-up circuit in a low-power state as described in any of the foregoing embodiments, or includes a motherboard as described in any of the foregoing embodiments.

[0028] In this embodiment, the electronic device includes a motherboard network wake-up circuit in low-power state as described in any of the foregoing embodiments, or includes a motherboard as described in any of the foregoing embodiments. Therefore, it has at least all the beneficial effects brought about by the technical solutions of the foregoing embodiments, which will not be elaborated here. In specific implementations, the electronic device is a computer device, which may be a laptop, all-in-one computer, PC (i.e., personal computer), cloud computer, industrial control system, or server, etc.

[0029] Figure 4 This is a flowchart illustrating a low-power motherboard network wake-up method according to an embodiment of the present invention. This low-power motherboard network wake-up method is applied to a low-power motherboard network wake-up circuit as described in any of the preceding embodiments, and the low-power motherboard network wake-up circuit is applied to the motherboard of a computer device; as... Figure 4 As shown, the motherboard network wake-up method under low power conditions includes the following steps S110-S150.

[0030] S110. When the motherboard receives an external wake-up signal in the low-power state motherboard network wake-up circuit, the network card in the low-power state motherboard network wake-up circuit sends a first control signal to the motherboard network wake-up module in the low-power state motherboard network wake-up circuit.

[0031] Wherein, the first standby power supply is used to supply power to the network card when the motherboard is in a low-power mode, and when the motherboard is in a low-power mode, the SIO chip in the motherboard network wake-up circuit causes the motherboard standby power control module to control the second standby power supply in the motherboard network wake-up circuit to stop supplying power to the CPU chip.

[0032] In this embodiment, simultaneously combined Figure 1 The first backup power supply 40 supplies power to the network card 30, the motherboard wake-up module 70, and the SIO chip 10 when the motherboard is in low-power mode, while the second backup power supply 50 stops supplying power to the CPU chip 20. In low-power mode, the second backup power supply 50 not only stops supplying power to the CPU chip 20, but the first backup power supply 40 also maintains only the RTC battery voltage and the +3.3V_STBY voltage required by the network card 30, the motherboard wake-up module 70, and the SIO chip 10, thus maintaining the motherboard in low-power mode to achieve low power consumption.

[0033] If the network card 30 receives an external wake-up signal while the motherboard is in low-power mode, for example, when the motherboard is located inside the computer case used in the cloud classroom, and another smart terminal (such as a tablet computer, laptop computer, smartphone, desktop computer, etc.) remotely connected to the computer sends a wake-up signal to the network card 30 of the computer, the network card 30 will generate a first control signal and send the first control signal to the motherboard network wake-up module 70 when it receives the external wake-up signal while the motherboard is in low-power mode.

[0034] In one embodiment, step S110 includes: When the motherboard receives an external wake-up signal while in low-power mode, the network card sends a low-level WAKE_N signal to the motherboard's network wake-up module as the first control signal.

[0035] In this embodiment, when the network card receives an external wake-up signal while the motherboard is in low-power mode, more specifically, it sends a low-level WAKE_N signal to the motherboard network wake-up module as the first control signal. The low-level WAKE_N signal can cause the motherboard network wake-up module 70 to indirectly influence the motherboard standby power control module 60, so that the motherboard standby power control module 60 no longer controls the second standby power supply 50 to stop supplying power to the CPU chip 20.

[0036] S120. When the motherboard wake-up module receives the first control signal, it sends a second control signal to the SIO chip.

[0037] In this embodiment, simultaneously combined Figure 1 When the motherboard network wake-up module 70 receives the first control signal, in order to enable the subsequent wake-up and power-on of the CPU chip 20, the motherboard network wake-up module 70 also needs to generate a second control signal and send the second control signal to the SIO chip 10.

[0038] In one embodiment, such as Figure 1 and Figure 3 As shown, the motherboard wake-up module 70 includes a third MOSFET Q3, a first diode D1, a first transient voltage suppressor TVS1, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The source of the third MOSFET Q3 is connected to the network card 30 and also to the first standby power supply 40 through the third resistor R3. The gate of the third MOSFET Q3 is connected to the first standby power supply 40 through the fourth resistor R4. The drain of the third MOSFET Q3 is connected to the cathode of the first diode D1. The anode of the first diode D1 is grounded through the first transient voltage suppressor TVS1 and also to the SIO chip 10 through the fifth resistor R5. Figure 5 As shown, step S120 includes: S121, the third MOS transistor of the motherboard network wake-up module is saturated and turned on, and the drain of the third MOS transistor outputs a low level to the negative terminal of the first diode; S122, The first diode pulls the PBTNJ_SIO signal to a low level through the low level output from the drain of the third MOS transistor, which serves as the second control signal.

[0039] In this embodiment, the motherboard network wake-up module 70 is also powered by the +3.3V_STBY voltage of the first standby power supply 40 and works normally when the motherboard is in low power mode. After the network card 30 receives a wake-up signal from the outside, it will output a low-level WAKE_N signal to the motherboard network wake-up module 70. At this time, the third MOSFET Q3 is saturated and turned on. After its drain outputs a low level, it pulls the PBTNJ_SIO signal output to the SIO chip 10 low through the first diode D1. The PBTNJ_SIO signal is input to the SIO chip 10. After the SIO chip 10 receives the PBTNJ_SIO signal as low, it will pull the 5VSB_CTL_N signal low, thereby making the first MOSFET Q1 and the second MOSFET Q2 in the motherboard standby power control module 60 saturated and turned on.

[0040] S130. When the SIO chip receives the second control signal, it sends a third control signal to the motherboard standby power control module in the motherboard network wake-up circuit under low power conditions, and sends a fourth control signal to the CPU chip after waiting for a preset waiting time after the third control signal is issued.

[0041] In this embodiment, simultaneously combined Figure 1 When the SIO chip 10 receives the second control signal, it generates a third control signal and sends the third control signal to the motherboard standby power control module 60. After the third control signal is sent, it waits for a preset waiting time (such as 100ms, 200ms, 300ms, 400ms, etc., and the preset waiting time is not limited to the above example and can be customized according to actual needs) and then sends a fourth control signal to the CPU chip 20.

[0042] In one embodiment, such as Figure 1 and Figure 2 As shown, the motherboard standby power control module 60 includes a first MOSFET Q1, a second MOSFET Q2, a first capacitor C1, a second capacitor C2, a first resistor R1, and a second resistor R2. The source of the first MOSFET Q1 is connected to the first standby power supply 40, the drain of the first MOSFET Q1 is connected to the second standby power supply 50, and the gate of the first MOSFET Q1 is connected to the SIO chip 10 through the first resistor R1. The gate of the first MOSFET Q1 is also grounded through the first capacitor C1 and the second capacitor C2 connected in parallel. The gate of the second MOSFET Q2 is connected to the first standby power supply through the second resistor R2, the source of the second MOSFET Q2 is grounded, and the drain of the second MOSFET Q2 is connected to the SIO chip 10. Figure 6 As shown, step S130 includes: S131. When the SIO chip receives the second control signal, it pulls the 5VSB_CTL_N signal to a low level as the third control signal and sends the third control signal to the motherboard standby power control module. S132. After waiting for a preset waiting time, the SIO chip outputs a low-level PBTN signal as the fourth control signal and sends the fourth control signal to the CPU chip.

[0043] In this embodiment, please combine with Figures 1-3In a specific implementation, the first MOSFET Q1 can be a PMOS transistor, and the second MOSFET Q2 can be an NMOS transistor. When the SIO chip 10 starts working after being connected to the +V3.3_STBY signal provided by the first backup power supply 40, it outputs a 5VSB_CTL_N signal at a high level of 3.3V. At this time, the first MOSFET Q1 and the second MOSFET Q2 are reverse-biased and cut off, so that the motherboard backup power control module 60 controls the second backup power supply 50 to stop supplying power to the CPU chip 20. At this time, the motherboard is in a low-power mode.

[0044] Subsequently, since the network card 30 has been powered and working normally by the +3.3V_STBY voltage of the first backup power supply 40, after receiving the wake-up signal from the outside, it will output a low-level WAKE_N signal to the motherboard network wake-up module 70. Under the indirect influence of the motherboard network wake-up module 70 on the motherboard backup power control module 60, the first MOSFET Q1 and the second MOSFET Q2 will be controlled to saturate and conduct, so that the motherboard backup power control module 60 will no longer control the second backup power supply 50 to stop supplying power to the CPU chip 20, and prepares for the subsequent control of the second backup power supply 50 to supply power to the CPU chip so that the CPU chip 20 can be powered on. At this time, the motherboard also exits the low power mode.

[0045] S140. When the motherboard standby power control module receives the third control signal, it controls the second standby power supply to supply power to the CPU chip in the motherboard network wake-up circuit under low power mode, so that the motherboard exits the low power mode.

[0046] In this embodiment, simultaneously combined Figure 1 When the motherboard standby power control module 60 receives the third control signal, it controls the second standby power supply 50 to supply power to the CPU chip 20 and prepares for the CPU chip 20 to power on, so that the motherboard exits the low power mode.

[0047] In one embodiment, step S140 includes: When the motherboard standby power control module receives the third control signal, it controls the second standby power supply to sequentially power on the unpowered components on the motherboard, so that the motherboard exits the low-power mode and supplies power to the CPU chip.

[0048] In this embodiment, when the motherboard standby power control module receives the third control signal, it controls the second standby power supply to sequentially power on the unpowered components on the motherboard in a time sequence to provide other operating voltages such as +V3.3A, +V5.0A, and +V1.8A. The unpowered components on the motherboard should be powered on sequentially in a time sequence, rather than powering on all components on the motherboard simultaneously.

[0049] S150, The CPU chip powers on when it receives the fourth control signal.

[0050] In this embodiment, the CPU chip 20 powers on upon receiving a fourth control signal, which can be a low-level PBTN signal sent by the SIO chip. Furthermore, in specific implementations, the chip 20 mentioned in this application can be replaced with a chipset.

[0051] As can be seen, the embodiments of this method can achieve network wake-up when the motherboard is in a low-power state and the CPU chip is powered off, and the network card receives a wake-up signal from the outside.

[0052] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0053] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of each unit is merely a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0054] The steps in the method of this invention can be adjusted, merged, or reduced in order according to actual needs. The units in the device of this invention can be merged, divided, or reduced according to actual needs. Furthermore, the functional units in the various embodiments of this invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0055] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a terminal, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.

[0056] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A motherboard network wake-up circuit in a low-power state, applied to the motherboard of a computer device, characterized in that, The system includes an SIO chip, a CPU chip, a network card, a first backup power supply, a second backup power supply, a motherboard backup power control module, and a motherboard wake-up module, all mounted on the motherboard. The first backup power supply is connected to the motherboard wake-up module, the motherboard backup power control module, the SIO chip, the second backup power supply, and the network card. The motherboard wake-up module is also connected to the SIO chip and the network card. The second backup power supply is also connected to the CPU chip and the motherboard backup power control module. The SIO chip is also connected to the CPU chip. The first backup power supply powers the network card and the SIO chip when the motherboard is in a low-power mode. The SIO chip enables the motherboard backup power control module to control the second backup power supply to stop powering the CPU chip when the motherboard is in a low-power mode. When the network card receives an external wake-up signal while the motherboard is in low-power mode, it sends a first control signal to the motherboard's network wake-up module. Upon receiving the first control signal, the motherboard's network wake-up module sends a second control signal to the SIO chip. The SIO chip, upon receiving the second control signal, sends a third control signal to the motherboard's standby power control module, and after waiting for a preset waiting time after sending the third control signal, sends a fourth control signal to the CPU chip. The motherboard's standby power control module, upon receiving the third control signal, controls the second standby power supply to power the CPU chip, causing the motherboard to exit low-power mode. The CPU chip powers on upon receiving the fourth control signal.

2. The motherboard network wake-up circuit under low power consumption state according to claim 1, characterized in that, The motherboard standby power control module includes a first MOSFET, a second MOSFET, a first capacitor, a second capacitor, a first resistor, and a second resistor. The source of the first MOSFET is connected to the first standby power supply, the drain of the first MOSFET is connected to the second standby power supply, and the gate of the first MOSFET is connected to the SIO chip through the first resistor. The gate of the first MOSFET is also grounded through the first capacitor and the second capacitor connected in parallel. The gate of the second MOSFET is connected to the first standby power supply through the second resistor, the source of the second MOSFET is grounded, and the drain of the second MOSFET serves as a connection terminal.

3. The motherboard network wake-up circuit under low power consumption state according to claim 1, characterized in that, The motherboard wake-up module includes a third MOSFET, a first diode, a first transient voltage suppressor, a third resistor, a fourth resistor, and a fifth resistor. The source of the third MOSFET is connected to the network card and is also connected to the first standby power supply through the third resistor. The gate of the third MOSFET is connected to the first standby power supply through the fourth resistor. The drain of the third MOSFET is connected to the cathode of the first diode. The anode of the first diode is grounded through the first transient voltage suppressor and is also connected to the SIO chip through the fifth resistor.

4. A motherboard, characterized in that, Includes the motherboard network wake-up circuit in low-power state as described in any one of claims 1-3.

5. An electronic device, characterized in that, Includes the motherboard network wake-up circuit in low power state as described in any one of claims 1-3, or includes the motherboard as described in claim 4.

6. A method for motherboard network wake-up in a low-power state, characterized in that, The low-power state motherboard network wake-up circuit is applied to the motherboard of a computer device as described in any one of claims 1-3. The motherboard network wake-up method under low power conditions includes: When the network card in the motherboard network wake-up circuit under low power mode receives an external wake-up signal while the motherboard is in low power mode, it sends a first control signal to the motherboard network wake-up module in the motherboard network wake-up circuit under low power mode; wherein, the first standby power supply is used to supply power to the network card when the motherboard is in low power mode, and when the motherboard is in low power mode, the SIO chip in the motherboard network wake-up circuit under low power mode causes the motherboard standby power control module to control the second standby power supply in the motherboard network wake-up circuit under low power mode to stop supplying power to the CPU chip; When the motherboard wake-up module receives the first control signal, it sends a second control signal to the SIO chip. When the SIO chip receives the second control signal, it sends a third control signal to the motherboard standby power control module in the motherboard network wake-up circuit under low power conditions, and sends a fourth control signal to the CPU chip after waiting for a preset waiting time after the third control signal is sent. When the motherboard standby power control module receives the third control signal, it controls the second standby power supply to supply power to the CPU chip in the motherboard network wake-up circuit under low power mode, so that the motherboard exits the low power mode. The CPU chip powers on when it receives the fourth control signal.

7. The motherboard network wake-up method under low power consumption state according to claim 6, characterized in that, When the motherboard receives an external wake-up signal while in low-power mode, the network card in the low-power motherboard network wake-up circuit sends a first control signal to the motherboard network wake-up module in the low-power motherboard network wake-up circuit, including: When the motherboard receives an external wake-up signal while in low-power mode, the network card sends a low-level WAKE_N signal to the motherboard's network wake-up module as the first control signal.

8. The motherboard network wake-up method under low power consumption state according to claim 6, characterized in that, The motherboard wake-up module includes a third MOSFET, a first diode, a first transient voltage suppressor, a third resistor, a fourth resistor, and a fifth resistor. The source of the third MOSFET is connected to the network card and is also connected to the first standby power supply through the third resistor. The gate of the third MOSFET is connected to the first standby power supply through the fourth resistor. The drain of the third MOSFET is connected to the cathode of the first diode. The anode of the first diode is grounded through the first transient voltage suppressor and is also connected to the SIO chip through the fifth resistor. When the motherboard wake-up module receives the first control signal, it sends a second control signal to the SIO chip, including: The third MOS transistor of the motherboard network wake-up module is saturated and turned on, and the drain of the third MOS transistor outputs a low level to the negative terminal of the first diode; The first diode pulls the PBTNJ_SIO signal low through the drain of the third MOS transistor to serve as the second control signal.

9. The motherboard network wake-up method under low power consumption state according to claim 6, characterized in that, The motherboard standby power control module includes a first MOSFET, a second MOSFET, a first capacitor, a second capacitor, a first resistor, and a second resistor. The source of the first MOSFET is connected to the first standby power supply, the drain of the first MOSFET is connected to the second standby power supply, and the gate of the first MOSFET is connected to the SIO chip through the first resistor. The gate of the first MOSFET is also grounded through the first capacitor and the second capacitor connected in parallel. The gate of the second MOSFET is connected to the first standby power supply through the second resistor, the source of the second MOSFET is grounded, and the drain of the second MOSFET is connected to the SIO chip. When the SIO chip receives the second control signal, it sends a third control signal to the motherboard standby power control module in the motherboard network wake-up circuit under low power conditions, and sends a fourth control signal to the CPU chip after waiting for a preset waiting time after the third control signal is issued, including: When the SIO chip receives the second control signal, it pulls the 5VSB_CTL_N signal to a low level as the third control signal and sends the third control signal to the motherboard standby power control module. After waiting for a preset waiting time, the SIO chip outputs a low-level PBTN signal as the fourth control signal and sends the fourth control signal to the CPU chip.

10. The motherboard network wake-up method under low power consumption state according to claim 6, characterized in that, When the motherboard standby power control module receives the third control signal, it controls the second standby power supply to power the CPU chip in the motherboard's wake-up circuit under low power conditions, so that the motherboard exits low power mode, including: When the motherboard standby power control module receives the third control signal, it controls the second standby power supply to sequentially power on the unpowered components on the motherboard, so that the motherboard exits the low-power mode and supplies power to the CPU chip.

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