Computer system starting method and device, electronic equipment and storage medium

Abstract

The application provides a computer system starting method and device, electronic equipment and storage medium, which can be applied to the technical field of computers. The method comprises the following steps: in the case that the computer system is powered on, performing a first initialization task; the first initialization task comprises performing an initialization configuration operation on a first device of the computer system; in the case that the first initialization task is completed, allocating device resources to a plurality of processors based on global resource information of the device resources, and determining local resource information of each of the plurality of processors; performing a plurality of second initialization tasks in parallel by using the plurality of processors, and determining initial resource allocation results of each of the plurality of processors; in the case that the plurality of second initialization tasks are all completed, performing resource uniformization adjustment according to the plurality of initial resource allocation results to obtain target resource allocation results; and in response to the completion of the resource adjustment, loading an operating system of the computer system to start the computer system.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to a computer system startup method, apparatus, electronic device, and storage medium. Background Technology

[0002] Multiprocessor computer systems utilize multiple CPUs (Central Processing Units) working together and leveraging high-speed interconnect buses to achieve parallel computing. This enables them to meet the massive data processing needs of scenarios such as scientific computing and AI (Artificial Intelligence) training, avoiding task delays. Multiprocessor computer systems offer significant advantages over single-processor computer systems.

[0003] In multi-processor computer systems, multiple processors are connected via an interconnect bus. Each processor is also connected to its own memory and other external devices. These external devices require initial configuration before normal use. However, with increasing system scalability, the number of external devices is growing, and as device functions become more complex, the configuration time increases. Traditional serial configuration methods in related technologies consume significant time and lead to wasted computing resources, directly resulting in a substantial decrease in computer startup efficiency. Summary of the Invention

[0004] In view of the above problems, this application provides a computer system booting method, apparatus, electronic device and storage medium.

[0005] According to one aspect of this application, a computer system startup method is provided. The computer system includes multiple processors. The computer system startup method includes: upon power-on completion of the computer system, executing a first initialization task; the first initialization task includes performing an initialization configuration operation on a first device of the computer system, the first device including a display device; upon completion of the first initialization task, allocating device resources to the multiple processors based on global resource information of the device resources, determining local resource information of each of the multiple processors, the local resource information indicating the allocation result of device resources for the multiple processors under the global address; and using the multiple processors to execute multiple second initialization tasks in parallel, determining the initial resource allocation result of each of the multiple processors; the second initialization tasks include... Based on local resource information, resource allocation and initialization operations are performed on multiple second devices currently associated with the processor. After all second initialization tasks have been completed, resource unification adjustments are performed based on the multiple initial resource allocation results to obtain a target resource allocation result. The target resource allocation result includes a first target allocation result and a second target allocation result. The first target allocation result indicates the allocation result of device resources under the global address for multiple second devices, and the second target allocation result indicates the allocation result of device resources under the global address reserved for hot-swappable devices not currently associated with the processor. The second target allocation result is determined based on the first target allocation result. In response to the completion of resource adjustment, the operating system of the computer system is loaded to start the computer system.

[0006] According to another aspect of this application, a computer system startup apparatus is provided, comprising: an execution module, configured to execute a first initialization task upon completion of power-on of the computer system; the first initialization task includes performing initialization configuration operations on a first device of the computer system, the first device including a display device; a first determination module, configured to, upon completion of the first initialization task, allocate device resources to multiple processors based on global resource information of device resources, and determine local resource information of each of the multiple processors, the local resource information indicating the allocation result of device resources for the multiple processors under a global address; and a second determination module, configured to execute multiple second initialization tasks in parallel using the multiple processors, and determine the initial resource allocation result of each of the multiple processors; the second initialization task includes performing initialization configuration operations on a first device of the computer system, the first device including a display device; a first determination module, configured to, upon completion of the first initialization task, allocate device resources to multiple processors based on global resource information ... first determination module, configured to perform initialization configuration operations on a first device of the computer system, the first device including a display device; a second determination module, configured to, upon completion of the first initialization task, allocate device resources to multiple processors based on global resource information, and determine local resource information of each of the multiple processors, the first determination module, configured to, execute multiple second initialization tasks in parallel using the multiple processors, and determine the initial resource allocation result of each of the multiple processors; the second initialization task includes performing initialization configuration operations on a first device of the computer system, the first device including a display device; a The system includes: an information module for performing resource allocation and initialization operations on multiple second devices currently associated with the processor; an adjustment module for performing unified resource adjustment based on multiple initial resource allocation results after multiple second initialization tasks have been completed, to obtain a target resource allocation result, which includes a first target allocation result and a second target allocation result. The first target allocation result indicates the allocation result of device resources under the global address for multiple second devices, and the second target allocation result indicates the allocation result of device resources under the global address for hot-swappable devices not currently associated with the processor. The second target allocation result is determined based on the first target allocation result. A loading module is used to load the operating system of the computer system in response to the completion of resource adjustment, so as to start the computer system.

[0007] Another aspect of this application provides an electronic device comprising: one or more processors; and a memory for storing one or more computer programs, wherein the steps of the one or more computer programs are executed on the one or more processors to implement the methods described above.

[0008] Another aspect of this application provides a computer-readable storage medium having a computer program or instructions stored thereon, which, when executed by a processor, implement the steps of the above-described method.

[0009] Another aspect of this application provides a computer program product, including a computer program or instructions that, when executed by a processor, implement the steps of the above-described method. Attached Figure Description

[0010] The above-mentioned contents, other objects, features and advantages of this application will become clearer from the following description of embodiments of this application with reference to the accompanying drawings, in which the accompanying drawings are provided.

[0011] Figure 1 A computer system architecture diagram according to an embodiment of this application is shown.

[0012] Figure 2 A flowchart of a computer system startup method according to an embodiment of this application is shown.

[0013] Figure 3A A schematic diagram illustrating MMIO resource allocation and adjustment according to an embodiment of this application is shown.

[0014] Figure 3B A schematic diagram illustrating MMIO resource allocation and adjustment according to another embodiment of this application is shown.

[0015] Figure 3C A schematic diagram illustrating the allocation and adjustment of BUS number resources according to an embodiment of this application is shown.

[0016] Figure 3D A flowchart of a computer system startup method according to another embodiment of this application is shown.

[0017] Figure 4 A structural block diagram of a computer system startup apparatus according to an embodiment of this application is shown.

[0018] Figure 5 A block diagram of an electronic device suitable for implementing a computer system startup method according to an embodiment of this application is shown. Detailed Implementation

[0019] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of this application for ease of explanation. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The terms “comprising,” “including,” etc., as used herein indicate the presence of features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0021] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0022] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0023] In the technical solution of this application, the user information (including but not limited to user personal information, user image information, user device information, such as location information) and data (including but not limited to data used for analysis, stored data, and displayed data) involved are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, storage, use, processing, transmission, provision, disclosure, and application of related data all comply with relevant laws, regulations, and standards, take necessary confidentiality measures, do not violate public order and good morals, and provide corresponding operation entry points for users to choose to authorize or refuse.

[0024] This application relates to the fields of computer technology and server technology, and can be applied, for example, to multi-processor computer systems. For ease of understanding, some of the technical terms mentioned herein are described below:

[0025] The CPU (Central Processing Unit) is the core of a computer system for computation and control, and is the final execution unit for information processing and program execution.

[0026] BIOS (Basic Input Output System) is the boot firmware stored in the motherboard's flash memory, responsible for hardware initialization and booting the computer's operating system.

[0027] PCIe (Peripheral Component Interconnect express) is a high-speed serial computer expansion bus standard used to connect various external devices to a computer, such as graphics cards, network cards, and storage controllers. A computer can use this interface to connect one or more peripheral devices. For example, PCIe devices, often simply called "high-speed bus expansion devices," can be connected to the motherboard through a PCIe slot to expand the computer's functionality.

[0028] UEFI (Unified Extensible Firmware Interface) is a computer firmware standard whose main functions include hardware initialization, operating system booting, and system security control.

[0029] AI (Artificial Intelligence) is a technology that enables machines to have the ability to perceive, learn, and make decisions by simulating intelligent behavior.

[0030] NUMA (Non-Uniform Memory Access) is a memory architecture design for multiprocessor computers that optimizes the scalability and efficiency of multiCPU systems through localized memory access and inter-node interconnection.

[0031] SSD (Solid State Drive) is an electronic storage device based on flash memory chips, primarily used for storing and quickly reading and writing data.

[0032] A bus is a common communication channel used in a computer system to connect various functional components (such as CPU, memory, input / output devices, etc.), and it usually refers to PCIe.

[0033] MMIO (Memory-Mapped Input / Output) is a technique that maps peripheral registers or input / output ports to the CPU's memory address space, allowing the CPU to directly manipulate peripheral registers using regular memory access instructions without using dedicated input / output instructions.

[0034] I / O (Input / Output) is the core interface used by computers to connect to external devices.

[0035] OS (Operating System) is the core software of a computer system, responsible for managing and coordinating hardware and software resources.

[0036] The BAR (Base Address Register) is a critical register in the PCIe device configuration space, used to store the device's base address in system memory or I / O address space. The system uses the BAR to determine the physical location of device resources and enable data exchange between the CPU and the device.

[0037] EBG (Elastic Business Gateway), often simply called a "gateway," is a key component in computer systems, primarily used for unified management, security control, and traffic scheduling.

[0038] Memory is a hardware component used for temporary storage of data and instructions, and it serves as a high-speed data exchange bridge between the CPU and external storage (such as SSD).

[0039] A core is the basic computing unit of a CPU, responsible for computation and control tasks.

[0040] Uncore components are a collection of components in the CPU that do not directly participate in core computing tasks, but provide key support functions for computing core tasks. They include auxiliary components such as memory controllers and graphics processors.

[0041] PCIe is a high-speed serial computer expansion bus standard widely used to connect high-performance peripherals (such as graphics cards, SSDs, and network cards) to the host, offering significant advantages in scalability and ease of use. In practical applications, PCIe devices exchange data at high speed with the CPU via the PCIe bus. The system needs to allocate a BAR area as MMIO space for PCIe devices, which is a critical resource window for communication between PCIe devices and the host. During initialization, the BIOS / UEFI first completes the initialization of the configuration space, including allocating memory, I / O resources, setting interrupt routes, and configuring DMA (Direct Memory Access Channel) and other basic settings. Subsequently, it loads specific device drivers for more refined configuration, such as power management strategies and performance optimization parameters, ultimately bringing the device into normal operating condition.

[0042] In terms of reliability, multi-processor computer systems support redundancy in components such as CPU and memory, enabling automatic switching in the event of hardware failure and ensuring the continuity of critical business operations. Regarding scalability, multi-processor computer systems can flexibly improve performance by adding CPUs and memory to adapt to data growth demands. They can also leverage NUMA technology to optimize resource scheduling and improve resource utilization in virtualization scenarios. Therefore, multi-processor computer systems have significant advantages over single-processor computer systems.

[0043] In multi-processor computer systems, various external devices require initialization and configuration before normal use (e.g., PCIe devices need to calculate their resource requirements, allocate bus numbers, MMIO, and I / O resources, and load and run drivers to configure the device). This configuration is handled by the BIOS. After the system powers on, the BIOS is loaded first, and the BIOS program scans for devices, initializes them, and allocates resources. This process is generally performed serially, completing the initialization of one device before proceeding to the next. In large multi-processor computer systems, as system scalability increases, the number of external devices also grows significantly. Furthermore, as device functions become more complex, the time required for device configuration increases. The traditional serial configuration method becomes too time-consuming and leads to wasted computing resources, directly resulting in a significant decrease in computer startup efficiency and increased difficulty in resource scheduling.

[0044] In view of this, embodiments of this application provide a computer system startup method, comprising: upon powering on the computer system, executing a first initialization task; the first initialization task includes performing an initialization configuration operation on a first device of the computer system; upon completion of the first initialization task, allocating device resources to multiple processors based on global resource information of the device resources, and determining local resource information for each of the multiple processors; utilizing the multiple processors to execute multiple second initialization tasks in parallel, and determining initial resource allocation results for each of the multiple processors; upon completion of all the multiple second initialization tasks, performing resource unification adjustment based on the multiple initial resource allocation results to obtain a target resource allocation result; and in response to the completion of resource adjustment, loading the operating system of the computer system to start the computer system.

[0045] According to an embodiment of this application, after the computer system powers on, a first initialization task is executed first; then, independent local resource information is allocated to each processor; subsequently, multiple processors execute a second initialization task in parallel based on their respective local resource information. Each processor initializes a second device based on its local resource information. After completion, the initial resource allocation results of each processor are adjusted to unify resource allocation, resolving issues of continuity, consistency, and conflict of device resources connected to each processor, and reserving flexible device resources for hot-swappable devices. After the resource unification adjustment is completed, the system startup process continues until startup is complete.

[0046] It is understood that the computer system startup method (hereinafter referred to as the method) provided in this application distributes the initialization operation of the second device required during the computer system startup process to the processor where the second device is located and executes it in parallel. This avoids the slow startup process caused by the serial execution of the drivers of all the second devices in the computer system. At the same time, it solves the technical problems of continuity, consistency and conflict of device resources connected to each processor. In addition, it also takes into account the resource allocation problem of hot-swappable devices in advance.

[0047] Figure 1 A computer system architecture diagram according to an embodiment of this application is shown.

[0048] like Figure 1As shown, the computer system architecture can be, for example, a 4-way computer system. The computer system architecture may include a first processor (CPU0), a second processor (CPU1), a third processor (CPU2), and a fourth processor (CPU3), which are connected via an interconnect bus. Exemplarily, external devices connected to the first processor include a gateway (EBG), five high-speed bus expansion devices (PCIe devices), and eight memory modules; external devices connected to the second processor include five high-speed bus expansion devices (PCIe devices) and eight memory modules; external devices connected to the third processor include five high-speed bus expansion devices (PCIe devices) and eight memory modules; and external devices connected to the fourth processor include five high-speed bus expansion devices (PCIe devices) and eight memory modules. All external devices require initial configuration before normal use.

[0049] In terms of application scenarios, this method has a significantly expanded scope of application. It can not only be used for the initialization of PCIe devices, but also be widely adapted to the initialization and configuration process of other types of devices. It can be used in all cases where the ownership of the device can be clearly defined, and it is not limited to the adjustment and allocation of specific resources such as BUS number, MMIO, and I / O.

[0050] From the perspective of processing level, this method is applicable to parallel initialization and configuration at the level of computer system components, and can also be extended to parallel processing at the level of virtual components after virtualization, demonstrating cross-level technical adaptability.

[0051] It should be noted that this application uses a 4-way computer system as an example, but it is also applicable to 2-way computer systems, 8-way computer systems and other forms of multi-way computer systems, and is not limited to a specific hardware architecture.

[0052] Figure 2 A flowchart of a computer system startup method according to an embodiment of this application is shown.

[0053] like Figure 2 As shown, the method includes operations S210 to S250. The computer system includes multiple processors.

[0054] In operation S210, after the computer system has been powered on, a first initialization task is executed; the first initialization task includes performing an initialization configuration operation on a first device of the computer system, the first device including a display device.

[0055] In operation S220, after the first initialization task is completed, device resources are allocated to multiple processors based on the global resource information of the device resources, and the local resource information of each of the multiple processors is determined. The local resource information indicates the allocation result of device resources for multiple processors under the global address.

[0056] In operation S230, multiple processors execute multiple second initialization tasks in parallel to determine the initial resource allocation results of each processor. The second initialization tasks include performing resource allocation and initialization operations on multiple second devices currently associated with the processor based on local resource information.

[0057] In operation S240, after multiple second initialization tasks have been completed, resource unification adjustment is performed based on multiple initial resource allocation results to obtain target resource allocation results. The target resource allocation results include a first target allocation result and a second target allocation result. The first target allocation result indicates the allocation result of device resources under the global address for multiple second devices, and the second target allocation result indicates the allocation result of device resources under the global address for hot-pluggable devices that are not currently associated with the processor. The second target allocation result is determined based on the first target allocation result.

[0058] When operating S250, in response to the completion of resource adjustment, the computer system's operating system is loaded to start the computer system.

[0059] The processor is a CPU, and multiple processors each have a unique number. For example, the main processor can be identified from multiple processors based on their numbers. For instance, among multiple processors numbered CPU0, CPU1, CPU2, and CPU3, the main processor is CPU0.

[0060] The first device can include a display device, and can also include core and uncore components. A display device is an output device in a computer system responsible for converting electronic documents into visual images. For example, a monitor.

[0061] Once the computer system has powered on, the main processor CPU0 can perform the first initialization task on the computer system's display device. This first initialization task can be understood as a common initialization task, which may include initializing the display device, turning on the screen, outputting initialization information, and initializing Core and Uncore. After turning on the screen, a status code (POST code) is output.

[0062] Device resources are the basic resources in a computer system that can be managed and accessed, including hardware resources and software resources. For example, hardware resources include BUS, I / O devices, MMIO, etc., while software resources include I / O drivers, etc.

[0063] Global resource information represents the resource range (under global address) of device resources to be allocated in a computer system.

[0064] In one embodiment, upon completion of the first initialization task, the main processor CPU0 can allocate device resources to multiple processors based on the global resource information of the device resources and the number of processors, thereby obtaining the local resource information of each processor. The local resource information represents the resource sub-range (under global address) of the device resources allocated to each processor. For example, device resources include BUS resources (bus number resources), which assign a unique ID to each device, and each device must have a BUS number. For example, a BUS number is 8 bits, ranging from 0 to 255, and the global resource information of the BUS resources can be represented as 0~255. In a 4-way computer system, more than 4 processors can be allocated BUS resources ranging from 0 to 255. For example, CPU0, CPU1, CPU2, and CPU3 each receive 64 BUS resources. The local resource information of the BUS resources corresponding to CPU0, CPU1, CPU2, and CPU3 can then be represented as 0~63, 64~127, 128~191, and 192~255, respectively.

[0065] It should be noted that the above representations of global and local resource information are only for illustrative purposes. In actual applications, other forms can be used (e.g., resource ranges can be in interval or set form, and resources can also be hexadecimal addresses, etc.), and no restrictions are imposed here.

[0066] The second device is an external device connected to the processor, such as PCIe or memory. Each processor can be associated with multiple second devices.

[0067] The second initialization task includes performing resource allocation and initialization operations on multiple second devices currently associated with the processor, based on local resource information. The initialization operations on the second devices may include driving the second devices.

[0068] Multiple processors execute a second initialization task in parallel on their respective second devices, resulting in initial resource allocation results for each processor. These initial resource allocation results characterize the device resources allocated to each processor based on actual needs.

[0069] For example, CPU0 performs resource allocation operations on multiple second devices recognizable by CPU0 based on local resource information, obtaining an initial resource allocation result C0; CPU1 performs resource allocation operations on multiple second devices recognizable by CPU1 based on local resource information, obtaining an initial resource allocation result C1; CPU2 performs resource allocation operations on multiple second devices recognizable by CPU2 based on local resource information, obtaining an initial resource allocation result C2; and CPU3 performs resource allocation operations on multiple second devices recognizable by CPU3 based on local resource information, obtaining an initial resource allocation result C3. The resource allocation operations are performed in parallel with the initialization threads corresponding to CPU0, CPU1, CPU2, and CPU3.

[0070] If the initial resource allocation results for each processor are inconsistent with the local resource information, it may lead to discontinuities or conflicts between the initial resource allocation results of CPU0 and CPU1. Therefore, the main processor CPU0 needs to perform resource unification adjustments on the multiple initial resource allocation results corresponding to each processor to obtain the first target allocation result. The first target allocation result is the allocation result of device resources under the global address for multiple second devices. Based on the first target allocation result, device resources can be pre-allocated for hot-pluggable devices that are not currently associated with any processor to obtain the second target allocation result. The second target allocation result indicates the allocation result of device resources under the global address for hot-pluggable devices that are not currently associated with any processor.

[0071] For example, suppose the local resource information of CPU0 is [0~63], and the initial resource allocation result of CPU0 is [0~50]. Meanwhile, the local resource information of CPU1 is [64~127], and the initial resource allocation result of CPU1 is [64~120]. This results in a discontinuity between the initial resource allocation results of CPU0 ([0~50]) and CPU1 ([64~120]). To address this, CPU0 can perform a resource unification adjustment operation on the initial resource allocation results of each CPU, adjusting the initial resource allocation result of CPU1 ([64~120]) to [51~107], resulting in the first target allocation results of [0~50] and [51~107]. This process can be repeated to ensure that the first target allocation results of each CPU are continuous in the global address space. For example, after adjusting the resource allocation results of each CPU to a unified and continuous global resource space, a flexible resource space can be reserved at the end of the adjusted global resource space for hot-swappable devices to avoid resource waste and enable hot-swappable devices to immediately obtain a continuous address space when inserted.

[0072] Furthermore, the unified adjustment of resources based on multiple initial resource allocation results is highly flexible and not limited to a specific adjustment mode. For various types of resources and descriptive information, linear or nonlinear strategies can be designed according to their inherent characteristics to achieve accurate and efficient unified adjustment.

[0073] Once resource adjustments are complete, the computer system's operating system is loaded to start the computer system.

[0074] According to the embodiments of this application, the tasks to be performed during device initialization are finely broken down before the computer system starts. Specifically, the computer system first performs a first initialization task on the first device, then allocates the second initialization tasks corresponding to each processor to each processor. Each processor performs resource allocation and initialization operations in parallel on multiple identifiable second devices under its own topology to obtain initial resource allocation results. Finally, a unified resource adjustment is performed on multiple initial resource allocation results to ensure that all second devices can work efficiently and in coordination within a unified address space. This solves the technical problem of discontinuous or conflicting device resources connected to each processor, improves resource utilization during system initialization, increases system execution efficiency, and shortens system preparation time. Furthermore, based on adjusting the resource allocation results of each CPU to a unified and continuous global resource space, a flexible resource space for hot-swappable devices can be reserved at the end of the adjusted global resource space to avoid resource waste and enable immediate access to continuous address space when hot-swappable devices are inserted. Furthermore, the initialization operations of the second device required during the computer system boot process are distributed to the processor where the second device is located and executed in parallel. This avoids the slow boot process caused by the serial execution of the drivers for all the second devices in the computer system, thus solving the initialization delay problem caused by the concentrated serial processing of tasks in multi-way computer systems and significantly improving the system boot speed and device operation stability.

[0075] According to an embodiment of this application, the second device includes a high-speed bus extension device; the second initialization task includes performing the following operations in parallel using a processor: allocating device resources to multiple high-speed bus extension devices based on local resource information, determining an initial resource allocation result; the initial resource allocation result indicates the allocation result of device resources for multiple high-speed bus extension devices under a local address; the local resource information represents a local address; and performing initialization operations on multiple high-speed bus extension devices according to the initial resource allocation result.

[0076] High-speed bus expansion devices are PCIe devices, meaning the second device includes PCIe devices.

[0077] In one embodiment, the processor CPU1 is connected to 10 PCIe devices. The main processor CPU0 loads local resource information into multiple processors respectively. Based on the local resource information [64~127], the processor CPU1 allocates device resources to multiple high-speed bus expansion devices respectively. Each high-speed bus expansion device only needs 1 device resource. Therefore, the initial resource allocation result is [64~74].

[0078] The initial resource allocation result indicates the allocation of device resources within the local address represented by the local resource information to multiple high-speed bus extension devices.

[0079] The device resources allocated to each of the multiple high-speed bus expansion devices are determined from the initial resource allocation results, and initialization operations are performed on the high-speed bus expansion devices based on the device resources.

[0080] According to the embodiments of this application, based on the actual resource requirements of the high-speed bus expansion device, the device resources are allocated to the high-speed bus expansion device within the spatial range corresponding to the local resource information, thereby accurately identifying the resource requirements and allocation status of the high-speed bus expansion devices associated with each processor, ensuring the rationality and accuracy of resource allocation.

[0081] According to embodiments of this application, the plurality of processors includes a master processor and at least one slave processor; the device resources include a bus number, a memory-mapped input / output space, and an input / output space.

[0082] The main processor can be responsible for global control and general computing; the slave processors improve the parallel computing efficiency of the second initialization task through division of labor and cooperation.

[0083] For example, taking CPU0, CPU1, CPU2 and CPU3 as an example, CPU0 is the master processor, and CPU1, CPU2 and CPU3 are all slave processors.

[0084] Device resources include bus number (BUS), memory-mapped input / output space (MMIO), and input / output space (I / O).

[0085] According to an embodiment of this application, performing the first initialization task includes using the main processor to perform the following operations: initializing the display device, making the display device available, and outputting initialization information via the initialized display device.

[0086] The main processor initializes the display device, making it available. After initialization, the display device outputs initialization information.

[0087] Initialization information may include hardware identifiers (such as graphics card model and firmware version) and system status (such as capacity and device detection results). For example, after the system powers on, the main CPU (i.e., CPU0) first executes the system's common initialization tasks, such as initializing the display device, turning on the screen, and outputting initialization information, turning on the screen and outputting a status code (POSTCode).

[0088] Initialization information is typically output as text superimposed on the upper left corner of the display device, or displayed through a graphical interface.

[0089] After initialization, the display device can respond to the CPU's graphics output instructions (such as register operations via MMIO mapping) and support dynamic adjustment of display parameters (such as switching resolutions).

[0090] According to an embodiment of this application, allocating device resources to multiple processors based on global resource information of device resources and determining the local resource information of each of the multiple processors includes performing the following operations using the main processor: creating task configuration files for the second initialization task for each of the multiple processors; allocating device resources to the multiple processors based on the number of multiple processors and global resource information of device resources, and determining the local resource information of each of the multiple processors; and writing the local resource information of each of the multiple processors into the task configuration files of each of the multiple processors respectively.

[0091] The task configuration file is a context space used to record information associated with the execution of the second initialization task.

[0092] The main processor creates context spaces for the second initialization task for multiple processors (which may include the main processor itself).

[0093] The main processor can divide the processors equally based on the number of processors and the global resource information of the device resources, thereby obtaining the local resource information of each processor.

[0094] In one embodiment, the device resources include a BUS number (e.g., 8 bits), and the global resource information of the BUS number is represented as [0~255]. The number of CPUs is 4, and CPU0 can be allocated the BUS number equally to each CPU according to the number of CPUs. Then, the local resource information of CPU0 is represented as [0~63], the local resource information of CPU1 is represented as [64~127], the local resource information of CPU2 is [128~191], and the local resource information of CPU3 is [192~255].

[0095] In another embodiment, the device resources include MMIO space (e.g., 2GB), the global resource information of MMIO space is represented as [4000 0000~BFFF FFFF], the number of CPUs is 4, and CPU0 can divide the MMIO space equally among each CPU according to the number of CPUs. Then the local resource information of CPU0 is represented as [4000 0000~5FFF FFFF], the local resource information of CPU1 is represented as [6000 0000~7FFF FFFF], the local resource information of CPU2 is [8000 0000~9FFF FFFF], and the local resource information of CPU3 is [A000 0000~BFFF FFFF].

[0096] The main processor writes the local resource information of each of the multiple processors into the context space of each of the multiple processors respectively.

[0097] According to the embodiments of this application, the global resource pre-allocation of the device resources is performed. The pre-allocation is implemented by allocating local resource information for the second device under each processor. When each processor performs resource allocation for its own second device, it performs pre-allocation operation within the resource sub-range (under local address) represented by the local resource information. The local resource information recorded in the task configuration file is not used as the actual resource allocation, but after each processor completes the resource allocation in the second initialization task, it is beneficial to quickly obtain the local resource information from the task configuration file as the basis for resource adjustment and unified allocation.

[0098] According to an embodiment of this application, performing initialization operations on multiple high-speed bus expansion devices includes: using the respective device drivers of the multiple high-speed bus expansion devices to perform initialization operations on the multiple high-speed bus expansion devices respectively, determining the respective device driver interfaces of the multiple high-speed bus expansion devices; and writing the respective device driver interfaces of the multiple high-speed bus expansion devices into a task configuration file.

[0099] Device drivers act as a bridge between the operating system and high-speed bus extension devices, responsible for translating the operating system's I / O requests into instructions that the high-speed bus extension devices can recognize.

[0100] For any one of multiple high-speed bus expansion devices, the device driver performs initialization operations on the high-speed bus expansion device, verifies the functionality of the high-speed bus expansion device through a standardized process, and provides a unified device driver interface for the operating system. The device driver interface is a protocol interface.

[0101] Write the device driver interface of the high-speed bus extension device into the context space corresponding to this high-speed bus extension device.

[0102] According to an embodiment of this application, based on local resource information, allocating device resources to multiple high-speed bus expansion devices and determining the initial resource allocation result includes: reading local resource information of device resources from a task configuration file; allocating device resources to multiple high-speed bus expansion devices associated with multiple processors based on the local resource information of device resources, determining the initial resource allocation result; and writing the initial resource allocation result into the task configuration file.

[0103] After the task configuration file is prepared, the multi-initialization thread parallel execution phase begins. Each initialization thread enumerates devices, allocates resources, and performs initialization operations in the context space. Here, we will take the execution process of one second initialization task (such as the process of CPU0 executing the second initialization task) as an example. The execution process of other second initialization tasks is the same and will not be described again here.

[0104] Read the local resource information (BUS sub-range, MMIO sub-range, I / O sub-range) of the device resources from the task configuration file, enumerate the PCIe devices connected to the CPU using an enumeration algorithm, start with the minimum value in the local resource information, traverse all PCIe devices by depth and allocate device resources to them, and determine the initial resource allocation result.

[0105] In one embodiment, the processor CPU0 is connected to 8 PCIe devices. The main processor CPU0 reads the local resource information of the device resources [0~63] from the task configuration file. Assuming that each PCIe device requires 2 device resources, the minimum value of 0 in the local resource information is used as the starting value. The enumeration algorithm is used to traverse all 8 PCIe devices. Therefore, the initial resource allocation result is [0~15].

[0106] Write the initial resource allocation results into the context space.

[0107] According to the embodiments of this application, by employing multiple initialization threads to enumerate devices, allocate resources, and perform initialization operations on the task configuration file, the complex processing flow before system startup is distributed to each processor for parallel execution, which significantly improves the utilization rate of computing resources in a multi-processor computer system, while greatly shortening the system processing time and effectively accelerating the system boot speed.

[0108] According to an embodiment of this application, based on local resource information of device resources, device resources are allocated to multiple high-speed bus expansion devices, and the initial resource allocation result is determined by: determining the upper limit and lower limit of the allocatable range of device resources based on the allocatable range of device resources represented by the local resource information; and allocating device resources to multiple high-speed bus expansion devices based on the upper limit and lower limit of the allocatable range to determine the initial resource allocation result.

[0109] The upper limit of the allocatable range is the maximum value of the allocatable range of the device resources represented by the local resource information.

[0110] The lower limit of the allocatable range is the minimum value of the allocatable range of the device resources represented by the local resource information. For example, if the local resource information is [0, 63], then 0 is the upper limit of the allocatable range, and 63 is the lower limit of the allocatable range.

[0111] The enumeration algorithm is used to enumerate the PCIe devices connected to the CPU. Starting with the lower limit of the allocatable range, all PCIe devices are traversed to the depth and resources are allocated. The maximum value during the allocation process is recorded.

[0112] Starting with the minimum value of the BUS subrange, traverse all PCIe devices using a depth-first search algorithm and assign BUS numbers to them. After the assignment is complete, record the maximum value and check if it exceeds the BUS subrange.

[0113] In one embodiment, the upper limit of the allocatable range is 63, and the maximum value of the process of allocating BUS numbers to multiple high-speed bus extension devices is 70. Then, the upper limit of the initial resource allocation result is determined based on the upper limit of the allocatable range 63.

[0114] In one embodiment, the upper limit of the allocatable range is 63, and the maximum value of the process of allocating BUS numbers to multiple high-speed bus extension devices is 50. Therefore, the upper limit of the initial resource allocation result is determined based on the maximum value of 50.

[0115] According to embodiments of this application, performing resource unification adjustment based on multiple initial resource allocation results to obtain a target resource allocation result includes using the main processor to perform the following operations: reading the initial resource allocation results of each of the multiple processors from their respective task configuration files; performing resource unification adjustment on the device resources of each of the multiple high-speed bus expansion devices based on the multiple initial resource allocation results to obtain a first target allocation result, the first target allocation result indicating the allocation result of device resources under the global address for the multiple high-speed bus expansion devices; and reserving device resources for the currently unassociated hot-swappable devices based on the first target allocation result, according to a preset hot-swappable device resource quota and the number of hot-swappable devices currently not associated with the processor, to obtain a second target allocation result, the second target allocation result indicating the allocation result of device resources reserved under the global address for the currently unassociated hot-swappable devices.

[0116] After multiple processors have completed multiple second initialization tasks in parallel, the initial resource allocation results of each processor are written to their respective task configuration files. Then, the main processor reads the initial resource allocation results of each processor from their respective task configuration files.

[0117] Based on the characteristics of the device resources, adjustment rules are determined; then, based on multiple initial resource allocation results and adjustment rules, a dynamic adaptation algorithm can be used to uniformly adjust the device resources of multiple high-speed bus expansion devices to obtain the first target allocation result.

[0118] Unified resource allocation for multiple high-speed bus expansion devices refers to adjusting the initial resource allocation of each processor to obtain the resource allocation results (global contiguous resource space) for all high-speed bus expansion devices associated with the multi-way computer system. After obtaining the adjusted global contiguous resource space, a flexible resource area can be reserved at the end of the global contiguous resource space for hot-swappable devices. The size of this flexible resource area can be dynamically calculated based on the number of currently idle hot-swappable devices in the system (for example, reserving 256MB of space for each idle hot-swappable slot).

[0119] The initial resource allocation result represents the allocation of device resources under the local address space to all high-speed bus extension devices associated with the processor.

[0120] The first target allocation result represents the allocation of device resources under the global address space for all high-speed bus extension devices currently associated with the multi-way computer system. The second target allocation result indicates the allocation of device resources under the global address space for hot-swappable devices not currently associated with the multi-way computer system.

[0121] According to embodiments of this application, the resource allocation of multiple high-speed bus expansion devices is uniformly adjusted, integrating device resources originally located in different local address ranges into a single global address range. This not only ensures the rationality and accuracy of resource allocation but also avoids device compatibility issues caused by inconsistent device resource ranges, thus providing a resource foundation for the normal operation of each device and significantly improving the overall performance and reliability of the multi-processor computer system. Furthermore, after adjusting the resource allocation results of each CPU to a unified and continuous global resource space, a flexible resource space can be reserved at the end of the adjusted global resource space for hot-swappable devices to avoid resource waste and simultaneously enable hot-swappable devices to immediately obtain continuous address space upon insertion.

[0122] According to an embodiment of this application, the plurality of processors includes N processors in numerical order, where N is an integer greater than 1; the resource unification adjustment of the device resources of the plurality of high-speed bus expansion devices according to the plurality of initial resource allocation results to obtain the first target allocation result includes: determining the first target allocation result of the first processor according to the initial resource allocation result of the first processor; using the first target allocation result of the first processor as a reference, adjusting the initial resource allocation results of the second to Nth processors in numerical order to obtain the first target allocation result of each of the N processors; wherein, the first target allocation result of the Nth processor is determined according to the initial resource allocation result of the Nth processor and the first target allocation result of the (N-1)th processor.

[0123] In one embodiment, the device resource is MMIO, and there is a decoder on the bus. The consecutive numbering of MMIOs is beneficial for the decoder to lock the entire MMIO by only performing "range matching", which saves the power consumption of gate circuits. Therefore, the adjustment rule is determined to be the rule of consecutive numbering.

[0124] When the device resources are MMIO, if the initial resource allocation result of the first processor exceeds or does not exceed the allocatable range of the local resource information, the initial resource allocation result of the first processor will be determined as the first target allocation result of the first processor.

[0125] According to the numbering order, the initial resource allocation result of the second processor is adjusted to unify the resources based on the first target allocation result of the first processor, so as to obtain the first target allocation result of the second processor.

[0126] Based on the upper limit of the first target allocation result of the first processor and the spatial range of the initial resource allocation result of the second processor, the multiple MMIOs already allocated in the initial resource allocation result of the second processor are adjusted sequentially. The lower limit of the first target allocation result of the second processor is the next digit after the upper limit of the first target allocation result of the first processor; the upper limit of the first target allocation result of the second processor is the adjusted value of the upper limit of the initial resource allocation result of the second processor.

[0127] Following the numbering order, the initial resource allocation result of the (n+1)th processor is adjusted based on the first target allocation result of the (N-1)th processor to obtain the first target allocation result of the Nth processor. The process of determining the first target allocation result of each of the N processors is the same as the above process and will not be repeated here.

[0128] If the upper limit of the first target allocation result of the Nth processor is greater than the maximum value of the global resource information, the upper limit of the first target allocation result of the Nth processor is adjusted to the maximum value of the global resource information; otherwise, no adjustment is made.

[0129] Figure 3A A schematic diagram illustrating MMIO resource allocation and adjustment according to an embodiment of this application is shown.

[0130] like Figure 3A As shown, the device resources are MMIO. In the pre-allocation stage, the global resource information of the device resources is represented in hexadecimal as [4000 0000~BFFF FFFF]. In the post-allocation stage, the number of processors is 4. Based on the global resource information of the device resources, the device resources are allocated to the 4 processors to obtain the local resource information of the 1st processor [4000 0000~5FFF FFFF], the local resource information of the 2nd processor [6000 0000 ~ 7FFF FFFF], the local resource information of the 3rd processor [8000 0000 ~ 9FFF FFFF], and the local resource information of the 4th processor [A000 0000 ~ BFFF FFFF]. Four processors execute their respective second initialization tasks in parallel. After allocation, the initial resource allocation results are obtained for the first processor [4000 0000~4F00 0000], the second processor [6000 0000~60F0 0000], the third processor [8000 0000~800F 0000], and the fourth processor [A000 0000~A0FF 0000]. The initial resource allocation results represent the allocated device resources. The initial resource allocation results of each processor do not exceed the allocatable range of the local resource information. The initial resource allocation result of the first processor is determined as the first target allocation result of the first processor. Based on the first target allocation result of the first processor, the initial resource allocation results of the second to fourth processors are adjusted in sequence according to the numbering order to obtain the first target allocation results of each of the four processors, thereby obtaining the continuous and complete first target allocation results of the first to fourth processors [4000 0000~50FE 0000].

[0131] Figure 3B A schematic diagram illustrating MMIO resource allocation and adjustment according to another embodiment of this application is shown.

[0132] like Figure 3BAs shown, the device resources are MMIO. Before pre-allocation, the global resource information of the device resources is represented in hexadecimal as [4000 0000~BFFF FFFF]. After pre-allocation, the number of processors is 4. Based on the global resource information of the device resources, the device resources are allocated to the 4 processors to obtain the local resource information of the 1st processor [4000 0000~5FFF FFFF], the local resource information of the 2nd processor [6000 0000~7FFF FFFF], the local resource information of the 3rd processor [8000 0000~9FFF FFFF], and the local resource information of the 4th processor [A000 0000~BFFF FFFF]. Four processors execute their respective second initialization tasks in parallel. After allocation, the initial resource allocation results are obtained for the first processor [4000 0000~4F00 0000], the second processor [6000 0000~60F0 0000], the third processor [8000 0000~A00F 0000], and the fourth processor [A0000000~A0FF 0000]. The initial resource allocation results represent the allocated device resources. The initial resource allocation results of the first, second, and fourth processors do not exceed the allocatable range of the local resource information, while the initial resource allocation result of the third processor exceeds the allocatable range of the local resource information. The overflow state (Overflowed) can be marked as 1. The initial resource allocation result of the first processor is determined as the first target allocation result of the first processor. Based on the upper limit of the first target allocation result of the first processor, 4F00 0000, the initial resource allocation result of the second processor is adjusted to obtain the first target allocation result of the second processor. Based on the upper limit of the first target allocation result of the second processor, the initial resource allocation result of the third processor is adjusted to obtain the first target allocation result of the third processor. Based on the upper limit of the first target allocation result of the third processor, the initial resource allocation result of the fourth processor is adjusted to obtain the first target allocation result of the fourth processor. The upper limit of the first target allocation result of the fourth processor, 70FE 0000, is less than the upper limit of the global resource information, BFFF FFFF. Thus, a continuous and complete first target allocation result [4000 0000 ~70FE 0000] is obtained from the first processor to the fourth processor.

[0133] I / O and MMIO have similar characteristics. Therefore, the adjustment rules are also consecutive numbered rules. When the device resource is I / O, the process of obtaining the second target allocation result based on the initial resource allocation result of each of the N processors is similar to the process of obtaining the second target allocation result when the device resource is MMIO, and will not be elaborated here.

[0134] When the device resource is a BUS number, the adjustment rule can be a non-continuous rule.

[0135] If the initial resource allocation result of the first processor does not exceed the allocatable range of the local resource information of the first processor, the initial resource allocation result of the first processor is determined as the first target allocation result of the first processor; if the initial resource allocation result of the first processor exceeds the allocatable range of the local resource information, the local resource information of the first processor is determined as the first target allocation result of the first processor.

[0136] In order of numbering, the initial resource allocation results of each of the N processors are adjusted individually to obtain the first target allocation result for each of the N processors.

[0137] For example, for the nth processor, if the upper limit of the initial resource allocation result of the nth processor is less than or equal to the maximum value of the local resource information of the nth processor, the initial resource allocation result of the nth processor is determined as the first target allocation result of the nth processor; if the upper limit of the initial resource allocation result of the nth processor is greater than the maximum value of the local resource information of the nth processor, the local resource information of the nth processor is determined as the first target allocation result of the nth processor. The process of determining the first target allocation result of each of the N processors is the same as the above process, and will not be repeated here.

[0138] Figure 3C A schematic diagram illustrating the allocation and adjustment of BUS number resources according to an embodiment of this application is shown.

[0139] like Figure 3CAs shown, the device resource is the BUS number. Before pre-allocation, the global resource information of the device resource is represented in decimal [0~255]. After pre-allocation, the number of processors is 4. Based on the global resource information, the device resource is evenly distributed among the 4 processors to obtain the local resource information of the 1st processor [0~63], the 2nd processor [64~127], the 3rd processor [128~191], and the 4th processor [192~255]. The 4 processors execute their respective second initialization tasks in parallel, and after allocation, the initial resource allocation results for each of the 4 processors are obtained. The initial resource allocation results represent the allocated device resources. The initial resource allocation results of the processors are adjusted so that the initial resource allocation results of each processor do not exceed the allocatable range of the local resource information. Therefore, the local resource information of the first processor is determined as the first target allocation result of the first processor, the local resource information of the second processor is determined as the first target allocation result of the second processor, the local resource information of the third processor is determined as the first target allocation result of the third processor, and the local resource information of the fourth processor is determined as the first target allocation result of the fourth processor.

[0140] According to embodiments of this application, local resource information is pre-allocated to multiple processors based on global resource information. After each processor completes the second initialization task of the second device based on the local resource information, it feeds back the initial resource allocation result to the main processor. The main processor performs unified resource adjustment, so that the device resources of all second devices in the multi-way computer system are in a continuous and unified spatial range (this result is consistent with the serial processing process), enabling all second devices in the system to work in coordination. Using this method in an m-way computer system, the initialization time of the second device can be shortened by (m-1) / m, that is, shortened to 1 / m of the original time. Taking a 4-way computer system as an example, the initialization time is shortened to 1 / 4 of the original time.

[0141] According to embodiments of this application, the initial resource allocation result includes a first initial allocation result, a second initial allocation result, and a third initial allocation result; wherein: the first initial allocation result indicates the allocation result of bus numbers under a first local address for multiple high-speed bus expansion devices; the range of the first local address is determined based on the allocatable range of bus numbers; the second initial allocation result indicates the allocation result of memory-mapped input / output spaces under a second local address for multiple high-speed bus expansion devices; the range of the second local address is determined based on the allocatable range of memory-mapped input / output spaces; the third initial allocation result indicates the allocation result of input / output spaces under a third local address for multiple high-speed bus expansion devices; the range of the third local address is determined based on the allocatable range of input / output spaces.

[0142] The first initial allocation result is the allocation result of device resources as bus number, the second initial allocation result is the allocation result of device resources as memory-mapped input / output space, and the third initial allocation result is the allocation result of device resources as input / output space.

[0143] Based on the allocatable range corresponding to the global resource information of the computer system and the number of processors, the local resource information of each processor's bus number is determined. The range of the first local address is the allocatable range corresponding to the local resource information of the processor's bus number.

[0144] Based on the allocatable range of the memory-mapped input / output space corresponding to the global resource information of the computer system and the number of processors, the local resource information of the memory-mapped input / output space for each processor is determined. The range of the second local address is the allocatable range corresponding to the local resource information of the processor's memory-mapped input / output space.

[0145] The local resource information of each processor's input / output space is determined based on the allocatable range of the global resource information of the computer system and the number of processors. The range of the third local address corresponds to the allocatable range of the processor's local resource information of its input / output space.

[0146] Figure 3D A flowchart of a computer system startup method according to another embodiment of this application is shown.

[0147] like Figure 3D As shown, the method includes operations S310 to S370.

[0148] In step S310, the first initialization task is executed.

[0149] In step S320, based on the global resource information of the device resources, device resources are allocated to multiple processors to obtain the local resource information of the device resources.

[0150] In step S330, task configuration files for the second initialization tasks are created for the multiple processors respectively, and the multiple second initialization tasks are started.

[0151] In step S340, based on the local resource information of the device resources, device resources are allocated to multiple high-speed bus extension devices to determine the initial resource allocation result.

[0152] In step S350, initialization operations are performed on the multiple high-speed bus expansion devices using their respective device drivers to determine the device driver interfaces of each device.

[0153] In step S360, after all the second initialization tasks have been completed, resource unification adjustment is performed based on the results of multiple initial resource allocations.

[0154] In step S370, in response to the completion of resource adjustment, the operating system of the computer system is loaded to start the computer system.

[0155] According to an embodiment of this application, the first initial allocation result includes the initial bus number of each of the multiple high-speed bus expansion devices and the first overflow status information; the first overflow status information is used to indicate whether the allocated initial bus number exceeds the allocatable range of bus numbers.

[0156] The allocatable range of bus numbers is determined based on local resource information. For example, if the local resource information is [0~63], then the allocatable range of bus numbers is [0~63].

[0157] The initial bus number is the bus number already assigned in the first initial allocation result. For example, if the first initial allocation result is [0~50], the initial bus number is [0~50].

[0158] If the initially assigned bus number exceeds the allocatable range of bus numbers, the first overflow status information, BUS overflow, is 1; otherwise, it is 0.

[0159] For example, if the first initial allocation result is [0~50] and the allocatable range of bus numbers is [0~63], and the allocated initial bus number does not exceed the allocatable range of bus numbers, then the first overflow status information BUS overflow is 0.

[0160] According to an embodiment of this application, the first overflow status information is determined based on the following operations: determining an upper limit value of the allocated initial bus numbers based on a plurality of initial bus numbers; and determining the first overflow status information based on the upper limit value of the allocatable range of bus numbers and the upper limit value of the allocated initial bus numbers.

[0161] The upper limit of the initial bus number is the maximum value.

[0162] If the upper limit of the allocatable range of bus numbers is greater than or equal to the upper limit of the initially allocated bus numbers, the first overflow status information BUS overflow is set to 0 to indicate that there is no overflow.

[0163] If the upper limit of the allocatable range of bus numbers is less than the upper limit of the initially allocated bus numbers, the first overflow status information is determined, and the BUS overflow is marked as 1, indicating an overflow.

[0164] According to an embodiment of this application, the second initial allocation result includes the initial memory-mapped input / output space of each of the multiple high-speed bus expansion devices and the second overflow status information; the second overflow status information is used to indicate whether the allocated initial memory-mapped input / output space exceeds the allocatable range of the memory-mapped input / output space.

[0165] The allocatable range of the memory-mapped input / output space is determined based on local resource information. For example, if the local resource information is [8000 0000~9FFF FFFF], then the allocatable range of the memory-mapped input / output space is [8000 0000~9FFF FFFF].

[0166] The initial memory-mapped input / output space is the memory-mapped input / output space already allocated in the first initial allocation result. For example, if the memory-mapped input / output space already allocated in the first initial allocation result is [8000 0000~A00F 0000], the initial memory-mapped input / output space is [8000 0000~A00F 0000].

[0167] If the allocated initial memory-mapped input / output space exceeds the allocatable range of the memory-mapped input / output space, the first overflow status information MMIO overflow is 1; otherwise, it is 0.

[0168] For example, if the first initial allocation result is [8000 0000~A00F 0000], the allocatable range of the memory-mapped input / output space is [8000 0000~9FFF FFFF], and the allocated initial memory-mapped input / output space exceeds the allocatable range of the memory-mapped input / output space, then the first overflow status information MMIO overflow is 1.

[0169] According to an embodiment of this application, the second overflow state information is determined based on the following operations: determining the upper limit of the allocated initial memory-mapped input / output space based on multiple initial memory-mapped input / output spaces; and determining the second overflow state information based on the upper limit of the allocatable range of the initial memory-mapped input / output space and the upper limit of the allocated initial memory-mapped input / output space.

[0170] The upper limit of the initial memory-mapped input / output space is the maximum value.

[0171] If the upper limit of the allocatable range of the memory-mapped input / output space is greater than or equal to the upper limit of the initially allocated memory-mapped input / output space, the first overflow status information MMIO overflow is set to 0, indicating that no overflow has occurred.

[0172] If the upper limit of the allocatable range of the memory-mapped input / output space is less than the upper limit of the initially allocated memory-mapped input / output space, the first overflow status information is determined, and the MMIO overflow is marked as 1, indicating an overflow.

[0173] According to an embodiment of this application, the third initial allocation result includes the initial input / output space of each of the multiple high-speed bus expansion devices and the third overflow status information; the third overflow status information is used to indicate whether the allocated initial input / output space exceeds the allocatable range of the input / output space.

[0174] The allocatable range of the input and output space is determined based on local resource information. For example, if the local resource information is [64~127], then the allocatable range of the input and output space is [64~127].

[0175] The initial input / output space is the input / output space already allocated in the first initial allocation result. For example, the first initial allocation result is the input / output space already allocated in [64~120], and the initial input / output space is [64~120].

[0176] If the allocated initial input / output space exceeds the allocatable range of the input / output space, the first overflow status information I / O overflow is 1; otherwise, it is 0.

[0177] For example, the first initial allocation result is [64~120], the allocatable range of the input / output space is [64~127], the allocated initial input / output space does not exceed the allocatable range of the input / output space, and the first overflow status information I / Ooverflow is 0.

[0178] According to an embodiment of this application, the third overflow state information is determined based on the following operations: determining the upper limit of the allocated initial input / output space based on multiple initial input / output spaces; and determining the third overflow state information based on the upper limit of the allocatable range of the initial input / output space and the upper limit of the allocated initial input / output space.

[0179] The upper limit of the initial input / output space is the maximum value.

[0180] If the upper limit of the allocatable range of the input / output space is greater than or equal to the upper limit of the initially allocated input / output space, the first overflow status information I / O overflow is set to 0, indicating that no overflow has occurred.

[0181] If the upper limit of the allocatable range of the input / output space is less than the upper limit of the initially allocated input / output space, the first overflow status information is determined, and the I / O overflow is marked as 1, which represents an overflow.

[0182] Figure 4 A structural block diagram of a computer system startup apparatus according to an embodiment of this application is shown.

[0183] like Figure 4 As shown, the computer system startup device 400 of this embodiment includes an execution module 410, a first determination module 420, a second determination module 430, an adjustment module 440, and a loading module 450.

[0184] The execution module 410 is used to execute a first initialization task after the computer system has been powered on; the first initialization task includes performing an initialization configuration operation on a first device of the computer system, the first device including a display device.

[0185] The first determining module 420 is used to allocate device resources to multiple processors based on the global resource information of the device resources after the first initialization task is completed, and to determine the local resource information of each of the multiple processors. The local resource information indicates the allocation result of device resources for multiple processors under the global address.

[0186] The second determining module 430 is used to execute multiple second initialization tasks in parallel using multiple processors to determine the initial resource allocation results of each of the multiple processors; the second initialization tasks include performing resource allocation operations and initialization operations on multiple second devices currently associated with the processor based on local resource information.

[0187] The adjustment module 440 is used to perform resource unification adjustment based on multiple initial resource allocation results after multiple second initialization tasks have been completed, to obtain a target resource allocation result. The target resource allocation result includes a first target allocation result and a second target allocation result. The first target allocation result indicates the allocation result of device resources under the global address for multiple second devices, and the second target allocation result indicates the allocation result of device resources under the global address for hot-pluggable devices that are not currently associated with the processor. The second target allocation result is determined based on the first target allocation result.

[0188] Loading module 450 is used to load the operating system of the computer system in response to the completion of resource adjustments, so as to start the computer system.

[0189] Figure 5 A block diagram of an electronic device suitable for implementing a computer system startup method according to an embodiment of this application is shown.

[0190] Figure 5 The electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0191] like Figure 5As shown, a computer electronic device 500 according to an embodiment of this application includes a processor 501, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 502 or a program loaded from a storage portion 508 into a random access memory (RAM) 503. The processor 501 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 501 may also include onboard memory for caching purposes. The processor 501 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of this application.

[0192] RAM 503 stores various programs and data required for the operation of electronic device 500. Processor 501, ROM 502, and RAM 503 are interconnected via bus 504. Processor 501 executes various operations of the method flow according to embodiments of this application by executing programs in ROM 502 and / or RAM 503. It should be noted that programs may also be stored in one or more memories other than ROM 502 and RAM 503. Processor 501 may also execute various operations of the method flow according to embodiments of this application by executing programs stored in one or more memories.

[0193] According to embodiments of this application, the electronic device 500 may further include an input / output (I / O) interface 505, which is also connected to a bus 504. The electronic device 500 may also include one or more of the following components connected to the input / output (I / O) interface 505: an input section 506 including a keyboard, mouse, etc.; an output section 507 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 508 including a hard disk, etc.; and a communication section 509 including a network interface card such as a LAN card, modem, etc. The communication section 509 performs communication processing via a network such as the Internet. A drive 510 is also connected to the input / output (I / O) interface 505 as needed. A removable medium 511, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 510 as needed so that computer programs read from it can be installed into the storage section 508 as needed.

[0194] According to embodiments of this application, the method flow according to embodiments of this application can be implemented as a computer software program. For example, embodiments of this application include a computer program product comprising a computer program carried on a computer-readable storage medium, the computer program containing program code for performing the methods shown in the flowchart. In such embodiments, the computer program can be downloaded and installed from a network via communication section 509, and / or installed from removable medium 511. When the computer program is executed by processor 501, it performs the functions defined in the system of embodiments of this application. According to embodiments of this application, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0195] This application also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the computer system startup method according to the embodiments of this application.

[0196] According to embodiments of this application, the computer-readable storage medium can be a non-volatile computer-readable storage medium. Examples include, but are not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this application, the computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0197] For example, according to embodiments of this application, a computer-readable storage medium may include the ROM 502 and / or RAM 503 described above and / or one or more memories other than ROM 502 and RAM 503.

[0198] Embodiments of this application also include a computer program product, which includes a computer program containing program code for performing the methods provided in the embodiments of this application. When the computer program product is run on an electronic device, the program code is used to enable the electronic device to implement the computer system startup method provided in the embodiments of this application.

[0199] When the computer program is executed by the processor 501, it performs the functions defined in the system / apparatus of this application embodiment. According to the embodiments of this application, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0200] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and may be downloaded and installed via the communication section 509, and / or installed from a removable medium 511. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0201] According to embodiments of this application, program code for executing the computer programs provided in the embodiments of this application can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0202] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions. Those skilled in the art will understand that the features described in the various embodiments of this application can be combined and / or combined in various ways, even if such combinations are not explicitly described in this application. In particular, without departing from the spirit and teachings of this application, the features described in the various embodiments of this application can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of this application.

[0203] The embodiments of this application have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of this application. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Without departing from the scope of this application, those skilled in the art can make various substitutions and modifications, all of which should fall within the scope of this application.

Claims

1. A computer system startup method, characterized in that, The computer system includes multiple processors, and the method includes: Upon completion of the computer system power-on, a first initialization task is executed; the first initialization task includes performing initialization configuration operations on a first device of the computer system, the first device including a display device. Once the first initialization task is completed, device resources are allocated to multiple processors based on the global resource information of the device resources, and the local resource information of each of the multiple processors is determined. The local resource information indicates the allocation result of device resources for multiple processors under the global address. Multiple processors are used to execute multiple second initialization tasks in parallel to determine the initial resource allocation results of each processor; the second initialization tasks include performing resource allocation operations and initialization operations on multiple second devices currently associated with the processor based on the local resource information; After multiple second initialization tasks have been completed, resource unification adjustment is performed based on multiple initial resource allocation results to obtain the target resource allocation result. The target resource allocation result includes a first target allocation result and a second target allocation result. The first target allocation result indicates the allocation result of device resources under the global address for multiple second devices, and the second target allocation result indicates the allocation result of device resources under the global address for hot-pluggable devices that are not currently associated with the processor. The second target allocation result is determined based on the first target allocation result. Once resource adjustments are complete, the computer system's operating system is loaded to start the computer system.

2. The method according to claim 1, characterized in that, The second device includes a high-speed bus extension device; the second initialization task includes performing the following operations in parallel using the processor: Based on local resource information, device resources are allocated to multiple high-speed bus expansion devices to determine the initial resource allocation result. The initial resource allocation result indicates the allocation of device resources for the multiple high-speed bus expansion devices under the local address. Local resource information represents the local address; and... Based on the initial resource allocation results, perform initialization operations on multiple high-speed bus expansion devices.

3. The method according to claim 2, characterized in that, Multiple processors include a master processor and at least one slave processor; The device resources include bus number, memory-mapped input / output space, and input / output space.

4. The method according to claim 3, characterized in that, The execution of the first initialization task includes performing the following operations using the main processor: Initialize the display device to make it available so that initialization information can be output via the initialized display device.

5. The method according to claim 3, characterized in that, The global resource information based on device resources is used to allocate device resources to multiple processors, and the local resource information of each processor is determined, including the operation performed using the main processor: Create separate task configuration files for the second initialization task for each of the multiple processors; Based on the number of processors and global resource information of the devices, allocate device resources to the multiple processors and determine the local resource information of each processor; and The local resource information of each of the multiple processors is written into the respective task configuration files of each processor.

6. The method according to claim 5, characterized in that, The initialization operation for multiple high-speed bus expansion devices includes: By utilizing the respective device drivers of multiple high-speed bus expansion devices, initialization operations are performed on the multiple high-speed bus expansion devices to determine the device driver interfaces of the multiple high-speed bus expansion devices. Write the device driver interfaces of multiple high-speed bus expansion devices into the task configuration file.

7. The method according to claim 5, characterized in that, The process of allocating device resources to multiple high-speed bus expansion devices based on local resource information and determining the initial resource allocation results includes: Read local resource information of device resources from the task configuration file; For the multiple high-speed bus expansion devices associated with the multiple processors, based on the local resource information of the device resources, device resources are allocated to the multiple high-speed bus expansion devices to determine the initial resource allocation result; and Write the initial resource allocation results to the task configuration file.

8. The method according to claim 7, characterized in that, The local resource information based on device resources is used to allocate device resources to multiple high-speed bus extension devices, and the initial resource allocation result is determined as follows: Based on the allocatable range of device resources represented by local resource information, determine the upper limit and lower limit of the allocatable range of device resources; Based on the upper and lower limits of the allocatable range, device resources are allocated to multiple high-speed bus extension devices to determine the initial resource allocation result.

9. The method according to claim 5, characterized in that, The step of performing resource unification adjustment based on multiple initial resource allocation results to obtain the target resource allocation result includes performing the following operations using the main processor: Read the initial resource allocation results of each processor from its respective task configuration file; Based on multiple initial resource allocation results, the device resources of multiple high-speed bus expansion devices are uniformly adjusted to obtain the first target allocation result. The first target allocation result indicates the allocation result of device resources under the global address for multiple high-speed bus expansion devices. as well as Based on the first target allocation result, according to the preset hot-swappable device resource quota and the number of hot-swappable devices not currently associated with the processor, device resources are reserved for the hot-swappable devices not currently associated with the processor to obtain the second target allocation result. The second target allocation result indicates the allocation result of device resources reserved for the hot-swappable devices not currently associated with the processor under the global address.

10. The method according to claim 9, characterized in that, The multiple processors include N processors in numerical order, where N is an integer greater than 1; the step of uniformly adjusting the device resources of the multiple high-speed bus expansion devices according to multiple initial resource allocation results to obtain the first target allocation result includes: Based on the initial resource allocation result of the first processor, determine the first target allocation result of the first processor; Based on the first target allocation result of the first processor, the initial resource allocation results of the second to Nth processors are adjusted sequentially according to their numbering order to obtain the first target allocation results of each of the N processors. Specifically, the first target allocation result of the Nth processor is determined based on the initial resource allocation result of the Nth processor and the first target allocation result of the (N-1)th processor.

11. The method according to claim 10, characterized in that, The initial resource allocation results include a first initial allocation result, a second initial allocation result, and a third initial allocation result; wherein: The first initial allocation result indicates the allocation result of the bus number under the first local address for multiple high-speed bus extension devices; the range of the first local address is determined based on the allocatable range of the bus number; The second initial allocation result indicates the allocation result of the memory-mapped input / output space under the second local address for multiple high-speed bus extension devices; the range of the second local address is determined based on the allocatable range of the memory-mapped input / output space; The third initial allocation result indicates the allocation result of the input / output space under the third local address for multiple high-speed bus expansion devices; the range of the third local address is determined based on the allocatable range of the input / output space.

12. The method according to claim 11, characterized in that, The first initial allocation result includes the initial bus number of each of the multiple high-speed bus expansion devices and the first overflow status information; the first overflow status information is used to indicate whether the allocated initial bus number exceeds the allocatable range of bus numbers. The first overflow status information is determined based on the following operations: Based on multiple initial bus numbers, determine the upper limit of the allocated initial bus numbers; The first overflow status information is determined based on the upper limit of the allocatable range of the bus number and the upper limit of the initial bus number that has been allocated.

13. The method according to claim 11, characterized in that, The second initial allocation result includes the initial memory-mapped input / output space of each of the multiple high-speed bus expansion devices and the second overflow status information; the second overflow status information is used to indicate whether the allocated initial memory-mapped input / output space exceeds the allocatable range of the memory-mapped input / output space; The second overflow status information is determined based on the following operations: Based on multiple initial memory-mapped input / output spaces, determine the upper limit of the allocated initial memory-mapped input / output space; The second overflow status information is determined based on the upper limit of the allocatable range of the initial memory-mapped input / output space and the upper limit of the allocated initial memory-mapped input / output space.

14. The method according to claim 11, characterized in that, The third initial allocation result includes the initial input / output space of each of the multiple high-speed bus expansion devices and the third overflow status information; the third overflow status information is used to indicate whether the allocated initial input / output space exceeds the allocatable range of the input / output space. The third overflow status information is determined based on the following operations: Based on multiple initial input / output spaces, determine the upper limit of the allocated initial input / output space; The third overflow state information is determined based on the upper limit of the allocatable range of the initial input / output space and the upper limit of the allocated initial input / output space.

15. An electronic device comprising: One or more processors; Memory, used to store one or more computer programs. The characteristic feature is that the one or more processors execute the one or more computer programs to implement the steps of the method according to any one of claims 1 to 4.

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