A method and system for co-predicting wafer defects and yield

Abstract

This application relates to a method and system for collaborative prediction of wafer defects and yield. The method includes constructing a training dataset; then constructing a dual-task deep learning model, which includes: a defect feature extraction module, which extracts defect feature vectors from preprocessed wafer defect images using channel attention and spatial attention mechanisms; a defect classification module, which classifies defect types based on the defect feature vectors output by the defect feature extraction module; and a yield correlation analysis module, which divides the wafer surface into grid cells based on a graph neural network to construct a defect-yield correlation graph, and outputs the yield loss corresponding to each type of defect or defect combination by learning the spatial distribution and interaction of defects; then, the image of the wafer to be inspected is input into the trained dual-task deep learning model, and the defect classification result and the corresponding yield loss are output. This application can improve the accuracy of wafer defect detection and the precision of yield prediction.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of chip defect analysis, in particular to a wafer defect and yield collaborative prediction method and system. BACKGROUND

[0002] With the rapid development of the semiconductor industry, chip manufacturing processes are constantly advancing towards smaller feature sizes and higher integration. In the chip manufacturing process, the detection and classification of wafer surface defects are crucial to ensure chip yield. Wafer defects, such as scratches, particle contamination, metal residues, and oxide layer defects, can directly affect the performance and reliability of chips. Therefore, accurately identifying and classifying these defects and analyzing their impact on the yield of the final product is key to improving chip manufacturing efficiency and reducing costs.

[0003] Currently, the detection of wafer defects mainly relies on high-resolution imaging technologies such as scanning electron microscopes (SEM). However, as process technology advances, defects on wafers become increasingly small, and traditional machine vision techniques based on manually designed features face challenges in identifying these small-sized defects. In addition, existing technologies lack accuracy and generalization ability in defect classification, especially when facing different process wafers, which requires re-tuning of feature parameters, resulting in low detection efficiency.

[0004] Currently, there are several common chip detection methods:

[0005] 1. From the perspective of equipment, electrical detection and testing of chips are carried out:

[0006] Patent application CN118115038A discloses an LED chip defect detection method, device, equipment and storage medium. The method includes: selecting a plurality of chip process detection models corresponding to a plurality of device nodes respectively, and inputting chip process data of each device node in a target time period into the corresponding chip process detection model to obtain a corresponding process yield; calculating the process pass rate of the target LED chip produced in the target time period based on the weight data corresponding to each device node and the corresponding process yield; determining whether the product grade of the target LED chip is a pre-set defective grade based on the process pass rate; performing chip electrical detection on the target LED chip of the defective grade to obtain a chip defect detection result.

[0007] However, this method of selectively testing batches of chips based on good product grades can easily hide some small defects and make it difficult to find them.

[0008] 2. Defect classification based on numerical detection results of wafers

[0009] The prior art CN120673102A discloses a wafer defect classification method, which classifies defects by obtaining multi-modal test information of the wafer and generating multiple test maps, and considers different modal test information to improve classification accuracy. Among them, the method needs to perform tests in different dimensions such as direct current (DC), function (Function) or margin (Margin), and generate test maps according to specific test values, so its operation difficulty and cost in the defect identification process are relatively high. In addition, the method needs manual participation to define attention maps, which limits the automation degree and processing speed.

[0010] And the applicant notices that as the number and types of small size defects on the wafer gradually increase, the above two types of traditional defect detection methods are difficult to improve in detection efficiency and accuracy.

[0011] 3. Yield loss prediction according to defect density

[0012] Patent application CN113609814A provides a wafer yield loss prediction method and a self-defined defect density pattern self-reporting system, wherein the wafer yield loss prediction method includes sequentially obtaining the overall defect density of all chips on the wafer; establishing a defect density data model; obtaining the defect density pattern of the wafer; sequentially analyzing the failure rate of all chips in the defect density pattern; and predicting the yield loss of the wafer.

[0013] Similarly, the applicant notices that in some production lines integrating multiple complex processes, the number of small size defects on the wafer is large, but the types or effects of the defects may differ significantly. In this case, predicting yield loss according to defect density may result in a significant difference between yield loss and actual yield loss.

[0014] In summary, there is an urgent need for a means of quickly and efficiently detecting wafer defects. SUMMARY

[0015] The purpose of the present application is to provide a wafer defect and yield collaborative prediction method and system, which partially solves or alleviates the above-mentioned deficiencies in the prior art, and can improve the accuracy of wafer defect detection and the precision of yield prediction.

[0016] To solve the above-mentioned technical problems, the present application specifically adopts the following technical solutions: The first aspect of the present application is to provide a wafer defect and yield collaborative prediction method, comprising the following steps: constructing a training data set, the training data set comprising pre-processed wafer defect images and wafer normalized yield data; constructing a dual-task deep learning model, the dual-task deep learning model comprising: a defect feature extraction module, which extracts a defect feature vector from the pre-processed wafer defect image using a channel attention mechanism and a spatial attention mechanism; a defect classification module, which classifies defect types based on the defect feature vector output by the defect feature extraction module; a yield correlation analysis module, which divides the wafer surface into grid cells based on a graph neural network to construct a defect yield correlation graph, and outputs a yield loss corresponding to each type of defect or defect combination by learning the spatial distribution and interaction of defects; constructing a loss function using wafer normalized yield data, and training the dual-task deep learning model using the loss function, then inputting the image of the wafer to be detected into the trained dual-task deep learning model, and outputting the defect classification result and the corresponding yield loss.

[0017] Further, the processing flow of the channel attention mechanism is: using an initial convolution layer to perform initial feature extraction on the pre-processed wafer defect image to obtain an initial feature map; performing global average pooling on each channel of the initial feature map to obtain global features; transforming the global features through a fully connected layer to obtain channel attention weights; multiplying the channel attention weights with each channel of the initial feature map to obtain a weighted feature map. Further, the processing flow of the spatial attention mechanism is: performing global maximum pooling and global average pooling on the weighted feature map; concatenating the results of the global maximum pooling and the global average pooling in the channel dimension to form a concatenated feature representation; inputting the concatenated feature representation into a convolution layer to extract spatial correlation information; using an activation function to process the output of the convolution layer to generate spatial attention weights; element-wise multiplying the generated spatial attention weights with the weighted feature map to obtain the final defect feature vector.

[0018] Furthermore, the step of dividing the wafer surface into grid cells based on a graph neural network to construct a defect yield correlation graph includes: dividing the wafer surface into M×N grid cells, each grid cell serving as a node in the graph, and the features of each node including: one-hot encoding of the defect type within the grid cell, the number of defects, and the defect area ratio; the connection of edges in the graph neural network is based on the spatial proximity and circuit function relationships between grid cells, and each edge is assigned a weight, the weight being determined by the distance between grid cells and / or the circuit function correlation. Further, the step also includes: updating the node features using a graph attention mechanism, including: calculating the attention coefficient of each node to its neighboring nodes; and using the attention coefficient to perform weighted aggregation of the features of neighboring nodes to update the node features.

[0019] Furthermore, the dual-task deep learning model is trained using a hybrid loss function, which is specifically:

[0020] L total =α×L1+β×L2;

[0021] ;

[0022] ;

[0023] Among them, L total The loss function is a mixture of loss functions; L1 is the defect classification loss; L2 is the yield correlation loss; N is the number of defect types. It is the actual type of defect. M is the probability of the defect type predicted by the model; M is the number of samples. It is the yield loss calculated by the model. It represents the actual yield loss in production; α and β are preset hyperparameters.

[0024] Furthermore, the method includes the following steps: based on the defect classification results and corresponding yield losses output by the dual-task deep learning model, generating optimization and adjustment suggestions for the front-end manufacturing process according to a preset rule base. Further, the method includes the following steps: based on the defect classification results and corresponding yield losses output by the dual-task deep learning model, assigning a yield risk value to each grid cell, and mapping the yield risk value to a corresponding color using a heatmap drawing tool to generate a heatmap. Further, the wafer is a 7nm or lower process wafer.

[0025] Secondly, this application also discloses a wafer defect and yield collaborative prediction system. The system includes: a dataset construction module configured to construct a training dataset, the training dataset including preprocessed wafer defect images and wafer normalized yield data; a dual-task deep learning model construction module configured to construct a dual-task deep learning model, the dual-task deep learning model including: a defect feature extraction module, the defect feature extraction module extracting defect feature vectors from the preprocessed wafer defect images using channel attention and spatial attention mechanisms; a defect classification module, classifying defect types based on the defect feature vectors output by the defect feature extraction module; a yield correlation analysis module, dividing the wafer surface into grid cells based on a graph neural network to construct a defect-yield correlation graph, and outputting the yield loss corresponding to each type of defect or defect combination by learning the spatial distribution and interaction of defects; and a defect and yield output module configured to construct a loss function using wafer normalized yield data, and train the dual-task deep learning model using the loss function, then inputting the image of the wafer to be detected into the trained dual-task deep learning model, and outputting the defect classification result and the corresponding yield loss.

[0026] Beneficial technical effects: It is worth noting that with the miniaturization of wafer defects and the increasing complexity of defect types, traditional defect detection and identification methods are facing enormous pressure in terms of identification efficiency and accuracy.

[0027] To address this issue, this invention provides a method for focusing attention resources on key defect identification. Specifically, this invention focuses on the two core stages of feature recognition design and loss design, gradually introducing spatial distribution and yield correlation to focus attention, so as to quickly learn and filter out defects that have a significant impact on yield through model learning.

[0028] It should be noted that when there are many small-sized defects distributed on the wafer, comprehensive identification would face enormous data processing pressure. Furthermore, due to the inherent and difficult-to-deconstruct correlation between the defects themselves, the interrelationships between defects, and the final yield of the wafer, it is difficult to improve the accuracy of defect identification.

[0029] To address this, this invention, by introducing spatial distribution relationships and yield correlations step by step, can guide the model to focus its attention resources highly on defect areas that significantly impact yield, thereby reducing the model's computational burden. Simultaneously, by dually restricting and guiding the degree of defect analysis / resources in terms of spatial correlation and yield correlation, not only is the computational burden reduced, but the model's output results are also ensured to have high reliability. Because the focus on defects is gradually guided in the two stages of defect spatial correlation and yield correlation, highly concerned defects are more likely to have a substantial impact on the wafer, such as causing partial circuit failure.

[0030] Furthermore, from another perspective, in the yield prediction process, this invention abandons the conventional approach of calculating the wafer failure rate based on the defect distribution density, and instead adopts a technical approach for defect identification based on an association map constructed from indirect parameters (i.e., not directly setting the wafer defect map based on the overall defect density / spacing).

[0031] Conversely, this invention uses a grid as the analysis unit (i.e., nodes) and constructs the grid's features based on core dimensions such as one-hot encoding of defect types, defect quantity, and defect area ratio. Simultaneously, this invention determines the weights of edges between grids based on the distance between grids and the functional correlation between circuits, thus representing, to some extent, the potential interactions between grids. This association graph, constructed based on the substantial characteristics of defects (such as type, quantity, and area ratio) and spatial and functional distribution relationships (i.e., assigning weights to edges), avoids the predictive risks arising from traditional one-size-fits-all analysis approaches (i.e., analyzing only based on distribution density).

[0032] For example, this one-size-fits-all approach may lead to the overlooking of some minor defects that have a substantial impact, resulting in excessively delayed defect warnings. However, this invention, by identifying defects through a correlation diagram constructed based on substantial features, spatial relationships, and functional connections, makes it easier to accurately identify the origins of core minor defects, preventing the defects from escalating and causing a more severe impact on production line yield.

[0033] In other words, the technical solution of this invention has at least the following technical advantages: 1. This invention proposes an integrated solution based on deep learning, which can simultaneously handle wafer defect classification and yield correlation analysis, realizing a closed loop of classification-correlation-feedback, thereby improving the efficiency of yield improvement. 2. This invention designs an end-to-end dual-task deep learning model, which includes two parallel tasks: defect classification and yield correlation analysis. This model can simultaneously optimize the two tasks within a unified framework, realizing information sharing and collaborative optimization. 3. This invention innovatively introduces graph neural networks (GNNs) to construct a defect-yield correlation graph, learning the spatial distribution and interaction of defects on yield through graph structure, thereby more accurately predicting yield loss. 4. This invention can handle the case of multiple defect combinations, providing more comprehensive guidance for process optimization by analyzing the interaction between different defect types and their combined impact on yield. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. The elements or parts in the drawings are not necessarily drawn to scale. Obviously, the drawings described below are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0035] Figure 1 This is a flowchart of a method for co-predicting wafer defects and yield according to this application.

[0036] Figure 2 This is a flowchart of a wafer selective detection method according to this application.

[0037] Figure 3 This is a flowchart of a wafer yield analysis model screening method according to this application.

[0038] Figure 4 This is a schematic diagram of the module structure of a wafer defect and yield co-prediction system in one embodiment of this application.

[0039] Figure 5 This is a schematic diagram of the module structure of a wafer selective detection system in one embodiment of this application.

[0040] Figure 6 This is a schematic diagram of the module structure of a wafer yield analysis model screening system in one embodiment of this application. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0042] In this document, suffixes such as "module," "component," or "unit" used to denote elements are used solely for the purpose of illustrative purposes and have no specific meaning in themselves. Therefore, "module," "component," or "unit" can be used interchangeably. In this document, terms such as "upper," "lower," "inner," "outer," "front," "rear," "one end," and "the other end," indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. In this document, unless otherwise expressly specified and limited, terms such as "installed," "equipped with," and "connected" should be interpreted broadly. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium; it can be a connection within two elements. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances. In this document, "and / or" includes any and all combinations of one or more of the listed related items. "Multiple" in this document means two or more, i.e., it includes two, three, four, five, etc.

[0043] Figure 1 A flowchart of a wafer defect and yield co-prediction method according to this application is shown. (Refer to...) Figure 1 The method specifically includes the following steps: S1, constructing a training dataset, which includes preprocessed wafer defect images and wafer normalized yield data;

[0044] S2. Construct a dual-task deep learning model, wherein the dual-task deep learning model includes:

[0045] The defect feature extraction module extracts defect feature vectors from the preprocessed wafer defect image using channel attention and spatial attention mechanisms. The defect classification module classifies defect types based on the defect feature vectors output by the defect feature extraction module. The yield correlation analysis module divides the wafer surface into grid cells based on a graph neural network to construct a defect yield correlation graph, and outputs the yield loss corresponding to each type of defect or defect combination by learning the spatial distribution and interaction of defects.

[0046] S3. Construct a loss function using normalized wafer yield data, and use the loss function to train the dual-task deep learning model. Then, input the image of the wafer to be inspected into the trained dual-task deep learning model, and output the defect classification result and the corresponding yield loss.

[0047] The following disclosure provides a specific embodiment applicable to a wafer defect and yield co-prediction method of this application, which includes the following steps:

[0048] Step S101: Dataset Construction

[0049] 1) Data Collection

[0050] This invention is applied to the wafer inspection stage of chip manufacturing, specifically targeting defect screening and yield optimization for 7nm and below advanced process wafers (such as logic chip wafers and memory chip wafers). During chip mass production, more than 20 typical defects may appear on the wafer surface, such as scratches, particle contamination, metal residue, and oxide layer defects. The type, location, and number of these defects directly affect the final chip yield (for example, if a 7nm logic wafer has ≥3 particle defects with a diameter >0.1μm, the yield may decrease by 15%-20%).

[0051] To achieve accurate classification of wafer defects and yield correlation analysis, high-quality raw data is first required. Specifically, this application acquires wafer surface images (i.e., wafer defect images) using high-resolution scanning electron microscopy (SEM). These images, with a resolution of up to 5000×5000 pixels, can clearly capture various minute defects on 7nm process logic wafers. This application has collected over 100,000 image samples, covering 20 typical wafer defect types, such as scratches, particle contamination, metal residue, and oxide layer defects. The type, location, and quantity of these defects directly affect the final chip yield. In addition to images of single defects, this application also collects image samples containing combinations of multiple defects. For example, some wafers may simultaneously have scratches and particle contamination, or metal residue and oxide layer defects superimposed. These combinations of multiple defects are very common in actual production and have a more complex impact on yield. Therefore, this application ensures that the dataset contains a sufficient number of samples of multiple defect combinations so that the model can learn the interactions between different defects and their combined impact on yield.

[0052] In addition to defect images, this application also collected corresponding wafer-level yield data. This data includes the test yield Y% for each wafer (where Y represents the percentage of yield) and failure markers for each chip unit. This yield data helps this application understand the specific impact of different defects (including single defects and combinations of multiple defects) on chip performance. Furthermore, this application also collected process auxiliary data, such as etching time and deposition temperature. This data can provide important references for subsequent process optimization.

[0053] 2) Data preprocessing:

[0054] Denoising: Adaptive Gaussian filtering is used to denoise the defect image. Adaptive Gaussian filtering dynamically adjusts the filtering parameters based on the local features of the image, effectively removing random noise while preserving the detailed information of the defects. This step significantly improves the image quality and lays the foundation for subsequent feature extraction and analysis.

[0055] Image enhancement: Image enhancement is performed using histogram equalization and edge sharpening techniques. Histogram equalization adjusts the grayscale distribution of the image, enhancing contrast and making the grayscale difference between defects and the background more apparent. Edge sharpening highlights the edge features of defects, helping the model to more accurately locate their positions. The combination of these two techniques significantly improves the analyzability of the image.

[0056] Defect Region Cropping: This method uses threshold segmentation to extract the region of interest (ROI) of the defect, eliminating invalid background. By setting an appropriate threshold, the defect region in the image is separated from the background, cropping out the area containing the defect, reducing interference from invalid information, and improving the model's processing efficiency and accuracy. For cases with multiple defects, this application extracts the ROI of each defect separately and records their relative positions in the image for subsequent analysis of the interactions between defects.

[0057] 3) Preprocessing of yield data

[0058] The yield data Y% is mapped to the [0,1] interval. Normalization ensures a consistent data range, facilitating model processing and learning. Specifically, this application converts the yield data Y% to Y∈[0,1], where 0 represents the lowest yield and 1 represents the highest yield.

[0059] Step S101 involves labeling the preprocessed data to construct a "defect-yield" aligned dataset. This application labels the type, location, number, and corresponding yield loss for each defect. For a single defect, such as a wafer with a particulate defect, this application labels the particulate defect as "particulate contamination," its location as "wafer center region," its quantity as "3," and its corresponding yield loss as "15%." For combinations of multiple defects, this application also provides detailed labeling. For example, if a wafer has both scratches and particulate contamination, this application labels the scratch as "scratch," its location as "wafer edge region," and its quantity as "1"; the particulate contamination as "particulate contamination," its location as "wafer center region," and its quantity as "5." Simultaneously, this application labels the overall yield loss of the wafer as "25%" and records the relative positional relationship between scratches and particulate contamination. In this way, this application can establish a direct correlation between defect features (including single defects and combinations of multiple defects) and yield loss, providing high-quality training data for subsequent deep learning model training.

[0060] Step S102: Deep Learning Model Construction

[0061] This invention designs an "end-to-end dual-task deep learning model," which includes three core modules:

[0062] Defect feature extraction module: An improved neural network convolutional layer is used to insert "channel attention mechanism" and "spatial attention mechanism" to focus on enhancing the feature response of small-sized defects (such as 0.1-0.3μm particles). Channel attention focuses on the gray-scale difference features of defects, and spatial attention focuses on the edge contour features of defects, which solves the problem of insufficient extraction of low-contrast defect features by traditional CNNs.

[0063] The input to the defect feature extraction module is the initial input image I, which undergoes preprocessing operations such as denoising, contrast enhancement, and ROI extraction to obtain the preprocessed image I′: I′=Preprocess(I);

[0064] In some embodiments, the processing flow of the channel attention mechanism is as follows: initial feature extraction is performed on the preprocessed wafer defect image using an initial convolutional layer to obtain an initial feature map; global average pooling is performed on each channel of the initial feature map to obtain global features; the global features are transformed through a fully connected layer to obtain channel attention weights; and the channel attention weights are multiplied by each channel of the initial feature map to obtain a weighted feature map.

[0065] In some embodiments, a more specific channel attention mechanism can be:

[0066] Initial convolutional layer feature extraction:

[0067] The input image is convolved using a 3x3 convolution kernel, followed by a BN layer and ReLU activation.

[0068] F = ReLU(BN(Conv(I′,kernelsize=3,padding=1))); where F represents the feature map output by the convolutional layer, Conv represents the convolution operation, BN represents batch normalization, ReLU represents the ReLU activation function, kernelsize=3 indicates that the convolution kernel size used in the convolution operation is a 3x3 matrix. padding=1 indicates that a ring of pixels (usually 0) is added around the edges of the input image so that the size of the output image after convolution is the same as the input image. This setting helps to preserve edge information and avoid shrinking the feature map size.

[0069] First, global average pooling is performed on the feature map of each channel to obtain the global features of each channel;

[0070] Where Fc is the feature map of the c-th channel, H and W are the height and width of the feature map, respectively; i,j represent the spatial dimension indices of the feature map.

[0071] The global features are then transformed through two fully connected layers (usually two linear layers, with a non-linear activation function such as ReLU in between) to obtain the channel attention weights.

[0072] Att(c) = σ(W2δ(W1GAP(c)));

[0073] Where δ is a non-linear activation function (such as ReLU), W1 and W2 are the weights of the fully connected layer, σ is the final activation function (such as Sigmoid), and Att(c) is the attention weight of the c-th channel.

[0074] The attention weights are then multiplied by each channel of the original feature map to obtain the weighted feature map: Fc′=Att(c)×Fc;

[0075] The weighted feature maps are then fused to obtain the final channel attention feature map: Where Fout is the output feature map and C is the total number of channels.

[0076] In some embodiments, the processing flow of the spatial attention mechanism is as follows: global max pooling and global average pooling are performed on the weighted feature map; the results of global max pooling and global average pooling are concatenated along the channel dimension to form a concatenated feature representation; the concatenated feature representation is input into a convolutional layer to extract spatial correlation information; the output of the convolutional layer is processed using an activation function to generate spatial attention weights; the generated spatial attention weights are multiplied element-wise with the weighted feature map to obtain the final defect feature vector.

[0077] In some embodiments, a more specific spatial attention mechanism may be: first performing global max pooling (GMP) and global average pooling (GAP): ; Where i,j represent the spatial dimension indices of the feature map, i traverses the height H, and j traverses the width W.

[0078] The results of GMP and GAP are then concatenated along the channel dimension, and spatial correlation is extracted through a 7x7 convolutional layer: Fconcat=Concat(GMP(Fout),GAP(Fout)); Fspatial=Conv7x7(Fconcat); where Fconcat is the feature map after concatenating the results of GMP and GAP along the channel dimension, Fspatial is the feature map after extracting spatial correlation through a 7x7 convolutional layer, and Concat is the concatenation operation.

[0079] Then, the Sigmoid activation function is used to generate weights, which are then multiplied element-wise with the original feature map Fout to enhance important spatial locations in the feature map: M = σ(Fspatial); Fweighted = Fout ⊙ M;

[0080] Where M represents the weights generated using the Sigmoid activation function, σ represents the Sigmoid activation function, ⊙ represents element-wise multiplication, and Fweighted represents the feature map after spatial attention weighting.

[0081] Finally, the defect feature extraction module generates the target feature vector through a final convolutional layer, including:

[0082] Fweighted features are convolved using 3x3 kernels to integrate dual attention to enhance feature maps;

[0083] F′=Conv3×3(Fweighted);

[0084] Followed by a batch normalization layer to reduce internal covariate bias;

[0085] F′′=BN(F′); F′′ is the normalized feature map;

[0086] Then, the ReLU activation function is applied to increase the nonlinear expressive power of the network;

[0087] Ffinal = ReLU(F′′);

[0088] Ffinal represents the final output defect feature vector.

[0089] Defect classification module: Based on the 1024-dimensional feature vector output by the feature extraction module, it is connected to a fully connected layer and uses a parametric activation function to classify 20 types of defects (outputting the probability value P of each type of defect, such as "particle defect P=0.98").

[0090] Example of the processing procedure for the defect classification module:

[0091] The feature vectors are mapped to the defect type space through a fully connected layer;

[0092] Z=W2 ReLU(W1 Ffinal+b1)+b2; where Z represents the output of the fully connected layer, and W1,W2 and b1,b2 represent the weights and biases of the fully connected layer, respectively;

[0093] Then use the LeakyReLU or PReLU activation function: A=LeakyReLU(Z) or A=PReLU(Z); where A represents the output after activation;

[0094] The final output is a vector containing the probabilities of all defect types: P = Softmax(A); where P represents the final classification probability distribution.

[0095] Yield Correlation Analysis Module: This invention innovatively introduces a graph neural network (GNN) to construct a defect-yield correlation graph. The wafer is divided into 10000×10000 grid cells. The defect type (represented by one-hot encoding), defect quantity, and defect area ratio within each grid cell are used as node features. The distance between grid cells (whether they are adjacent) and the circuit functional correlation (such as whether they belong to the same SRAM area) are used as edge weights. Through the message passing mechanism of the GNN, the influence of the spatial distribution and interaction of defects on the yield is learned, and the yield loss weight W corresponding to each type of defect / defect combination is output (e.g., "core circuit area scratch defect W=0.25", indicating that the defect causes a 25% decrease in yield).

[0096] Construction of Graph Neural Networks (GNNs):

[0097] Step 1: Constructing the Defect-Yield Correlation Graph. To analyze the relationships, we must first express them mathematically. The input to a GNN is not a simple image or vector, but a graph:

[0098] 1. Node

[0099] This application divides the entire wafer surface into a huge grid, such as 10000x10000 cells. Each grid cell is a node. Each node has its own characteristics that describe the situation within the grid:

[0100] Defect type: Represented by one-hot encoding, for example, [1,0,0,...] represents a particle defect.

[0101] Number of defects: There are several defects in this grid.

[0102] Defect area percentage: How much of the grid area are occupied by defects in total.

[0103] 2. Edge

[0104] This application needs to define which mesh cells are related and connect them with an edge. There are two main types of relationships: spatial proximity: if two meshes are neighbors (adjacent), an edge is connected between them. This reflects the spatial clustering of defects. Circuit function relationship: if two meshes belong to the same important circuit function area (e.g., both in the SRAM memory area), an edge is also connected between them. This reflects the impact of defects on critical functions.

[0105] 3. Edge Weight

[0106] Not all relationships are equally important. This application assigns a weight to each edge, representing the closeness of the relationship: the closer the distance, the higher the weight. The more important the functional association, the higher the weight (for example, edges belonging to the same CPU core area have a higher weight than edges belonging to the same peripheral circuit area).

[0107] Step 2: Message Passing and Learning in GNN

[0108] 1. Adjacent Relationships: Each node (grid cell) "chats" with all its neighboring nodes, exchanging characteristic information. 2. Information Integration: Each node integrates and updates the information obtained from its neighbors, combining it with its own information. 3. Iterative Process: This chatting and information integration process goes through several rounds. After each round, each node gains a deeper understanding of the overall defect distribution on the wafer.

[0109] In some implementations, the method further includes the step of updating the features of nodes using a graph attention mechanism, including: calculating the attention coefficient of each node to its neighboring nodes; and using the attention coefficient to perform weighted aggregation of the features of the neighboring nodes to update the features of the nodes.

[0110] In some implementations, updating node features using graph attention mechanisms can be more specifically achieved by: calculating the attention coefficient of each node to its neighboring nodes; using the attention coefficients to perform weighted aggregation of the features of the neighboring nodes; and updating the node feature representation.

[0111] The formula for calculating the attention coefficient is as follows: ;

[0112] Among them, h i and h j Let be the feature vectors of node i and node j, respectively; W is the learnable weight matrix; and a is the learnable weight vector. This indicates a vector concatenation operation.

[0113] The aggregation formula is:

[0114] ;

[0115] Where N(i) is the set of neighboring nodes of node i, and σ is a non-linear activation function.

[0116] Graph Attention (GAT) is used in GNNs, which means that during the conversation, each node does not treat all its neighbors the same. It determines which neighbor's information is more important and assigns it a higher weight. For example, a node might pay more attention to information from its core GPU neighbors than to messages from less important edge neighbors.

[0117] Step 3: Output yield loss weights

[0118] After several rounds of iterative learning, GNN has gained an understanding of each defect (or combination of defects) in the entire wafer system.

[0119] Output: It outputs a weight vector. Each value in this vector corresponds to the weight of the yield loss for a defect type (or combination). For example, the value for "core circuit area scratch defect" in the output weight is 0.25. This means that, based on the model's learning and analysis, the occurrence of this defect will lead to a 25% decrease in the final product yield.

[0120] Here is an example of the yield correlation analysis module:

[0121] The wafer surface is divided into M×N grid cells, each grid cell is a node in the graph, and the characteristics of each node include: one-hot encoding of the defect type in the grid cell, the number of defects, and the defect area ratio.

[0122] Node characteristics: Node(i) = {defecttypei, defectcounti, defectarearatioi};

[0123] The node feature Node(i) consists of three parts: first, defecttypei, which uses one-hot encoding to represent the defect type at the i-th node; second, defectcounti, which records the number of defects in the grid cell where the node is located; and finally, defectarearatioi, which represents the area ratio of the defects in the grid cell.

[0124] In a graph neural network, the connection of edges is based on the spatial proximity and circuit function relationship between grid cells, and each edge is assigned a weight, which is determined by the distance between grid cells and / or the circuit function correlation.

[0125] In some embodiments, edge weights: ;

[0126] Where, ω d and ω f The preset fusion weights; S ij Spatial proximity factor: C ij This is the functional correlation factor.

[0127] In some embodiments, the spatial proximity factor and the functional correlation factor can be set in the following ways:

[0128] According to node v i and node v jThe spatial proximity factor is determined by the distance between nodes. For example, the smaller the node distance, the larger the spatial proximity factor.

[0129] The mapping relationship between node distance and spatial proximity factor can be preset by the user. For example, the node distance and spatial proximity factor can be inversely proportional. Alternatively, different proximity values ​​can be set as spatial proximity factors for different distance ranges. Specifically, when the node distance falls within a first distance range, the spatial proximity factor can use the first proximity value; when the node distance falls within a second distance range, the spatial proximity factor can use the second proximity value; when the node distance falls within a third distance range, the spatial proximity factor can use the third proximity value, and so on; where the distance gradually increases from the first to the third distance range, while the proximity value gradually decreases from the first to the third proximity value.

[0130] According to node v i and node v j The functional correlation factor is determined by the circuit's function. For example, different circuits are divided into different functional levels according to functional partitions (e.g., divided into at least level one and level two according to importance). Specifically, the functional correlation factor can be determined based on the functional level of the circuits to which two nodes belong. For example, when both nodes are level one, the functional correlation factor is the first correlation value; when one node is level one and the other is level two, the functional correlation factor is the second correlation value; when both nodes are level two, the functional correlation factor is the third correlation value, and the first correlation value gradually increases to the third correlation value.

[0131] Alternatively, in other embodiments, the spatial proximity factor and functional relevance factor can be set in the following ways: ;

[0132] p i and p j These are nodes v i and v j The center coordinates; σ is the scale parameter that controls the distance decay rate;

[0133] And C ij Functional correlation factor: ;

[0134] Among them, I( R( ) is the importance weight of the functional area to which the node belongs; ) is the identifier of the functional area to which the node belongs; δ(a,b) is the Kronecker function: ;

[0135] For example, in some embodiments, the edge weights can be... or Furthermore, the setting method for the spatial proximity factor or functional correlation factor can be found in the above embodiments.

[0136] GNNs learn the impact of the spatial distribution and interactions of defects on yield through a message passing mechanism.

[0137] H(l+1)=GNN(H(l),EdgeWeight);

[0138] Where H(l) represents the node feature representation of the l-th layer, and GNN represents a graph neural network;

[0139] Then output the weight of the yield loss for each defect (or combination of defects):

[0140] W = GNNOutput(H(L));

[0141] W represents the final yield loss weight vector, and L represents the number of layers in the GNN;

[0142] Step S103: Model Training and Optimization

[0143] In some embodiments, the dual-task deep learning model is trained using a hybrid loss function, which is specifically:

[0144] L total =α×L1+β×L2;

[0145] ;

[0146] ;

[0147] Among them, L total The loss function is a mixture of loss functions; L1 is the defect classification loss; L2 is the yield correlation loss; N is the number of defect types. It is the actual type of defect. M is the probability of the defect type predicted by the model; M is the number of samples. It is the yield loss calculated by the model. It represents the actual yield loss in production; α and β are preset hyperparameters.

[0148] In some embodiments, the following is an example of a training and optimization process:

[0149] Define the hybrid loss function: The hybrid loss function consists of two parts: defect classification loss L1 and yield correlation loss L2, and its formula is as follows: L total =α×L1+β×L2;

[0150] Where L1 is the defect classification loss, which uses the cross-entropy loss function to optimize the accuracy of defect classification. Its formula is as follows:

[0151] ;

[0152] Where N is the number of defect types, It is the actual defect type (usually one-hot encoded). This is the probability of the defect type predicted by the model. The cross-entropy loss function measures the difference between the model's predicted probability distribution and the true distribution. The smaller the L1 value, the higher the accuracy of the model in identifying defect types, which can reduce test misjudgments.

[0153] L2 represents the yield-related loss, which uses the mean squared error loss function to optimize the error between the yield loss weight W and the actual yield loss. Its formula is as follows:

[0154] ;

[0155] Where M is the number of samples, These are the yield loss weights calculated by the model. This represents the actual yield loss in production. The mean squared error loss function measures the difference between the model's predicted value and the actual value. The smaller the L2 value, the more accurate the model's prediction of yield loss, which can help optimize production strategies and reduce yield loss.

[0156] α and β are the weighting coefficients for defect classification loss and yield correlation loss, respectively. In this model, α = 0.4 and β = 0.6 are set to balance the weights of the two tasks. This weighting reflects the core objective of improving chip yield in semiconductor testing; therefore, a higher weight is given to the yield correlation loss to ensure that the accuracy of yield correlation prediction is optimized first during model training.

[0157] Training strategy:

[0158] Batch size Z: In each iteration, Z samples are randomly selected from the training dataset for training to improve the model's generalization ability.

[0159] Training rounds: Set the training rounds to 100 rounds, and process the entire training dataset once in each round.

[0160] Early stopping method: By monitoring the loss on the validation set, if the loss on the validation set does not decrease for 5 consecutive rounds, training is stopped to avoid overfitting.

[0161] Optimizer: The Adam optimizer is used for parameter updates, and its adaptive learning rate helps the model converge quickly.

[0162] During training, model performance can be periodically evaluated on a validation set, including defect classification accuracy and yield correlation prediction accuracy. Based on the evaluation results, the model structure, loss function weights, or training strategies can be adjusted to further improve model performance.

[0163] Through the above training and optimization process, this application finally obtains a trained deep learning model that can accurately classify wafer defects and predict their impact on yield in practical applications, thereby providing strong technical support for the chip manufacturing process.

[0164] Step S104: Defect classification and yield correlation reasoning:

[0165] In step S104, this application inputs the scanning electron microscope (SEM) image of the wafer to be inspected into the trained model to perform defect classification and yield correlation inference. The following is a detailed inference process:

[0166] 1. Input the SEM image of the wafer to be inspected.

[0167] First, the input SEM images undergo the same preprocessing operations as during training, including denoising, contrast enhancement, and ROI extraction, to ensure that the input data received by the model is in a consistent format.

[0168] 2. Defect Classification

[0169] The model first identifies defect features in the image through the defect feature extraction module, and then outputs the defect classification result through the defect classification module.

[0170] The defect classification results include defect type, location coordinates, and confidence level. For example, the model might output: "Location (X=120, Y=350): Metal residue defect, confidence level 0.96"

[0171] 3. Yield loss weight W

[0172] Next, the model calculates the yield loss weight W corresponding to each defect through the yield correlation analysis module.

[0173] The yield loss weight W quantifies the impact of different defect types on the final yield. For example, if the model outputs W=0.25, it means that the defect causes a 25% decrease in yield.

[0174] 4. Overall wafer yield prediction value Y

[0175] Based on the yield loss weights W for all defects, the model further predicts the overall wafer yield Ypred. The overall wafer yield prediction Ypred is the result after comprehensively considering the impact of all defects on yield, providing a basis for the final quality assessment of the wafer.

[0176] In some embodiments, the method may further include the steps of: assigning a yield risk value to each grid cell based on the defect classification results and corresponding yield loss output by the dual-task deep learning model, and mapping the yield risk value to a corresponding color using a heatmap drawing tool to generate a heatmap. In some embodiments, to visually display high-risk defect areas on the wafer, a defect distribution-yield impact heatmap can be generated by the model. The heatmap uses color coding to represent the defect density and yield risk of different areas, where darker colors indicate higher defect density or greater yield risk; the heatmap can help engineers quickly identify critical defect areas on the wafer, providing guidance for subsequent process optimization and defect repair.

[0177] 5. Results Output and Report Generation

[0178] The model integrates defect classification results, yield loss weights W, overall wafer yield predictions Ypred, and a defect distribution-yield impact heatmap into a detailed analysis report. This report not only provides detailed defect information but also yield predictions and risk assessments, offering data support for decision-making in the chip manufacturing process.

[0179] Step S105: Process optimization feedback

[0180] In some embodiments, step S105 includes: generating optimization and adjustment suggestions for the front-end manufacturing process based on the defect classification results and corresponding yield loss output by the dual-task deep learning model and a preset rule base.

[0181] In some embodiments, a more specific step S105 may be: In step S105, based on the yield correlation results obtained in step S104, this application will output targeted process adjustment suggestions to optimize the process flow. This step is a key link in forming a detection-analysis-optimization closed loop, aiming to directly guide actual process improvements through the analysis results of the model, thereby improving chip yield and quality. The following is a detailed process optimization feedback process:

[0182] 1. Analyze the correlation results of yield.

[0183] Using the yield loss weight W and the overall wafer yield prediction value Ypred output from the model in step S104, the main defect types affecting yield and their distribution are identified. Simultaneously, a defect distribution-yield impact heatmap can be used to determine high-risk defect areas on the wafer.

[0184] 2. Matching the preset rule base

[0185] Based on the identified primary defect types, the system queries a pre-defined rule base to obtain corresponding process adjustment suggestions. The pre-defined rule base is a database containing various defect types and recommended process adjustment measures.

[0186] For example, the rule base contains the following entries:

[0187] Particle contamination defect: It is recommended to optimize the photoresist coating speed to 5 mm / s to reduce particle adsorption.

[0188] Metal residue defects: It is recommended to check the purity and flow rate of the etching gas and optimize the etching process parameters.

[0189] Oxide layer defects: It is recommended to adjust the deposition temperature to the optimal range to reduce the occurrence of defects.

[0190] 3. Suggestions for adjusting the output process

[0191] Based on the model analysis results and suggestions from the preset rule base, targeted process adjustment suggestions are output.

[0192] For example, if the model identifies that the proportion of particle defects in the core circuit area exceeds 5%, the process adjustment suggestion is as follows: "If the proportion of particle defects in the core circuit area exceeds 5%, it is recommended to optimize the photoresist coating speed to 5 mm / s according to the rule library RQ-101 to reduce particle adsorption."

[0193] 4. Implement process adjustments

[0194] Submit process adjustment suggestions to the process engineer, who will then adjust the corresponding process parameters based on the suggestions. After implementation, monitor the effects of the process adjustments, collect new wafer inspection data, and assess whether the yield has improved.

[0195] 5. Continuous optimization and feedback

[0196] The effects of the implemented process adjustments are fed back into the model to further optimize its predictive capabilities. Through continuous process optimization and model iteration, a dynamic "detection-analysis-optimization" closed loop is formed, continuously improving chip manufacturing yield and quality.

[0197] 6. Documentation and Knowledge Accumulation

[0198] Record the suggestions, implementation process, and effects of each process adjustment to form a knowledge base. Utilize this knowledge to provide a reference for future process optimization, accelerating the development of new processes and the improvement of existing ones. This step achieves process optimization feedback based on yield correlation results, outputting targeted process adjustment suggestions, forming a closed loop of detection-analysis-optimization.

[0199] In some embodiments, this application also discloses a wafer selectivity detection method, referring to... Figure 2 The specific steps are as follows: S201: Obtain the preprocessed image of the wafer to be inspected;

[0200] In some embodiments, the wafer is a wafer manufactured using a process of 7nm or below;

[0201] In some embodiments, step 201 includes: acquiring raw wafer defect data, including wafer surface images (5000×5000 pixels resolution, covering 7nm process logic wafers, containing 20 typical defects) obtained by scanning electron microscopy (SEM). The input SEM images are then subjected to the same preprocessing operations as during training, including denoising, contrast enhancement, and ROI extraction, to ensure that the input data received by the model is in a consistent format.

[0202] S202: Divide the wafer image to be inspected into multiple grid units; for example, divide it using a single die as the basic unit. Each die is considered a grid unit. Alternatively, a single die can be further divided into smaller, regular grids, such as a preliminary grid array of 100x100 or 500x500.

[0203] S203: Perform a coarse-grained defect pre-scan on the wafer image to identify the preliminary defect type and spatial distribution. The spatial distribution includes the distribution range and the functional importance region. The distribution range is the size of the physical area spanned by the defect on the wafer surface and the number of grid cells it covers. The functional importance region is the importance level of the circuit functional area corresponding to the location of the defect.

[0204] In one specific embodiment, the pre-scanning process is performed by a lightweight deep learning model or a highly optimized traditional image processing pipeline. For example, a pruned and quantized lightweight convolutional neural network (such as MobileNetV3 or ShuffleNetV2) can be used as the backbone feature extractor, coupled with a Single Shot Detector (SSD) or a fast variant of YOLO as the detection head. The model receives complete or segmented wafer images and outputs the bounding box coordinates and preliminary classification results for each identified defect. The classification here is coarse-grained, aiming to categorize defects into a limited number of broad categories such as particulate contamination, scratches, patches, and metal residues, thereby achieving an optimal balance between speed and accuracy of basic information.

[0205] After identifying the initial type and location of the defect, a quantitative analysis of its spatial distribution is immediately initiated. This analysis mainly revolves around two core dimensions. The first dimension is the distribution range. The system uses the pre-divided sub-chip-level grid from step S202 as a benchmark to calculate the total number of grid cells covered and spanned by the bounding box or pixel-level mask of each defect. This reveals the spatial influence and potential network effects of the defect. For example, a long but narrow scratch may have a small physical area, but because it covers numerous grid cells, its distribution range index will be high, indicating a greater risk.

[0206] Secondly, and more crucially, is the determination of functionally important regions. The system incorporates a functional map associated with the chip design layout. Once a defect is located, its coordinates are quickly mapped onto this digital map, allowing the system to query the corresponding circuit functional area attributes. The system assigns each defect a functional importance level based on its location. For example, defects located in the processor core computing unit or static memory array area are marked as highest priority, while defects located in the blank or filled areas on the chip's periphery are marked as low priority. This step links purely visual defects to the chip's actual function, a key step in achieving accurate yield prediction.

[0207] S204: Based on the initial defect type, a defect type rating is obtained. Step S204 primarily assigns a quantitative risk score or qualitative risk level to the various defects identified in the coarse-grained pre-scan, i.e., the defect type rating. This rating is not based on the apparent morphological characteristics of the defects, but rather integrates prior knowledge and failure analysis experience in the semiconductor manufacturing field. Its fundamental purpose is to pre-determine the inherent probability that different types of defects will lead to chip functional failure.

[0208] In one specific embodiment, this step relies on a pre-generated defect-failure association rule base embedded in the system. This rule base is built based on data mining of a large amount of historical wafer test data and failure analysis reports. Guided by this rule base, the system first classifies all identified preliminary defect types into risk categories. For example, they are divided into two basic categories: "Category I defects" and "Category II defects." Category I defects typically refer to defect types that have a direct and strong causal relationship with chip failure, such as "circuit breaks" that cause physical circuit disconnections, "bridging defects" that cause short circuits between different circuit nodes, and "via defects" that block interconnects. Once these defects occur, they almost inevitably lead to the loss of function of the circuit they are associated with, and are therefore given the highest risk rating. Category II defects, on the other hand, refer to defect types that have a conditional association with chip failure. Whether they ultimately lead to failure depends heavily on their specific physical parameters and the environment in which they occur. Common Category II defects include "particulate contamination," "surface contamination," "shallow scratches," and "micro-protrusions." For these defects, their initial risk rating is usually lower than that of Category I defects. In addition, more refined evaluation logic can be initiated. For example, the final rating of a "particulate contamination" defect will be dynamically adjusted based on its composition (whether it is a conductive particle) and size (whether it is sufficient to cause a short circuit or open circuit).

[0209] The final step, S204, outputs a comprehensive defect type rating for each identified defect. This rating can be a discrete level label (such as "high," "medium," or "low") or a quantified score.

[0210] S205: Obtain the yield correlation rating based on the defect type rating and the spatial distribution, including: assigning a basic weight score to the defect type rating; performing weighted adjustment on the basic weight score based on the spatial distribution; mapping the score after weighted adjustment to a predefined yield correlation rating.

[0211] Step S205 is the core decision-making link, and its task is to comprehensively consider the internal risk of the defect (defect type rating) and the external impact (spatial distribution), and calculate a final yield correlation rating for each defect that can directly guide subsequent analysis resources.

[0212] In a specific embodiment, step S205 starts with assigning a basic weight score to the defect type rating from step S204. This basic score reflects the inherent risk level of this type of defect in isolation. A scoring mapping table is preset inside the system. For example, a critical defect (such as a circuit break) classified as a "type I defect" will obtain a relatively high basic score (such as 80 points). And a conditional defect (such as particle contamination) classified as a "type II defect" will obtain a medium basic score (such as 50 points), leaving room for subsequent score adjustment by combining other factors. This design ensures that the innate severity of the defect occupies a fundamental weight in the decision-making.

[0213] After establishing the basic score, the system then enters the dynamic weighted adjustment stage based on the spatial distribution. This stage is the key to refined decision-making, aiming to correct the basic score from two independent but complementary dimensions. The first dimension is the distribution range, and the system adds points according to the number of grid cells covered by the defect. The more grid cells covered, the wider the impact range of the defect and the stronger its potential destructiveness. For example: if the number of covered grid cells exceeds N1, add 20 points; between N2 and N1 (N2 < N1), add 10 points, and if less than N2, add 5 points. The second dimension is the functional importance. The system performs strong weighting according to the functional importance level of the location where the defect is located. Defects located in key areas such as the CPU core and SRAM storage array will have their harmfulness significantly amplified, so a weight addition of up to 30 points may be triggered; located in secondary functional areas (such as buffer areas), add 10 points, and located in non-functional / blank areas, no points are added. The weighted scores based on the above two dimensions will be added to the basic weight score to generate a comprehensive score.

[0214] Then, through a mapping mechanism, the calculated comprehensive score is converted into the final operational instruction—the yield correlation rating. The system presets clear score range thresholds. For example, a comprehensive score of 80 or higher is mapped to a "high" yield correlation rating; a score between 60 and 80 is mapped to a "medium" rating; and a score below 60 is mapped to a "low" rating.

[0215] S206: Select whether to perform yield analysis based on the yield correlation rating results.

[0216] The purpose of step S206 is to dynamically and hierarchically allocate computing resources based on the yield correlation rating generated in step S205, thereby achieving accurate and efficient in-depth analysis of defects. This on-demand allocation mechanism ensures that valuable computing resources are prioritized for analyzing defects that pose the greatest threat to chip yield, thus maximizing computational efficiency while ensuring analytical accuracy.

[0217] In one specific embodiment, the system internally pre-loads one or more pre-trained defect yield correlation models of varying complexity. For defects rated as having "high" yield correlation, the system will invoke an end-to-end dual-task deep learning model based on GNN. This model will simulate the spatial interaction and influence transmission of defects based on the constructed wafer defect correlation map, and ultimately output the quantitative yield loss weight caused by the defect (or combination of defects), thereby providing the most direct data support for process optimization.

[0218] For defects rated as having a "medium" yield correlation, considering their manageable risk and potentially large number, the system will invoke a simplified model. This model can be a lightweight variant of the full model, such as a distillation-based lightweight model for the aforementioned GNN-based end-to-end dual-task deep learning model. Its task is to quickly and accurately classify and locate defects and estimate their approximate yield impact, but it no longer performs complex spatial relationship reasoning. This strategy significantly saves computation time while meeting basic analytical needs.

[0219] For defects rated as having "low" yield correlation, the system adopts the most economical processing strategy. These defects are typically isolated points with minimal impact on yield or minor anomalies located in non-functional areas. The system does not invoke any complex pre-trained models for in-depth analysis, but only records their location and coarse classification results for later statistical queries. This approach avoids wasting computational resources on a large number of noisy defects, thereby improving the overall system throughput.

[0220] In some embodiments, this application also discloses a wafer yield analysis model screening method, referring to... Figure 3 The specific steps are as follows:

[0221] S301: Construct a training dataset, which includes preprocessed wafer defect images and wafer normalized yield data.

[0222] S302: Defect classification is performed on the preprocessed wafer defect image using a defect classification model. The defect classification model includes: a defect feature extraction module, which extracts defect feature vectors from the preprocessed wafer defect image; and a defect classification module, which classifies the defect type based on the defect feature vectors extracted by the defect feature extraction module.

[0223] S303: Divide the wafer surface into grid cells, and construct a yield correlation analysis model based on graph neural network with grid cells as nodes and spatial or functional relationships between grid cells as edges. The characteristics of each grid cell include defect type, defect number and defect area ratio.

[0224] S304: Set at least two grid cell partitioning schemes to obtain at least two yield correlation analysis models, construct a yield loss function using wafer normalized yield data, and train at least two yield correlation analysis models using the yield loss function respectively. After training, obtain the training efficiency data corresponding to at least two yield correlation analysis models.

[0225] In one specific embodiment, to determine the optimal mesh partitioning scheme, this application first needs to set up a set of candidate schemes and perform pre-training and evaluation. Specifically, this application predefines at least two different mesh cell partitioning schemes, such as a coarse-grained scheme (e.g., dividing each die into a 10x10 mesh) and a fine-grained scheme (e.g., dividing into a 100x100 mesh). Each partitioning scheme corresponds to a unique graph structure used to construct an independent yield correlation analysis model.

[0226] After the model construction is completed, this application enters the training phase. Using a pre-prepared training dataset containing wafer defect images and corresponding yield labels, this application trains at least two yield correlation analysis models in parallel. The core objective of the training can be to minimize the yield loss function of each model, which is typically expressed as mean squared error, etc., to measure the difference between the model's predicted yield and the actual yield. Through iterative optimization, each model learns the defect-yield correlation under its specific grid division.

[0227] After all models have completed training, this application systematically acquires and records the training efficiency data for each model. The training efficiency data mainly includes two aspects: first, model training time, which is the total time consumed from the start of training to model convergence; and second, model computational complexity, which quantifies the total computational resources consumed to complete the entire training process, typically measured by the total number of floating-point operations performed during training. This efficiency data will provide crucial quantitative basis for subsequent comprehensive evaluation and selection of the optimal solution.

[0228] In a specific embodiment, the training efficiency score is as follows:

[0229] ;

[0230] Wherein, λ1 and λ2 are preset hyperparameters. In this application, λ1 is set to 0.3 and λ2 is set to 0.7, thus favoring the selection of grid partitioning schemes with smaller single inference computation and lower hardware computing power requirements, even if their training time may be slightly longer. This configuration is beneficial to reducing long-term deployment costs and hardware barriers; T is the model training time score; C is the model computational complexity score based on the number of floating-point operations.

[0231] Model training time score T: refers to the total time consumed by the model from the start of training until convergence.

[0232] ;

[0233] in, This indicates the moment when the model converges. This indicates the moment when the model begins training.

[0234] Model computational complexity score C: Here, C specifically refers to the computational complexity of the model during the inference phase. It measures the computational resources required to perform a complete defect classification and yield correlation analysis on a single unknown wafer image using a trained yield correlation analysis model, typically measured in floating-point operations per inference iteration (Inference FLOPs).

[0235] ;

[0236] In one specific embodiment, this application provides two targeted technical paths for determining the grid cell partitioning scheme: a uniform partitioning scheme and a non-uniform partitioning scheme. The uniform partitioning scheme uses a uniform grid granularity to partition the entire wafer surface. Its advantages are uniformity, ease of implementation, and suitability for chip types with relatively uniform circuit layout.

[0237] The non-uniform partitioning scheme is a more complex and refined partitioning strategy. Its core lies in its adaptive partitioning based on the wafer's circuit layout, rather than a uniform partitioning standard. Specifically, in the core functional areas of the chip, such as CPU / GPU computing units and cache areas—critical regions highly sensitive to defects—the system automatically adopts a finer mesh granularity. This refined partitioning can capture smaller defects and more accurately analyze their potential impact on yield. Conversely, in non-core functional areas of the wafer, such as edge blank areas or redundant circuit areas with less impact on performance, the system uses a relatively coarser mesh granularity. The advantage of this approach is that it can significantly reduce the number of nodes and edges in the entire graph structure while maintaining the analysis accuracy of core areas, thereby effectively controlling the computational complexity of the model and improving overall training and inference efficiency. Through this non-uniform partitioning strategy based on focused analysis of key areas, this application achieves an optimal balance between computational resources and analysis accuracy.

[0238] S305: Use the validation set to verify the accuracy of at least two completed yield correlation analysis models to obtain accuracy data corresponding to at least two yield correlation analysis models;

[0239] After the model training phase is completed, this application proceeds to the accuracy verification stage. The purpose of this step is to objectively evaluate the generalization ability and prediction accuracy of the models obtained under different mesh partitioning schemes. This application utilizes a validation set independent of the training set and with real-label data to systematically test at least two previously trained yield correlation analysis models. Wafer defect data from the validation set are sequentially input into each trained model, allowing the model to output its predicted yield value. Subsequently, this application precisely compares these predicted values ​​with the known real yield values ​​in the validation set. The predictive performance of each model is quantified by calculating predefined accuracy evaluation metrics (such as mean squared error (MSE) or coefficient of determination (R²).

[0240] S306: Use training efficiency data and accuracy data to screen at least two completed yield correlation analysis models to obtain the final yield correlation analysis model.

[0241] In one specific embodiment, the training efficiency data and accuracy data are weighted and scored to obtain a comprehensive score. The yield correlation analysis model with the highest comprehensive score is selected as the final yield correlation analysis model. The comprehensive score is as follows:

[0242] ;

[0243] Where S represents the overall score; A represents the training efficiency score; E represents the accuracy score; w a and wb w is the preset weighting coefficient. a ∈[0,1],w b ∈[0,1], in this application, w is set a =0.3, w b The assignment strategy of setting the value to 0.7 takes into account the efficiency of training and inference while ensuring the accuracy of model prediction. This allows us to select the yield correlation analysis model with the highest comprehensive score from all candidate models as the final version to be used in the actual production environment.

[0244] The above embodiments provide a mechanism for filtering the mesh partitioning granularity in a graph neural network model. By filtering the mesh partitioning granularity, a balance between analytical accuracy and computational efficiency can be achieved to a certain extent. That is, by filtering the partitioning granularity from both training efficiency and training accuracy dimensions, suitable partitioning schemes can be selected for different types of wafer products. Furthermore, this filtering mechanism, while improving the reliability of the partitioning granularity, avoids situations where inappropriate partitioning granularity leads to excessively large (or unsuitable) nodes or edges in the graph neural network, resulting in exponential growth in computational resource requirements and making deployment difficult under the time-sensitive requirements of actual production lines.

[0245] Further reference Figure 4 As an implementation of the aforementioned method for co-predicting wafer defects and yield, this application provides an embodiment of a co-predicting wafer defect and yield system. This embodiment is similar to... Figure 1 Corresponding to the method embodiments shown, this device can be specifically applied to various electronic devices.

[0246] refer to Figure 4A wafer defect and yield co-prediction system includes: a dataset construction module 110 configured to construct a training dataset, the training dataset including preprocessed wafer defect images and wafer normalized yield data; a dual-task deep learning model construction module 120 configured to construct a dual-task deep learning model, the dual-task deep learning model including: a defect feature extraction module, the defect feature extraction module extracting defect feature vectors from the preprocessed wafer defect images using channel attention and spatial attention mechanisms; a defect classification module, classifying defect types based on the defect feature vectors output by the defect feature extraction module; a yield correlation analysis module, dividing the wafer surface into grid cells based on a graph neural network to construct a defect-yield correlation graph, and outputting the yield loss corresponding to each type of defect or defect combination by learning the spatial distribution and interaction of defects; and a defect and yield output module 130 configured to construct a loss function using wafer normalized yield data, and train the dual-task deep learning model using the loss function, then inputting the image of the wafer to be detected into the trained dual-task deep learning model, and outputting the defect classification result and the corresponding yield loss.

[0247] Further reference Figure 5 As an implementation of the above-mentioned wafer selective inspection method, this application provides an embodiment of a wafer selective inspection system, which is similar to... Figure 2 Corresponding to the method embodiments shown, this device can be specifically applied to various electronic devices.

[0248] refer to Figure 5A wafer selective inspection system includes: an image acquisition module 210 configured to acquire a preprocessed image of a wafer to be inspected; a mesh division module 220 configured to divide the image of the wafer to be inspected into multiple mesh units; a pre-scanning module 230 configured to perform a coarse-grained defect pre-scan on the image of the wafer to be inspected, identifying preliminary defect types and spatial distribution; the spatial distribution includes the distribution range and functional importance regions, the distribution range being the size of the physical area spanned by the defect on the wafer surface and the number of mesh units covered, and the functional importance region being the importance level of the circuit functional area corresponding to the location of the defect; a defect type rating module 240 configured to perform a rating based on the preliminary defect type to obtain a defect type rating; and a yield correlation rating module 250 configured to perform a rating based on the yield correlation. The yield correlation rating is obtained based on defect type rating and spatial distribution, including: assigning a basic weight score to the defect type rating; adjusting the basic weight score based on spatial distribution; mapping the weighted score to a predefined yield correlation rating; and a yield analysis module 260 configured to select whether to perform yield analysis based on the yield correlation rating result, including: the yield correlation rating result includes three levels: high, medium, and low; if the yield correlation rating result is high, a pre-trained defect yield correlation model is called for yield analysis; if the yield correlation rating result is medium, a pre-trained lightweight model is called for yield analysis, the pre-trained lightweight model being obtained by distillation of the pre-trained defect yield correlation model; and if the yield correlation rating result is low, no yield analysis is performed.

[0249] Further reference Figure 6 As an implementation of the above-mentioned wafer yield analysis model screening method, this application provides an embodiment of a wafer yield analysis model screening system, which is similar to... Figure 3 Corresponding to the method embodiments shown, the system can be specifically applied to various electronic devices.

[0250] refer to Figure 6A wafer yield analysis model screening system includes: a dataset construction module 310 configured to construct a training dataset, which includes preprocessed wafer defect images and normalized wafer yield data; a defect classification module 320 configured to classify defects in the preprocessed wafer defect images using a defect classification model, the defect classification model including: a defect feature extraction module, which extracts defect feature vectors from the preprocessed wafer defect images; and a defect classification module, which classifies defect types based on the defect feature vectors; and a yield correlation analysis model construction module 330 configured to divide the wafer surface into grid cells and construct a yield correlation analysis model based on a graph neural network, with grid cells as nodes and spatial or functional relationships between grid cells as edges, wherein the features of each grid cell include defects. The model includes: a type, number of defects, and defect area ratio; a training efficiency data acquisition module 340, configured to set at least two grid cell partitioning schemes to obtain at least two yield correlation analysis models, construct a yield loss function using wafer normalized yield data, and train at least two yield correlation analysis models using the yield loss function respectively, and obtain training efficiency data corresponding to at least two yield correlation analysis models after training; an accuracy data acquisition module 350, configured to use a validation set to verify the accuracy of at least two trained yield correlation analysis models to obtain accuracy data corresponding to at least two yield correlation analysis models; and a model selection module 360, configured to use training efficiency data and accuracy data to select at least two trained yield correlation analysis models to obtain the final yield correlation analysis model.

[0251] In another aspect, this application also provides a computer-readable storage medium, which may be included in the electronic device described in the above embodiments; or it may exist independently and not assembled into the electronic device. The aforementioned computer-readable storage medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to perform the following... Figure 1The methods shown above. Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a computer terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention. The embodiments of the present invention have been described above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art, under the guidance of the present invention, can make many other forms without departing from the spirit and scope of the claims, and these all fall within the protection scope of the present invention.

Claims

1. A wafer defect and yield co-forecasting method, characterized in that, The method comprises the following steps: constructing a training data set comprising pre-processed wafer defect images and wafer normalized yield data; constructing a dual-task deep learning model comprising: a defect feature extraction module that extracts a defect feature vector from the pre-processed wafer defect image using a channel attention mechanism and a spatial attention mechanism; a defect classification module that classifies defect types based on the defect feature vector output by the defect feature extraction module; a yield correlation analysis module that divides the wafer surface into grid cells based on a graph neural network to construct a defect yield correlation graph and outputs a yield loss corresponding to each type of defect or defect combination by learning the spatial distribution and interaction of defects; using wafer normalized yield data to construct a loss function and training the dual-task deep learning model using the loss function, and then inputting the image of the wafer to be detected into the trained dual-task deep learning model to output a defect classification result and a corresponding yield loss; wherein dividing the wafer surface into grid cells based on a graph neural network to construct a defect yield correlation graph comprises: dividing the wafer surface into M×N grid cells, each grid cell serving as a node in the graph, and the features of each node including defect type one-hot encoding, defect quantity, and defect area proportion in the grid cell; the connection of edges in the graph neural network is based on the spatial proximity and circuit function relationship between grid cells, and each edge is assigned a weight determined by the distance between grid cells and / or circuit function correlation, thereby increasing the weight of key defects.

2. The method of claim 1, wherein the method further comprises: The processing flow of the channel attention mechanism is as follows: initial feature extraction of the pre-processed wafer defect image is performed using an initial convolutional layer to obtain an initial feature map; global average pooling is performed on each channel of the initial feature map to obtain global features; the global features are transformed through a fully connected layer to obtain channel attention weights; the channel attention weights are multiplied by each channel of the initial feature map to obtain a weighted feature map.

3. The method of claim 2, wherein the method further comprises: The processing flow of the spatial attention mechanism is as follows: global maximum pooling and global average pooling are performed on the weighted feature map; the results of global maximum pooling and global average pooling are concatenated in the channel dimension to form a concatenated feature representation; the concatenated feature representation is input into a convolutional layer to extract spatial correlation information; an activation function is used to process the output of the convolutional layer to generate spatial attention weights; the generated spatial attention weights are multiplied element by element with the weighted feature map to obtain the final defect feature vector.

4. The method of claim 1, wherein the method further comprises: The method further comprises the following steps: updating the features of the nodes using a graph attention mechanism, including: calculating the attention coefficients of each node for its neighbor nodes; using the attention coefficients to weight and aggregate the features of the neighbor nodes to update the features of the nodes.

5. The wafer defect and yield co-prediction method according to any one of claims 1-4, characterized in that: the dual-task deep learning model is trained using a hybrid loss function, and the hybrid loss function is specifically: L total = α x L1+ β x L2; ； ； wherein L total is a hybrid loss function; L1 is a defect classification loss; L2 is a yield correlation loss; N is the number of classes of defect types, is the actual defect type, is the defect type probability predicted by the model; M is the number of samples, is the yield loss calculated by the model, is the real yield loss in actual production; and α and β are preset hyperparameters.

6. The method of claim 1-4, wherein, the method further comprises the following steps: Based on the defect classification result and the yield loss output by the dual-task deep learning model, an optimization adjustment suggestion for the front-end manufacturing process is generated according to a preset rule base.

7. The method of claim 1-4, wherein the method further comprises: Further comprising the steps of: Based on the defect classification result and the yield loss output by the dual-task deep learning model, a yield risk value is assigned to each grid cell, and the yield risk value is mapped to the corresponding color by using a heat map drawing tool to generate a heat map.

8. The method of claim 1-4, wherein: The wafer is a wafer of 7nm and below process.

9. A wafer defect and yield co-forecasting system, comprising: The system comprises: A data set construction module configured to construct a training data set, the training data set comprising pre-processed wafer defect images and wafer normalized yield data; A dual-task deep learning model construction module configured to construct a dual-task deep learning model, the dual-task deep learning model comprising: A defect feature extraction module that extracts a defect feature vector from the pre-processed wafer defect image using a channel attention mechanism and a spatial attention mechanism; A defect classification module that classifies defect types based on the defect feature vector output by the defect feature extraction module; A yield correlation analysis module that divides the wafer surface into grid cells based on a graph neural network to construct a defect yield correlation graph, and outputs a yield loss corresponding to each type of defect or defect combination by learning the spatial distribution and interaction of defects; The wafer surface is divided into MxN grid cells, each grid cell is a node in the graph, and the features of each node include: defect type one-hot encoding, defect quantity and defect area proportion in the grid cell; The connection of edges in the graph neural network is based on the spatial proximity relationship and circuit function relationship between grid cells, and each edge is assigned a weight, which is determined by the distance and / or circuit function correlation between grid cells, thereby increasing the weight of key defects; A defect and yield output module configured to construct a loss function using wafer normalized yield data, and train the dual-task deep learning model using the loss function, and then input the image of the wafer to be detected into the trained dual-task deep learning model to output the defect classification result and the corresponding yield loss. ​

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