A semiconductor device and a manufacturing method

Abstract

The application provides a semiconductor device and a manufacturing method, and relates to the technical field of semiconductors. It is found that, after a groove structure is formed on a long polysilicon channel, a high-aspect-ratio region with a very high aspect ratio is formed in a shoulder area of the groove structure during a re-etching process of the sidewall oxide layer on both sides of the groove structure. The aspect ratio of the high-aspect-ratio region is far beyond the working range of a high-density plasma oxide deposition process, so that the oxide filling structure formed in the groove structure based on the high-density plasma oxide deposition process may have a bubble defect, which affects the performance of the device. In view of this situation, the oxide interface and the polysilicon interface in the groove structure are adjusted to be flush before the high-density plasma oxide deposition process is performed, so that the high-aspect-ratio region is eliminated, the aspect ratio of the groove structure meets the working range of the high-density plasma oxide deposition process, and then a dense oxide filling structure is formed, which guarantees the electrical isolation performance.

Description

Technical Field

[0001] This application relates to semiconductor technology, specifically to a semiconductor device and its manufacturing method. Background Technology

[0002] With the continuous development of power electronics technology towards higher efficiency, higher power density, and higher switching speed, semiconductor devices have undergone a major technological revolution from planar gates to trench gates. The trench gate structure, by embedding the gate in the form of a trench inside the semiconductor to construct a vertical conductive channel, greatly increases the cell density and effectively reduces the on-resistance, becoming a key technology for mainstream power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors, hereinafter referred to as MOS) and IGBTs (Insulated Gate Bipolar Transistors).

[0003] Specifically, in the cellular region of a device, to achieve the lowest possible on-resistance and the highest possible current density, the gate structure is typically designed / formed during fabrication as a "continuous trench" that runs through a row or column of cells. That is, the gate structure often exhibits a polysilicon channel running through multiple cells and sidewall oxide layers on both sides during fabrication.

[0004] In the subsequent fabrication of cells (such as forming control gates, forming inter-cell isolation structures, etc.), the aforementioned polysilicon channels often need to be locally processed (such as local etching and local filling). Due to the difference between the polysilicon channel and the sidewall oxide layer, local processing of the polysilicon channel may lead to the formation of defects (voids) near the polysilicon channel, which may seriously affect the performance of semiconductor devices, especially defects that appear near the junction of the terminal region and the cell region.

[0005] Therefore, optimizing the fabrication process of polycrystalline silicon channels is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] In view of this, embodiments of this application provide a semiconductor device and manufacturing method. To address the problem of shoulder defects that easily occur when forming grooves in long polysilicon channels, an additional interface adjustment process is added to reduce the depth-to-width ratio of the grooves and avoid the formation of defects.

[0007] In a first aspect, this application provides a method for fabricating a semiconductor device. The method includes providing a substrate, wherein the substrate includes at least one polysilicon channel and sidewall oxide layers formed on both sides of the polysilicon channel, the polysilicon channel and the sidewall oxide layers having the same extension direction on the substrate surface; performing a first etching process on at least one local region of the polysilicon channel to form at least one groove structure corresponding to the at least one local region; performing a second etching process on the sidewall oxide layer, thereby causing at least a portion of the groove sidewalls of the groove structure to expand into the sidewall oxide layer, wherein the sidewall oxide layer is etched to form an oxide interface in a first sidewall facing the extension direction in the groove sidewall, the oxide interface extending beyond the polysilicon interface in the first sidewall in the extension direction to form high aspect ratio regions on both sides of the polysilicon interface; adjusting the oxide interface and the polysilicon interface to be flush to eliminate the high aspect ratio regions; and performing a high-density plasma oxide deposition process on the groove structure to form a dense oxide-filled structure within the groove structure.

[0008] In a second aspect, this application provides a semiconductor device, which is manufactured based on the semiconductor device fabrication method described in the first aspect.

[0009] This application discovers that after forming a groove structure on a long polysilicon channel, the etch-back process for the sidewall oxide layer on both sides of the groove structure creates a high aspect ratio region in the shoulder area of ​​the groove structure. This high aspect ratio region far exceeds the operating range of the high-density plasma oxide deposition (HDPD) process, potentially leading to bubble defects in the oxide-filled structure formed within the groove structure based on HDPD, thus affecting device performance. To address this, this application adjusts the oxide interface and polysilicon interface within the groove structure to be flush before performing the HDPD process, eliminating the high aspect ratio region. This ensures that the aspect ratio of the groove structure meets the operating range of the HDPD process, resulting in a dense oxide-filled structure and guaranteeing its electrical isolation performance. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 These are fabrication layouts of semiconductor devices provided in some embodiments of this application.

[0012] Figure 2 This is a schematic diagram of the structure of a substrate with a polysilicon channel provided in some embodiments of this application.

[0013] Figure 3 This is a schematic diagram of the structure after forming the groove structure provided in some embodiments of this application.

[0014] Figure 4 This is an exemplary flowchart of a semiconductor device fabrication method provided in some embodiments of this application.

[0015] Figure 5 This is a schematic diagram of the structure after adjusting the groove structure interface according to some embodiments of this application.

[0016] Figure 6 This is an exemplary flowchart of some embodiments of the present application for adjusting the groove structure based on a high aspect ratio oxide filling process.

[0017] Figure 7 This is a schematic diagram of a groove structure with an oxide-filled layer provided in some embodiments of this application.

[0018] Figure 8 This is an exemplary flowchart of a method for determining etching process execution parameters provided in some embodiments of this application.

[0019] Figure 9 This is a schematic diagram of the temporal variation of deposition parameters in a high-density plasma oxide deposition process provided in some embodiments of this application.

[0020] Among them, 100 is a semiconductor device; 110 is a cell region; 120 is a terminal region; 111 is a trench gate; 112 is a source region; 113 is a drain region; 114 is an isolation grid; 210 is a polysilicon channel; 220 is a sidewall oxide layer; 230 is a groove structure; 231 is a first sidewall; 232 is a second sidewall; 2311 is a polysilicon interface; 2312 is an oxide interface; 240 is a high aspect ratio region; and 250 is an oxide filling layer. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0023] In this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0024] Application Overview:

[0025] To further illustrate the technical problems described in the aforementioned "Background Art", this application also provides an exemplary layout of a semiconductor device ( Figure 1 ).like Figure 1 As shown, the semiconductor device 100 may include a cell region 110 and a terminal region 120, wherein the cell region 110 is located in the middle of the semiconductor device 100, and the terminal region 120 is disposed around the cell region 110.

[0026] Cell region 110, also known as the active region, is the core operating area of ​​the device. It is composed of cells arranged in a tightly connected array. Each cell is a complete semiconductor unit (such as an SGT MOS cell). Termination region 120 is located at the outermost edge of cell region 110. Its main function is to withstand and dissipate the high electric field at the chip edge when the device is in the off state, thereby protecting the active device in cell region 110 and preventing it from premature breakdown under high drain-source voltage.

[0027] Within the cell region 110, the individual cells of the semiconductor device 100 are typically arranged in a pure array to function as repeating and fully functional individuals. However, to optimize performance (such as current carrying capacity, heat distribution, and reliability), they are connected in parallel to form an array.

[0028] Taking a row of cells in a MOS unit as an example, based on the aforementioned trench gate, the semiconductor device 100 in the cell region 110 may include multiple rows of trench gates 111, source regions 112 and drain regions 113 formed on both sides of the trench gates 111 respectively, and isolation grids 114 for separating each cell.

[0029] In actual fabrication, the aforementioned source region 112 and drain region 113, or other internal structures, are generally formed within the corresponding cells using conventional semiconductor processes (such as doping and etching processes based on mask layers, etc.) (e.g., formed by doping a silicon substrate). However, based on the aforementioned trench gate technology, when forming the trench gate 111 and isolation grid 114, it is often necessary to first form channels spanning each cell and isolation structures between rows of cells (i.e., the lateral portion of the isolation grid 114), then fill the channels with polysilicon to form polysilicon channels and other related structures (such as oxide layers on the sidewalls of the polysilicon channels), and then form the trench gate 111 based on the polysilicon channels. Finally, based on the formed trench gate 111, an isolation structure between rows of cells (i.e., the vertical portion of the isolation grid 114) is formed.

[0030] Based on the aforementioned fabrication process of the trench gate 111, its actual fabrication process or subsequent processes often involve etching and backfilling of the polysilicon channel. For example, in an SGT MOS, its gate structure can be presented as a stacked shield gate and control gate. After forming the polysilicon channel, it is necessary to etch the polysilicon channel to leave the remaining portion of the polysilicon channel in the depth direction and configure it as a shield gate. Then, oxide dielectric and polysilicon are sequentially filled on top to form an inter-gate isolation dielectric layer and a control gate. As another example, at the location of the polysilicon channel between cells, etching can be performed to remove the polysilicon and then oxide can be backfilled to form an inter-cell isolation structure (i.e., the longitudinal portion of the aforementioned isolation grille 114).

[0031] The aforementioned processes often involve etching polysilicon and backfilling oxides. However, considering that the backfilled oxides often require electrical isolation, there is a requirement for structural density. This is generally achieved using a high-density plasma (HDP) oxide deposition process (hereinafter referred to as HDP process).

[0032] HDP (High-density Plasma) refers to a plasma-assisted deposition process. For example, plasma can be released during oxide deposition or during the deposition of an oxide layer of a certain thickness. Based on plasma assistance (generally manifested as bombardment of the deposition surface), residual moisture and other defects causing non-density in the oxide filler can be removed, thereby achieving a higher fill density (i.e., better compactness).

[0033] However, the aspect ratio (AR) that the HDP process can accommodate is relatively limited. AR = Depth / Width of the structure. The HDP process often accommodates a relatively small AR; when the AR is large, performing the HDP process can easily result in bubble defects. Currently, its maximum adaptable AR is generally around 6 (with a limit of around 9).

[0034] With advancements in semiconductor device manufacturing processes and the development of trench gate technology, trench gates in semiconductor devices often possess a small surface area but a large depth. Etching the polysilicon channel alone often fails to meet the AR (Advanced Radiation Protection) requirements of HDPs (High-Density Packaging). Therefore, etching the surrounding structures of the polysilicon channel (such as the sidewall oxide layer) is necessary to expand the AR of the area to be filled, thus meeting the AR requirements of HDPs.

[0035] However, considering that polysilicon etching is often done using dry etching, it cannot simultaneously etch the surrounding silicon oxide structure, requiring wet etching to re-etch the silicon oxide. Given that the extension of polysilicon channels spans multiple cells, the etching of the surrounding structure can easily create depressions at the shoulders of the trench structure, forming a high aspect ratio region, further negatively impacting the HDP process (increasing the likelihood of defect formation).

[0036] To further illustrate this situation, this application provides a schematic diagram of the structure of a polysilicon channel after etching, which requires etching and backfilling in semiconductor devices. Figure 2 ) and a schematic diagram of the structure after etching the oxide layers on both sides ( Figure 3 ).in, Figure 2 and Figure 3 Only the local cell regions that need to be etched are displayed.

[0037] like Figure 2 As shown, the local cell region to be etched includes a relatively long polysilicon channel 210 and sidewall oxide layers 220 formed on both sides of the polysilicon channel 210. Given the aforementioned etching requirements, when forming a trench that can be filled using the HDP process, the polysilicon channel 210 can be etched first, and then the sidewall oxide layers 220 can be etched back to reduce the AR (Advanced Residual Aspect) of the trench and meet the requirements of the HDP process.

[0038] Figure 2 This illustrates the situation after a groove structure 230 is formed on the polysilicon channel 210. That is, in Figure 2 In the local cell region shown, only the polysilicon channel 210 is etched to form a groove structure 230. Figure 2 In the process, the etched area of ​​the polysilicon channel 210 appears as a darker color (or a higher fill density fill pattern).

[0039] exist Figure 2 In the groove structure 230, there are a first sidewall 231 and a second sidewall 232. The first sidewall 231 is at the junction with the unetched polysilicon channel 210, and the second sidewall 232 can be the sidewall oxide layer 220 exposed by the groove structure 230.

[0040] The aforementioned groove structure 230 on the polysilicon channel 210 is often formed using a dry etching process. This involves exposing the portion of the trench to be etched through a mask layer, and then removing the polysilicon or a portion of the polysilicon in the trench using dry etching. In the aforementioned example, forming a control gate requires removing a portion of the polysilicon, while forming an inter-cell isolation structure requires removing all of the polysilicon.

[0041] based on Figure 2 In subsequent fabrication, the groove structure 230 shown needs to be laterally expanded (mainly by expanding the second sidewall 232) to reduce the AR of the groove structure 230.

[0042] Specifically, the size of the groove structure 230 can be increased and its AR (Advanced Radiation Protection) reduced by removing the oxide layer on the sidewalls within the groove structure 230 through a wet etching process. The second sidewall 232 exposed in the groove structure 230 will be etched and retracted in the wet etching environment.

[0043] However, considering that the wet etching process is isotropic, during the inward shrinkage of the second sidewall 232, the sidewall oxide layer 220 will gradually be exposed at the first sidewall 231. During the etching process, the sidewall oxide layer 220 exposed at the first sidewall 231 will also be etched, thereby forming a high aspect ratio area at the shoulder of the groove structure 230.

[0044] Specifically, the groove structure 230 formed based on the aforementioned process is in Figure 3 It is shown in the middle.

[0045] like Figure 3 As shown, after the sidewall oxide layer 220 is etched back, the second sidewall 232 extends into the interior of the sidewall oxide layer 220, thereby increasing the size between the second sidewalls 232 to reduce AR. At the first sidewall 231, in addition to the polysilicon interface 2311 that intersects with the polysilicon channel 210, an oxide interface 2312 is also formed due to the inward shrinkage of the aforementioned second sidewall 232.

[0046] Based on the aforementioned etching process, it can be seen that after the oxide interface 2312 is exposed to the etching environment, it will be etched, causing the oxide interface 2312 to cross the polysilicon interface 2311 in the first sidewall 231 in the extension direction of the polysilicon channel 210, and forming a high aspect ratio region 240 on both sides of the polysilicon interface 2311.

[0047] like Figure 3 As shown, the aforementioned high aspect ratio region 240 is formed at the four corners of the groove structure 230, and its surface aperture size is generally the inward dimension of the aforementioned second sidewall 232. For example, taking an SGT MOS as an example, during lateral etching, the etching depth of the sidewall oxide layer 220 can be 1100 Å, and the depth etching depth of the polysilicon channel can be 11000 Å. Based on the aforementioned etching depth, the depth of the high aspect ratio region 240 will also be additionally etched by 1100 Å during its formation. Therefore, the aspect ratio AR = (11000 Å + 1100 Å) / 1100 Å = 11 here is much larger than the normal HDP filling range, which may lead to defects at the filling location of the high aspect ratio region 240.

[0048] Therefore, how to overcome the problem of shoulder defects that easily occur when forming grooves in long polysilicon channels, ensure the density of oxide filling, and improve the reliability of devices (especially avoiding defects caused by the aforementioned situation between the cell region and the terminal region) is a technical problem that urgently needs to be solved by those skilled in the art.

[0049] It should be noted that the aforementioned high aspect ratio region is formed based on the local processing of a long polysilicon channel. This is the cause of the technical problem identified in this application after multiple tests and slice analyses during the actual semiconductor device fabrication process. Significant creative effort was put into identifying this technical problem.

[0050] In response to this situation, before performing the high-density plasma oxide deposition process, this application adjusts the oxide interface and polysilicon interface within the groove structure to make them flush, thereby eliminating areas with high aspect ratios. This ensures that the aspect ratio of the groove structure meets the working range of the high-density plasma oxide deposition process, thus forming a dense oxide-filled structure and guaranteeing its electrical isolation performance.

[0051] To further illustrate the adjustments made to the semiconductor device fabrication method in this application, the following will be combined with... Figures 4-9 The method for fabricating the semiconductor device provided in this application and the structural changes of the semiconductor device during the process are described in detail.

[0052] Exemplary semiconductor device fabrication method:

[0053] To further illustrate the optimization of local processing of polysilicon channels in this application, this application also provides an exemplary flowchart of a semiconductor device fabrication method ( Figure 4 ).

[0054] like Figure 4 As shown, the semiconductor device fabrication method P400 provided in this application may include the following steps:

[0055] S410 provides a substrate.

[0056] S420. Perform a first etching process on at least one local area of ​​the polysilicon channel to remove part of the polysilicon in the local area of ​​the polysilicon channel to form a groove structure.

[0057] S430, Perform a second etching process on the sidewall oxide layer, thereby expanding at least a portion of the trench sidewall of the trench structure into the sidewall oxide layer.

[0058] S440. Align the oxide interface with the polysilicon interface to eliminate high aspect ratio regions.

[0059] S450. A high-density plasma oxide deposition process is performed on the groove structure to form a dense oxide-filled structure within the groove structure.

[0060] In the aforementioned S410, the substrate can refer to a semiconductor substrate with a polysilicon channel and sidewall oxide layer already formed. It is generally a semiconductor device with a trench gate structure, such as a MOS or IGBT. For example, the aforementioned substrate can be a MOSFET formed on a 12-inch wafer.

[0061] Furthermore, based on the technical problem solved by this application, the aforementioned polysilicon channel often connects multiple cells (such as a column or a row of cells) in the substrate, and the sidewall oxide layer extends in the same direction as the polysilicon channel and is disposed on both sides of the polysilicon channel.

[0062] In the aforementioned S420, the local region can refer to the area in the semiconductor device where an etching and backfilling process is required for the polysilicon channel. As mentioned earlier, in the fabrication process of a gate structure based on a shielded gate, the aforementioned polysilicon channel can refer to the untreated shielded gate; therefore, the local region can refer to the area in the gate structure where a control gate needs to be formed. Furthermore, in the fabrication process of the inter-cell isolation structure, the aforementioned local region can reflect the cell interface with the polysilicon channel.

[0063] In some embodiments, the aforementioned localized areas can be exposed and etched through a mask layer. Specifically, during the execution of S420, photoresist can be formed on the substrate surface, and then exposed and developed based on the localized areas to form a mask layer that exposes these areas. By exposing the localized areas through the mask layer, when the substrate is placed in an etching environment, the localized areas are exposed to the etching environment and etched, thereby removing a portion of the polysilicon in the localized areas of the polysilicon channel to form a trench structure.

[0064] In some embodiments, the aforementioned first etching process is generally implemented based on a dry etching process. Polysilicon etching typically employs dry etching with chlorine-based gases, bromine-based gases, or fluorine-based gases to ensure high selectivity (avoiding damage to the underlying gate oxide layer) and good anisotropy (forming vertical sidewalls). Considering the protection of the oxide layer during this process, HBr or SF6 is preferred.

[0065] Similar to the determination of the aforementioned local regions, the amount of polysilicon etched in the polysilicon channel is also related to the structure it forms. For example, when forming an inter-cell isolation structure, it is often necessary to remove all the polysilicon to achieve electrical isolation between cells. As another example, when forming a gate structure with a shielding gate, it is often necessary to retain a portion of the polysilicon as the shielding gate in the gate structure.

[0066] Taking the medium-to-low voltage power device SGT MOS as an example, the width of the polysilicon trench used to form the shielding gate can be about 2000 Å, and the etching depth of the aforementioned first etching process can be 11000 Å. In addition, the width of the sidewall oxide layer can be about 2000 Å.

[0067] In the aforementioned S430, the second etching process can be understood as the re-etching process of the sidewall oxide layer exposed at its second sidewall based on the groove structure on the polysilicon channel. In actual execution, it is generally implemented based on a wet etching process. Among them, the wet etching process for oxides often relies on the hydrofluoric acid (HF) system, which lacks oxidant and hardly etches polysilicon.

[0068] like Figure 3 As shown, exposed in the groove structure (i.e. Figure 3 The sidewall oxide layer of the groove structure 230 in the middle (i.e. Figure 3 The sidewall oxide layer 220, wherein the etched portion is understood as the second sidewall 232 of the trench structure 230, is etched in the trench sidewall toward the polysilicon channel (i.e. Figure 3 An oxide interface (i.e., ...) is formed in the first sidewall of the polysilicon channel 210 in the extension direction. Figure 3 The oxide interface 2312 in the extension direction crosses the polycrystalline silicon interface in the first sidewall (i.e., Figure 3 The polycrystalline silicon interface 2311) forms high aspect ratio regions on both sides of the polycrystalline silicon interface (i.e. Figure 3 The high aspect ratio region (240) in the middle. For the specific formation principle, please refer to the above. Figure 3 The relevant descriptions will not be repeated here.

[0069] As described above, in SGT MOS, the etching amount of the second etching process can be 1100 Å. Then the aspect ratio AR of the high aspect ratio region = (11000 Å + 1100 Å) / 1100 Å = 11 is much larger than the normal HDP filling range.

[0070] In the aforementioned S440, "adjusting the oxide interface and the polysilicon interface to be flush" is a technique used to eliminate the aforementioned high aspect ratio region. Based on the semiconductor device fabrication process and the formation mechanism of the aforementioned high aspect ratio region, the aforementioned process of adjusting the oxide interface and polysilicon interface can be achieved from two aspects: filling and re-etching. Furthermore, in actual implementation, the two can also be combined.

[0071] When using a filler process, the aforementioned high aspect ratio regions can be filled in to make the oxide interface flush with the polysilicon interface. More information on using filler processes to eliminate high aspect ratio regions can be found in [link to relevant documentation]. Figure 6 , 7 Related descriptions.

[0072] When using an etching process, the portion of the polysilicon interface that protrudes relative to the oxide interface can be removed, thus eliminating high aspect ratio regions and making the oxide interface flush with the polysilicon interface. Furthermore, after removing the protruding portion of the polysilicon interface relative to the oxide interface using etching, the first sidewall of the groove structure is often located outside the local area. More information on using etching processes to eliminate high aspect ratio regions and adjusting etching parameters based on this process can be found in [link to relevant documentation]. Figure 8 And its related descriptions.

[0073] To further illustrate the aforementioned elimination of high aspect ratio regions, let's take the infill process as an example, based on the infill process... Figure 3 After the high aspect ratio region of 240 is shown, the semiconductor device can be presented as Figure 5 The structure shown.

[0074] like Figure 5 As shown, both the first sidewall 231 and the second sidewall 232 of the groove structure 230 have a flat morphology. The first sidewall 231 still has an oxide interface 2312 and a polysilicon interface 2311, but the oxide interface 2312 is flush with the polysilicon interface 2311.

[0075] Following the aforementioned etching parameters, after removing the high aspect ratio region 240, the groove structure 230 is... Figure 5 The AR in the semiconductor device shown is approximately 2.9 (11000Å + 1100Å) / (2000Å + 1100Å + 1100Å). This meets the execution requirements of the HDP process. Furthermore, the groove structure without back etching (i.e., Figure 2The AR of the groove structure 230 shown is approximately 5.5 (11000 Å / 2000 Å). This demonstrates that the aforementioned etching process can significantly reduce the AR of the groove structure, further simplifying the HDP process.

[0076] In the aforementioned S450, the oxide dense-filled structure can refer to an oxide-filled structure that has a dense film layer after ion bombardment. To ensure the density of the oxide filling, the high-density plasma oxide deposition process, namely the aforementioned HDP process, often introduces gas at high power during the vapor phase deposition of oxides, using plasma to assist the deposition process and improve the density of the deposited oxide.

[0077] Specifically, the HDP process achieves chemical vapor deposition (CVD) using high-density plasma. The deposition process primarily involves silicon source gas (silicon precursor, such as silane (SiH4)), oxidant, and sputtering gas. The HDP process mainly achieves this by plasma treatment (high-power acceleration) of the sputtering gas, causing gas dissociation and depositing silicon oxide in the target area of ​​the substrate. Simultaneously, the plasma bombards the surface, removing excess material deposited on the interstitial sidewalls and preventing void formation.

[0078] In the aforementioned S450, the HDP process can generally be performed using high bias power. Here, bias power is the power applied through a radio frequency (RF) bias electrode in the semiconductor deposition process, which is used to accelerate ion bombardment of the substrate surface in a plasma environment.

[0079] When a higher bias power is used, the ions gain higher kinetic energy, forming directional deposition. The ions bombard the surface vertically, improving the bottom-filling ability of aspect ratio structures, especially at the bottom of deeper trenches.

[0080] For example, H2 can be used as the sputtering gas and the aforementioned HDP process can be performed with high bias power (e.g., 9000W) to achieve oxide backfilling of the groove structure.

[0081] In some embodiments, this application has found that prolonged HDP filling under high bias power may affect the equipment hardware, damaging the dome top nozzle and potentially leading to wafer defects (such as particle contamination or deterioration of the filled film caused by the aforementioned nozzle damage). To overcome this problem, this application proposes segmented filling during HDP processing, as detailed in [reference needed]. Figure 9 And its related descriptions.

[0082] After forming a dense oxide-filled structure using the aforementioned HDP process, further processing can be performed based on the specific structure formed. For example, for a gate structure with a shielding gate, the aforementioned polysilicon channel is formed in the cell region of the semiconductor device, so that the etched polysilicon channel is configured as the shielding gate of each semiconductor cell. To form a control gate, after forming the oxide-filled structure, a control gate can also be formed within the oxide-filled structure. In this case, the oxide-filled structure is formed within each semiconductor cell and configured as the inter-gate isolation dielectric layer between the shielding gate and the control gate in the corresponding semiconductor cell. Thus, the inter-gate isolation dielectric layer between the shielding gate and the control gate can be formed by the oxide-filled structure, ensuring electrical isolation between the shielding gate and the control gate.

[0083] In addition, the aforementioned oxide dense-filled structure can also be directly configured as an inter-cell isolation structure to separate the gate structures of each cell.

[0084] Therefore, this application found that the etch-back process for the sidewall oxide layer on both sides of the groove structure will form a high aspect ratio region with an extremely high aspect ratio in the shoulder area of ​​the groove structure. The aspect ratio of this high aspect ratio region is far beyond the working range of the high-density plasma oxide deposition process, which may cause the oxide filling structure formed in the groove structure based on the high-density plasma oxide deposition process to have bubble defects, affecting the device performance.

[0085] In response to this situation, the semiconductor device fabrication method P400 provided in this application can adjust the oxide interface and polysilicon interface in the groove structure before performing the high-density plasma oxide deposition process, so as to make them flush to eliminate the high aspect ratio region, and make the aspect ratio of the groove structure meet the working range of the high-density plasma oxide deposition process, thereby forming a dense oxide-filled structure and ensuring its electrical isolation performance.

[0086] Exemplary method for eliminating high aspect ratio regions:

[0087] To further illustrate the processing of high aspect ratio regions in the aforementioned fabrication method, this application describes in detail the methods for eliminating high aspect ratio regions based on two approaches: filling and etching. Among them, Figure 6 , Figure 7 This can reflect the method of eliminating areas with high aspect ratios by using a filling process. Figure 8 The descriptions and related information can reflect the method and parameter configuration process for eliminating high aspect ratio regions using re-etching technology.

[0088] Following the preceding discussion on using filling processes to eliminate high aspect ratio regions, alternative filling processes can be employed to fill these regions before performing high-density plasma oxide deposition (HDPD). Furthermore, considering the high aspect ratio (AR) characteristics of these regions, filling them can be achieved using a High Aspect Ratio Process (HARP). This involves performing a HARP process on the groove structure to fill the high aspect ratio regions with oxide, thus leveling them.

[0089] The HARP process is a non-plasma vapor deposition process based on the thermochemical reaction of ozone (O3) and tetraethyl orthosilicate (TEOS), which can currently fill trenches with an aspect ratio (AR) of 7:1 to 12:1. In the aforementioned example, the AR of the high aspect ratio region meets the requirements of the HARP process, thus enabling the filling of the high aspect ratio region.

[0090] Furthermore, it should be noted that with the advancement of semiconductor technology, the aforementioned high aspect ratio region can also be achieved by other oxide deposition techniques capable of filling high AR depressions.

[0091] Furthermore, to ensure complete filling of the high aspect ratio region, the filling amount of the aforementioned HARP process can be greater than the size of the high aspect ratio region, so that the oxide layer portion filled by the HARP process enters the aforementioned local region.

[0092] Figure 6 This is an exemplary flowchart of some embodiments of the present application for adjusting the groove structure based on a high aspect ratio oxide filling process.

[0093] like Figure 6 As shown, process P600 may include the following steps:

[0094] S610: Perform a high aspect ratio oxide filling process to form an oxide filling layer within the groove structure.

[0095] S620, Perform a third etching process on the oxide-filled layer to expose the polysilicon interface.

[0096] In the aforementioned S610, the oxide filling layer can refer to the oxide structure formed within the groove structure by a high aspect ratio oxide filling process. Based on the aforementioned filling requirement of the high aspect ratio region, the oxide filling layer at least fills the high aspect ratio region.

[0097] Considering that the HARP process typically fills all sidewalls of the groove structure simultaneously during filling, after filling the aforementioned high aspect ratio region, an oxide filler layer will also form on the polysilicon interface and the second sidewall of the groove structure. Therefore, a certain thickness of oxide filler layer will be deposited on the polysilicon interface in this step. When etching is repeated, this filler layer will be preferentially etched, preventing further etching. Figure 2 → Figure 3 Similar defects in the process.

[0098] To further illustrate this point, this application also provides a schematic diagram of a semiconductor device having an oxide-filled layer formed on it. Figure 7 ).in, Figure 7 The semiconductor device shown can reflect Figure 3 The semiconductor device shown is after being processed by the aforementioned S610.

[0099] like Figure 7 As shown, the oxide filling layer 250 can fill the high aspect ratio region 240. In addition to filling the aforementioned high aspect ratio region 240, the oxide filling layer 250 also deposits a certain thickness on the second sidewall 232 and the polysilicon interface 2311.

[0100] Considering that the high aspect ratio region 240 in the HARP deposition process has multiple deposited surfaces, the oxide filling amount for filling the high aspect ratio region 240 is generally less than the etching amount when forming the high aspect ratio region 240 (e.g., less than 1100 Å). The oxide filling layer 250 deposited on the second sidewall 232 and the polysilicon interface 2311 is generally the same thickness. Therefore, after removing the oxide filling layer 250 deposited on the second sidewall 232 and the polysilicon interface 2311, the recess structure 230 of the semiconductor device will be restored to its original state. Figure 5 The situation is shown.

[0101] It should be noted that, in order to ensure the complete filling of the aforementioned high aspect ratio region 240, the aforementioned S610 can use multiple filling etching processes alternately to avoid the formation of void defects due to AR changes in the region when filling the high aspect ratio region 240.

[0102] In the aforementioned S620, considering that the HARP process in the aforementioned S610 will form an oxide filling layer of a certain thickness at the polysilicon interface, and that the oxide formed by the HARP process itself is not as dense as the oxide formed by the aforementioned HDP process, the oxide formed by the HARP process can be removed as much as possible before performing the HDP process, so that the groove structure is filled with a dense oxide filling structure as much as possible.

[0103] In the aforementioned S620, the oxide filling layer can be etched back (generally wet etching, referred to as the third etching process) based on the thickness of the oxide filling layer deposited at the polysilicon interface to expose the polysilicon interface. At this time, the high aspect ratio region within the groove structure is eliminated due to the filling of the aforementioned oxide filling layer, and simultaneously, there are no oxide filling layers on other interfaces of the groove structure, allowing its AR (Aspect Ratio) to... Figure 5 The situation shown is similar.

[0104] In some embodiments, considering the high AR (Advanced Partial Aspect Ratio) and corner structure of the aforementioned high aspect ratio region, bubble defects may exist in the HARP process. To avoid this, fabrication parameter testing can be performed before execution. Specifically, a high aspect ratio oxide filling process can be performed on multiple test substrates with high aspect ratio grooves based on multiple sets of candidate parameters to determine multiple candidate filling layers. Then, based on the substrate slice of the test substrate, the target filling layer and the target filling parameters corresponding to the target filling are determined from the multiple candidate filling layers. Finally, the target etching parameters are determined based on the thickness of the target filling layer deposited on the polysilicon interface. The target filling layer fills the high aspect ratio region, the target filling parameters are configured as the execution parameters for forming the oxide filling layer, and the target etching parameters are configured as the execution parameters for the third etching process.

[0105] In some embodiments, the target filling parameters in the aforementioned process may not be limited to the execution parameters of the HARP process, but may also include the parameters of each processing step when the HARP process and the etching process are executed alternately when filling a high aspect ratio region.

[0106] Therefore, based on the aforementioned filling process, the high aspect ratio area can be accurately filled, restoring the groove structure to the ideal state when the high aspect ratio area was not formed, and adapting to the requirements of the subsequent HDP process with a lower AR.

[0107] As mentioned above, in addition to the aforementioned filling process, etching can also be used to eliminate high aspect ratio regions. That is, after forming the high aspect ratio region, the polysilicon channel can be etched to remove the portion of the polysilicon interface protruding relative to the oxide interface in the high aspect ratio region. In other words, when using etching to eliminate high aspect ratio regions, a fourth etching process can be performed on the polysilicon channel to adjust the polysilicon interface to the oxide interface.

[0108] In some embodiments, the fourth etching process can be a dry etching process similar to the first etching process described above. That is, the portion of the polysilicon interface that protrudes relative to the oxide interface can be exposed through a mask layer, and then this portion can be removed by a dry etching process to eliminate the high aspect ratio region.

[0109] In the aforementioned process, considering that eliminating high aspect ratio regions involves further etching of the polysilicon interface, this situation may lead to a mismatch between the aforementioned local region and the expected size of the groove structure, requiring redesign of the local region.

[0110] To further illustrate this situation, this application also provides an exemplary flowchart of a method for determining etching process execution parameters based on the aforementioned influence of the etching process on the preparation parameters. Figure 8 ).

[0111] like Figure 8 As shown, the parameter determination method P800 may include the following steps:

[0112] S810. The sidewall etching amount of the sidewall oxide layer is determined based on the structural width of the oxide dense filling structure and the structural width of the polysilicon channel.

[0113] S820, based on the side etching amount of the sidewall oxide layer and the structural length of the oxide dense filling structure, determines the area range of the local region and the execution parameters of the fourth etching process.

[0114] In the aforementioned S810, the structural width of the oxide dense-filled structure can refer to the desired width of the groove structure. The structural width of the aforementioned polysilicon channel can be the width of the polysilicon channel itself. Based on the difference between the two, the amount of sidewall oxide etching (denoted as side etching amount) can be determined. Following the aforementioned situation, the structural width of the oxide dense-filled structure can be 4200 Å, and the structural width of the polysilicon channel is 2000 Å. Therefore, the side etching amount = (4200 Å - 2000 Å) / 2 = 1100 Å.

[0115] In the aforementioned S820, the structural length of the oxide dense-filled structure can refer to the length along the extension direction of the polysilicon channel. Considering that the etching of the oxide sidewalls will cause the same amount of etching in the extension direction of the polysilicon channel, and that the protruding parts of the polysilicon interface need to be removed subsequently, the side etching amount can be removed when determining the size of the local area.

[0116] Assuming the structure length of the oxide dense-filled structure is 8000 Å, then the local region's extent (length over the polysilicon channel) = 8000 Å - 2200 Å = 5800 Å. Therefore, the morphology of the mask layer can be determined based on the aforementioned local region, and the first etching process described above can be performed.

[0117] When the fourth etching process is implemented using a dry etching process, its etching parameters can be directly configured based on the structural length of the oxide dense-filled structure, thereby directly removing the protruding parts of the polysilicon interface.

[0118] When the fourth etching process is implemented using a wet etching process, unlike the second etching process which hardly etches polysilicon, when the wet etching process is used to etch polysilicon, the reagent used (often a mixed solution dominated by nitric acid (HNO3)) will also simultaneously etch silicon oxide.

[0119] In this case, if the fourth etching process is divided into etching of the oxide and etching of the polysilicon based on the actual etching amount, and the etching of the oxide is performed first, then the etching of the polysilicon in the fourth etching process is still the treatment of the protruding part of the polysilicon interface (i.e., its etching amount remains unchanged). It mainly divides the side etching amount of the aforementioned sidewall oxide layer into the etching amount of the second etching process and the etching amount of the fourth etching process.

[0120] For example, the amount of oxide etching (e.g., 100 Å) when polysilicon interface etching is completed in the fourth etching process can be determined based on the difference in etching rates between oxide and polysilicon in the fourth etching process. Then, this amount of etching (1100 Å - 100 Å = 1000 Å) can be subtracted in the second etching process so that the amount of sidewall oxide etching = the amount of etching in the second etching process (1000 Å) + the amount of etching in the fourth etching process (100 Å).

[0121] It should be noted that when the fourth etching process is implemented using a wet etching process, the selection ratio of the wet etching reagent for polysilicon to silicon oxide can be determined based on the specific reagent, as long as the etching rate for polysilicon is greater than the etching rate for silicon oxide.

[0122] Therefore, based on the above etching process, the polysilicon interface can be removed, and based on the above description, a groove structure of a specific size can be fabricated by adjusting the etching parameters.

[0123] Exemplary HDP process:

[0124] As can be seen from the foregoing, in some embodiments, this application has found that using HDP filling under high bias power for a long time may affect the equipment hardware, damage the gas nozzles of the reaction chamber top cover, and may even lead to wafer defects (such as particle contamination caused by the aforementioned gas nozzle damage or deterioration of the filled film).

[0125] Specifically, high-energy ions and electrons in the plasma gain extremely strong kinetic energy under high power (e.g., 9000W), which may cause them to sputter onto the gas nozzles on the top of the reaction chamber. During long-term operation (especially in deposition processes or alternating etching-deposition processes), the sputtered or vapor-deposited material gradually accumulates on the cooler nozzle surface, forming a deposition layer. As the thickness of the deposition layer increases, its adhesion decreases, and combined with the thermal cycling and mechanical vibrations during the process, it can lead to localized peeling. These peeled fragments fall onto the wafer surface in the form of particle defects (PDs), causing pattern defects.

[0126] To avoid this situation, this application can modulate the power during the high-density plasma oxide deposition process, switching to low-power deposition when it is sufficient. Specifically, during the high-density plasma oxide deposition process, the process can be performed on the groove structure based on at least two deposition parameters to form a dense oxide-filled structure within the groove structure. Specifically, for the first and second deposition parameters executed sequentially, the plasma power of the first deposition parameter is greater than that of the second deposition parameter, and the aspect ratio of the groove structure is greater when the first deposition parameter is executed than when the second deposition parameter is executed.

[0127] Furthermore, in actual implementation, the deposition parameters of the aforementioned two deposition processes can be adjusted not only for plasma power but also for the released gas. For example, the first deposition parameter includes a hydrogen release command, and the plasma power in the first deposition parameter is 8000W to 9000W (preferably 9000W). The second deposition parameter includes a helium release command and a nitrogen trifluoride release command, and the plasma power in the second deposition parameter is 3000W to 4000W (preferably 4000W).

[0128] In some embodiments, a hydrogen-based HDP process can be performed first based on the aforementioned 9000W plasma power to deposit a certain amount of oxide (e.g., 2500Å oxide). After achieving good bottom uniformity based on high-power HDP, the process is switched to a lower-power HDP process (i.e., a 4000W plasma power helium-based HDP process) to fill the remaining portion using helium-based sputtering capability.

[0129] Furthermore, to ensure the compactness of the filled oxide, etching gases (such as nitrogen trifluoride NF3) can be released intermittently during the aforementioned filling process (especially the filling stage based on 4000W) to open gaps for easy filling, prevent voids, and thus improve the compactness of the oxide.

[0130] To further illustrate this process, this application also provides a schematic diagram of the temporal variation of deposition parameters in a high-density plasma oxide deposition process. Figure 9 ).

[0131] like Figure 9 As shown, the horizontal axis reflects the deposition time, the left vertical axis reflects the power, and the text on the right reflects the release status of hydrogen, helium, and nitrogen trifluoride (i.e., the release switch of the corresponding gas). Figure 9 As shown, the solid line represents the power curve on the left side of the coordinate system, while the double line represents the gas release switch triggering status on the right side of the coordinate system. In the power curve, it initially operates at a high power (9000W), and after a certain period (e.g., after deposition of 2500 Å), it adjusts to a lower power (e.g., 4000W). At this point, 9000W and 4000W can be divided into two distinct deposition stages. Referring to the gas switch curve, in the 9000W stage, the hydrogen switch is on, while the helium and nitrogen trifluoride switches are off. In the 4000W stage, the hydrogen switch is off, the helium switch is on, and the nitrogen trifluoride switch is intermittently activated.

[0132] In addition, considering the etching effect of nitrogen trifluoride, when the nitrogen trifluoride switch is turned on, the flow rate of the helium switch can be reduced and the injection of the precursor can be stopped to wait for the nitrogen trifluoride etching to be completed.

[0133] Therefore, this application can reduce the execution time of high plasma power deposition processes, ensuring the bottom deposition condition while reducing the impact of high plasma power on the equipment hardware and avoiding damage to the gas nozzles on the top cover of the reaction chamber. Simultaneously, when using lower power to perform the deposition process, the interspersed introduction of etching gases such as nitrogen trifluoride ensures good oxide compactness even at lower plasma power.

[0134] Unexpected technical effects:

[0135] In summary, the semiconductor device and manufacturing method provided in this application have the following unexpected effects:

[0136] ① In response to the situation where the etch-back process of the sidewall oxide layer on both sides of the groove structure will form a high aspect ratio region (such as AR=11) in the shoulder area of ​​the groove structure, this application adjusts the oxide interface and polysilicon interface in the groove structure to make them flush before performing the high density plasma oxide deposition process, so as to eliminate the high aspect ratio region and significantly reduce the aspect ratio of the groove structure (such as AR≈3) to meet the working range of the high density plasma oxide deposition process, thereby forming a dense oxide filling structure and ensuring its electrical isolation performance.

[0137] ② In this application, the aforementioned high aspect ratio region is eliminated through HARP (High Aspect Ratio Reduction) filling. During filling, to ensure the formation of dense oxide, the HARP process can be reversed after filling, so that the oxide formed by the HARP process is only formed in the high aspect ratio region. Therefore, within the process tolerance range, the trench structure will not retain oxide formed by other HARP processes, allowing the oxide-dense filling structure to fill the trench structure as much as possible. It exhibits excellent electrical performance whether used as a trench isolation structure or as an inter-gate isolation dielectric layer.

[0138] ③ This application also provides the elimination of high aspect ratio regions through etching processes. Furthermore, to adapt to the dimensional changes in the groove structure caused by the etching process, this application also provides a method for adjusting the dimensions of the groove process based on the etching process. This method can avoid the influence of the etching process on the dimensions by configuring etching parameters in advance, thereby forming the desired groove structure dimensions.

[0139] ④ This application can use a wet etching process to eliminate high aspect ratio regions, thereby reducing the preparation and use of mask layers and lowering process design costs. Simultaneously, considering the simultaneous etching of silicon oxide by the wet etching process, the amount of oxide re-etching in the wet etching process is adjusted to make the oxide interface flush with the polysilicon interface, thus eliminating high aspect ratio regions.

[0140] ⑤ When performing high-density plasma oxide deposition (HDPD) processes, a combination of methods can be used. High-power plasma deposition processes can be used to deposit a certain thickness of oxide (e.g., 2500 Å) to ensure the density of the bottom deposition morphology and avoid defect formation. The remaining portion can be filled using lower plasma power. This reduces the execution time of the high-power plasma deposition process, minimizes its impact on the hardware, and avoids damage to the top nozzle of the reaction chamber and the resulting wafer defects.

[0141] ⑥ Different gases can be used in deposition processes with different plasma powers. In the high-plasma-power deposition stage, hydrogen can be used to improve the density of the oxide deposition, ensure deposition consistency, and avoid defects. In the lower-plasma-power deposition stage, helium is used to fill the remaining space based on helium's sputtering characteristics. Simultaneously, nitrogen trifluoride can be intermittently released for etching to ensure the oxide filling capacity and density even at lower plasma power.

[0142] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for fabricating a semiconductor device, characterized in that, The preparation method includes: A substrate is provided, wherein the substrate includes at least one polysilicon channel and sidewall oxide layers formed on both sides of the polysilicon channel; A first etching process is performed on at least one local area of ​​the polysilicon channel to remove a portion of the polysilicon in the local area to form a groove structure; A second etching process is performed on the sidewall oxide layer to expand at least a portion of the trench sidewall of the trench structure into the sidewall oxide layer, wherein the sidewall oxide layer is etched to form an oxide interface in a first sidewall in the trench sidewall facing the extension direction of the polysilicon channel, and the oxide interface extends across the polysilicon interface in the first sidewall in the extension direction to form high aspect ratio regions on both sides of the polysilicon interface. The oxide interface and the polysilicon interface are aligned to eliminate the high aspect ratio region. A high-density plasma oxide deposition process is performed on the groove structure to form a dense oxide-filled structure within the groove structure.

2. The semiconductor device fabrication method according to claim 1, characterized in that, The step of adjusting the oxide interface and the polycrystalline silicon interface to be flush includes: A high aspect ratio oxide filling process is performed on the groove structure to fill the high aspect ratio region with oxide to flatten the high aspect ratio region.

3. The semiconductor device fabrication method according to claim 2, characterized in that, The process of performing a high aspect ratio oxide filling process on the groove structure, filling the high aspect ratio region with oxide to fill the high aspect ratio region, includes: The high aspect ratio oxide filling process is performed to form an oxide filling layer in the groove structure, wherein the oxide filling layer at least fills the high aspect ratio region; A third etching process is performed on the oxide-filled layer to expose the polysilicon interface.

4. The semiconductor device fabrication method according to claim 3, characterized in that, The semiconductor device fabrication method includes: The high aspect ratio oxide filling process is performed on multiple test substrates with high aspect ratio grooves based on multiple sets of candidate parameters to determine multiple candidate filling layers; Based on the substrate slice of the test substrate, a target filling layer and a target filling parameter corresponding to the target filling are determined from the plurality of candidate filling layers, wherein the target filling layer fills the high aspect ratio region, and the target filling parameter is configured as the execution parameter for forming the oxide filling layer; Target etching parameters are determined based on the thickness of the target filling layer deposited on the polysilicon interface, wherein the target etching parameters are configured as execution parameters for the third etching process.

5. The semiconductor device fabrication method according to claim 1, characterized in that, The high-density plasma oxide deposition process performed on the groove structure to form a dense oxide-filled structure within the groove structure includes: A high-density plasma oxide deposition process is performed on the groove structure based on at least two deposition parameters to form a dense oxide-filled structure within the groove structure. Specifically, for the first deposition parameter and the second deposition parameter executed sequentially among the at least two deposition parameters, the plasma power of the first deposition parameter is greater than the plasma power of the second deposition parameter, and the aspect ratio of the groove structure when the first deposition parameter is executed is greater than the aspect ratio of the groove structure when the second deposition parameter is executed.

6. The semiconductor device fabrication method according to claim 5, characterized in that, The first deposition parameters include a hydrogen release command, and the plasma power in the first deposition parameters is 8000W to 9000W; The second deposition parameters include helium release command and nitrogen trifluoride release command, and the plasma power in the second deposition parameters is 3000W to 4000W.

7. The semiconductor device fabrication method according to claim 1, characterized in that, The step of adjusting the oxide interface and the polycrystalline silicon interface to be flush includes: A fourth etching process is performed on the polysilicon channel to adjust the polysilicon interface to the oxide interface.

8. The semiconductor device fabrication method according to claim 7, characterized in that, The semiconductor device fabrication method includes: The sidewall etching amount of the sidewall oxide layer is determined based on the structural width of the oxide dense filling structure and the structural width of the polysilicon channel. The area range of the local region and the execution parameters of the fourth etching process are determined based on the side etching amount of the sidewall oxide layer and the structural length of the oxide dense filling structure.

9. The semiconductor device fabrication method according to claim 1, characterized in that, The polysilicon channel is formed in the cell region of the semiconductor device, such that the etched polysilicon channel is configured as a shielding gate for each semiconductor unit. The fabrication method further includes: A control gate is formed within the oxide dense-filled structure, wherein the oxide dense-filled structure is formed within each semiconductor cell and configured as an inter-gate isolation dielectric layer between the shielding gate and the control gate in the corresponding semiconductor cell.

10. A semiconductor device, characterized in that, The semiconductor device is manufactured based on any one of the semiconductor device fabrication methods of claims 1 to 9.

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