atomically aggregated

Abstract

Techniques related to polyatomic operations are disclosed. In some embodiments, a cache control circuit caches a data value in a cache storage circuit, and receives a plurality of requests to atomically update the cached data value according to one or more arithmetic operations. The control circuit can perform the update to the cached data value based on the plurality of requests, and store operation information indicating a most recent requested atomic arithmetic operation for the updated data value, responsive to determining that the one or more arithmetic operations satisfy one or more criteria. The control circuit can flush to a memory hierarchy including a higher level of the cache storage circuit both the updated data value and the operation information, responsive to an event. This can advantageously aggregate atomic operations at the cache, and reduce operations to a higher level cache or memory, which can be the actual point of coherency for atomic requests.

Description

Technical Field

[0001] This disclosure relates generally to computer processor architecture, and more specifically to processing atomic operations. Background Technology

[0002] Description of related fields

[0003] In a distributed processor (e.g., a graphics processing unit), different cores can transmit atomic operation requests. A given atomic request may include an arithmetic operation to be performed on data at a target location. Different threads can transmit atomic requests to the same region of memory (e.g., corresponding to a cache line). Some atomic requests are "no-return," meaning the requesting thread does not need to immediately observe the new value after the operation is completed. Attached Figure Description

[0004] Figure 1A This is a diagram illustrating an overview of example graphics processing operations based on some implementation schemes.

[0005] Figure 1B This is a block diagram illustrating example graphical units according to some implementation schemes.

[0006] Figure 2 This is a block diagram illustrating an example aggregation of multiple atomic requests according to some implementation schemes.

[0007] Figure 3 This is a more detailed block diagram illustrating an example accumulation control circuit configured to process accumulated values ​​and metadata for aggregation, according to some implementation schemes.

[0008] Figure 4 This is a diagram illustrating example metadata fields based on some implementation schemes.

[0009] Figure 5 This is a flowchart illustrating example cache operations for atomic requests according to some implementation schemes.

[0010] Figure 6 This is a flowchart illustrating example methods based on some implementation schemes.

[0011] Figure 7 This is a block diagram illustrating an example computing device based on some implementation schemes.

[0012] Figure 8 These are illustrations illustrating example applications of systems and devices disclosed according to some implementation schemes.

[0013] Figure 9 This is a block diagram of an example computer-readable medium illustrating storage circuit design information according to some implementation schemes. Detailed Implementation

[0014] In the disclosed embodiments discussed in detail below, the control circuitry is configured to accumulate multiple atomic requests for the same memory region (e.g., by flushing to a consistency point) before making the results available to the requester. In a loose memory ordering context, the control circuitry may accumulate results until an event triggering the control circuitry to make the values ​​consistent occurs (e.g., the results are accessed, or an atomic operation whose order affects correctness is encountered). This merging may be referred to as “atomic aggregation”.

[0015] Atomic requests can be heterogeneous in various ways. For example, requests can come from different threads (spatial heterogeneity) and occur at different times (temporal heterogeneity). In the context of parallel processing, spatial heterogeneity can include aggregated requests from different single instruction multiple data (SIMD) groups, or even from different programs / shaders (e.g., different scheduled tasks or different thread groups running different shaders).

[0016] Atomic operations, consistency, and loose memory ordering

[0017] According to some implementations, the following paragraphs provide additional information regarding atomic operations, consistency, and loose memory ordering. In some implementations, atomic aggregation can be implemented in this context.

[0018] Various programming languages ​​and application programming interfaces (APIs) support atomic operations. For example, the Metal Shading Language (MSL) provides a series of atomic operation functions, including store, load, swap, retrieve, and modify (e.g., supporting addition, AND, maximum, minimum, bitwise OR, subtraction, and XOR operations), as well as modification (e.g., supporting maximum and minimum operations). Typically, the execution of an "atomic" operation is exclusive—during its execution, other processes or threads cannot read the state of the data modified by the operation, nor can they change that state. Therefore, from the requester's perspective, the action of an atomic operation (e.g., reading a data value, performing one or more operations on that data value as input, and storing the result) is executed as a single step. For atomic requests with no return value, the requester (e.g., a graphics shader program) does not immediately receive the result of the atomic operation (but may eventually observe it through subsequent instructions accessing the memory address where the result is stored).

[0019] Atomic functions can have different scopes, such as local atoms and device-level atoms. The consistency points for different scopes may differ. As an example, a lower-level shader cache might be the consistency point for a local atom, while a higher-level cache (which may be shared by multiple cores) might be the consistency point for a device-level atom. In some implementations, consistency control circuitry can provide consistency across multiple caches at a given level, for example, using snooping mechanisms, directory mechanisms, etc. Various atomic scopes can be implemented in different implementations.

[0020] Compared to strict memory models (e.g., memory models that require sequential consistency), relaxed memory models impose fewer constraints on the order of memory operations. In a relaxed model, newer memory operations can be executed earlier than older memory operations in certain scenarios, subject to any explicit synchronization instructions.

[0021] Many mathematical operations, backed by loosely packed memory sequential atoms, are binary-associative, thus forming a monoid when paired with an identity element. This identity element allows these operations to be performed independently of previous operations (and therefore independent of the consistent view of the memory) and subsequently merged without affecting the correctness of the result. For example, the following table provides the identity elements for some arithmetic operations:

[0022]

[0023] In this table, it should be noted that IMIN refers to the minimum value of a 32-bit signed integer, and UMIN refers to the minimum value of a 32-bit unsigned integer.

[0024] Certain graphics workloads heavily utilize atomic operations with no return value. For example, some renderers might perform the following process: generating geometry clusters during resource import, distributing compressed geometry clusters, calculating the cluster detail level selection (e.g., to achieve a target average triangle size), culling clusters, routing small triangle clusters to the software rasterizer (e.g., writing to the pixel visibility buffer using a "no return value atomic maximum" operation), rasterizing large triangle clusters in hardware (e.g., also using atomic operations), and performing deferred material application. In this example workload, improvements to atomic performance can significantly impact overall performance, especially if the renderer does not bin primitives into spatial tiles before rasterization (making thread group atomics unhelpful for performance scaling).

[0025] Overview of Atomic Polymerization

[0026] In some implementations, cache control circuitry can accumulate the results of multiple addition operations at a given cache level. For example, consider multiple atomic addition instructions at the same location in memory. In this example, the first instruction adds 7, the second adds 5, and the third adds 8 (where the labels "first," "second," and "third" indicate the execution order of the instructions, which may differ from the program order of the instructions). In this example, the location in memory has a value of 10 before these three instructions are executed.

[0027] The control circuit can add the input value of the first instruction to the identity value (0 for addition) and store the result (7) in a cache line. The control circuit can then add the input value of the second instruction to the stored result and store the updated result (12) in a cache line. After executing the third instruction, the accumulated result is 20.

[0028] In response to a refresh event, the processor needs to add the accumulated result to the value at that location in memory. Therefore, the control circuitry can track the most recently executed operation (addition in this example) and cause that operation to be performed between the value at the memory location and the accumulated result. This mechanism provides a consistent result of 30 for these three addition operations. This refresh control could involve initiating a single transaction that identifies the operation to a higher level in the cache / memory hierarchy. Alternatively, the refresh control could involve retrieving the value from the location in memory and performing the operation locally. As another alternative, this could involve, for example, using one or more listener requests to communicate with another cache in the distributed consistency scheme.

[0029] Examples of refresh events include, but are not limited to: a request to access a location in memory that returns a value to the program; evicting a cache line for cache maintenance reasons; a timeout; a programmer-controlled disabled bit on an atomic instruction; or a requested atomic operation that is not associated with a previously aggregated operation (which may be referred to as a conflict in this document).

[0030] The control circuitry can also ensure that accumulated operations meet certain criteria. It can examine recent atomic operations to help determine whether the next operation can be accumulated. Examples of checks for aggregation criteria include: checking binary associative algebra operations, checking for loose memory ordering, checking that a request has no return value, checking for compatible data types, and checking that atomic operations access the same memory region (e.g., cache lines).

[0031] The disclosed techniques can advantageously reduce bandwidth by decreasing higher-level cache / memory accesses, and can also directly improve performance by allowing aggregate atomic operations to be performed at a greater rate (relative to execution at coherent points, listening for each atomic request, etc.). Further disclosed techniques can facilitate performance scaling in graphics processor designs, for example, when increasing the number of shaders / coherent caches at a given cache level.

[0032] Overview of Graphics Processing

[0033] refer to Figure 1A The diagram illustrates a flowchart of an example processing flow 100 for processing graphics data. In some embodiments, the transformation and lighting process 110 may involve processing lighting information of vertices received from the application based on defined light source positions, reflectivity, etc., assembling vertices into polygons (e.g., triangles), and transforming polygons to the correct size and orientation based on their positioning in three-dimensional space. The clipping process 115 may involve discarding polygons or vertices outside the visible area. In some embodiments, geometry processing may be performed flexibly and efficiently using object shaders and mesh shaders prior to rasterization. The rasterization process 120 may involve defining segments within each polygon and assigning initial color values ​​to each segment, for example, based on the texture coordinates of the polygon vertices. Segments may specify the properties of the pixels they overlap, but the actual pixel properties may be determined based on combining multiple segments (e.g., in a framebuffer), ignoring one or more segments (e.g., if they are covered by other objects), or both. The shading process 130 may involve altering pixel components based on lighting, shadows, bump mapping, semi-transparency, etc. Shaded pixels may be assembled in framebuffer 135. Modern GPUs typically include programmable shaders that allow application developers to customize shading and other processing. Therefore, in various implementations, Figure 1A The example components can be executed in various sequences, in parallel, or omitted. Additional processing procedures can also be implemented.

[0034] Now for reference Figure 1B A simplified block diagram of an exemplary graphics unit 150 according to some embodiments is shown. In the exemplary embodiments, the graphics unit 150 includes a programmable shader 160, a vertex pipe 185, a fragment pipe 175, a texture processing unit (TPU) 165, an image write buffer 170, and a memory interface 180. In some embodiments, the graphics unit 150 is configured to use the programmable shader 160 to process both vertex data and fragment data, and the programmable shader may be configured to process the graphics data in parallel using multiple execution pipelines or instances.

[0035] In an illustrated embodiment, vertex tube 185 may include various fixed-function hardware configured to process vertex data. Vertex tube 185 may be configured to communicate with programmable shader 160 to coordinate vertex processing. In an illustrated embodiment, vertex tube 185 is configured to pass processed data to fragment tube 175 or programmable shader 160 for further processing.

[0036] In the illustrated embodiment, fragment tube 175 may include various fixed-function hardware configured to process pixel data. Fragment tube 175 may be configured to communicate with programmable shader 160 to coordinate fragment processing. Fragment tube 175 may be configured to perform rasterization on polygons from vertex tube 185 or programmable shader 160 to generate fragment data. Vertex tube 185 and fragment tube 175 may be coupled to memory interface 180 (coupling not shown) to access graphics data.

[0037] In the illustrated embodiment, programmable shader 160 is configured to receive vertex data from vertex tube 185 and fragment data from fragment tube 175 and TPU 165. Programmable shader 160 may be configured to perform vertex processing tasks on the vertex data, which may include various transformations and adjustments to the vertex data. For example, in the illustrated embodiment, programmable shader 160 is also configured to perform fragment processing tasks on pixel data, such as texturing and shading. Programmable shader 160 may include multiple sets of execution pipelines for parallel processing of data.

[0038] In some implementations, programmable shaders include pipelines configured to execute one or more different SIMD groups in parallel. Each pipeline may include various stages configured to perform operations (such as fetch, decode, dispatch, execute, etc.) within a given clock cycle. The concept of a processor “pipeline” is well understood and refers to the concept of dividing the “work” of a processor executing instructions into multiple stages. In some implementations, instruction decoding, dispatch, execution (i.e., performing), and rollback can be examples of different pipeline stages. Many different pipeline architectures may have different element / part orders. Various pipeline stages perform such steps on instructions during one or more processor clock cycles, then pass the instructions or operations associated with the instructions to other stages for further processing.

[0039] The term "SIMD group" is intended to be interpreted in its well-known sense, referring to a set of threads for which processing hardware processes the same instructions in parallel using different input data for different threads. A SIMD group may also be referred to as a SIMT (Single Instruction Multithreaded) group, a Single Instruction Parallel Thread (SIPT), or a channel stack thread. Various types of computer processors may include multiple sets of pipelines configured to execute SIMD instructions. For example, graphics processors typically include programmable shader cores configured to execute instructions in a SIMD manner for a set of related threads. Other examples of names that can be used for a SIMD group include: wavefront, clique, or warp. A SIMD group may be part of a larger group of threads executing the same program, which may be split into multiple SIMD groups (within which threads can execute lockstep) based on the computer's parallel processing capabilities. In some implementations, each thread is assigned to a hardware pipeline (which may be referred to as a "channel") that fetches operands for that thread and executes the specified operation in parallel with other pipelines in that group of threads. It should be noted that processors can have numerous pipelines, allowing multiple individual SIMD groups to execute in parallel. In some implementations, each thread has a private operand store, for example, in a register file. Therefore, reading a specific register from the register file provides a version of the register for each thread in the SIMD group.

[0040] As used herein, the term "thread" includes its meaning well known in the art and refers to a sequence of program instructions that can be scheduled to execute independently of other threads. A SIMD group may include multiple threads to execute in lockstep. A task or process (which may correspond to a computer program) may include multiple threads. Threads of a given task may or may not share resources such as registers and memory. Therefore, when switching between threads of the same task, a context switch may or may not be performed.

[0041] In some implementations, multiple programmable shader units 160 are included in the GPU. In these implementations, global control circuitry can assign work to different sub-parts of the GPU, which in turn can assign work to shader cores for processing by the shader pipeline.

[0042] In the illustrated implementation, TPU 165 is configured to schedule fragment processing tasks from programmable shader 160. In some implementations, TPU 165 is configured to prefetch texture data and assign initial colors to fragments for further processing by programmable shader 160 (e.g., via memory interface 180). TPU 165 may be configured to provide fragment components, for example, in normalized integer or floating-point format. In some implementations, TPU 165 is configured to provide fragments in a 2×2 format, grouped into sets of four (“fragment quadruples”), which are pipelined by a set of four programmable shaders 160.

[0043] In some embodiments, the image write buffer 170 is configured to store processed tiles of the image, and operations can be performed on the rendered image before it is transferred for display or transferred to memory for storage. In some embodiments, the graphics unit 150 is configured to perform tile-based deferred rendering (TBDR). In tile-based rendering, different portions of the screen space (e.g., squares or rectangles of pixels) can be processed individually. In various embodiments, the memory interface 180 facilitates communication with one or more of various memory hierarchies.

[0044] As discussed above, a graphics processing unit (GPU) typically includes dedicated circuitry configured to perform certain graphics processing operations requested by the computing system. This may include, for example, fixed-function vertex processing circuitry, pixel processing circuitry, or texture sampling circuitry. A GPU can also perform non-graphics computational tasks that can be performed using GPU shader cores but without the use of fixed-function graphics hardware. As an example, machine learning workloads (which may include inference, training, or both) are typically assigned to the GPU due to its parallel processing capabilities. Therefore, the computational cores executed by the GPU may include program instructions specifying machine learning tasks, such as implementing neural network layers or other aspects of a machine learning model to be executed by the GPU shaders. In some cases, non-graphics workloads may also use dedicated graphics circuitry for purposes different from what was initially intended.

[0045] In other implementations, the various circuits and techniques discussed herein with reference to graphics processors can be implemented in other types of processors. These other types of processors may include general-purpose processors such as CPUs or machine learning or artificial intelligence accelerators with dedicated parallel processing capabilities. These other types of processors may not be configured to execute graphics instructions or perform graphics operations. For example, other types of processors may not include the fixed-function hardware included in a typical GPU. Machine learning accelerators may include dedicated hardware for certain operations, such as implementing neural network layers or other aspects of machine learning models. Generally, there may be design trade-offs between memory requirements, computational power, power consumption, and the programmability of machine learning accelerators. Therefore, different implementations may focus on different performance goals. Developers can choose from multiple potential hardware goals for a given machine learning application, such as general-purpose processors, GPUs, and various dedicated machine learning accelerators.

[0046] Example atomic polymerization control circuit

[0047] Figure 2 This is a block diagram illustrating an example aggregation of multiple atomic requests according to some implementation schemes. In this illustrated implementation, the processor includes lower-level cache circuitry 210 and higher-level cache / memory circuitry 205. As used herein, a "lower" cache level refers to a level closer to the underlying processor circuitry, while a "higher" cache level refers to a level closer to the backing memory. Note that the hierarchical structure may include various other levels not shown.

[0048] In the illustrated implementation, the lower-level cache circuit 210 receives multiple atomic requests 200A-200N. For multiple requests to the same atomic region of memory, the atomic aggregation control circuit 215 is configured to accumulate multiple requests that meet certain criteria. An example of an atomic region of memory is a cache line, but other atomic regions of different granularities may also be tracked in various implementations. As shown, circuit 215 can generate a single “aggregated” transaction for multiple atomic requests and send it to the higher-level cache / memory circuit 205. This can advantageously reduce the number of transactions sent to the higher-level circuit 205 compared to sending a separate transaction for each atomic request.

[0049] In the illustrated implementation, higher-level cache / memory circuitry 205 is configured to store data evicted from lower-level cache 210 in a write-back implementation. In other implementations, circuitry 205 may implement write-through technology. In some implementations, circuitry 205 acts as a coherence point for multiple caches 210.

[0050] In some implementations, circuit 210 is a Level 1 (L1) cache for shader cores, and circuit 205 is a Level 2 (L2) cache shared by multiple shader cores. In other implementations, circuit 210 is an L2 cache in a multi-GPU system (potentially a multi-die system), and circuit 205 is a memory cache shared by multiple L2 caches. These are non-limiting examples to illustrate that specific cache levels can vary in different implementations.

[0051] Figure 3 This is a more detailed block diagram illustrating an example accumulation control circuit configured to process accumulated values ​​and metadata for aggregation, according to some embodiments. In the illustrated example, the graphics processor includes higher-level cache / memory circuitry 305, cache control circuitry 310, cache storage circuitry 320, and shader circuitry 330. In some embodiments, circuitry 305 corresponds to... Figure 2 Circuit 205, and circuits 310 and 320 correspond to circuit 210.

[0052] In some implementations, shader circuitry 330 is configured to execute instructions of a shader program. This may include forming and executing a SIMD group from a thread of a given thread group. In some implementations, cache storage 320 is an L1 cache for shader circuitry 330 (and the GPU may include multiple instances of shader circuitry 330 with corresponding L1 caches). In some implementations, shader circuitry 330 includes an execution pipeline with arithmetic logic unit (ALU) circuitry 334 configured to perform operations specified by certain instructions. However, for certain atomic instructions, shader circuitry 330 is configured to submit an atomic request (e.g., request 302, which includes one or more values ​​and an operation for the request) to cache control 310, such that the operation is performed by cache control circuitry 310, rather than within circuitry 330. In non-GPU implementations, one or more processor pipelines (e.g., CPU pipelines) may access cache storage 320 via cache control 310, similar to shader circuitry 330.

[0053] In some embodiments, cache control circuitry 310 is configured to perform various operations on cache storage 320 (e.g., checking for hits and misses in the content-addressable tag array, performing maintenance operations, selecting entries for eviction, etc.). In an exemplary embodiment, cache control 310 includes atomic accumulation control circuitry 315, which can be configured to handle various atomic aggregation operations discussed herein, including performing and accumulating requested operations using ALU circuitry 314.

[0054] In some implementations, cache storage 320 is a random access memory configured to store data of cache lines controlled by circuitry 310. In an illustrative example, atom accumulation control circuitry 315 is configured to store the accumulated value 304 from aggregate atoms and metadata 306 in cache storage 320 (the metadata may be stored in its corresponding cache line or stored separately).

[0055] Metadata 306 can reflect various information about the cumulative value 304, as shown in the following reference. Figure 4 This is discussed in detail. In various implementations, metadata 306 indicates the most recent operation performed to update the cumulative value 304. In some implementations, metadata 306 also indicates whether a given row is an atomic row (a row where one or more atomic requests have been locally aggregated).

[0056] Various operations can lead to "conflicts" that halt atomic aggregations (e.g., operations that trigger a refresh to a consistency point). For example, atomic requests that do not meet the criteria for atomic aggregation may cause a conflict. An example criterion is a request operation that has a specific algebraic relationship with a previous operation (e.g., the two operations are identical, the two operations belong to the same set of swap operations, etc.). Another example criterion is atomic requests with the same data type (or data types within a set of similar data types). Other criteria may also exist, such as a loose memory ordering pattern, a request being "without a return value" (requests with a return value may trigger a refresh), and so on. Furthermore, external events such as eviction or other cache maintenance operations may also cause a refresh.

[0057] Control 315 may include conflict checking circuitry configured to allocate / evict cache lines and update cache lines, as discussed above. Control 315 may implement a finite state machine, for example, that changes state based on various inputs, such as the state of a cache line, replacement information, requested operations, etc., to perform various disclosed operations.

[0058] When a conflict occurs, cache control circuitry 310 is configured to pass the accumulated value 304 and metadata 306 (or at least a portion thereof indicating a recent operation) to higher-level circuitry 305. In some embodiments, cache control 310 then serves the request that caused the conflict (e.g., populating the accumulated value 304 with an identity value associated with the operation and updating the metadata 306 to reflect the operation).

[0059] After the refresh, circuit 305 is configured to use ALU 324 to perform operations indicated by the refresh metadata on the refreshed accumulated value and stored value 308. This allows for non-conflicting atomic aggregation of subsequent operations.

[0060] Figure 4 This is an illustration of example fields of metadata 306 according to some implementations. In the illustrated example, the metadata for a memory region (e.g., a cache line) includes an atomic field 410, a type field 420, an operation field 430, and a validity field 440. The atomic field 410 may indicate whether the memory region is an atomic region (e.g., whether an atomic request has been processed to update the region). The type field 420 may indicate the data type of the most recent operation (e.g., a 16-bit integer, a 32-bit integer, a 32-bit floating-point number, a 64-bit floating-point number, etc.). The operation field 430 may indicate the most recent operation performed on the atomic region. The validity field 440 may indicate whether the metadata is valid. In some implementations, metadata 306 may also indicate a context ID, virtual address, etc., associated with the memory region.

[0061] In some implementations, metadata 306 is at least partially compressed (potentially compressed to the same storage location as cache line data) before being written. For example, an exemplified field might initially be encoded using N bits, but could be stored using NM bits after compression. Control circuitry can then decode the metadata 306 when it is retrieved.

[0062] In summary, in some implementations, for atomic requests that do not return a value, a cache miss results in the allocation of a line in the cache, the recording of the atomic operation in the metadata, and the initialization of the identity value to 304. A hit request triggers a conflict check, while requests that do not cause a conflict update the cache line and metadata. In the event of a conflict, the control circuitry refreshes the accumulated value and metadata, records the operation performed by the incoming request, and initializes the value 304 to the identity value of the incoming operation.

[0063] Figure 5This is a flowchart illustrating the method according to some implementation schemes. At 505, in the illustrated example, the cache control circuitry receives an atomic request. At 510, the control circuitry determines whether a cache miss exists. If so, the process proceeds to 520, and the control circuitry allocates a cache line, writes the appropriate operand (e.g., an identity value) to the cache line, and generates metadata to reflect the operation. If a cache hit exists at 510, the process proceeds to 530, and the control circuitry determines whether a conflict exists. If so, the process proceeds to 540, and the control circuitry refreshes the hit cache line (including the latest operation reflected in the metadata), allocates a new cache line, writes the operand, and generates metadata to reflect the new operation. If no conflict exists at 530, the process proceeds to 550, and the control circuitry accumulates the incoming operation with the hit cache line and updates the metadata (note that if the incoming operation is the same as a previous operation or is encoded as belonging to the same group of operations as a previous operation, it may not be necessary to update the metadata).

[0064] For atomic requests with return values, in the event of a cache miss, the control circuitry can forward the request to the consistency point (without allocating a cache line in cache store 320). In the event of a cache hit, the control circuitry can perform a flush, invalidating the cache region (e.g., a cache line with accumulated value 304) and forwarding the incoming atomic request to the consistency point, ensuring that the request is processed sequentially relative to requests generated by the flush. Therefore, a request to retrieve a consistent value (e.g., an atomic operation with a return value) can ensure that value 308 reflects the consistent value before responding to the request.

[0065] It should be noted that while this document discusses various graphics processing unit (GPU) implementations, similar techniques can be used with other types of processors (e.g., CPUs, microcontrollers, etc.). Therefore, GPU implementations are not intended to limit the scope of this disclosure. Similar parallel processing techniques can be used on non-GPU processors, within the GPU-specific SIMD or thread group context discussed herein.

[0066] Examples of conflict resolution under consensus points

[0067] In other implementations, instead of flushing in response to a conflict, cache control 310 can retrieve value 308 from circuit 305 and perform one or more operations locally to correctly update the accumulated value 304. For example, for a requested atomic multiplication following a series of additions, cache control 310 can retrieve value 308, add that value to the accumulated value 304, perform a multiplication on the result to generate a new accumulated value 304, and then update metadata 306 to reflect the multiplication. In these implementations, circuit 305 can lock its corresponding cache line until the operations of cache control 310 are complete, thereby maintaining consistency.

[0068] In other implementations, instead of maintaining consistency at a central point, consistency can be maintained among multiple different caches at the same level, for example, using a snooping mechanism. In these implementations, cache control 310 can acquire ownership of a location (potentially retrieving dirty data from one or more other caches at the same level) before executing an incoming request that causes a conflict. More generally, conflict-related updates can be performed at the processor that caused the conflict (e.g., by retrieving a value from another cache, updating the value based on a previous aggregation, and performing the operation that caused the conflict), or by another processor (e.g., by transferring the accumulated value, the previously performed operation, the new operation, and the new value to another processor). In these implementations, aggregation can significantly reduce snooping (e.g., because a given cache can aggregate multiple operations before a snooping is required), which can improve performance by avoiding snooping latency, at least in some cases.

[0069] Example Method

[0070] Figure 6 This is a flowchart illustrating an example method for atomic polymerization according to some implementation schemes. Figure 6 The methods shown can be used in conjunction with any of the computer circuits, systems, devices, elements, or components disclosed herein. In various embodiments, some of the method elements shown may be executed concurrently in a different order than shown, or may be omitted. Additional method elements may also be executed as needed.

[0071] At 610, in the illustrated embodiment, the computing device (e.g., cache control 310) caches the data values ​​in a cache store (e.g., cached in cache circuitry 210).

[0072] At 620, in the illustrated implementation, the computing device receives multiple requests to atomically update cached data values ​​based on one or more arithmetic operations. Some of these requests may originate from different SIMD groups. Some of these requests may originate from different thread groups. Requests from different SIMD groups or thread groups may correspond to different programs (e.g., shaders). These requests may arrive at different times while the atomic aggregation results are cached.

[0073] At 630, in an exemplary implementation, in response to determining that the one or more arithmetic operations satisfy one or more criteria, the computing device performs an update to the data value in the cache based on the multiple requests. In some implementations, cache control circuitry for cache storage includes one or more ALUs configured to perform arithmetic operations. These ALUs may be different from the ALUs in the execution units of the processor pipeline and may be configured to perform only a subset of the arithmetic operations that the entire processor is configured to perform. Updates may be used for atomic operations that do not request a return value (other atomic operations may cause conflicts).

[0074] Standards may include one or more relationships between the current arithmetic operation and the most recently requested atomic arithmetic operation (e.g., the operations are the same operations, the operations are a set of operations (e.g., commutative operations), etc.), one or more relationships between data types, etc.

[0075] At 640, in the illustrated embodiment, the computing device stores operation information indicating the most recently requested atomic arithmetic operation for an updated data value. The device may store metadata, including the operation information, along with the corresponding updated data value in a cache line. The metadata may also indicate: whether one or more values ​​in the cache line correspond to an atomic operation, one or more data types corresponding to the atomic operation, valid indicators for different portions of the cache line, or a combination thereof. The device may maintain the metadata at the cache line granularity.

[0076] At 650, in the illustrated implementation, the computing device responds to an event to refresh the following information to a higher level in the memory hierarchy, including cache storage circuitry: the updated data value and operation information.

[0077] The event can be a cache eviction or cache maintenance operation. The event can also be a first request with a first arithmetic operation that does not meet one or more criteria. After a refresh, the device can store the data used for the first request (e.g., the algebraic identity value corresponding to the first arithmetic operation) in the cache storage circuitry based on the first arithmetic operation, and update the operation information to reflect the first arithmetic operation.

[0078] The higher levels in a memory hierarchy can be a consistency point used to request an atomic update of cached data values. The higher levels can include circuitry (e.g., one or more ALUs) configured to perform operations indicated by refreshed operation information on input values, including the updated data value and data values ​​stored in the higher levels of the memory hierarchy.

[0079] The concept of “execution” is broad and can refer to 1) the processing of instructions throughout the entire execution pipeline (e.g., through fetch, decode, execute, and rollback stages), and 2) the processing of instructions at an execution unit or execution subsystem of such a pipeline (e.g., an integer execution unit or a load-memory unit). The latter meaning can also be referred to as a “perform” instruction. Thus, a “perform” addition instruction refers to adding two operands to produce a result, which in some implementations can be achieved by circuitry at the execution stage of the pipeline (e.g., an execution unit). Conversely, “execute” an addition instruction can refer to the entire operation that occurs throughout the pipeline as a result of an addition instruction. Similarly, a “perform” “load” instruction may include (e.g., retrieving a value from a cache, memory, or the stored result of another instruction) and storing the retrieved value in a register or other location.

[0080] As used herein, in the context of instructions, the term "completion" refers to the submission of the result of an instruction to the architectural state of the processor or processing element. For example, the completion of an addition instruction includes writing the result of the addition instruction to the destination register. Similarly, the completion of a load instruction includes writing a value (e.g., a value retrieved from a cache or memory) to the destination register or its representation.

[0081] The concept of a processor "pipeline" is well-known and refers to the division of the "work" a processor does on instructions into multiple stages. In some implementations, instruction decoding, dispatching, execution (i.e., performing), and rollback can be examples of different pipeline stages. Many different pipeline architectures may have different element / part orders. Various pipeline stages perform these steps on instructions during one or more processor clock cycles, then pass the instruction or the operation associated with the instruction to other stages for further processing.

[0082] Example device

[0083] Now for reference Figure 7The diagram illustrates a block diagram of an example embodiment of device 700. In some embodiments, the components of device 700 may be included within a system-on-a-chip. In some embodiments, device 700 may be included in a mobile device that may be battery-powered. Therefore, the power consumption of device 700 may be an important design consideration. In the illustrated embodiment, device 700 includes a structure 710, a computing complex 720, an input / output (I / O) bridge 750, a cache / memory controller 745, a graphics unit 775, and a display unit 765. In some embodiments, as a supplement to or alternative to the illustrated components, device 700 may also include other components (not shown), such as video processor encoders and decoders, image processing or recognition elements, computer vision elements, etc.

[0084] Structure 710 may include various interconnects, buses, MUXs, controllers, etc., and may be configured to facilitate communication between various components of device 700. In some embodiments, portions of structure 710 may be configured to implement various different communication protocols. In other embodiments, structure 710 may implement a single communication protocol, and components coupled to structure 710 may internally switch from a single communication protocol to other communication protocols.

[0085] In the illustrated embodiments, computing complex 720 includes a bus interface unit (BIU) 725, a cache 730, and cores 735 and 740. In various embodiments, computing complex 720 may include a variety of numbers of processors, processor cores, and caches. For example, computing complex 720 may include one, two, four, or any other suitable number of processor cores. In one embodiment, cache 730 is a set-associative L2 cache. In some embodiments, cores 735 and 740 may include internal instruction and data caches. In some embodiments, coherence units (not shown) in architecture 710, cache 730, or elsewhere in device 700 may be configured to maintain coherence between the various caches of device 700. BIU 725 may be configured to manage communication between computing complex 720 and other elements of device 700. Processor cores (such as cores 735 and 740) may be configured to execute instructions of a specific instruction set architecture (ISA) that may include operating system instructions and user application instructions. These instructions can be stored in a computer-readable medium, such as memory coupled to the memory controller 745 discussed below.

[0086] In some implementations, the computational composite 720 implements the disclosed atomic polymerization technique, which can improve performance, reduce power consumption, or both.

[0087] As used herein, the term "coupled to" can indicate one or more connections between elements, and coupling can include intermediate elements. For example, in Figure 7 In this context, the graphics unit 775 can be described as being "coupled" to memory via structure 710 and cache / memory controller 745. In contrast, in... Figure 7 In the exemplary implementation, the graphics unit 775 is "directly coupled" to the structure 710 because there are no intermediate elements.

[0088] The cache / memory controller 745 can be configured to manage data transfer between the structure 710 and one or more caches and memories. For example, the cache / memory controller 745 may be coupled to an L3 cache, which in turn may be coupled to system memory. In other embodiments, the cache / memory controller 745 may be directly coupled to memory. In some embodiments, the cache / memory controller 745 may include one or more internal caches. The memory coupled to the controller 745 can be any type of volatile memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), dual data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, etc., and / or low-power versions of SDRAM, such as LPDDR4, etc.), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices may be coupled onto a circuit board to form a memory module, such as a single in-line memory module (SIMM), a dual in-line memory module (DIMM), etc. Alternatively, these devices can be mounted with integrated circuits in a chip-stacked configuration, a package-stacked configuration, or a multi-chip module configuration. The memory coupled to the controller 745 can be any type of non-volatile memory, such as NAND flash memory, NOR flash memory, nanometer RAM (NRAM), magnetoresistive RAM (MRAM), phase-change RAM (PRAM), raceway memory, memristor memory, etc. As noted above, the memory can store program instructions executable by the computing complex 720 to cause the computing device to perform the functionality described herein.

[0089] The graphics unit 775 may include one or more processors, such as one or more graphics processing units (GPUs). For example, the graphics unit 775 may receive graphics-oriented instructions, such as OpenGL. ® Metal or Direct3D ®Instructions. The graphics unit 775 can execute dedicated GPU instructions or perform other operations based on received graphics-oriented instructions. The graphics unit 775 is typically configured to process large blocks of data in parallel and can construct an image in a framebuffer for output to a display, which may be included in a device or may be a separate device. The graphics unit 775 may include a transformation engine, a lighting engine, a triangle engine, and a rendering engine in one or more graphics processing pipelines. The graphics unit 775 can output pixel information for displaying the image. In various embodiments, the graphics unit 775 may include programmable shader circuitry, which may include highly parallel execution cores configured to execute graphics programs, which may include pixel tasks, vertex tasks, and computation tasks (which may be graphics-dependent or not).

[0090] In some implementations, the graphics unit 775 implements the disclosed atomic polymerization technique, which can improve performance, reduce power consumption, or both.

[0091] Display unit 765 can be configured to read data from a frame buffer and provide a stream of pixel values ​​for display. In some embodiments, display unit 765 can be configured as a display pipeline. Additionally, display unit 765 can be configured to blend multiple frames to produce an output frame. Furthermore, display unit 765 may include one or more interfaces (e.g., MIPI) for coupling to a user display (e.g., a touchscreen or an external display). ® Or embedded display port (eDP)).

[0092] I / O bridge 750 may include various components configured to implement functionalities such as Universal Serial Bus (USB) communication, security, audio, and low-power always-on connectivity. I / O bridge 750 may also include interfaces such as pulse-width modulation (PWM), general-purpose input / output (GPIO), serial peripheral interface (SPI), and internal integrated circuit (I2C). Various types of peripheral devices and equipment can be coupled to device 700 via I / O bridge 750.

[0093] In some embodiments, device 700 includes network interface circuitry (not explicitly shown) that can be connected to structure 710 or I / O bridge 750. This network interface circuitry can be configured to communicate via various networks, which can be wired networks, wireless networks, or both. For example, the network interface circuitry can be configured to communicate via a wired local area network (LAN), a wireless LAN (e.g., via Wi-Fi), or Wi-Fi. ™The network interface circuitry can communicate via one or more cellular networks using one or more radio access technologies, or wide area networks (e.g., the Internet or a virtual private network). In some embodiments, the network interface circuitry is configured to communicate via one or more cellular networks using one or more radio access technologies. In some embodiments, the network interface circuitry is configured to use device-to-device communication (e.g., Bluetooth). ® or Wi-Fi ™ Communication can be achieved through direct connection, etc. In various implementations, this network interface circuit can provide device 700 with connectivity to various types of other devices and networks.

[0094] Example Application

[0095] Now go to Figure 8 This illustrates various types of systems that may include any of the circuits, devices, or systems discussed above. The system or device 800, which may utilize one or more of the techniques described herein in combination with or otherwise, can be used in a wide range of fields. For example, the system or device 800 may be used as part of the hardware of a system such as a desktop computer 810, a laptop computer 820, a tablet computer 830, a cellular or mobile phone 840, or a television 850 (or a set-top box coupled to a television).

[0096] Similarly, the disclosed components can be used in wearable devices 860, such as smartwatches or health monitoring devices. In many embodiments, a smartwatch can perform a variety of different functions—for example, access to email, cellular services, calendars, health monitoring, etc. Wearable devices can also be designed to perform only health monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communications to emergency medical services, etc. Other types of devices are also envisioned, including devices worn around the neck, implantable devices, and glasses or helmets designed to provide computer-generated reality experiences, such as those based on augmented reality and / or virtual reality.

[0097] System or device 800 can also be used in a variety of other contexts. For example, system or device 800 can be used in the context of a server computer system (such as a dedicated server) or on shared hardware implementing cloud-based services 870. Furthermore, system or device 800 can be implemented in a wide range of dedicated everyday devices, including common household devices 880 such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is often referred to as the “Internet of Things” (IoT). Components can also be implemented in various modes of transportation. For example, system or device 800 can be used in control systems, guidance systems, entertainment systems, etc., of various types of vehicles 890.

[0098] Figure 8The applications illustrated herein are merely exemplary and are not intended to limit the potential future applications of the disclosed systems or devices. Other example applications include, but are not limited to, portable gaming devices, music players, data storage devices, and unmanned aerial vehicles.

[0099] Example computer-readable media

[0100] Various example circuits have been described in detail above in this disclosure. It is intended that this disclosure cover not only embodiments including such circuits, but also computer-readable storage media that include design information specifying such circuits. Therefore, this disclosure is intended to support claims that cover not only devices including the disclosed circuits, but also storage media specifying such circuits in a format recognized by a computing system configured to generate a simulation model of hardware circuitry, a manufacturing system configured to generate hardware (e.g., integrated circuits) including the disclosed circuits. Claims regarding such storage media are intended to cover entities that, for example, generate circuit designs but do not themselves perform complete operations (such as design simulation, design synthesis, circuit fabrication, etc.).

[0101] Figure 9 This is a block diagram illustrating an example non-transitory computer-readable storage medium storing circuit design information according to some embodiments. In the illustrated embodiment, a computing system 940 is configured to process the design information. This may include executing instructions included in the design information, interpreting instructions included in the design information, compiling, transforming, or otherwise updating the design information. Thus, in some embodiments, the design information (e.g., by programming the computing system 940) controls the computing system 940 to perform various operations discussed below.

[0102] In the illustrated example, computing system 940 processes the design information to generate both a computer simulation model of hardware circuitry 960 and lower-level design information 950. In other embodiments, computing system 940 may generate only one of these outputs, may generate other outputs based on the design information, or both. Regarding the computational simulation, computing system 940 may execute instructions in a hardware description language, which includes register-transfer-level (RTL) code, behavioral code, structural code, or some combination thereof. The simulation model may perform the functionality specified by the design information, facilitate verification of the functional correctness of the hardware design, generate power consumption estimates, generate timing estimates, etc.

[0103] In the illustrated example, computing system 940 further processes the design information to generate lower-level design information 950 (e.g., gate-level design information, netlists, etc.). As shown, this may include synthesis operations such as constructing multi-level networks, optimizing the network using technology-independent techniques, technology-dependent techniques, or both, and outputting a gate network (with potential constraints based on a library of available gate pairs, size adjustments, delays, power, etc.). Based on the lower-level design information 950 (and potentially other inputs), semiconductor manufacturing system 920 is configured to manufacture integrated circuit 930 (which may correspond to the functionality of analog model 960). Note that computing system 940 can generate different analog models based on design information at various descriptive levels (including information 950, 915, etc.). Data representing design information 950 and model 960 may be stored on medium 910 or one or more other media.

[0104] In some embodiments, lower-level design information 950 controls (e.g., programs) the semiconductor manufacturing system 920 to manufacture integrated circuit 930. Therefore, when processed by the manufacturing system, the design information can program the manufacturing system to manufacture circuits including the various circuits disclosed herein.

[0105] The non-transitory computer-readable storage medium 910 may include any of a variety of suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 910 may be an installation medium, such as a CD-ROM, floppy disk, or magnetic tape device; computer system memory or random access memory, such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; non-volatile memory, such as flash memory; magnetic media, such as hard disk drives or optical storage devices; registers, or other similar types of memory elements. The non-transitory computer-readable storage medium 910 may also include other types of non-transitory memory or combinations thereof. Therefore, the non-transitory computer-readable storage medium 910 may include two or more memory media; such media may reside in different locations—for example, in different computer systems connected via a network.

[0106] Design information 915 can be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. The formats of various design information can be recognized by one or more applications executed by computing system 940, semiconductor manufacturing system 920, or both. In some embodiments, design information may also include one or more cell libraries specifying the composition, layout, or both of integrated circuit 930. In some embodiments, design information is specified wholly or partially in the form of a netlist specifying cell library elements and their connectivity. Individually, the design information discussed herein may or may not include sufficient information for manufacturing the corresponding integrated circuit. For example, design information may specify circuit elements to be manufactured but not their physical layout. In this case, design information may need to be combined with layout information to actually manufacture the specified circuit.

[0107] In various implementations, integrated circuit 930 may include one or more custom macrocells, such as memory and analog or mixed-signal circuitry. In this case, design information may include information associated with the included macrocells. Such information may include, but is not limited to, schematic capture databases, mask design data, behavioral models, and device or transistor-level netlists. Mask design data may be formatted according to a Graphical Data System (GDSII) or any other suitable format.

[0108] The semiconductor manufacturing system 920 may include any of the various suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of the deposited material, modifying the material (e.g., by doping the material or by using ultraviolet treatment to modify the dielectric constant), etc. The semiconductor manufacturing system 920 may also be configured to perform various tests on the manufactured circuits to ensure proper operation.

[0109] In various embodiments, integrated circuit 930 and model 960 are configured to operate according to a circuit design specified by design information 915, which may include performing any of the functionalities described herein. For example, integrated circuit 930 may include Figure 1B , Figures 2 to 3 and Figure 7 Any of the various components shown. Additionally, integrated circuit 930 can be configured to perform the various functions described herein in conjunction with other components. Furthermore, the functionality described herein can be performed by multiple interconnected integrated circuits.

[0110] As used herein, a phrase in the form of “design information specifying a circuit configured to…” does not imply that the circuit in question must be manufactured to satisfy the element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated action or will include the specified components. Similarly, stating that “instructions of a hardware description programming language” are “executable” to program a computing system to generate a computer simulation model does not mean that the instructions must be executed to satisfy the element, but rather specifies the characteristics of those instructions. In this case, additional features associated with the model (or the circuit represented by the model) may similarly relate to the characteristics of those instructions. Therefore, an entity selling a computer-readable medium having instructions that satisfy the stated characteristics may provide an infringing product even if another entity actually executes those instructions on the medium.

[0111] It should be noted that, at least in the context of digital logic, a given design can be implemented using a variety of different gate arrangements, circuit techniques, etc. However, once a digital logic design is specified, those skilled in the art do not need to perform extensive experiments or studies to determine those specific implementations. Instead, they understand the process for reliably and predictably producing one or more circuit implementations that provide the functionality described by the design information. Different circuit implementations may affect the performance, area, power consumption, etc., of a given design (potentially involving trade-offs between different design goals), but the logical function remains unchanged between different circuit implementations of the same circuit design.

[0112] In some implementations, instructions included in the design information instructions provide RTL information (or other higher-level design information) and can be executed by a computing system to synthesize a gate-level netlist representing the hardware circuitry based on the RTL information as input. Similarly, these instructions provide behavioral information and can be executed by the computing system to synthesize netlists or other lower-level design information. This lower-level design information can be used to program the manufacturing system 920 to manufacture the integrated circuit 930.

[0113]

[0114] The various techniques described herein can be executed by one or more computer programs. The term "program" will be broadly interpreted to encompass a sequence of instructions in a programming language executable by a computing device. These programs can be written in any suitable computer language, including lower-level languages ​​such as assembly and higher-level languages ​​such as Python. The program can be written in a compiled language such as C or C++ or an interpreted language such as JavaScript.

[0115] Program instructions may be stored on a “computer-readable storage medium” or “computer-readable medium” to facilitate execution of those instructions by a computer system. Generally, these phrases include any tangible or non-transitory storage medium or memory medium. The terms “tangible” and “non-transitory” are intended to exclude the propagation of electromagnetic signals but do not otherwise limit the type of storage medium. Therefore, the phrase “computer-readable storage medium” or “computer-readable medium” is intended to cover types of storage devices that do not necessarily store information permanently (e.g., random access memory (RAM)). Thus, the term “non-transitory” is a limitation on the nature of the medium itself (i.e., the medium cannot be a signal), which contrasts with limitations on the persistence of data storage in media (e.g., RAM and ROM).

[0116] The phrases “computer-readable storage medium” and “computer-readable medium” are intended to refer to storage media within a computer system as well as removable media such as CD-ROMs, Memory Sticks, or portable hard disk drives. These phrases encompass any type of volatile memory within a computer system, including DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc., as well as non-volatile memory such as magnetic media (e.g., hard disk drives) or optical storage devices. These phrases are explicitly intended to cover the memory of servers that facilitate the download of program instructions, the memory within any intermediate computer systems involved in the download, and the memory of all destination computing devices. Furthermore, these phrases are intended to cover combinations of different types of memory.

[0117] Furthermore, the computer-readable medium or storage medium may reside on one or more computer systems in a first group in which a program is executed, and on one or more computer systems in a second group connected to the first group via a network. In a later example, the second group of computer systems may provide program instructions to the first group of computer systems for execution. In short, the phrases "computer-readable storage medium" and "computer-readable medium" can include two or more media that may reside in different locations (e.g., in different computers connected via a network).

[0118] This disclosure includes references to “implementation” or groups of “implementation” (e.g., “some implementations” or “various implementations”). An implementation is a different specific implementation or instance of the disclosed concepts. References to “implementation,” “an implementation,” and “a particular implementation,” etc., do not necessarily refer to the same implementation. A large number of possible implementations are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the substance or scope of this disclosure.

[0119] This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all specific implementations of all these embodiments will necessarily exhibit any or all of the potential advantages. Whether a particular embodiment achieves an advantage depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an embodiment falling within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular embodiment may include other circuitry outside the scope of this disclosure, in conjunction with one embodiment of the disclosed embodiments, which negates or diminishes one or more of the disclosed advantages. Furthermore, suboptimal design execution of a particular embodiment (e.g., the implementing technique or tool) may also negate or diminish the disclosed advantages. Even assuming an implementation of the technique, the realization of advantages may still depend on other factors, such as the environmental circumstances in which the implementation is deployed. For example, the inputs provided to a particular embodiment may prevent one or more problems addressed in this disclosure from occurring in a particular context, and as a result, the benefits of its solution may not be realized. In view of the existence of possible factors outside this disclosure, it is hereby expressed that any potential advantages described herein should not be construed as a limitation of the claims that must be satisfied in order to prove infringement. Rather, the identification of such potential advantages is intended to illustrate the types of improvements available to the designer who benefits from this disclosure. Describing such advantages permanently (e.g., stating that a particular advantage "may occur") is not intended to convey a question about whether such advantages can actually be realized, but rather to recognize that the realization of such advantages often depends on the technological reality of additional factors.

[0120] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on this disclosure, even where only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative and not restrictive, without any statement to the contrary in this disclosure. Therefore, this application is intended to allow for claims covering the disclosed embodiments, as well as such alternatives, modifications, and equivalents, which will be apparent to those skilled in the art to the advantage of this disclosure.

[0121] For example, features in this application can be combined in any suitable manner. Therefore, new claims may be made for any such combination of features during the filing of this application (or an application claiming priority thereto). Specifically, referring to the appended claims, features of dependent claims may be combined with features of other dependent claims, including claims dependent on other independent claims, where appropriate. Similarly, features from the respective independent claims may be combined where appropriate.

[0122] Thus, although the appended dependent claims may be drafted such that each dependent claim depends from a single other claim, additional dependencies are also contemplated. Any combination of dependent features consistent with the present disclosure is contemplated and such combinations may be claimed in this application or another application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0123] In appropriate cases, it is also contemplated that a claim drafted in one format or statutory type (e.g., apparatus) is intended to support a corresponding claim in another format or statutory type (e.g., method).

[0124]

[0125] Since the present disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the following paragraphs, as well as the definitions provided throughout the present disclosure, will be used to determine how claims drafted based on the present disclosure are to be interpreted.

[0126] Unless the context clearly dictates otherwise, references to items in the singular form (i.e., a noun or noun phrase preceded by "a", "an", or "the") are intended to mean "one or more". Thus, without accompanying context, a reference to an "item" in a claim does not exclude additional instances of that item. "Multiple" items refers to a collection of two or more items in the set of items.

[0127] The word "may" is used herein in an allowable sense (i.e., having the potential to be able to), rather than in a mandatory sense (i.e., must).

[0128] The terms "comprising" and "including" and their forms are open-ended and mean "including but not limited to".

[0129] When the term "or" is used in the present disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context otherwise provides. Thus, the statement "x or y" is equivalent to "x or y, or both" and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either x or y, but not both" make clear that "or" is used in an exclusive sense.

[0130] The expressions “w, x, y, or z, or any combination thereof” or “...at least one of w, x, y, and z” are intended to cover all possibilities involving a single element up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase “...at least one of w, x, y, and z” therefore refers to at least one element in the set [w, x, y, z], thus covering all possible combinations of that list of elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0131] In this disclosure, various “labels” may precede nouns or noun phrases. Unless the context otherwise provides, different labels used for features (e.g., “first circuit,” “second circuit,” “specific circuit,” “given circuit,” etc.) refer to different instances of the feature. Additionally, unless otherwise stated, the labels “first,” “second,” and “third” do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0132] The phrase "based on" is used to describe one or more factors that influence the determination. This term does not exclude the possibility that additional factors might influence the determination. That is, the determination may be based solely on the specified factors or on the specified factors along with other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover implementations where A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on."

[0133] The phrases “responding to” and “responding” describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, whether these factors are used in conjunction with or independently of the specified factor. That is, the effect may respond solely to these factors, or it may respond to the specified factor as well as other unspecified factors. Consider the phrase “responding to B and executing A.” This phrase specifies that B is a factor that triggers the execution of A or triggers a specific result of A. This phrase does not exclude that the execution of A may also respond to certain other factors, such as C. This phrase also does not exclude that the execution of A may be jointly executed in response to B and C. This phrase is also intended to cover implementation schemes where A is executed solely in response to B. As used herein, the phrase “responding” is synonymous with the phrase “at least partially responding to.” Similarly, the phrase “responding to” is synonymous with the phrase “at least partially responding to.”

[0134]

[0135] Within this disclosure, different entities (which may be referred to differently as “units,” “circuits,” other components, etc.) may be described or protected by the claims as being “configured” to perform one or more tasks or operations. This expression—[entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a tangible thing). More specifically, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be considered “configured” to perform a task even if the structure is not currently being operated. Thus, an entity described or stated as being “configured” to perform a task refers to tangible things such as devices, circuits, systems with processor units, and memory storing program instructions executable to perform the task. This phrase is not used herein to refer to intangible things.

[0136] In some cases, various units / circuits / components may be described herein as a collection of entities that perform tasks or operations. It should be understood that these entities are "configured" to perform those tasks / operations, even if not specifically stated otherwise.

[0137] The term "configured as" is not intended to mean "able to be configured as." For example, an unprogrammed FPGA is not considered "configured as" to perform a specific function. However, the unprogrammed FPGA can be "configurable as" to perform that function. After proper programming, the FPGA can then be considered "configured as" to perform a specific function.

[0138] For the purposes of this U.S. patent application based on this disclosure, the statement in the claims that a structure is “configured” to perform one or more tasks is expressly intended not to invoke 35 USC § 112(f) for that claim element. If an applicant wishes to invoke part 112(f) during the filing of a U.S. patent application based on this disclosure, it will use the “component for [performing a function]” structure to state the elements of the claims.

[0139] Different “circuits” may be described in this disclosure. These circuits, or “circuits”, constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom-designed or taken from standard libraries. In various specific implementations, circuits may include digital components, analog components, or a combination of both, depending on the circumstances. Certain types of circuits may be commonly referred to as “cells” (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such cells also refer to circuits or circuitry.

[0140] Therefore, the circuits / units / components and other elements illustrated in the accompanying drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the function of that circuit. For example, a particular “decoding unit” can be described as having the function of executing “the opcode of a processing instruction and routing that instruction to one or more of a plurality of functional units,” meaning that the decoding unit is “configured” to perform that function. To those skilled in the art of computers, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0141] In various implementations, as discussed in the preceding paragraphs, circuits, cells, and other elements can be defined by the functions or operations they are configured to perform. The arrangement of these circuits / cells / components relative to each other and the manner in which they interact form a microarchitecture definition of hardware, which is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, a microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall within the broader structure described by the microarchitecture definition. That is, those skilled in the art, with the microarchitecture definition provided according to this disclosure, can implement this structure without excessive experimentation and using the application of a person of ordinary skill in the art, by encoding the description of the circuits / cells / components in a hardware description language (HDL) such as Verilog or VHDL. The HDL description is often expressed in a way that can be revealed as functional. However, for those skilled in the art, the HDL description is a way of translating the structure of a circuit, cell, or component into the details of the next level of implementation. Such HDL descriptions can take the following forms: behavioral code (which is typically non-synthesizable), Register Transfer Language (RTL) code (which is typically synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). HDL descriptions can be sequentially synthesized against a library of cells designed for a given integrated circuit manufacturing technology and can be modified for timing, power, and other reasons to obtain a final design database that is sent to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuitry or portions thereof can also be custom-designed in a schematic editor and captured into the integrated circuit design along with the synthesized circuitry. The integrated circuit can include transistors and other circuit elements (e.g., passive components such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some implementations may implement multiple integrated circuits coupled together to implement the hardware circuitry, and / or discrete components may be used in some implementations. Alternatively, the HDL design can be synthesized into a programmable logic array such as a Field Programmable Gate Array (FPGA) and implemented within the FPGA. This decoupling between the design of a set of circuits and their subsequent low-level implementations often results in a situation where the circuit or logic designer never specifies a particular set of structures for the low-level implementation that goes beyond a description of what the circuit is configured to do, because that process is performed at different stages of the circuit implementation process.

[0142] The fact that a circuit can be implemented to the same specifications using many different low-level combinations of circuit elements results in a large number of equivalent circuit structures. As noted, these low-level circuit implementations can vary depending on the manufacturing technology, the foundry chosen to manufacture the integrated circuit, the cell library provided for a particular project, and so on. In many cases, the choice of different design tools or methods to produce these different implementations can be arbitrary.

[0143] Furthermore, for a given implementation, a single concrete implementation of the circuit's specific functional specifications typically involves a large number of devices (e.g., millions of transistors). Therefore, the shearing volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single implementation, let alone a large number of equivalent possible implementations. To this end, this disclosure describes the structure of a circuit using functional abbreviations commonly used in industry.

Claims

1. An apparatus, the apparatus comprising: Cache storage circuit; The cache control circuit is configured to: The data values ​​are cached in the cache storage circuit. Receive multiple requests to atomically update cached data values ​​based on one or more arithmetic operations; In response to determining that the one or more arithmetic operations satisfy one or more criteria, an update to the cached data value is performed based on the plurality of requests; Store operation information indicating the most recently requested atomic arithmetic operation for the updated data value; as well as In response to the event, the following items are refreshed to the higher level of the memory hierarchy that includes the cache storage circuitry: The updated data values; and The operation information.

2. The apparatus of claim 1, wherein the cache control circuit includes an arithmetic logic unit circuit configured to perform the arithmetic operation.

3. The apparatus according to claim 1, wherein: The event is a first request having a first arithmetic operation that does not meet one or more of the criteria; and The cache control circuit is also configured to, after the refresh: Based on the first arithmetic operation, the data used for the first request is stored in the cache storage circuit; and Update the operation information to reflect the first arithmetic operation.

4. The apparatus according to claim 1, wherein: The higher levels in the memory hierarchy are consistency points used for the request to atomically update cached data values; and The higher level in the memory hierarchy includes circuitry configured to perform the operation indicated by refreshed operation information on an input value, the input value including the updated data value and the data value stored in the higher level of the memory hierarchy.

5. The apparatus of claim 1, wherein the cache control circuit is configured to store metadata including the operation information together with the corresponding updated data value in a cache line.

6. The apparatus of claim 5, wherein the metadata further indicates: Whether one or more values ​​in the cache line correspond to an atomic operation; The cache line contains one or more data types corresponding to one or more values ​​of atomic operations; and The valid indicators for different parts of the cache line.

7. The apparatus of claim 5, wherein the cache control circuitry is configured to maintain the metadata at the cache line granularity.

8. The apparatus of claim 1, wherein the event is a cache eviction or cache maintenance operation.

9. The apparatus of claim 1, wherein the cache control circuitry is configured to perform the update for atomic operations that do not request a return value.

10. The apparatus of claim 1, wherein at least some of the plurality of requests come from different Single Instruction Multiple Data (SIMD) groups.

11. The apparatus of claim 1, wherein at least some of the plurality of requests originate from different thread groups corresponding to different programs.

12. The apparatus of claim 1, wherein the one or more criteria comprise: One or more relationships between the current arithmetic operation and the most recently requested atomic arithmetic operation; and One or more relationships between data types.

13. A method, the method comprising: The computing system caches the data values ​​in cache storage; The computing system receives multiple requests to atomically update cached data values ​​based on one or more arithmetic operations; In response to determining that the one or more arithmetic operations satisfy one or more criteria, the computing system performs an update on the cached data values ​​based on the plurality of requests; The computing system stores operation information indicating the most recently requested atomic arithmetic operation for the updated data value; as well as In response to the event, the computing system refreshes the following to a higher level in the memory hierarchy, including the cache storage: The updated data values; and The operation information.

14. The method of claim 13, wherein the event is a first request having a first arithmetic operation that does not satisfy one or more of the criteria, the method further comprising, after the refresh: The computing system, based on the first arithmetic operation, stores the data used for the first request in the cache storage; and The computing system updates the operation information to reflect the first arithmetic operation.

15. The method of claim 13, wherein the higher level in the memory hierarchy is a consistency point for the request to atomically update cached data values, the method further comprising: The higher level in the memory hierarchy includes circuitry that performs the operation indicated by refreshed operation information on an input value, the input value including the updated data value and the data value stored in the higher level of the memory hierarchy.

16. The method of claim 13, wherein at least some of the plurality of requests originate from different thread groups corresponding to different programs.

17. The method of claim 13, wherein the one or more criteria comprise: One or more relationships between the current arithmetic operation and the most recently requested atomic arithmetic operation; as well as One or more relationships between data types.

18. A non-transitory computer-readable medium storing instructions of a hardware description programming language, which, when processed by a computing system, program the computing system to generate a computer simulation model, wherein the model represents hardware circuitry comprising: Cache storage circuit; The cache control circuit is configured to: The data values ​​are cached in the cache storage circuit. Receive multiple requests to atomically update cached data values ​​based on one or more arithmetic operations; In response to determining that the one or more arithmetic operations satisfy one or more criteria, an update to the cached data value is performed based on the plurality of requests; Store operation information indicating the most recently requested atomic arithmetic operation for the updated data value; as well as In response to the event, the following items are refreshed to the higher level of the memory hierarchy that includes the cache storage circuitry: The updated data values; and The operation information.

19. The non-transitory computer-readable medium according to claim 18, wherein: The event is a first request having a first arithmetic operation that does not meet one or more of the criteria; and The cache control circuit is also configured to, after the refresh: Based on the first arithmetic operation, the data used for the first request is stored in the cache storage circuit; and Update the operation information to reflect the first arithmetic operation.

20. The non-transitory computer-readable medium of claim 18, wherein at least some of the plurality of requests originate from different thread groups corresponding to different programs.

Images