Vehicle-mounted millimeter wave radar data access method and device, equipment and storage medium

Abstract

The invention discloses a vehicle-mounted millimeter wave radar data access method and device, equipment and a storage medium, and relates to the technical field of vehicle-mounted millimeter wave radars. The method comprises the steps that an access request is acquired, and the access request comprises a logic address of data to be accessed and a corresponding access type; distributing the priority of each port corresponding to the access type according to preset access priorities, wherein the preset access priorities comprise that the priority of write access is higher than that of read access, the priorities of one-dimensional, two-dimensional and non-one-two-dimensional data write access are sequentially reduced, and the priorities of two-dimensional, non-one-two-dimensional and one-dimensional data read access are sequentially reduced; according to the priority of each port, calling each port in sequence to carry out bus address mapping on the logic address to obtain a bus address; and accessing the to-be-accessed data in the memory according to the bus address. According to the method and the device, the problem of bandwidth allocation caused by interleaving of different types of data access of multiple ports is avoided, so that the bandwidth utilization rate is improved.

Description

Technical Field

[0001] This application belongs to the field of vehicle-mounted millimeter-wave radar technology, and particularly relates to a method, apparatus, device and storage medium for accessing vehicle-mounted millimeter-wave radar data. Background Technology

[0002] Automotive 4D (4D) high-resolution millimeter-wave radar, also known as automotive 4D imaging millimeter-wave radar, or simply automotive 4D imaging radar, refers to information in four dimensions: range, velocity, horizontal angle, and pitch angle or elevation.

[0003] Compared to traditional automotive millimeter-wave radar (three-dimensional "range, azimuth, and velocity"), automotive 4D millimeter-wave radar offers the advantage of high resolution, meaning it provides higher resolution of targets in both the range and angular dimensions. The resulting clusters of scattered points are dozens of times larger than those of traditional automotive millimeter-wave radar, typically tens of thousands of points per second (15-20 frames), according to current radar manufacturers' product specifications. This dense combination of scattered points is called a point cloud, which can, to a certain extent, represent the outline of the target, achieving an "imaging" effect.

[0004] In related technologies, when accessing data from vehicle-mounted 4D millimeter-wave radar, the interweaving of different types of data access from multiple ports leads to bandwidth allocation issues, resulting in low bandwidth utilization. Summary of the Invention

[0005] The purpose of this application is to provide a method, apparatus, device, and storage medium for accessing vehicle-mounted millimeter-wave radar data, in order to solve the problem of bandwidth allocation caused by the interweaving of different types of data access across multiple ports in related technologies, which in turn leads to low bandwidth utilization.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] In a first aspect, embodiments of this application provide a method for accessing vehicle-mounted millimeter-wave radar data, comprising: obtaining an access request, wherein the access request includes a logical address of the data to be accessed and a corresponding access type, the access type including at least one of the following: one-dimensional data write access, two-dimensional data write access, non-one-dimensional / two-dimensional data write access, one-dimensional data read access, two-dimensional data read access, and non-one-dimensional / two-dimensional data read access; allocating a priority to each port corresponding to the access type according to a preset access priority, wherein the preset access priority includes: the priority of write access is higher than the priority of read access, the priority of one-dimensional data write access, the priority of two-dimensional data write access, and the priority of non-one-dimensional / two-dimensional data write access decreases sequentially, and the priority of two-dimensional data read access, the priority of non-one-dimensional / two-dimensional data read access, and the priority of one-dimensional data read access decreases sequentially; according to the priority of each port, sequentially calling each port to perform bus address mapping on the corresponding logical address of the data to be accessed, to obtain the bus address of the data to be accessed in the memory; and accessing the data to be accessed in the memory according to the bus address.

[0008] Secondly, embodiments of this application provide an access device for vehicle-mounted millimeter-wave radar data, comprising: an acquisition module, configured to acquire an access request, the access request including a logical address of the data to be accessed and a corresponding access type, the access type including at least one of the following: one-dimensional data write access, two-dimensional data write access, non-one-dimensional / two-dimensional data write access, one-dimensional data read access, two-dimensional data read access, and non-one-dimensional / two-dimensional data read access; an allocation module, configured to allocate a priority to each port corresponding to the access type according to a preset access priority, the preset access priority including: the priority of write access is higher than the priority of read access, the priority of one-dimensional data write access, the priority of two-dimensional data write access, and the priority of non-one-dimensional / two-dimensional data write access decreases sequentially, and the priority of two-dimensional data read access, the priority of non-one-dimensional / two-dimensional data read access, and the priority of one-dimensional data read access decreases sequentially; a mapping module, configured to sequentially call each port to perform bus address mapping on the logical address of the corresponding data to be accessed according to the priority of each port, to obtain the bus address of the data to be accessed in the memory; and an access module, configured to access the data to be accessed in the memory according to the bus address.

[0009] Thirdly, embodiments of this application provide an electronic device, including: a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the method described in the first aspect of this application.

[0010] Fourthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the method described in the first aspect of this application.

[0011] The above-described technical solutions adopted in the embodiments of this application can achieve the following beneficial effects:

[0012] In this embodiment, when accessing vehicle-mounted millimeter-wave radar data, an access request is obtained. The access request includes the logical address of the data to be accessed and the corresponding access type. Based on a preset access priority, priorities are assigned to each port corresponding to the access type. The preset access priorities include: write access has a higher priority than read access; the priorities of one-dimensional data write access, two-dimensional data write access, and non-one-dimensional / two-dimensional data write access decrease sequentially; the priorities of two-dimensional data read access, non-one-dimensional / two-dimensional data read access, and one-dimensional data read access decrease sequentially. Based on the priority of each port, each port is sequentially invoked to perform bus address mapping on the logical address of the corresponding data to be accessed, obtaining the bus address of the data to be accessed in memory. The data to be accessed is then accessed in memory based on the bus address. This embodiment uses independent ports and increases their write access priority. By rationally allocating the priorities of each port, it avoids the interleaving of different types of data access from multiple ports, which leads to bandwidth allocation problems and thus improves bandwidth utilization. Attached Figure Description

[0013] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0014] Figure 1 A flowchart illustrating a method for accessing vehicle-mounted millimeter-wave radar data, provided as an embodiment of this application;

[0015] Figure 2 A schematic diagram of a memory access time slot provided for one embodiment of this application;

[0016] Figure 3 A flowchart illustrating a method for accessing vehicle-mounted millimeter-wave radar data, provided as another embodiment of this application;

[0017] Figure 4 A schematic diagram of a Cube storage structure provided in one embodiment of this application;

[0018] Figure 5 A schematic diagram of DDR4 address mapping provided for one embodiment of this application;

[0019] Figure 6A schematic diagram of LPDDR4 address mapping provided for one embodiment of this application;

[0020] Figure 7 A schematic diagram of a distributed inline ECC mechanism provided for one embodiment of this application;

[0021] Figure 8 A schematic diagram of an address mapping extension structure under a distributed inline ECC mechanism is provided as an embodiment of this application;

[0022] Figure 9 A schematic diagram of a device for accessing vehicle-mounted millimeter-wave radar data is provided as an embodiment of this application;

[0023] Figure 10 This is a schematic diagram of the structure of an electronic device provided in one embodiment of this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] The terms "first," "second," etc., used in this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein. Furthermore, "and / or" in this application indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship. It should be noted that all data involved in this application was obtained with the user's authorization.

[0026] Automotive 4D high-resolution millimeter-wave radar, also known as automotive 4D imaging millimeter-wave radar, or simply automotive 4D imaging radar, uses 4D to refer to four dimensions: range, velocity, azimuth, and elevation. In addition to the three-dimensional measurement of range, azimuth, and velocity, automotive 4D millimeter-wave radar adds an extra dimension (elevation) to the measurement of data from traditional automotive millimeter-wave radar.

[0027] Compared to traditional automotive millimeter-wave radar, the advantage of automotive 4D millimeter-wave radar lies in its high resolution, meaning it provides higher resolution of targets in both range and angle dimensions. The number of point clusters obtained is dozens of times greater than that of traditional automotive millimeter-wave radar, typically tens of thousands of points per second (15-20 frames), according to current radar manufacturers' product specifications. This dense combination of point clusters is called a point cloud, which can, to a certain extent, represent the outline of the target, achieving an "imaging" effect.

[0028] In related technologies, when accessing data from vehicle-mounted 4D millimeter-wave radar, the interweaving of different types of data access from multiple ports leads to bandwidth allocation problems, resulting in low bandwidth utilization. To address this, this application proposes a method, apparatus, electronic device, and storage medium for accessing vehicle-mounted millimeter-wave radar data, thereby resolving the problem of low bandwidth utilization caused by the interweaving of different types of data access from multiple ports in related technologies.

[0029] The technical solutions provided by the various embodiments of this application are described in detail below with reference to the accompanying drawings.

[0030] Figure 1 This is a flowchart illustrating a method for accessing vehicle-mounted millimeter-wave radar data, provided as an embodiment of this application. Figure 1 As shown in the embodiments of this application, the method for accessing vehicle-mounted millimeter-wave radar data may specifically include the following steps:

[0031] S101, Obtain an access request. The access request includes the logical address of the data to be accessed and the corresponding access type.

[0032] In this embodiment, the execution entity of the vehicle-mounted millimeter-wave radar data access method is a vehicle-mounted millimeter-wave radar data access device, which can be located in an electronic device. This electronic device can be a terminal device or a server. The terminal device can be a mobile phone, tablet computer, desktop computer, laptop, vehicle-mounted device, etc.; the server can be a standalone server or a server cluster composed of multiple servers. In this embodiment, the vehicle-mounted millimeter-wave radar data access device can specifically be located in a vehicle-mounted 4D millimeter-wave radar.

[0033] Vehicle-mounted millimeter-wave radar includes a transmitting antenna and a receiving antenna. It transmits and receives reflected electromagnetic waves and processes the received electromagnetic waves to calculate the target's azimuth angle.

[0034] Taking a vehicle-mounted 4D millimeter-wave radar with 12 transmit antennas (Tx) and 16 receive antennas (Rx) as an example, its analog-to-digital converter (ADC) sampling rate is 512 quadrature (IQ) points, each sampling point is stored in 16 bits, the linear frequency modulation pulse (chirp) accumulation is 128, and it adopts time division multiple access (TDMA) multi-input multi-output (MIMO) mode. Its sampled data size is 48 megabytes (MB).

[0035] The following describes the storage bottlenecks of vehicle-mounted 4D millimeter-wave radar data in related technologies. For example... Figure 2 The diagram shows a schematic of memory access time slots. Cube0-3 represent different data cube (Cube) frames, and Cube_n-1D Write (wide beam / narrow beam) / 2D Read / 2D Write / 3D Write / 3D Read represent the relevant Cube processing procedures. The example uses a 12T16R module, a vehicle-mounted 4D millimeter-wave radar comprising 12 Tx and 16 Rx.

[0036] Assuming from Figure 2 Extracting the bandwidth limit scenario from the DDR time slots shown ( Figure 2 (The third and fourth circles in the middle) Calculate the theoretical bandwidth requirement under a 50 millisecond (ms) frame time condition as follows:

[0037] The average bandwidth requirement is 3.857 GB / s.

[0038] Peak bandwidth requirement: 4.171 GB / s

[0039] In addition, access requests typically include requests for Artificial Intelligence (AI) and Central Processing Unit (CPU), with theoretical peak bandwidth requirements of >1GB / s and 500MB / s respectively. The total bandwidth requirement is 4.17 + 1.5 = 5.57GB / s.

[0040] In related technologies, the highest design speed of memory is 3200 MHz, with a 32-bit bus width and a total bandwidth utilization of about 43%, resulting in a total bandwidth of 5.117 GB / s < 5.57 GB / s, which does not meet application requirements. Therefore, a new bandwidth solution must be found.

[0041] As can be seen from the above, the main factors causing memory bandwidth bottlenecks are the following two points: 1) bandwidth tolerance and bandwidth utilization, and 2) bandwidth allocation problems caused by interleaving of multi-port data access. Among them, the bandwidth tolerance in problem 1) is mainly determined by the memory's operating frequency and bus width, which are not optimized in this embodiment.

[0042] This application's embodiment solves the aforementioned problem 2) the bandwidth allocation problem caused by interleaved multi-port data access through multi-port priority allocation. Specifically:

[0043] When a user accesses vehicle-mounted millimeter-wave radar data (write access or read access), an access request is initiated. The access request may include, but is not limited to, the logical address of the data to be accessed and the access type of the data to be accessed. The data to be accessed includes data to be written and / or data to be read, i.e., vehicle-mounted millimeter-wave radar data to be written to memory and / or vehicle-mounted millimeter-wave radar data to be read from memory. Each access request corresponds to a logical address and an access type for each piece of data to be accessed. Those skilled in the art will understand that an access request may include one or more pieces of data to be written, along with their corresponding logical addresses and access types, and may also include the logical addresses and access types of data to be read, but not the data to be read itself.

[0044] A logical address, also known as a virtual address, refers to the address of a memory unit, storage unit, or network host as seen from the application's perspective within a computer architecture. It differs from the bus address, also known as the physical address. Logical addresses are typically translated into bus addresses using address translators or mapping functions.

[0045] The specific access type may include, but is not limited to, at least one of the following: one-dimensional data write access (referred to as 1D write), two-dimensional data write access (referred to as 2D write), non-one-dimensional and two-dimensional data write access (referred to as non-1D2D write), one-dimensional data read access (referred to as 1D read), two-dimensional data read access (referred to as 2D read), and non-one-dimensional and two-dimensional data read access (referred to as non-1D2D read).

[0046] S102, according to the preset access priority, assign the priority of each port corresponding to the access type.

[0047] In this embodiment, port priority refers to the priority of an independent port of the memory controller, with different access types corresponding to different independent ports. To meet the Chirp write time limit requirements, 1D memory needs to be prioritized, followed by 2D access which is limited by peak bandwidth. Therefore, access priorities are set, i.e., the priority allocation of each port is as follows:

[0048] Write access > Read access;

[0049] Write priority: 1D write > 2D write > non-1D / 2D write

[0050] Read priority: 2D read > non-1D 2D read > 1D read (1D has no read access requirement)

[0051] In other words, the preset access priorities are as follows: write access has a higher priority than read access, and the priorities of one-dimensional data write access, two-dimensional data write access, and non-one-dimensional / two-dimensional data write access decrease in that order. The priorities of two-dimensional data read access, non-one-dimensional / two-dimensional data read access, and one-dimensional data read access decrease in that order.

[0052] Based on the pre-set access priorities, the priority of each access type in the access request is determined, and then the priority of each port corresponding to each access type is assigned.

[0053] In this application embodiment, an independent port is used in the design and its write access priority is increased. By reasonably allocating the priority of each port, the interleaving of different types of data access on multiple ports is avoided, which leads to bandwidth allocation problems and thus improves bandwidth utilization.

[0054] S103, according to the priority of each port, sequentially calls each port to perform bus address mapping on the logical address of the corresponding data to be accessed, and obtains the bus address of the data to be accessed in the memory.

[0055] In this embodiment, based on the priority order of each port, the logical address of the data to be accessed corresponding to that port is sequentially called in descending order of priority to perform bus address mapping. That is, the logical address of the data to be accessed is converted into the bus address of the data to be accessed in memory. For example, an address translator or mapping function can be used to convert the logical address into a bus address.

[0056] S104 accesses the data to be accessed in the memory according to the bus address.

[0057] In this embodiment, when the data to be accessed is write data, the write data included in the access request is written to the bus address obtained above in the memory. When the data to be accessed is read data, the read data is read from the bus address obtained above in the memory.

[0058] It should be noted that the memory in the embodiments of this application may include, but is not limited to, at least one of the following memories: Double Data Rate Synchronous Dynamic Random Access Memory 4 (DDR SDRAM4, abbreviated as DDR4) and Low Power Double Data Rate Synchronous Dynamic Random Access Memory 4 (LPDDR SDRAM4, abbreviated as LPDDR4), etc.

[0059] In summary, the vehicle-mounted millimeter-wave radar data access method of this application adopts independent ports and increases their write access priority. By reasonably allocating the priority of each port, it avoids the intertwining of different types of data access on multiple ports, which leads to bandwidth allocation problems and thus improves bandwidth utilization.

[0060] Figure 3 This is a flowchart illustrating a method for accessing vehicle-mounted millimeter-wave radar data, provided as another embodiment of this application. Figure 3 As shown, in Figure 1 Based on the illustrated embodiment, the method for accessing vehicle-mounted millimeter-wave radar data in this application embodiment may specifically include the following steps:

[0061] The step S101 in the above embodiment, "obtaining an access request, the access request including the logical address of the data to be accessed and the corresponding access type", may specifically include the following steps S301-S304.

[0062] S301, Obtain the collection order of the data to be accessed.

[0063] In this embodiment, the bandwidth utilization in problem 1) is mainly determined by the memory's bus address access mode and refresh frequency. This embodiment solves the bandwidth utilization problem in problem 1) by optimizing the data cube (Cube) storage address. Specifically:

[0064] For the three data access methods of 1D storage, 2D computation, and 3D extraction, all vehicle-mounted millimeter-wave radar modules include both continuous and non-continuous data access methods. To improve the read and write efficiency of the memory, from the perspective of extraction characteristics, the storage structure should have the following features:

[0065] 1) The R-dimensional direction is correlated with the D-dimensional direction, that is, the number of memory bus address rows mapped to R*D is a fixed value.

[0066] 2) Non-contiguous address access operations in the TX and R directions.

[0067] 3) D-direction continuous address operation.

[0068] 4) The burst length of LPDDR4 is 16, while that of DDR4 is 8 and the bit width is 32 bits. Therefore, the minimum burst size in the R direction should be 64 bytes to avoid bandwidth loss.

[0069] 5) To avoid excessive bandwidth contention caused by accessing other ports, the burst length of 2D computing access to DDR is limited to 32.

[0070] To meet computational requirements, the actual optimized Cube storage structure model is as follows: Figure 4 As shown, the corresponding mathematical expression is:

[0071] Addr(Mn(i,j,k))=(Cell_SIZE*D_WIDTH)*i+(Cell_SIZE*D_WIDTH*R_WIDTH)*j+Cell_SIZE*k;

[0072] Where Addr is the logical address of the data to be accessed, Mn(i,j,k) is the nth storage unit Cell, n is the acquisition order or input sequence, (i,j,k) is the three-dimensional coordinate of the storage unit in the coordinate system (R, TX, D), where i, j, and k are all natural numbers, and Cell_SIZE is the size of the storage unit. Cell_SIZE is 64 bytes only when using 1D-Write and 2D-Read, otherwise it is 128 bytes. D_WIDTH and R_WIDTH are the widths of the storage unit in the D and R dimensions, respectively.

[0073] Therefore, in this embodiment of the application, when generating an access request, the collection order n of the data to be accessed is first obtained, for example... Figure 4 As shown, n starts from 0.

[0074] S302, determine the three-dimensional coordinates of the storage unit corresponding to the data to be accessed in the optimized storage structure model according to the acquisition order.

[0075] In this embodiment, based on the acquisition order n of the data to be accessed, the three-dimensional coordinates (i, j, k) of the storage cell corresponding to the data to be accessed in the optimized Cube storage structure model are determined, where n = i + R_WIDTH*j + (R_WIDTH*TX_WIDTH)*k, and T_WIDTH is the width of the storage cell in the TX dimension. For example Figure 4As shown, when n = 0, (i, j, k) = (0, 0, 0), and when n = 1, (i, j, k) = (1, 0, 0). k is the quotient of (n / (R_WIDTH*TX_WIDTH)) rounded down, j is the quotient of (n / (R_WIDTH*TX_WIDTH)) divided by R_WIDTH and rounded down, and i is the remainder of (n / R_WIDTH).

[0076] S303 generates the logical address of the data to be accessed based on the three-dimensional coordinates of the storage unit and the optimized storage structure model.

[0077] In this embodiment, the logical address Addr of the data to be accessed is calculated based on the three-dimensional coordinates (i, j, k) of the storage cell determined in step S302. Specifically, the logical address Addr(Mn(i, j, k)) can be calculated using the formula described above.

[0078] S304. Generate an access request based on the logical address of the data to be accessed. The access request includes the logical address of the data to be accessed and the corresponding access type.

[0079] S305 assigns priority to each port corresponding to the access type based on the preset access priority.

[0080] S306, according to the priority of each port, sequentially calls each port to perform bus address mapping on the logical address of the corresponding data to be accessed, and obtains the bus address of the data to be accessed in memory.

[0081] S307 accesses the data to be accessed in memory based on the bus address.

[0082] In this embodiment, steps S305-S307 are the same as steps S102-S104 in the above embodiment, and will not be repeated here.

[0083] Since the row mapping position of the address map is determined by the size of the D dimension, to adapt to the bandwidth utilization problem of different radar modules, the address map can be adjusted to solve the needs of short bursts and high-frequency read / write access of regional addresses. Specifically, the step S306 above, "to perform bus address mapping on the logical address of the corresponding data to be accessed to obtain the bus address of the data to be accessed in memory", may include the following steps: adjusting the positions of the column address, array group address, array address, row address, and chip select address in the logical address to obtain the bus address.

[0084] As a first feasible implementation, when the memory is 4th generation Double Data Rate Synchronous Dynamic Random Access Memory (DDR4), the vehicle-mounted millimeter-wave radar includes 12 transmitting antennas and 16 receiving antennas, and the minimum burst size of the data to be accessed is 64 bytes, such as Figure 5 As shown, step S306 in the above embodiment, "mapping the logical address of the corresponding data to be accessed to obtain the bus address of the data to be accessed in the memory", may specifically include the following steps:

[0085] S501 reserves the 0th to 2nd columns of the logical address in the 1st to 3rd bits of the bus address.

[0086] S502 adjusts the array group address in the logical address to the 4th bit of the bus address.

[0087] In this embodiment of the application, Table 1 is a mapping table of the 12T16R radar module based on DDR4 address.

[0088] Table 1. Mapping table of 12T16R radar module based on DDR4 address

[0089]

[0090] The actual burst length of DDR4 is 8. Therefore, the addresses of columns 0 to 2 in the logical address, namely Col[2:0], are retained in the lowest 3 bits of the bus address, namely bits 1 to 3. At the same time, the array group (Bank Group) address in the logical address, namely BG address, is adjusted to the 4th bit of the bus address to increase the number of Bank Group switching times and improve access efficiency.

[0091] S503 reserves the 4th to 9th columns of the logical address in the 5th to 10th bits of the bus address.

[0092] In this embodiment of the application, the positions of the 4th to 9th columns of the logical address, namely Col[9:4], remain unchanged, that is, they are still the 5th to 10th bits of the bus address.

[0093] S504 adjusts the 3rd column address in the logical address to the 11th bit of the bus address.

[0094] In this embodiment of the application, the third column address in the logical address, namely Col[3], is adjusted to the 11th bit of the bus address.

[0095] S505 adjusts the array address in the logical address to the 12th to 13th bits of the bus address and sets them to be consecutive.

[0096] In this embodiment, the array address Bank[1:0] in the logical address is adjusted to the 12th to 13th bits of the bus address, and Bank[1:0] is set to be consecutive. This can effectively ensure that four array banks can be opened at the same time in a short period of time, avoiding the time consumed by activating banks and frequently closing banks, and maximizing read and write efficiency.

[0097] S506 adjusts the addresses of rows 0 to 15 in the logical address to bits 14 to 29 of the bus address.

[0098] In this embodiment of the application, since the continuous data read volume for 2D calculation is 128*64B=8KB and the continuous data storage volume is 128*128B=16KB, the addresses of rows 0 to 15 in the logical address, namely Row[15:0], are adjusted to start from the 14th bit of the bus address, that is, bits 14 to 29. The single-line capacity is 32KB, which can avoid frequent line breaks and improve read and write efficiency.

[0099] S507 reserves the chip select address in the logical address in the 30th bit of the bus address.

[0100] In this embodiment of the application, the chip select address, i.e., CS, in the logical address is reserved in the 30th bit of the bus address.

[0101] As a second feasible implementation, when the memory is 4th generation low-power double data rate synchronous dynamic random access memory (LPDDR4), the vehicle-mounted millimeter-wave radar includes 12 transmitting antennas and 16 receiving antennas, and the minimum burst size of the data to be accessed is 64 bytes, such as Figure 6 As shown, step S103 in the above embodiment, "mapping the logical address of the corresponding data to be accessed to obtain the bus address of the data to be accessed in the memory", may specifically include the following steps:

[0102] S601 reserves the 0th to 2nd columns of the logical address in the 1st to 3rd bits of the bus address.

[0103] In this embodiment of the application, Table 2 is a mapping table of the 12T16R radar module based on LPDDR4 address.

[0104] Table 2. Mapping table of 12T16R radar module based on LPDDR4 address

[0105] Film selection address row address BANK address Column address 9~3 BANK address Column addresses 2-0 CS Row[15:0] BA[2:1] Col[9:3] BA[0] Col[2:0]

[0106] The actual burst length of LPDDR4 is 16, so the addresses of columns 0 to 2 in the logical address, namely Col[2:0], are reserved in the lowest 3 bits of the bus address, namely bits 1 to 3.

[0107] S602 adjusts the 0th array address in the logical address to the 4th bit of the bus address.

[0108] In this embodiment of the application, the 0th array address in the logical address, namely BA[0], is adjusted to the 4th bit of the bus address.

[0109] S603 adjusts the 3rd to 9th columns of the logical address to the 5th to 11th bits of the bus address.

[0110] In this embodiment of the application, the addresses of columns 3 to 9 in the logical address, namely Col[9:3], are reserved in the 5th to 11th bits of the bus address.

[0111] S604 adjusts the first array address in the logical address to the 12th to 13th bits of the bus address and sets them to be consecutive.

[0112] In this embodiment, the first array address in the logical address, namely BA[2:1], is adjusted to the 12th to 13th bits of the bus address, and BA[2:1] is set to be continuous. This can effectively ensure that four array banks can be opened at the same time in a short period of time, avoiding the time consumed by activating banks and frequently closing banks, and maximizing read and write efficiency.

[0113] S605 adjusts the addresses of rows 0 to 15 in the logical address to bits 14 to 29 of the bus address.

[0114] In this embodiment of the application, since the continuous data read volume for 2D calculation is 128*64B=8KB and the continuous data storage volume is 128*128B=16KB, the addresses of rows 0 to 15 in the logical address, namely Row[15:0], are adjusted to start from the 14th bit of the bus address, that is, bits 14 to 29. The single-line capacity is 32KB, which can avoid frequent line breaks and improve read and write efficiency.

[0115] S606 reserves the chip select address in the logical address in the 30th bit of the bus address.

[0116] In this embodiment of the application, the chip select address, i.e., CS, in the logical address is reserved in the 30th bit of the bus address.

[0117] Furthermore, under the conditions of accessing burst mode and a fixed operating frequency, the refresh mode can adopt a reasonable post-refresh method to improve bandwidth utilization. The post-refresh method involves periodically refreshing the memory's storage capacitors, which means periodically charging the memory's storage capacitors to ensure that data is not lost.

[0118] Furthermore, to ensure access security, a Functional Security Assurance (FUSA) mechanism can be set up.

[0119] As a first feasible implementation method, such as Figure 7 As shown, a DECC bridge can be set in each port. The DECC bridge includes an online error checking and correction mechanism. The method for accessing vehicle millimeter-wave radar data in this embodiment of the application may further include the following steps: calling each port to adopt the online error checking and correction mechanism and adding a check code to the bus address; when it is determined that a unit or double-bit error has occurred according to the check code, suspending the access request to locate the fault; when it is determined that a unit error has occurred according to the check code, writing the corrected data to the memory.

[0120] Specifically, to address the issues of low bandwidth utilization and low overall bandwidth in Share Inline ECC technologies, a distributed Inline ECC solution can be adopted. This solution involves each port containing a DECC bridge, with each DECC incorporating an Inline ECC mechanism. This approach balances security and bandwidth considerations, allows for flexible configuration, and employs a CPU software check mechanism to meet security requirements.

[0121] Inline ECC provides an end-to-end protection mechanism for Single Error Correction and Double Error Detection (SECDED) along the entire path from the memory controller (e.g., DDR controller) to the memory (e.g., DRAM) chip via a DECC bridge. The DECC protection granularity is 32 bits of data + 8 bits of parity (data + address), and the address mapping extension structure is as follows: Figure 8 As shown.

[0122] DECC supports conflict mode suspension, which can suspend bus access requests for fault location when a single / double bit error occurs.

[0123] DECC supports error correction and write-back functionality. When a unit (bit) error occurs, after ECC error correction is completed, the corrected data will be written back to memory to ensure data reliability.

[0124] As a second feasible implementation method, the method for accessing vehicle-mounted millimeter-wave radar data in this application embodiment may further include the following steps: using a software periodic readback security mechanism (Assumption of Use, AoU) to perform security monitoring on the access process.

[0125] Specifically, AoU provides basic functional testing and inserts an error diagnosis mechanism. This mechanism can occur periodically during startup or runtime, requiring only that the system allocate 8KB of space to write a predefined pattern (in programming, a pattern usually refers to a rule or pattern used to find specific information or structures in data. Different programming languages ​​and application scenarios may have different predefined forms of patterns), and periodically read back and compare within 1ms (the Fault Tolerant Time Interval (FTTI) requirement is <50ms).

[0126] When a system failure causes data to be missed in memory or data and address errors occur, other security mechanisms such as Etimer cannot detect it, while AoU can detect such failures very well.

[0127] In the CPU channel, the ASIL-B level requirements can be met through the AoU+DECC security mechanism. Since DECC is dynamically configurable, in addition to the CPU, ECC functionality can be enabled or disabled according to system performance requirements, which can appropriately improve system fault coverage while also considering system performance. Based on the above address mapping optimization scheme, by disabling DECC on ports 1 and 2 and enabling DECC on ports 3 and 4, at LPDDR4 and DDR4 3200Mbps speeds, the simulated and measured bandwidth utilization rate is 60% > 43%, with a bandwidth margin of 13.2%, meeting the bandwidth requirements.

[0128] In summary, the vehicle-mounted millimeter-wave radar data access method of this application adopts independent ports and increases their write access priority. By rationally allocating the priorities of each port, it avoids the interleaving of different types of data access from multiple ports, which leads to bandwidth allocation problems and thus improves bandwidth utilization. By designing a new data cube storage structure, it maximizes throughput bandwidth and improves access efficiency. Adaptive address mapping configurations are used for different high-performance radar modules. By optimizing address mapping, the overall efficiency is improved by 17%, and the bandwidth margin is 13.2% (>10%), which can meet bandwidth requirements and has higher reliability. The distributed inline ECC+AoU solution, under the condition of meeting ASIL-B security level, can improve the overall bandwidth utilization of the system by solving the bandwidth allocation problem.

[0129] Figure 9 This is a schematic diagram of a device for accessing vehicle-mounted millimeter-wave radar data, provided as an embodiment of this application. Figure 9 As shown, the vehicle-mounted millimeter-wave radar data access device 900 of this application embodiment may specifically include: an acquisition module 901, an allocation module 902, a mapping module 903, and an access module 904. Wherein:

[0130] The acquisition module 901 is used to acquire an access request. The access request includes the logical address of the data to be accessed and the corresponding access type. The access type includes at least one of the following: one-dimensional data write access, two-dimensional data write access, non-one-dimensional / two-dimensional data write access, one-dimensional data read access, two-dimensional data read access, and non-one-dimensional / two-dimensional data read access.

[0131] The allocation module 902 is used to allocate the priority of each port corresponding to the access type according to the preset access priority. The preset access priority includes: the priority of write access is higher than the priority of read access, the priority of one-dimensional data write access, two-dimensional data write access and non-one-dimensional / two-dimensional data write access decreases in sequence, and the priority of two-dimensional data read access, non-one-dimensional / two-dimensional data read access and one-dimensional data read access decreases in sequence.

[0132] The mapping module 903 is used to sequentially call each port according to its priority to perform bus address mapping on the logical address of the corresponding data to be accessed, so as to obtain the bus address of the data to be accessed in the memory.

[0133] Access module 904 is used to access the data to be accessed in the memory according to the bus address.

[0134] In the embodiments of this application, the specific process by which each module and unit in the vehicle-mounted millimeter-wave radar data access device implements its function can be found in the relevant descriptions in the embodiments of the vehicle-mounted millimeter-wave radar data access method described above, and will not be repeated here.

[0135] In summary, the vehicle-mounted millimeter-wave radar data access device of this application adopts independent ports and increases their write access priority. By rationally allocating the priorities of each port, it avoids the interleaving of different types of data access from multiple ports, thus preventing bandwidth allocation problems and improving bandwidth utilization. A novel data cube storage structure is designed to maximize throughput bandwidth and improve access efficiency. Adaptive address mapping configurations are used for different high-performance radar modules. By optimizing address mapping, the overall efficiency is improved by 17%, and the bandwidth margin is 13.2% (>10%), which meets bandwidth requirements and has higher reliability. The distributed Inline ECC+AoU solution, while meeting ASIL-B safety standards, improves the overall system bandwidth utilization by solving the bandwidth allocation problem.

[0136] This application also provides an electronic device. For example... Figure 10As shown, the electronic device 1000 can vary considerably due to differences in configuration or performance. It may include one or more processors 1001 and memory 1002, and the memory 1002 may store one or more application programs or data. The memory 1002 may be temporary or persistent storage. The application programs stored in the memory 1002 may include one or more modules (not shown), each module may include a series of computer-executable instructions in the electronic device 1000. Furthermore, the processor 1001 may be configured to communicate with the memory 1002 and execute the series of computer-executable instructions in the memory 1002 on the electronic device 1000. The electronic device 1000 may also include one or more power supplies 1003, one or more wired or wireless network interfaces 1004, one or more input / output interfaces 1005, and one or more keyboards 1006.

[0137] Specifically, in this embodiment, the electronic device includes a memory and one or more programs, wherein one or more programs are stored in the memory, and one or more programs may include one or more modules, and each module may include a series of computer-executable instructions for use in the electronic device, and is configured to be executed by one or more processors. The one or more programs include computer-executable instructions for performing the following:

[0138] Obtain an access request, which includes the logical address of the data to be accessed and the corresponding access type. The access type includes at least one of the following: one-dimensional data write access, two-dimensional data write access, non-one-dimensional / two-dimensional data write access, one-dimensional data read access, two-dimensional data read access, and non-one-dimensional / two-dimensional data read access.

[0139] Based on the preset access priority, the priority of each port corresponding to the access type is assigned. The preset access priority includes: the priority of write access is higher than the priority of read access, the priority of one-dimensional data write access, two-dimensional data write access and non-one-dimensional / two-dimensional data write access decreases in sequence, and the priority of two-dimensional data read access, non-one-dimensional / two-dimensional data read access and one-dimensional data read access decreases in sequence.

[0140] Based on the priority of each port, the logical address of the corresponding data to be accessed is mapped to the bus address in turn to obtain the bus address of the data to be accessed in memory.

[0141] The data to be accessed is accessed in memory based on the bus address.

[0142] The electronic device in this application employs independent ports and increases their write access priority. By rationally allocating the priorities of each port, it avoids the interleaving of different types of data access from multiple ports, thus preventing bandwidth allocation problems and improving bandwidth utilization. A novel data cube storage structure is designed to maximize throughput bandwidth and improve access efficiency. Adaptive address mapping configurations are used for different high-performance radar modules. By optimizing address mapping, the overall efficiency is improved by 17%, with a bandwidth margin of 13.2% (>10%), meeting bandwidth requirements and providing higher reliability. The distributed InlineECC+AoU solution, while meeting ASIL-B security standards, improves the overall system bandwidth utilization by resolving bandwidth allocation issues.

[0143] This application also proposes a readable storage medium storing one or more computer programs, each including instructions. When executed by a processor in an electronic device comprising multiple applications, the program or instructions enable the processor to perform the various processes of the above-described method for accessing vehicle-mounted millimeter-wave radar data, specifically for executing:

[0144] Obtain an access request, which includes the logical address of the data to be accessed and the corresponding access type. The access type includes at least one of the following: one-dimensional data write access, two-dimensional data write access, non-one-dimensional / two-dimensional data write access, one-dimensional data read access, two-dimensional data read access, and non-one-dimensional / two-dimensional data read access.

[0145] Based on the preset access priority, the priority of each port corresponding to the access type is assigned. The preset access priority includes: the priority of write access is higher than the priority of read access, the priority of one-dimensional data write access, two-dimensional data write access and non-one-dimensional / two-dimensional data write access decreases in sequence, and the priority of two-dimensional data read access, non-one-dimensional / two-dimensional data read access and one-dimensional data read access decreases in sequence.

[0146] Based on the priority of each port, the logical address of the corresponding data to be accessed is mapped to the bus address in turn to obtain the bus address of the data to be accessed in memory.

[0147] The data to be accessed is accessed in memory based on the bus address.

[0148] The readable storage medium in this application employs independent ports and increases their write access priority. By rationally allocating the priorities of each port, it avoids the interleaving of different types of data access from multiple ports, thus preventing bandwidth allocation problems and improving bandwidth utilization. A novel data cube storage structure is designed to maximize throughput bandwidth and improve access efficiency. Adaptive address mapping configurations are used for different high-performance radar modules. Through optimized address mapping, overall efficiency is improved by 17%, with a bandwidth margin of 13.2% (>10%), meeting bandwidth requirements and providing higher reliability. The distributed Inline ECC+AoU solution, while meeting ASIL-B security standards, improves overall system bandwidth utilization by resolving bandwidth allocation issues.

[0149] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0150] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.

[0151] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0152] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1A device that provides the functions specified in one or more boxes.

[0153] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0154] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0155] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0156] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0157] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0158] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0159] This application can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0160] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0161] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A method for accessing vehicle-mounted millimeter-wave radar data, characterized in that, include: Obtain an access request, wherein the access request includes the logical address of the data to be accessed and the corresponding access type, wherein the access type includes at least one of the following: one-dimensional data write access, two-dimensional data write access, non-one-dimensional / two-dimensional data write access, one-dimensional data read access, two-dimensional data read access, and non-one-dimensional / two-dimensional data read access. According to the preset access priority, the priority of each port corresponding to the access type is assigned. The preset access priority includes: the priority of write access is higher than the priority of read access, the priority of one-dimensional data write access, the priority of two-dimensional data write access and the priority of non-one-dimensional data write access decrease in sequence, and the priority of two-dimensional data read access, the priority of non-one-dimensional data read access and the priority of one-dimensional data read access decrease in sequence. Based on the priority of each port, each port is sequentially invoked to perform bus address mapping on the logical address of the corresponding data to be accessed, so as to obtain the bus address of the data to be accessed in the memory. The data to be accessed is accessed in the memory according to the bus address.

2. The method according to claim 1, characterized in that, The methods for obtaining the logical address of the data to be accessed include: Obtain the collection order of the data to be accessed; The three-dimensional coordinates of the storage unit corresponding to the data to be accessed in the optimized storage structure model are determined according to the acquisition order. The logical address of the data to be accessed is generated based on the three-dimensional coordinates of the storage unit and the optimized storage structure model.

3. The method according to claim 2, characterized in that, The step of generating the logical address of the data to be accessed based on the three-dimensional coordinates of the storage unit and the optimized storage structure model includes: The logical address of the data to be accessed is determined according to the following formula corresponding to the optimized storage structure model: Addr(Mn(i,j,k))=(Cell_SIZE*D_WIDTH)*i+(Cell_SIZE*D_WIDTH*R_WIDTH)*j+Cell_SIZE*k; Wherein, Addr is the logical address of the data to be accessed, Mn(i,j,k) is the nth storage unit, n is the acquisition order, (i,j,k) is the three-dimensional coordinate of the storage unit, Cell_SIZE is the size of the storage unit, and D_WIDTH and R_WIDTH are the widths of the storage unit in the D and R dimensions, respectively.

4. The method according to claim 1, characterized in that, The step of mapping the logical address of the data to be accessed to a bus address to obtain the bus address of the data to be accessed in memory includes: The positions of the column address, array group address, array address, row address, and chip select address in the logical address are adjusted to obtain the bus address.

5. The method according to claim 4, characterized in that, The memory is a fourth-generation double-rate synchronous dynamic random access memory (DDR4), the vehicle-mounted millimeter-wave radar includes 12 transmitting antennas and 16 receiving antennas, and the minimum burst size of the data to be accessed is 64 bytes. The step of mapping the logical address of the data to be accessed to a bus address to obtain the bus address of the data to be accessed in memory includes: The addresses in columns 0 to 2 of the logical address are retained in bits 1 to 3 of the bus address; Adjust the array group address in the logical address to the 4th bit of the bus address; The addresses in columns 4 to 9 of the logical address are retained in bits 5 to 10 of the bus address; Adjust the third column address in the logical address to the 11th bit of the bus address; Adjust the array address in the logical address to the 12th to 13th bits of the bus address, and set them to be consecutive; Adjust the addresses of rows 0 to 15 in the logical address to bits 14 to 29 of the bus address; The chip select address in the logical address is retained in the 30th bit of the bus address.

6. The method according to claim 4, characterized in that, The memory is a fourth-generation low-power double-rate synchronous dynamic random access memory (LPDDR4), the vehicle-mounted millimeter-wave radar includes 12 transmitting antennas and 16 receiving antennas, and the minimum burst size of the data to be accessed is 64 bytes. The step of mapping the logical address of the data to be accessed to a bus address to obtain the bus address of the data to be accessed in memory includes: The addresses in columns 0 to 2 of the logical address are retained in bits 1 to 3 of the bus address; Adjust the 0th array address in the logical address to the 4th bit of the bus address; Adjust the 3rd to 9th columns of the logical address to the 5th to 11th bits of the bus address; Adjust the first array address in the logical address to the 12th to 13th bits of the bus address, and set them to be consecutive; Adjust the addresses of rows 0 to 15 in the logical address to bits 14 to 29 of the bus address; The chip select address in the logical address is retained in the 30th bit of the bus address.

7. The method according to claim 1, characterized in that, Each port is equipped with a DECC bridge, the DECC bridge including an online error checking and correction mechanism, and the method further includes: Each port employs the online error checking and correction mechanism, adding a checksum to the bus address; When a single or double-digit error is determined based on the checksum, the access request is suspended to locate the fault. When a unit error is determined to have occurred based on the check code, the corrected data is written back to the memory.

8. The method according to claim 1, characterized in that, Also includes: A software-based periodic readback security mechanism is employed to monitor the access process.

9. A device for accessing vehicle-mounted millimeter-wave radar data, characterized in that, include: The acquisition module is used to acquire an access request, which includes the logical address of the data to be accessed and the corresponding access type. The access type includes at least one of the following: one-dimensional data write access, two-dimensional data write access, non-one-dimensional / two-dimensional data write access, one-dimensional data read access, two-dimensional data read access, and non-one-dimensional / two-dimensional data read access. The allocation module is used to allocate the priority of each port corresponding to the access type according to the preset access priority. The preset access priority includes: the priority of write access is higher than the priority of read access, the priority of one-dimensional data write access, the priority of two-dimensional data write access and the priority of non-one-dimensional and two-dimensional data write access decreases in sequence, and the priority of two-dimensional data read access, the priority of non-one-dimensional and two-dimensional data read access and the priority of one-dimensional data read access decreases in sequence. The mapping module is used to sequentially call each port according to its priority to perform bus address mapping on the logical address of the corresponding data to be accessed, so as to obtain the bus address of the data to be accessed in the memory. An access module is used to access the data to be accessed in the memory according to the bus address.

10. An electronic device, characterized in that, It includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the method as described in any one of claims 1-8.

11. A readable storage medium, characterized in that, A program or instructions are stored on the readable storage medium, which, when executed by a processor, implement the steps of the method as described in any one of claims 1-8.

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