Multi-quantum circuit mapping method based on noise perception

Abstract

The invention discloses a multi-quantum circuit mapping method based on noise perception, and relates to the technical field of quantum computing compilation, and the method specifically comprises the steps: based on an original coupling graph of a target quantum device architecture, judging whether the maximum logic quantum bit number in a quantum circuit set is smaller than a preset threshold value of the physical quantum bit number in the original coupling graph or not; analyzing each partition in the pre-processed coupling graph to obtain a partition suitable for mapping of each quantum circuit; and based on the effective physical partition of the target quantum architecture, for each sub-line in the quantum line set, constructing a logic quantum bit interaction diagram of each quantum line, and obtaining a mapping and optimization scheme of each quantum line in combination with quantitative calibration of the comprehensive quality of each physical quantum bit. According to the method, hardware topology is optimized through preprocessing of noise perception, iterative pruning and partitioning are performed by utilizing the minimum spanning tree, and multi-quantum circuit mapping for improving fidelity and reducing the number of inserted SWAP gates is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of quantum computing compilation, and particularly relates to a multi-quantum circuit mapping method based on noise perception. BACKGROUND

[0002] Traditional single-circuit execution mode can cause low utilization of quantum computer resources, and multi-quantum circuit mapping can improve the overall efficiency of the quantum computing system by executing multiple quantum circuits in parallel. However, as the scale of quantum computing devices continues to expand, how to effectively manage and allocate quantum computing resources has become one of the key bottlenecks restricting the development of quantum computing.

[0003] Existing multi-quantum circuit mapping usually regards the hardware topology structure as a static and fixed input condition, partitions the original coupling graph, and does not fully consider the possible negative impact of high error rate bits and connections on overall performance. This method ignores the high error rate factor, which can cause unnecessary interference to the performance of the hardware system during actual operation, thereby affecting the execution effect of the circuit.

[0004] At the same time, the existing method usually adopts a resource management mode that tightly couples hardware partitioning and circuit allocation. In this mode, the partition decision is not an independent global planning stage, but an instant calculation in response to specific circuit allocation requests. The core logic is to search for a locally optimal physical subgraph in all available hardware resources for each circuit in the sequence. This circuit-driven, serialized resource allocation strategy has a design flaw, that is, the final hardware partition is not the result of global optimization, but the result of successive superposition of multiple local optimal decisions. This strategy causes the allocation result to be highly sensitive to the processing order, and systematically causes the connectivity of the hardware physical topology to degrade, causing resource fragmentation. This not only makes it difficult for subsequent circuits to find a complete and efficient execution area of the topology structure, but also damages the overall performance and resource utilization of parallel tasks due to the path dependence of the compilation process. SUMMARY

[0005] To solve the above technical problems, the present application provides a multi-quantum circuit mapping method based on noise perception.

[0006] To achieve the above purpose, the present application adopts the following technical solutions:

[0007] A multi-quantum circuit mapping method based on noise perception optimizes the architecture topology of a target quantum device in steps S1 to S3, and realizes the mapping of each quantum circuit in the quantum circuit set:

[0008] Step S1: Based on the original coupling graph of the target quantum device architecture, determine whether the maximum number of logical qubits in the quantum circuit set is less than the preset threshold of the number of physical qubits in the original coupling graph. If yes, generate an effective coupling graph by filtering physical qubits and physical coupling edges with high error rates, and proceed to step S2. Otherwise, use the original coupling graph as the effective coupling graph and proceed to step S2.

[0009] Step S2: Each connected component in the effective coupling graph is treated as a partition, and each partition is analyzed and optimized to obtain the effective physical partitions of the target quantum device architecture.

[0010] Step S3: Based on the effective physical partitioning of the target quantum device architecture, construct the logical qubit interaction diagram of each quantum circuit for each sub-circuit in the quantum circuit set, and obtain the mapping and optimization scheme of each quantum circuit by combining the quantitative calibration of the overall quality of each physical qubit.

[0011] Further, step S1 filters the original coupling graph according to the following steps:

[0012] Step S11: Obtain the readout error rate of the physical qubits and the two-qubit gate error rate of the physical coupling edge of the target quantum device architecture, and determine the percentile node index and percentile edge index by ascending order, and further use the linear interpolation algorithm to obtain the node threshold and edge threshold.

[0013] Step S12: Determine whether the readout error rate of each physical qubit is not less than the node threshold. If yes, delete the physical qubit and all the physical coupling edges connected to it in the original coupling graph. Otherwise, retain the physical qubit and all the physical coupling edges connected to it. Determine whether the two-qubit gate error rate of each physical coupling edge is not less than the edge threshold. If yes, delete the physical coupling edge in the original coupling graph. Otherwise, retain the physical coupling edge.

[0014] Furthermore, step S2 analyzes and optimizes each partition according to the following steps:

[0015] Step S21: Quantize and calibrate the overall quality of each physical qubit and each physical coupling edge in the effective coupling diagram.

[0016] Step S22: By determining whether the size of each partition is less than the preset minimum partition, find all partitions to be divided that are larger than the minimum partition, and calculate the quality score of the current partition based on the quantitative calibration of the combined quality of physical qubits and physical coupling edges.

[0017] Step S23: For each candidate partitioning strategy corresponding to each partition to be segmented, obtain the partitioning result and partition quality score corresponding to each candidate partitioning strategy, and then determine the global optimal partitioning strategy.

[0018] Step S24: Update the effective coupling graph using the globally optimal partitioning strategy, and repeat steps S22 to S24 until there are no partitioning strategies that can improve the partitioning quality, and use the obtained partitioning scheme as the effective physical partition of the target quantum device architecture.

[0019] Furthermore, step S21, which involves quantitatively calibrating the overall quality of each physical qubit and each physical coupling edge in the effective coupling diagram, specifically includes:

[0020] Calculate the node-wide fidelity of each physical qubit in the effective coupling graph using the following formulas:

[0021]

[0022] Among them, F v R represents the overall fidelity of the nodes, where α, β, and γ are weighting coefficients. v Let E be the readout error rate of the physical qubit v, and N(v) be the set of physical coupling edges connected to the physical qubit v. e Let e ​​be the two-qubit gate error rate of the physical coupling edge e, deg(v) be the degree of the physical qubit v, and N be the number of physical qubits in the effective coupling graph.

[0023] Calculate the combined edge weight of each physical coupling edge using the following formula:

[0024]

[0025] Among them, W uv E represents the edge composite weight. uv E is the two-qubit gate error rate of the physical coupling edge (u,v). min E is the minimum error rate of the two-qubit gate on the physical coupling edge of the effective coupling graph. max For the maximum value of the two-qubit gate error rate of the physically coupled edge in the effective coupling graph, F u F represents the node composite fidelity after normalization of the physical quantum bit u. v The node composite fidelity is the normalized value of the physical quantum bit v.

[0026] Further, step S22 calculates the partition quality score according to the following formula:

[0027]

[0028] Among them, Q pThe partition quality score is given by P, where P is the set of partitions in the effective coupled graph, a and b are weight coefficients, and E is the partition quality score. int (P i ) is partition P i The set of physical coupling edges contained therein. For partition P i Middle physical coupling edge e i The edge weights, W max For partition P i The corresponding maximum edge weight, D i For partition P i The diameter, For partition P i The average shortest path length, F v E represents the node composite fidelity after normalization of the physical quantum bit v. cut For the set of physically coupled edges that are being divided, For the set of physically coupled edges that are divided, e c The edge weights, W max_cut dinter represents the maximum combined edge weight corresponding to the set of physically coupled edges that are divided, and dinter represents the average shortest path length between the two partitions.

[0029] Further, step S23, determining the globally optimal partitioning strategy, specifically involves: for each partition to be partitioned, calculating the partition quality score corresponding to the partition under different candidate partitioning strategies, and further obtaining the quality gain corresponding to the partition under different candidate partitioning strategies; then, selecting the candidate partitioning strategy with the largest quality gain from each candidate partitioning strategy corresponding to each partition to be partitioned, and determining whether the quality gain of the candidate partitioning strategy is greater than a preset gain threshold; if so, then the candidate partitioning strategy is taken as the globally optimal partitioning strategy.

[0030] Further, step S23 generates candidate partitioning strategies for each partition to be segmented by using a strategy combining minimum spanning tree and multi-objective quality assessment as follows:

[0031] Step S23-1: For the coupled graph of the partition to be divided, construct the minimum spanning tree of the partition to be divided based on the edge comprehensive weight of each physical coupling edge in the coupled graph, with the goal of minimizing the sum of edge comprehensive weights. Each physical quantum bit in the coupled graph constitutes a vertex in the minimum spanning tree, and each physical coupling edge added to the minimum spanning tree constitutes a connecting edge in the minimum spanning tree. The edge comprehensive weight of each physical coupling edge is the weight of the corresponding connecting edge.

[0032] Step S23-2: Sort the weights of each connecting edge in the minimum spanning tree in descending order to form a weight sorting order. Based on the weight sorting order, remove one connecting edge in the minimum spanning tree one by one to construct a partitioning strategy that did not participate in step S23-3 until all partitioning strategies have participated in step S23-3.

[0033] Step S23-3: Using the partitioning strategy of step S23-2, tentatively partition the area to be divided to obtain sub-partition 1 and sub-partition 2, and determine whether the size of the two sub-partitions is not less than the preset minimum partition size. If yes, repeat steps S23-2 to S23-3. Otherwise, use the partitioning strategy as a candidate partitioning strategy for the area to be divided, and repeat steps S23-2 to S23-3.

[0034] Furthermore, step S3, which constructs the logical qubit interaction graph of the quantum circuit, specifically involves: each node of the logical qubit interaction graph corresponding to each logical qubit in the quantum circuit; the edges of the logical qubit interaction graph representing at least one two-qubit gate operation between two logical qubits; and the edge weights of the logical qubit interaction graph representing the number of two-qubit gate operations between two logical qubits.

[0035] Further, step S3 obtains the mapping and optimization schemes for each quantum circuit according to the following steps:

[0036] Step S31: Based on the logical qubit interaction diagram of the quantum circuit and the usage frequency of each logical qubit in the quantum circuit, sort the usage frequency of each logical qubit in descending order to form a logical qubit mapping priority list.

[0037] Step S32: Based on the effective physical partitions of the target quantum device architecture, determine the degree of each physical qubit, further add the physical qubit with the maximum degree to the pre-constructed maximum degree candidate set, and select the physical qubit with the maximum node comprehensive fidelity in the pre-constructed maximum degree candidate set as the seed physical qubit.

[0038] Step S33: Based on the logical qubit mapping priority list, map the logical qubit with the highest priority to the seed physical qubit, and then map each logical qubit to be mapped in the logical qubit mapping priority list to the effective physical partition in turn.

[0039] Further, step S33 maps each logical quantum to be mapped in the logical quantum bit mapping priority list to an effective physical partition according to the following steps:

[0040] S331: Based on all neighbors of the seed physical qubit, construct a first candidate neighbor set containing all unmapped physical qubits;

[0041] S332: When the first candidate neighbor set is not empty, map the logical qubit to be mapped to the physical qubit with the highest node synthesis fidelity in the candidate neighbor set; when the first candidate neighbor set is empty, select the unmapped physical qubits from the neighbor bits of the physical qubits that have established the mapping relationship to form the second candidate neighbor set.

[0042] S333: When the second candidate neighbor set is not empty, map the logical qubit to be mapped to the physical qubit with the highest node synthesis fidelity in the second candidate neighbor set;

[0043] S334: Repeat iterative steps S331 to S334 until all logical qubits have been mapped to the target quantum device.

[0044] The beneficial effects of adopting the above technical solution are as follows:

[0045] (1) The present invention adopts a partitioning algorithm based on minimum spanning tree. By comprehensively considering factors such as edge error rate, physical distance and connectivity through an improved weight function, the partitioning topology is optimized. Combined with the dual-objective evaluation mechanism of internal cohesion and inter-partition isolation, the cross-partition communication requirements are significantly reduced.

[0046] (2) This invention uses an error rate threshold pruning mechanism to comprehensively consider multiple dimensions of indicators such as the readout error rate of physical qubits and the error rate of dual quantum gates. It uses quantile statistics to automatically determine the pruning threshold, effectively isolate high error rate quantum resources, more accurately retain usable physical qubits, and improve fidelity.

[0047] (3) By setting adjustable parameters, the present invention can be flexibly configured according to different quantum hardware characteristics and task requirements, thus demonstrating good adaptability and optimization effect;

[0048] (4) In this invention, the two-stage process of seed mapping and iterative mapping fixes each decision within the range of the mapped area, avoiding invalid global exploration, reducing time complexity, and enabling a fast and low-cost mapping scheme. Attached Figure Description

[0049] Figure 1 This is a flowchart of the present invention;

[0050] Figure 2 This is the original coupling diagram of the target quantum device architecture in an embodiment of the present invention;

[0051] Figure 3This is a schematic diagram of a quantum circuit in an embodiment of the present invention;

[0052] Figure 4 This is an effective coupling diagram of the target quantum device architecture in an embodiment of the present invention;

[0053] Figure 5 This is a logic quantum bit interaction diagram according to an embodiment of the present invention;

[0054] Figure 6 This is a schematic diagram of the mapped circuit obtained in an embodiment of the present invention. Detailed Implementation

[0055] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings.

[0056] refer to Figure 1 A noise-aware multi-quantum circuit mapping method optimizes the topology of the target quantum device architecture according to steps S1 to S3, thereby realizing the mapping of each quantum circuit in the quantum circuit set.

[0057] Step S1: Based on the original coupling graph of the target quantum device architecture, determine whether the maximum number of logical qubits in the quantum circuit set is less than the preset threshold of the number of physical qubits in the original coupling graph. If yes, generate an effective coupling graph by filtering physical qubits and physical coupling edges with high error rates, and proceed to step S2. Otherwise, use the original coupling graph as the effective coupling graph and proceed to step S2.

[0058] Step S2: Each connected component in the effective coupling graph is treated as a partition, and each partition is analyzed and optimized to obtain the effective physical partitions of the target quantum device architecture.

[0059] Step S3: Based on the effective physical partitioning of the target quantum device architecture, construct the logical qubit interaction diagram of each quantum circuit for each sub-circuit in the quantum circuit set, and obtain the mapping and optimization scheme of each quantum circuit by combining the quantitative calibration of the comprehensive quality of each physical qubit.

[0060] Further, step S1 filters the original coupling graph according to the following steps:

[0061] Step S11: Obtain the readout error rate of physical qubits and the two-qubit gate error rate of physical coupling edges in the target quantum device architecture, and determine the percentile node index and percentile edge index by ascending order, and further use the linear interpolation algorithm to obtain the node threshold and edge threshold.

[0062] Step S12: Determine whether the readout error rate of each physical qubit is not less than the node threshold. If yes, delete the physical qubit and all the physical coupling edges connected to it in the original coupling graph. Otherwise, retain the physical qubit and all the physical coupling edges connected to it. Determine whether the two-qubit gate error rate of each physical coupling edge is not less than the edge threshold. If yes, delete the physical coupling edge in the original coupling graph. Otherwise, retain the physical coupling edge.

[0063] Furthermore, step S2 analyzes and optimizes each partition according to the following steps:

[0064] Step S21: Quantize and calibrate the overall quality of each physical qubit and each physical coupling edge in the effective coupling diagram.

[0065] Step S22: By determining whether the size of each partition is less than the preset minimum partition, find all partitions to be divided that are larger than the minimum partition, and calculate the quality score of the current partition based on the quantitative calibration of the combined quality of physical qubits and physical coupling edges.

[0066] Step S23: For each candidate partitioning strategy corresponding to each partition to be segmented, obtain the partitioning result and partition quality score corresponding to each candidate partitioning strategy, and then determine the global optimal partitioning strategy.

[0067] Step S24: Update the effective coupling graph using the globally optimal partitioning strategy, and repeat steps S22 to S24 until there are no partitioning strategies that can improve the partitioning quality, and use the obtained partitioning scheme as the effective physical partition of the target quantum device architecture.

[0068] Furthermore, step S21, which involves quantitatively calibrating the overall quality of each physical qubit and each physical coupling edge in the effective coupling diagram, specifically includes:

[0069] Calculate the node-wide fidelity of each physical qubit in the effective coupling graph using the following formulas:

[0070]

[0071] Among them, F v R represents the overall fidelity of the nodes, where α, β, and γ are weighting coefficients. v Let E be the readout error rate of the physical qubit v, and N(v) be the set of physical coupling edges connected to the physical qubit v. e Let e ​​be the two-qubit gate error rate of the physical coupling edge e, deg(v) be the degree of the physical qubit v, and N be the number of physical qubits in the effective coupling graph.

[0072] Calculate the combined edge weight of each physical coupling edge using the following formula:

[0073]

[0074] Among them, W uv E represents the edge composite weight. uv E is the two-qubit gate error rate of the physical coupling edge (u,v). min E is the minimum error rate of the two-qubit gate on the physical coupling edge of the effective coupling graph. max For the maximum value of the two-qubit gate error rate of the physically coupled edge in the effective coupling graph, F u F represents the node composite fidelity after normalization of the physical quantum bit u. v The node composite fidelity is the normalized value of the physical quantum bit v.

[0075] Further, step S22 calculates the partition quality score according to the following formula:

[0076]

[0077] Among them, Q p The partition quality score is given by P, where P is the set of partitions in the effective coupled graph, a and b are weight coefficients, and E is the partition quality score. int (P i ) is partition P i The set of physical coupling edges contained therein. For partition P i Middle physical coupling edge e i The edge weights, W max For partition P i The corresponding maximum edge weight, D i For partition P i The diameter, For partition P i The average shortest path length, F v E represents the node composite fidelity after normalization of the physical quantum bit v. cut For the set of physically coupled edges that are being divided, For the set of physically coupled edges that are divided, e c The edge weights, W max_cut dinter represents the maximum combined edge weight corresponding to the set of physically coupled edges that are divided, and dinter represents the average shortest path length between the two partitions.

[0078] Further, step S23, determining the globally optimal partitioning strategy, specifically involves: for each partition to be partitioned, calculating the partition quality score corresponding to the partition under different candidate partitioning strategies, and further obtaining the quality gain corresponding to the partition under different candidate partitioning strategies; then, selecting the candidate partitioning strategy with the largest quality gain from each candidate partitioning strategy corresponding to each partition to be partitioned, and determining whether the quality gain of the candidate partitioning strategy is greater than a preset gain threshold; if so, then the candidate partitioning strategy is taken as the globally optimal partitioning strategy.

[0079] Further, step S23 generates candidate partitioning strategies for each partition to be segmented by using a strategy combining minimum spanning tree and multi-objective quality assessment as follows:

[0080] Step S23-1: For the coupled graph of the partition to be divided, construct the minimum spanning tree of the partition to be divided based on the edge comprehensive weight of each physical coupling edge in the coupled graph, with the goal of minimizing the sum of edge comprehensive weights. Each physical quantum bit in the coupled graph constitutes a vertex in the minimum spanning tree, and each physical coupling edge added to the minimum spanning tree constitutes a connecting edge in the minimum spanning tree. The edge comprehensive weight of each physical coupling edge is the weight of the corresponding connecting edge.

[0081] Step S23-2: Sort the weights of each connecting edge in the minimum spanning tree in descending order to form a weight sorting order. Based on the weight sorting order, remove one connecting edge in the minimum spanning tree one by one to construct a partitioning strategy that did not participate in step S23-3 until all partitioning strategies have participated in step S23-3.

[0082] Step S23-3: Using the partitioning strategy of step S23-2, tentatively partition the area to be divided to obtain sub-partition 1 and sub-partition 2, and determine whether the size of the two sub-partitions is not less than the preset minimum partition size. If yes, repeat steps S23-2 to S23-3. Otherwise, use the partitioning strategy as a candidate partitioning strategy for the area to be divided, and repeat steps S23-2 to S23-3.

[0083] Furthermore, step S3, which constructs the logical qubit interaction graph of the quantum circuit, specifically involves: each node of the logical qubit interaction graph corresponding to each logical qubit in the quantum circuit; the edges of the logical qubit interaction graph representing at least one two-qubit gate operation between two logical qubits; and the edge weights of the logical qubit interaction graph representing the number of two-qubit gate operations between two logical qubits.

[0084] Further, step S3 obtains the mapping and optimization schemes for each quantum circuit according to the following steps:

[0085] Step S31: Based on the logical qubit interaction diagram of the quantum circuit and the usage frequency of each logical qubit in the quantum circuit, sort the usage frequency of each logical qubit in descending order to form a logical qubit mapping priority list.

[0086] Step S32: Based on the effective physical partitions of the target quantum device architecture, determine the degree of each physical qubit, further add the physical qubit with the maximum degree to the pre-constructed maximum degree candidate set, and select the physical qubit with the maximum node comprehensive fidelity in the pre-constructed maximum degree candidate set as the seed physical qubit.

[0087] Step S33: Based on the logical qubit mapping priority list, map the logical qubit with the highest priority to the seed physical qubit, and then map each logical qubit to be mapped in the logical qubit mapping priority list to the effective physical partition in turn.

[0088] Further, step S33 maps each logical quantum to be mapped in the logical quantum bit mapping priority list to an effective physical partition according to the following steps:

[0089] S331: Based on all neighbors of the seed physical qubit, construct a first candidate neighbor set containing all unmapped physical qubits;

[0090] S332: When the first candidate neighbor set is not empty, the logical qubit to be mapped is mapped to the physical qubit with the highest node synthesis fidelity in the candidate neighbor set; when the first candidate neighbor set is empty, the unmapped physical qubits are selected from the neighbor bits of the physical qubits that have established the mapping relationship to form the second candidate neighbor set.

[0091] S333: When the second candidate neighbor set is not empty, map the logical qubit to be mapped to the physical qubit with the highest node synthesis fidelity in the second candidate neighbor set;

[0092] S334: Repeat iterative steps S331 to S334 until all logical qubits have been mapped to the target quantum device.

[0093] The present invention will be further described below using IBMQ Nairobi as the target quantum device.

[0094] refer to Figure 2 The original IBMQ Nairobi coupling graph contains 7 physical qubit nodes, and Figure 2It contains the readout error rate of physical qubits and the two-qubit gate error rate of physical coupling edges, obtained programmatically from pre-published hardware properties of the target quantum backend according to the Qiskit framework. The architecture topology of the target quantum device is further optimized using the following steps. Figure 3 The quantum circuit shown is mapped onto the target quantum device:

[0095] The first step is to sort the readout error rate of physical qubits and the two-qubit gate error rate of physical coupling edges in ascending order, resulting in a sorted qubit readout error rate of [0.0183, 0.0193, 0.0199, 0.0223, 0.0225, 0.0258, 0.0580]. Then, linear interpolation is used to obtain the node threshold and edge threshold. Specifically, the percentile node index is preset to 95%, and an index value is calculated as index = 0.95 × (n-1), where n is the number of physical qubits, which is 7 in this case, resulting in an index value of 5.7. This value means that the result is located between the 6th element (index 5) and the 7th element (index 6) in the sorted list, with a greater bias towards the 7th element. According to the calculation formula: 6th value + (7th value - 6th value) × 0.7, the node threshold T is obtained. n The value is 0.048340. Similarly, the edge threshold T is obtained. e It is 0.012572.

[0096] Since the node readout error rate of Q0 in the original coupling graph is 0.058 > T n If the node is not used, it will be deleted along with its connected edges, and the node will no longer be used. For any edge, the two-qubit gate error rate of its physical coupling edge is less than T. e Therefore, all edges are preserved, thus we obtain Figure 4 The effective coupling graph shown has 6 nodes and 5 edges.

[0097] The second step, for an effective coupled graph, is to first calculate the node-to-node fidelity of each node and the edge-to-edge weight. For example, when calculating the node-to-node fidelity of Q1, we first obtain its node readout error rate R. v The value is 0.0199. There are two edges connected to this node with N(v) of (Q1, Q2) and (Q1, Q3). The two-qubit gate error rate E of these two edges is 0.0199. e The values ​​are 0.006983 and 0.006791 respectively. Therefore, the average two-qubit gate error rate of the edge connected to this node is 0.0069. Since the degree of Q1 is 2, the total number of nodes N in the processed coupled graph is 6, so the connectivity is 0.4. Therefore, the node overall fidelity of Q1 is calculated to be 0.5173.

[0098] Next, we need to calculate the combined weight of each edge. The smaller the weight, the better, as it indicates a low two-qubit gate error rate and high fidelity in connecting the two ends of the node. Taking (Q1, Q2) as an example, we first obtain the two-qubit gate error rate E of this edge. 12 The minimum two-qubit gate error rate E across all edges in the coupled graph is 0.006983. min The value is 0.006791, and the maximum value is E. max The weight is 0.012572. At the same time, the nodes at both ends of the edge also need to be normalized. Finally, the comprehensive weight of the edge (Q1, Q2) can be calculated to be 0.78.

[0099] Similarly, the final fidelity of each node is Q1: 0.5173, Q2: 0.3574, Q3: 0.5168, Q4: 0.3575, Q5: 0.6767, Q6: 0.3564, and the weights of each edge are (Q1, Q2): 0.78, (Q1, Q3): 0.50, (Q3, Q5): 1.25, (Q4, Q5): 0.54, (Q5, Q6): 1.17.

[0100] at present Figure 4 There is one connected component. Since the number of connected components is 6, the minimum partition requirement is met, so no further partitioning is needed. However, to illustrate the calculation method of the partition quality score, the following calculation is still based on this partition: First, calculate the isolation between partitions, which is the latter half of the quality score calculation formula. This is an indicator used to evaluate the degree of separation between different partitions, aiming to quantify and minimize potential crosstalk between partitions. Since there is only one partition, the number of partitions is no more than 1, this condition is not met, so the isolation between partitions is 0. Second, calculate the cohesion within the partition, which is the first half of the quality score calculation formula. This is a comprehensive indicator used to evaluate the quality of the partition itself, measuring whether the qubits within the partition are of high quality and tightly connected. The total node fidelity of this partition is 2.7821, the maximum value of the edge comprehensive weight is 1.25, and the weight of each edge is normalized and summed to obtain 1.608. The number of nodes in the partition |P| is 6, and D is the diameter of the partition, which is the maximum value of the shortest path between any two points in the graph. The length from Q2 to Q4 is 4. The total sum of the shortest paths between all 15 pairs of nodes is 32, so L avg The value is 2.133, where the weight coefficients a and b are preset to 0.6 and 0.4 respectively, and the quality of the partition can be calculated to be 0.23.

[0101] The third step, according to Figure 3 Quantum circuits construct logical qubit interaction diagrams, such as Figure 5As shown, q0 and q2 interact twice, q0 and q3 interact once, q1 and q2 interact once, and q2 and q3 interact once. Then, the usage frequency of each logical qubit is counted and sorted in descending order to form a logical qubit mapping priority list: q2: 4, q0: 3, q3: 2, q1: 1.

[0102] Next, we process the effective physical partitions, calculate the degree of each physical qubit within the partition, obtain the candidate set of the maximum degree {Q5}, and determine Q5 as the seed physical qubit. Then, we map the logic qubit q2, which is used most frequently, to Q5. Next, we process the logic qubits to be mapped in the order of the logic qubit mapping priority list. First, we process q0. Among all the neighbors of the seed physical qubit, we select {Q3, Q4, Q6} as the first candidate neighbor set. Among them, Q3 has the highest fidelity, so we map q0 to Q3. Similarly, we map q3 to Q4 and q1 to Q6. Therefore, the final initial mapping is {q2:Q5, q0:Q3, q3:Q4, q1:Q6}.

[0103] Since each gate in a quantum circuit needs to satisfy the nearest neighbor constraint when it is executed on a quantum device, in this embodiment... Figure 3 Quantum circuit mapping to Figure 4 In the effective coupling graph, each gate needs to be executed sequentially from left to right. First is gate (q2, q0). Based on the initial mapping {q2: Q5, q0: Q3, q3: Q4, q1: Q6}, q2 is mapped to Q5, q0 is mapped to Q3, and so on. Figure 4 It can be seen that Q5 and Q3 are connected by an edge, so the nearest neighbor constraint is satisfied.

[0104] Next is gate (q2, q3), where q2 maps to Q5 and q3 maps to Q4, still satisfying the nearest neighbor constraint; similarly, gates (q1, q2) and (q0, q2) satisfy the nearest neighbor constraint.

[0105] Only the gate (q3, q0) does not satisfy the nearest neighbor constraint, so we need to insert the SAPP gate (swap gate), that is, (q0, q2), to make it satisfy the nearest neighbor constraint. In this way, the mapping becomes {q0: Q5, q2: Q3, q3: Q4, q1: Q6}, and the original gate (q3, q0) becomes (q3, q2).

[0106] That is, under the initial mapping scheme, Figure 3 In the quantum circuit, only gate (q3, q0) does not satisfy the nearest neighbor constraint. Therefore, only one SWAP gate (q0, q2) needs to be inserted to satisfy the nearest neighbor constraint, resulting in the following: Figure 6 The diagram shown is a schematic of the mapping circuit.

[0107] The above description is merely a preferred embodiment of the present invention and does not constitute any limitation on the present invention. Any simple modifications, alterations, or equivalent structural changes made to the above embodiments based on the technical essence of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A noise-aware multi-quantum circuit mapping method, characterized in that, The architecture topology of the target quantum device is optimized according to steps S1 to S3 to achieve the mapping of each quantum circuit in the quantum circuit set: Step S1: Based on the original coupling graph of the target quantum device architecture, determine whether the maximum number of logical qubits in the quantum circuit set is less than the preset threshold of the number of physical qubits in the original coupling graph. If yes, generate an effective coupling graph by filtering physical qubits and physical coupling edges with high error rates, and proceed to step S2. Otherwise, use the original coupling graph as the effective coupling graph and proceed to step S2. Step S2: Each connected component in the effective coupling graph is treated as a partition, and each partition is analyzed and optimized to obtain the effective physical partitions of the target quantum device architecture. Step S3: Based on the effective physical partitioning of the target quantum device architecture, construct the logical qubit interaction diagram of each quantum circuit for each sub-circuit in the quantum circuit set, and obtain the mapping and optimization scheme of each quantum circuit by combining the quantitative calibration of the overall quality of each physical qubit.

2. The noise-aware multi-quantum circuit mapping method according to claim 1, characterized in that, Step S1 involves filtering the original coupling graph as follows: Step S11: Obtain the readout error rate of physical qubits and the two-qubit gate error rate of physical coupling edges in the target quantum device architecture, and determine the percentile node index and percentile edge index by ascending order, and further use the linear interpolation algorithm to obtain the node threshold and edge threshold. Step S12: Determine whether the readout error rate of each physical qubit is not less than the node threshold. If yes, delete the physical qubit and all the physical coupling edges connected to it in the original coupling graph. Otherwise, retain the physical qubit and all the physical coupling edges connected to it. Determine whether the two-qubit gate error rate of each physical coupling edge is not less than the edge threshold. If yes, delete the physical coupling edge in the original coupling graph. Otherwise, retain the physical coupling edge.

3. The noise-aware multi-quantum circuit mapping method according to claim 1, characterized in that, Step S2 involves analyzing and optimizing each partition as follows: Step S21: Quantize and calibrate the overall quality of each physical qubit and each physical coupling edge in the effective coupling diagram. Step S22: By determining whether the size of each partition is less than the preset minimum partition, find all partitions to be divided that are larger than the minimum partition, and calculate the quality score of the current partition based on the quantitative calibration of the combined quality of physical qubits and physical coupling edges. Step S23: For each candidate partitioning strategy corresponding to each partition to be segmented, obtain the partitioning result and partition quality score corresponding to each candidate partitioning strategy, and then determine the global optimal partitioning strategy. Step S24: Update the effective coupling graph using the globally optimal partitioning strategy, and repeat steps S22 to S24 until there are no partitioning strategies that can improve the partitioning quality, and use the obtained partitioning scheme as the effective physical partition of the target quantum device architecture.

4. The noise-aware multi-quantum circuit mapping method according to claim 3, characterized in that, The step S21, which involves quantitatively calibrating the overall quality of each physical qubit and each physical coupling edge in the effective coupling diagram, specifically includes: Calculate the node-wide fidelity of each physical qubit in the effective coupling graph using the following formulas: Among them, F v R represents the overall fidelity of the nodes, where α, β, and γ are weighting coefficients. v Let E be the readout error rate of the physical qubit v, and N(v) be the set of physical coupling edges connected to the physical qubit v. e Let e ​​be the two-qubit gate error rate of the physical coupling edge e, deg(v) be the degree of the physical qubit v, and N be the number of physical qubits in the effective coupling graph. Calculate the combined edge weight of each physical coupling edge using the following formula: Among them, W uv E represents the edge composite weight. uv E is the two-qubit gate error rate of the physical coupling edge (u,v). min E is the minimum error rate of the two-qubit gate on the physical coupling edge of the effective coupling graph. max For the maximum value of the two-qubit gate error rate of the physically coupled edge in the effective coupling graph, F u F represents the node composite fidelity after normalization of the physical quantum bit u. v The node composite fidelity is the normalized value of the physical quantum bit v.

5. The noise-aware multi-quantum circuit mapping method according to claim 4, characterized in that, Step S22 calculates the partition quality score according to the following formula: Among them, Q p The partition quality score is given by P, where P is the set of partitions in the effective coupled graph, a and b are weight coefficients, and E is the partition quality score. int (P i ) is partition P i The set of physical coupling edges contained therein. For partition P i Middle physical coupling edge e i The edge weights, W max For partition P i The corresponding maximum edge weight, D i For partition P i The diameter, For partition P i The average shortest path length, F v E represents the node composite fidelity after normalization of the physical quantum bit v. cut For the set of physically coupled edges that are being divided, For the set of physically coupled edges that are divided, e c The edge weights, W max_cut dinter represents the maximum combined edge weight corresponding to the set of physically coupled edges that are divided, and dinter represents the average shortest path length between the two partitions.

6. The noise-aware multi-quantum circuit mapping method according to claim 5, characterized in that, The step S23 of determining the globally optimal partitioning strategy specifically involves: for each partition to be partitioned, calculating the partition quality score corresponding to the partition under different candidate partitioning strategies, and further obtaining the quality gain corresponding to the partition under different candidate partitioning strategies; then, selecting the candidate partitioning strategy with the largest quality gain from each candidate partitioning strategy corresponding to each partition to be partitioned, and determining whether the quality gain of the candidate partitioning strategy is greater than a preset gain threshold. If so, the candidate partitioning strategy is taken as the globally optimal partitioning strategy.

7. The noise-aware multi-quantum circuit mapping method according to claim 3, characterized in that, Step S23 generates candidate partitioning strategies for each partition to be segmented by using a strategy combining minimum spanning tree and multi-objective quality assessment as follows: Step S23-1: For the coupled graph of the partition to be divided, construct the minimum spanning tree of the partition to be divided based on the edge comprehensive weight of each physical coupling edge in the coupled graph, with the goal of minimizing the sum of edge comprehensive weights. Each physical quantum bit in the coupled graph constitutes a vertex in the minimum spanning tree, and each physical coupling edge added to the minimum spanning tree constitutes a connecting edge in the minimum spanning tree. The edge comprehensive weight of each physical coupling edge is the weight of the corresponding connecting edge. Step S23-2: Sort the weights of each connecting edge in the minimum spanning tree in descending order to form a weight sorting order. Based on the weight sorting order, remove one connecting edge in the minimum spanning tree one by one to construct a partitioning strategy that did not participate in step S23-3 until all partitioning strategies have participated in step S23-3. Step S23-3: Using the partitioning strategy of step S23-2, tentatively partition the area to be divided to obtain sub-partition 1 and sub-partition 2, and determine whether the size of the two sub-partitions is not less than the preset minimum partition size. If yes, repeat steps S23-2 to S23-3. Otherwise, use the partitioning strategy as a candidate partitioning strategy for the area to be divided, and repeat steps S23-2 to S23-3.

8. The noise-aware multi-quantum circuit mapping method according to claim 1, characterized in that, The step S3 of constructing the logical qubit interaction graph of the quantum circuit specifically involves: each node of the logical qubit interaction graph corresponds to each logical qubit in the quantum circuit; the edges of the logical qubit interaction graph represent at least one two-qubit gate operation between two logical qubits; and the edge weights of the logical qubit interaction graph represent the number of two-qubit gate operations between two logical qubits.

9. The noise-aware multi-quantum circuit mapping method according to claim 8, characterized in that, Step S3 obtains the mapping and optimization schemes for each quantum circuit according to the following steps: Step S31: Based on the logical qubit interaction diagram of the quantum circuit and the usage frequency of each logical qubit in the quantum circuit, sort the usage frequency of each logical qubit in descending order to form a logical qubit mapping priority list. Step S32: Based on the effective physical partitions of the target quantum device architecture, determine the degree of each physical qubit, further add the physical qubit with the maximum degree to the pre-constructed maximum degree candidate set, and select the physical qubit with the maximum node comprehensive fidelity in the pre-constructed maximum degree candidate set as the seed physical qubit. Step S33: Based on the logical qubit mapping priority list, map the logical qubit with the highest priority to the seed physical qubit, and then map each logical qubit to be mapped in the logical qubit mapping priority list to the effective physical partition in turn.

10. The noise-aware multi-quantum circuit mapping method according to claim 9, characterized in that, Step S33 maps each logical quantum to be mapped in the logical quantum bit mapping priority list to an effective physical partition according to the following steps: S331: Based on all neighbors of the seed physical qubit, construct a first candidate neighbor set containing all unmapped physical qubits; S332: When the first candidate neighbor set is not empty, map the logical qubit to be mapped to the physical qubit with the highest node synthesis fidelity in the candidate neighbor set; When the first candidate neighbor set is empty, the unmapped physical qubits are selected from the neighbor bits of the physical qubits that have established a mapping relationship to form the second candidate neighbor set. S333: When the second candidate neighbor set is not empty, map the logical qubit to be mapped to the physical qubit with the highest node synthesis fidelity in the second candidate neighbor set; S334: Repeat iterative steps S331 to S334 until all logical qubits have been mapped to the target quantum device.

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