Neutral atom quantum compiling method and system for off-line pre-calculation

Abstract

The invention discloses a neutral atom quantum compiling method and system for off-line pre-calculation, and belongs to the field of quantum computation.The method comprises the two stages of off-line template construction and on-line compiling, specifically, in the off-line stage, a neutral atom array is abstracted into a two-dimensional grid, an effective gate candidate set is constructed based on the Rydberg blocking radius and the parallel execution limiting radius, and an effective gate candidate set is constructed based on the effective gate candidate set; generating a space template configured by the maximum parallel gate by using a satisfiability model theory solver, and expanding a template library through rotational symmetry; in the online stage, quantum circuits are layered, matching templates are retrieved, slot distribution, direction selection and conflict evaluation are carried out, and finally an executable operation sequence is generated through timing sequence routing coloring. According to the method, the compiling efficiency, the expandability and the circuit execution fidelity are remarkably improved, and the method is suitable for a large-scale neutral atom quantum computing platform.

Description

Technical Field

[0001] This invention relates to the field of quantum computing, and in particular to an offline pre-computation method and system for neutral atom quantum compilation. Background Technology

[0002] Quantum computing, as a next-generation computing paradigm, has attracted widespread attention due to its potential for exponential speedup. Among them, quantum computing platforms based on neutral atom arrays are gradually becoming one of the important candidate technologies for achieving quantum advantage due to their unique scalability, reconfigurability, and precise control over many-body interactions. In neutral atom systems, qubits are carried by individual atoms and can be dynamically rearranged using optical tweezers, thus achieving flexible qubit layout in space. This dynamic reconfigurability provides new possibilities for the optimization of quantum circuits, making parallel gate operations and qubit routing feasible at the hardware level. However, efficiently mapping abstract quantum algorithms to physically executable sequences of quantum operations still relies on powerful compilation frameworks adapted to the characteristics of neutral atoms. The core goal of quantum compilation is to achieve high-fidelity execution of quantum circuits while strictly adhering to hardware physical constraints, while improving system scalability and compilation efficiency.

[0003] Although some progress has been made in compilation methods for neutral atom quantum computing platforms in recent years, there are still obvious limitations and trade-offs: First, regarding fidelity, existing methods often improve parallelism by adding Rydberg excitation stages or additional routing operations. While this strategy speeds up computation to some extent, it introduces additional control errors and increases the risk of decoherence of idle qubits under unnecessary excitations, thereby reducing the overall execution fidelity of the quantum circuit.

[0004] Secondly, in terms of scalability, some solver-based optimization methods can obtain high-fidelity qubit mapping schemes, but they rely on global constraint solving, which has extremely high computational complexity. This leads to a significant decrease in efficiency when dealing with large-scale quantum circuits, making it difficult to meet the needs of practical quantum algorithms.

[0005] Furthermore, while most current methods perform reasonably well with small quantum circuits, their performance drops sharply as the circuit size and number of operations increase, making it difficult to maintain efficient compilation speeds.

[0006] Finally, existing technologies generally employ real-time or local optimization strategies, failing to effectively separate the static physical constraints of the hardware from the dynamic compilation tasks of the quantum circuits during the compilation process. This approach makes it difficult to achieve a balanced optimization between fidelity, efficiency, and scalability, becoming a bottleneck for neutral atom quantum compilation technology. Summary of the Invention

[0007] The purpose of this invention is to overcome the problems existing in the prior art and provide an offline pre-computation method and system for neutral atom quantum compilation. By solving the maximum parallel gate configuration under hardware constraints at the system level in one go, a reusable spatial template library is constructed to achieve efficient planning of qubit layout and gate operations. This method can not only significantly reduce the computational overhead of real-time compilation, but also improve system scalability while ensuring fidelity, fundamentally solving the trade-off problem between fidelity, efficiency and scalability in the prior art.

[0008] The objective of this invention is achieved through the following technical solution: Firstly, an offline pre-computation method for neutral atom quantum compilation is provided, comprising the following steps: S1. Offline template construction and standardization: The neutral atom array is abstracted into an n×n two-dimensional mesh, a parallel gate placement optimization model under regional constraints is established, the model is solved using a satisfiability modulus solver, and spatial normalization is performed on each solution to obtain a spatial template that maximizes parallelism. S2. Online Hierarchy and Candidate Retrieval: Convert the logic circuit into a directed acyclic graph, perform topological hierarchical division, and obtain the gate set for each layer; retrieve the candidate space template set that meets the capacity condition based on the number of gates in each layer; S3. Slot allocation: Assign the set of logic gates to the set of physical slots of the space template selected in step S2, wherein the minimum center distance matching anchoring strategy is adopted, and the specific allocation of each gate in the physical slot and the resulting set of movement paths are output. S4. Direction Selection and Movement Conflict Assessment: Select a direction for each two-qubit gate, assess the movement conflict cost, select the direction with the minimum incremental conflict, and output the set of directed movement paths and the cumulative conflict cost; S5. Template Selection: The globally optimal template is selected from the candidate template set based on the comprehensive cost function, which comprehensively considers conflict cost, movement path length and layer splitting penalty. S6. Temporal route coloring: Construct a motion conflict graph, allocate time groups through graph coloring, and generate parallel execution sequences; S7. Fidelity Assessment and Mapping Feedback: Calculate the mapping fidelity, and trigger backtracking optimization when it falls below the threshold.

[0009] In some embodiments, the constraints of the parallel gate placement optimization model include: When executing a two-qubit gate, the distance between the two atoms is less than the Rydberg blocking radius; For any two simultaneous two-qubit gates, the distance between any pair of atoms involved is greater than the execution limit radius.

[0010] In some embodiments, the spatial normalization process includes: Perform the following steps for each solution: , , The rotation.

[0011] In some embodiments, retrieving a set of candidate space templates that meet the capacity condition based on the number of doors in each layer includes: If the number of doors in a certain layer exceeds the maximum capacity of the template library, the layer is split into several sub-layers according to the recursive partitioning strategy until each sub-layer meets the capacity condition of a certain template. If the candidate space template set is empty, the layer splitting process is triggered and the search is repeated.

[0012] In some embodiments, the anchoring strategy includes: Fully anchored doors are matched based on minimum center distance; after the allocation of fully anchored doors is completed, some anchored doors are allocated to the remaining slots according to the nearest neighbor principle; the remaining unanchored doors are allocated using a greedy or local search strategy.

[0013] In some embodiments, the cost of incremental conflict in step S4 is: Where 'o' represents the alternative direction, This represents the incremental conflict cost of alternative directions. Indicates the cost of movement conflict. This represents the existing set of movement paths. This represents the newly generated set of movement paths.

[0014] In some embodiments, the comprehensive cost function is: in, Indicates the cost of conflict, The length of the movement path. For layer splitting penalty items, These are the weight parameters.

[0015] In some embodiments, step S6 employs a greedy coloring or heuristic minimum remaining color strategy to obtain an approximate minimum number of colors.

[0016] In some embodiments, a fidelity model is introduced in step S7: in, Indicates the fidelity of door operation. Indicates atomic transport fidelity. This indicates the fidelity of decoherence.

[0017] Secondly, an offline pre-computation neutral atom quantum compiler system is provided, comprising: The offline template construction and standardization module is used to abstract the neutral atom array into an n×n two-dimensional mesh, establish a parallel gate placement optimization model under regional constraints, solve the model using a satisfiability modulus solver, and perform spatial normalization on each solution to obtain a spatial template that maximizes parallelism. The online hierarchical and candidate retrieval module is used to convert logic circuits into directed acyclic graphs, perform topological hierarchical division, and obtain the gate set for each layer; and retrieve the candidate space template set that meets the capacity condition based on the number of gates in each layer. The slot allocation module is used to allocate a set of logic gates to a set of physical slots in a selected space template. It employs an anchoring strategy of minimum center distance matching and outputs the specific allocation of each gate in a physical slot and the resulting set of movement paths. The direction selection and movement conflict assessment module is used to select a direction for each two-qubit gate, assess the movement conflict cost, select the direction with the minimum incremental conflict, and output the set of oriented movement paths and the cumulative conflict cost. The template selection module is used to select the globally optimal template from the candidate space template set based on a comprehensive cost function, wherein the comprehensive cost function comprehensively considers conflict cost, movement path length and layer splitting penalty. The temporal routing coloring module is used to construct a movement conflict graph, allocate time groups through graph coloring, and generate parallel execution sequences; The fidelity assessment and mapping feedback module is used to calculate the mapping fidelity and trigger backtracking optimization when it falls below a threshold.

[0018] It should be further noted that the technical features corresponding to the above-mentioned options and embodiments can be combined or substituted with each other to form new technical solutions without conflict.

[0019] Compared with existing technologies, this invention has several significant advantages in the field of neutral quantum compilation: 1. This invention achieves a revolutionary improvement in compilation efficiency. By advancing the most computationally intensive and complex constraint solving process (i.e., SMT solving) to the offline pre-compilation stage, this method significantly reduces the computational burden of online compilation. During actual compilation, the compiler does not need to perform real-time solving, but only needs to quickly query and match applicable templates from a pre-generated database, thereby compressing the compilation time, which may traditionally take minutes or even hours, to within seconds. This approach not only significantly accelerates the compilation speed of quantum circuits but also enables the rapid deployment of large-scale quantum circuits, achieving an order-of-magnitude efficiency improvement.

[0020] 2. This method demonstrates superior scalability. By pre-generating multiple templates for atomic arrays of different sizes, a highly adaptable template library is constructed. Whether dealing with small quantum circuits or large, complex quantum circuits, suitable templates can be quickly found for compilation. This effectively avoids the exponential time growth problem faced by traditional compilation methods as circuit size increases, enabling the system to support flexible scheduling and deployment of larger-scale quantum circuits while maintaining high efficiency.

[0021] 3. In terms of hardware resource utilization, this invention also has significant advantages. Through the precise calculation of the SMT solver, each generated template represents the maximum parallelism and conflict-free gate operation configuration achievable within a specified region. This means that the parallel computing capability of the neutral atom array is fully utilized, which helps to reduce the overall number of Rydberg excitation stages, thereby directly improving the fidelity of the quantum circuit in actual execution. At the same time, this optimization ensures the efficient use of hardware resources, allowing each qubit to play a full role in the computation process.

[0022] 4. The template set generated by this invention possesses high versatility and reusability. These templates do not depend on any specific quantum algorithm, but rather construct a fundamental resource library that can be used to compile various quantum circuits on target neutral atom hardware. This versatility allows the template library to be reused in different tasks and application scenarios, greatly reducing the complexity and computational cost of subsequent compilation work, while providing a solid foundation for the long-term maintainability and scalability of the quantum computing platform. Attached Figure Description

[0023] Figure 1 This is a flowchart of an offline pre-computation neutral atom quantum compilation method according to the present invention; Figure 2 A schematic diagram illustrating the construction of a spatial template with progressively increasing dimensions according to the present invention; Figure 3 This is a schematic diagram illustrating the standardized extension of the present invention (geometric center alignment, node alignment); Figure 4 This is a schematic diagram of a movement path conflict according to the present invention; Figure 5 This is a schematic diagram illustrating the preferred template and the minimization of overall cost in this invention. Detailed Implementation

[0024] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] It should be noted that the defects in the solutions in the prior art are all the results of the inventors' practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed by the embodiments of this application in the following text should be the inventors' contributions to this application in the process of invention and creation, and should not be understood as technical content known to those skilled in the art.

[0026] In view of the technical problems pointed out in the background art, the present invention provides the following embodiments: In one exemplary embodiment, an offline pre-computation method for neutral atom quantum compilation is provided, such as... Figure 1 As shown, it includes the following steps: S1. Offline template construction and standardization: The neutral atom array is abstracted into an n×n two-dimensional mesh, a parallel gate placement optimization model under regional constraints is established, the model is solved using a satisfiability modulus solver, and spatial normalization is performed on each solution to obtain a spatial template that maximizes parallelism. S2. Online Hierarchy and Candidate Retrieval: Convert the logic circuit into a directed acyclic graph, perform topological hierarchical division, and obtain the gate set for each layer; retrieve the candidate space template set that meets the capacity condition based on the number of gates in each layer; S3. Slot allocation: Assign the set of logic gates to the set of physical slots of the space template selected in step S2, wherein the minimum center distance matching anchoring strategy is adopted, and the specific allocation of each gate in the physical slot and the resulting set of movement paths are output. S4. Direction Selection and Movement Conflict Assessment: Select a direction for each two-qubit gate, assess the movement conflict cost, select the direction with the minimum incremental conflict, and output the set of directed movement paths and the cumulative conflict cost; S5. Template Selection: The globally optimal template is selected from the candidate template set based on the comprehensive cost function, which comprehensively considers conflict cost, movement path length and layer splitting penalty. S6. Temporal route coloring: Construct a motion conflict graph, allocate time groups through graph coloring, and generate parallel execution sequences; S7. Fidelity Assessment and Mapping Feedback: Calculate the mapping fidelity, and trigger backtracking optimization when it falls below the threshold.

[0027] Specifically, in step S1, the present invention generates a gate execution mode library containing hardware compatibility and optimal parallelism through offline pre-compilation. The present invention first abstracts the neutral atom array into a two-dimensional... A square grid is used, where each grid point represents a potential qubit storage location. Subsequently, based on the physical constraints of the hardware, a parallel gate placement optimization model under region constraints is established. The core constraints of this model include: Reedburg blocking radius ( When performing a two-qubit gate, the distance between the two atoms must be less than [a certain value]. To achieve stable two-qubit entanglement.

[0028] Parallel execution limit radius ( To avoid crosstalk, for any two simultaneous two-qubit gates, the distance between any pair of atoms involved must be greater than the limit radius. .

[0029] Based on the above constraints, this invention transforms the problem of finding the maximum parallel gate configuration into a discrete optimization problem: from all possible effective gate positions... In this problem, a conflict-free maximum subset is selected. This invention utilizes a Satisfiability Modular Theory (SMT) solver to solve this optimization problem precisely. The solver encodes all constraints and, with the objective of maximizing the number of selected gates, outputs one or more optimal spatial layout schemes, each of which is a spatial template. To construct a scalable and rich template library, this invention iterates and enhances the above solution process: such as... Figure 2 As shown, first, templates are constructed in increasing sizes, starting with smaller array sizes (such as...). Start by gradually increasing At this scale, SMT solutions are run for each size, generating a series of templates suitable for hardware of different sizes. Then, utilizing the four-fold rotational symmetry of the square array, each solved template is... , , The template library is expanded fourfold in diversity without increasing computational cost through rotation. The entire template set generation process is completed offline and is independent of any specific quantum circuit. The final result is a static, reusable template dataset covering multiple spatial scales, providing an efficient, pre-computed optimized layout scheme for the subsequent online compilation stage.

[0030] Furthermore, in the offline phase, for the target n×n atom array, all possible two-qubit gate candidate pairs are enumerated and an effective candidate set is constructed. Its mathematical definition is: In the formula Represents the coordinates of grid points on the array. Indicates the interaction radius. A conflict graph is constructed based on the candidate set: if the distance between any two bit pairs is less than the limit radius... Then the corresponding gates conflict with each other. To obtain a space template that maximizes parallelism, a binary selection variable is introduced. Indicate whether to select the i-th candidate gate, and solve the following binary integer optimization problem: This problem is solved offline in batch processing by an SMT solver or an integer planner, yielding a set of maximum parallel gates. Next, spatial normalization is performed on each solution to form a template. Normalization includes geometric center alignment, node alignment, and symmetry expansion, such as... Figure 3 As shown, apply the following to each solution: , , Rotation to increase template diversity; the output of the offline module is a template library. Record template parallel capacity The database is stored using a capacity index and geometric normalization for fast retrieval during online operations.

[0031] For example, in step S2, the logic circuit is received in the online stage and converted into a directed acyclic graph, and topological layering is performed to obtain the gate set of each layer. The number of doors is If the number of doors in a certain layer exceeds the maximum capacity of the template library, then the layer is recursively split into several sub-layers until each sub-layer satisfies the capacity condition of a certain space template. For each layer... The template library is searched to obtain a set of candidate space templates: like If empty, the layer splitting process is triggered and the search is repeated. The output of this step is a set of candidate space templates and the anchoring information of the current layer door (from the physical location allocation of the previous layer), which is used for subsequent slot allocation.

[0032] For example, in step S3, the set of logic gates of the current layer is assigned to the set of physical slots of the selected space template. Prioritize maintaining consistency with the physical allocation of the previous layer to minimize movement. First, classify the anchoring of gates within the layer: fully anchored means both bits have physical locations in the previous layer; partially anchored means only one bit has a location; and unanchored means no allocated location. The module processes according to priority: first, for fully anchored gates, solve the minimum center distance matching problem and record the center position. And solve the following minimum matching to reduce displacement: Where A is the set of fully anchored gates. For one-to-one mapping, This represents the physical slot coordinates. This minimization can be achieved using the Hungarian algorithm or the minimum weight matching algorithm. After fully anchored gate allocation, some anchored gates are allocated to the remaining slots according to the nearest neighbor principle; the remaining unanchored gates are allocated using a greedy or local search strategy to further reduce the overall movement cost. The slot allocation finally outputs the specific allocation of each gate on the template slot and the resulting set of movement paths. .

[0033] For example, in step S4, direction selection and movement conflict assessment are performed, such as... Figure 4 As shown, each two-bit gate has two arrangement orientations in a fixed slot, corresponding to different allocations of single atoms to physical stations, thus generating different sets of AOD movement paths. The existing movement set is defined as... The newly generated move set is The conflict between the two movement paths is resolved through a binary function. The decision is made if paths block or intersect each other under the AOD constraint, then the value is 1. Based on this decision, the movement conflict cost is defined as follows: For each candidate direction o, calculate the incremental conflict cost brought by that direction. The direction selection problem can be transformed into selecting the direction with the minimum incremental cost among all possible directions: Direction selection and conflict assessment can be performed door-by-door during the slot allocation phase: the movement generated by each door whose direction is determined is then incorporated into the calculation. This influences subsequent decisions, thereby achieving a greedy minimization of cumulative cost. The output of this step is the set of directed moves and their cumulative conflict costs. .

[0034] For example, in step S5, template optimization and overall cost minimization are performed. To select the globally optimal template from the candidate template set, a comprehensive cost function is introduced to measure the overall cost of the mapping: in, The conflict cost calculated in step 4, The length of the movement path. The penalty term generated by the partitioning layer is used to control the partitioning cost. These are the weight parameters. Template optimization is the solution: This step iteratively performs slot allocation, direction selection, and conflict assessment on the candidate template set, comparing each template. Value and output the optimal template This includes the corresponding gate-slot allocation and movement plan. The final movement set is then incorporated into the global movement pool for use by subsequent layers, such as... Figure 5 As shown.

[0035] For example, in step S6, temporal route coloring is performed, and the selected set of moves in the current layer is regarded as vertices forming a move conflict graph. If two moves conflict with each other, an edge is added to the graph. This is achieved by... Graph coloring is performed by allocating time groups to ensure that moves within the same color class do not conflict, thus allowing for parallel execution. A greedy coloring or heuristic minimum remaining color strategy can be used to obtain an approximate minimum number of chromaticities in polynomial time. The output of this step is the time group index (time slice sequence) for each move, which is then integrated with the gate execution order to generate the final executable sequence.

[0036] For example, in step S7, the fidelity evaluation and mapping feedback module (quality control and backtracking) introduces a fidelity model to quantify the impact of the mapping scheme on the final quantum circuit fidelity: in, Indicates the fidelity of door operation. Indicates atomic transport fidelity. This indicates the fidelity of decoherence.

[0037] In the formula, each symbol corresponds to a hardware parameter and the resource consumption resulting from the mapping. Indicates the native fidelity of a single-qubit gate. This indicates the number of two-qubit gates in the current layer. This represents the probability that an atom is in an unwanted Rydberg excited state. This represents the total idle time of the qubit q in the current layer. This represents the system's coherence time. The fidelity evaluation module calculates local and global fidelity metrics after each layer of mapping is completed. When the fidelity falls below a preset threshold, mapping backtracking is triggered. Backtracking strategies can include reselecting a suboptimal template in the current layer, changing the direction of selection, or triggering finer-grained layer splitting, thereby adjusting the mapping scheme with fidelity as the primary constraint. This step feeds the fidelity information as part of the cost function back into the template optimization process, forming a closed-loop optimization.

[0038] In another exemplary embodiment, an offline pre-computation neutral atom quantum compiler system is provided, comprising: The offline template construction and standardization module is used to abstract the neutral atom array into an n×n two-dimensional mesh, establish a parallel gate placement optimization model under regional constraints, solve the model using a satisfiability modulus solver, and perform spatial normalization on each solution to obtain a spatial template that maximizes parallelism. The online hierarchical and candidate retrieval module is used to convert logic circuits into directed acyclic graphs, perform topological hierarchical division, and obtain the gate set for each layer; and retrieve the candidate space template set that meets the capacity condition based on the number of gates in each layer. The slot allocation module is used to allocate a set of logic gates to a set of physical slots in a selected space template. It employs an anchoring strategy of minimum center distance matching and outputs the specific allocation of each gate in a physical slot and the resulting set of movement paths. The direction selection and movement conflict assessment module is used to select a direction for each two-qubit gate, assess the movement conflict cost, select the direction with the minimum incremental conflict, and output the set of oriented movement paths and the cumulative conflict cost. The template selection module is used to select the globally optimal template from the candidate space template set based on a comprehensive cost function, wherein the comprehensive cost function comprehensively considers conflict cost, movement path length and layer splitting penalty. The temporal routing coloring module is used to construct a movement conflict graph, allocate time groups through graph coloring, and generate parallel execution sequences; The fidelity assessment and mapping feedback module is used to calculate the mapping fidelity and trigger backtracking optimization when it falls below a threshold.

[0039] The data flow between modules and the key implementation points are as follows: Offline template building and standardized module output template library The online hierarchical and candidate retrieval module inputs logic circuits and outputs a set of layers. With candidate template set Slot allocation module input and front-layer physical allocation and output gate-slot mapping and Direction selection and movement conflict assessment module input and output The template selection module compares candidate templates and outputs the results. The temporal routing coloring module outputs time groups based on the movement conflict graph. In implementation, the SMT solver can be used offline to obtain high-quality templates, while the Hungarian algorithm is used online to handle fully anchored matches, a greedy algorithm or local search is used to handle partial / unanchored assignments, and a graph coloring algorithm is used for temporal assignment. The online complexity is mainly determined by the matching complexity of each layer; the Hungarian algorithm has a complexity of O(n log n). (k is the number of gates in the layer); due to the template strategy, k is usually limited by the template capacity, and the overall online complexity is controllable in engineering and supports large-scale circuits.

[0040] In engineering implementation, the above modules should be constructed as collaborative subsystems, with information exchanged between modules through clear interfaces and standardized data structures. The offline module pre-computes to offload complex combinatorial optimizations from runtime, while the online module achieves efficient mapping through template retrieval and heuristic allocation, and makes decision corrections through conflict-based cost functions and fidelity feedback, thereby achieving high-efficiency, low-Rydberg stage, and high-fidelity quantum circuit mapping. The parameters in the above implementation scheme... All of these can be engineered and adjusted according to specific hardware characteristics and target requirements.

[0041] This invention achieves efficient mapping and scheduling of neutral atom quantum circuits through a combined offline and online compilation architecture. The offline module centralizes complex constraint solving in the preprocessing stage, forming a reusable template library, significantly reducing the runtime computational burden. The online module utilizes template retrieval, hierarchical mapping, anchored allocation, and conflict-aware strategies to achieve rapid matching and dynamic adjustment under limited resource conditions. Combined with timing routing and fidelity feedback, this invention can significantly reduce compilation time, the number of movement conflicts, and the number of Rydberg stages, while ensuring the feasibility of the results and improving overall circuit fidelity.

[0042] From a practical perspective, the compilation method of this invention has the following advantages: First, it has high scalability, enabling it to support larger-scale qubit arrays and deeper quantum circuits; second, it has high efficiency, reducing online compilation time from minutes or hours in traditional methods to less than seconds, meeting the needs of rapid deployment of large-scale quantum algorithms; third, it has high fidelity, effectively reducing performance loss caused by physical limitations through conflict detection and fidelity feedback mechanisms.

[0043] This invention is applicable not only to general quantum computing tasks but also to applications such as quantum optimization and quantum machine learning. Its modular design facilitates portability to different hardware platforms and allows for flexible parameter adjustments as physical devices evolve. Therefore, this invention provides a practically valuable compilation solution for advancing the practical application of neutral atom quantum computers and can play a crucial role in future large-scale quantum computing applications.

[0044] The above detailed embodiments are a description of the present invention. It should not be considered that the specific embodiments of the present invention are limited to these descriptions. For those skilled in the art, several simple deductions and substitutions can be made without departing from the concept of the present invention, and all of these should be considered to fall within the protection scope of the present invention.

Claims

1. A neutral atom quantum compilation method with offline pre-computation, characterized in that, Includes the following steps: S1. Offline template construction and standardization: The neutral atom array is abstracted into an n×n two-dimensional mesh, a parallel gate placement optimization model under regional constraints is established, the model is solved using a satisfiability modulus solver, and spatial normalization is performed on each solution to obtain a spatial template that maximizes parallelism. S2. Online Hierarchy and Candidate Retrieval: Convert the logic circuit into a directed acyclic graph, perform topological hierarchical division, and obtain the gate set for each layer; retrieve the candidate space template set that meets the capacity condition based on the number of gates in each layer; S3. Slot allocation: Assign the set of logic gates to the set of physical slots of the space template selected in step S2, wherein the minimum center distance matching anchoring strategy is adopted, and the specific allocation of each gate in the physical slot and the resulting set of movement paths are output. S4. Direction Selection and Movement Conflict Assessment: Select a direction for each two-qubit gate, assess the movement conflict cost, select the direction with the minimum incremental conflict, and output the set of directed movement paths and the cumulative conflict cost; S5. Template Selection: The globally optimal template is selected from the candidate template set based on the comprehensive cost function, which comprehensively considers conflict cost, movement path length and layer splitting penalty. S6. Temporal route coloring: Construct a motion conflict graph, allocate time groups through graph coloring, and generate parallel execution sequences; S7. Fidelity Assessment and Mapping Feedback: Calculate the mapping fidelity, and trigger backtracking optimization when it falls below the threshold.

2. The offline pre-computation neutral atom quantum compilation method according to claim 1, characterized in that, The constraints of the parallel gate placement optimization model include: When executing a two-qubit gate, the distance between the two atoms is less than the Rydberg blocking radius; For any two simultaneous two-qubit gates, the distance between any pair of atoms involved is greater than the execution limit radius.

3. The offline pre-computation neutral atom quantum compilation method according to claim 1, characterized in that, The spatial normalization process includes: Perform the following steps for each solution: , , The rotation.

4. The offline pre-computation neutral atom quantum compilation method according to claim 1, characterized in that, The step of retrieving a set of candidate space templates that meet the capacity condition based on the number of gates in each layer includes: If the number of doors in a certain layer exceeds the maximum capacity of the template library, the layer is split into several sub-layers according to the recursive partitioning strategy until each sub-layer meets the capacity condition of a certain template. If the candidate space template set is empty, the layer splitting process is triggered and the search is repeated.

5. The offline pre-computation neutral atom quantum compilation method according to claim 1, characterized in that, The anchoring strategy includes: Fully anchored doors are matched based on minimum center distance; after the allocation of fully anchored doors is completed, some anchored doors are allocated to the remaining slots according to the nearest neighbor principle; the remaining unanchored doors are allocated using a greedy or local search strategy.

6. The offline pre-computation method for neutral atom quantum compilation according to claim 1, characterized in that, The cost of incremental conflict in step S4 is: Where 'o' represents the alternative direction, This represents the incremental conflict cost of alternative directions. Indicates the cost of movement conflict. This represents the existing set of movement paths. This represents the newly generated set of movement paths.

7. The offline pre-computation method for neutral atom quantum compilation according to claim 1, characterized in that, The comprehensive cost function is: in, Indicates the cost of conflict, The length of the movement path. For layer splitting penalty items, These are the weight parameters.

8. The offline pre-computation neutral atom quantum compilation method according to claim 1, characterized in that, In step S6, a greedy coloring or heuristic minimum remaining color strategy is used to obtain an approximate minimum number of colors.

9. The offline pre-computation method for neutral atom quantum compilation according to claim 1, characterized in that, In step S7, a fidelity model is introduced: in, Indicates the fidelity of door operation. Indicates atomic transport fidelity. This indicates the fidelity of decoherence.

10. An offline pre-computation neutral atom quantum compiler system, characterized in that, include: The offline template construction and standardization module is used to abstract the neutral atom array into an n×n two-dimensional mesh, establish a parallel gate placement optimization model under regional constraints, solve the model using a satisfiability modulus solver, and perform spatial normalization on each solution to obtain a spatial template that maximizes parallelism. The online hierarchical and candidate retrieval module is used to convert logic circuits into directed acyclic graphs, perform topological hierarchical division, and obtain the gate set for each layer; Retrieve a set of candidate space templates that meet the capacity requirements based on the number of doors in each layer; The slot allocation module is used to allocate a set of logic gates to a set of physical slots in a selected space template. It employs an anchoring strategy of minimum center distance matching and outputs the specific allocation of each gate in a physical slot and the resulting set of movement paths. The direction selection and movement conflict assessment module is used to select a direction for each two-qubit gate, assess the movement conflict cost, select the direction with the minimum incremental conflict, and output the set of oriented movement paths and the cumulative conflict cost. The template selection module is used to select the globally optimal template from the candidate space template set based on a comprehensive cost function, wherein the comprehensive cost function comprehensively considers conflict cost, movement path length and layer splitting penalty. The temporal routing coloring module is used to construct a movement conflict graph, allocate time groups through graph coloring, and generate parallel execution sequences; The fidelity assessment and mapping feedback module is used to calculate the mapping fidelity and trigger backtracking optimization when it falls below a threshold.

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