Image data display systems, methods, electronic devices, and storage media

Abstract

This disclosure provides an image data display system, method, electronic device, and storage medium. The display system transmits data via a Serial Peripheral Interface (SPI) bus. The display system includes a master device and slave devices. The master device includes a data input circuit, a data output circuit, and a serial clock circuit. The serial clock circuit includes a phase-locked loop (PLL) circuit. The slave device includes a display device. The master device acquires the image data to be transmitted. The PLL circuit boosts the original master clock frequency of the serial clock circuit. The master device encodes and enhances the image data and transmits the processed image data. The master device dynamically shapes the master clock signal output by the serial clock circuit. The display device decodes and timestamps the received image data before displaying it. This disclosure can improve the display effect of image data without changing or at low cost with existing SPI displays.

Description

Technical Field

[0001] This disclosure relates to the field of image display technology, and in particular to an image data display system, method, electronic device, and storage medium. Background Technology

[0002] Currently, small-sized LCD or OLED (Organic Light-Emitting Diode) displays generally use the Serial Peripheral interface (SPI) to transmit data. However, due to the limited bandwidth of the SPI bus, under high resolution (such as 720p / 1080p) and high refresh rate (such as ≥60Hz) conditions, the signal is prone to distortion and timing errors, resulting in abnormal display or flickering.

[0003] Traditional solutions typically rely on upgrading the display chip or adopting a faster interface (such as MIPI / DSI), which increases costs and requires redeveloping hardware, and is difficult to be compatible with existing SPI displays. Summary of the Invention

[0004] In view of this, the purpose of this disclosure is to provide an image data display system, method, electronic device, and storage medium to improve the display effect of image data without changing or at low cost the existing SPI display screen.

[0005] In a first aspect, embodiments of this disclosure provide an image data display system. The display system transmits data via a Serial Peripheral Interface (SPI) bus. The display system includes a master device and slave devices. The master device includes a data input circuit, a data output circuit, and a serial clock circuit. The serial clock circuit includes a phase-locked loop (PLL) circuit. The slave device includes a display device. The master device is configured to: acquire image data to be transmitted; the PLL circuit is configured to: boost the original master clock frequency of the serial clock circuit, and the serial clock circuit outputs a master clock signal at the boosted target master clock frequency; the master device is configured to: encode and enhance the image data, and transmit the processed image data through the data output circuit based on the master clock signal output by the serial clock circuit; during data transmission, the master device is configured to: dynamically shape the master clock signal output by the serial clock circuit; and the display device is configured to: receive the image data transmitted by the data output circuit, decode and time-match the received image data, and then display it.

[0006] Secondly, embodiments of this disclosure provide a method for displaying image data, applied to a display system that transmits data via a serial peripheral interface (SPI) bus. The display system includes a master device and a slave device. The master device includes a data input circuit, a data output circuit, and a serial clock circuit. The serial clock circuit includes a phase-locked loop (PLL) circuit. The slave device includes a display device. The method includes: the master device acquiring image data to be transmitted; the PLL circuit boosting the original master clock frequency of the serial clock circuit, and the serial clock circuit outputting a master clock signal at the boosted target master clock frequency; the master device encoding and signal enhancement processing the image data, and transmitting the processed image data through the data output circuit based on the master clock signal output by the serial clock circuit; during data transmission, the master device dynamically shaping the master clock signal output by the serial clock circuit; and the display device receiving the image data transmitted by the data output circuit, decoding and timing-matching the received image data, and then displaying it.

[0007] Thirdly, embodiments of this disclosure provide an electronic device, including a processor and a memory, wherein the memory stores machine-executable instructions that can be executed by the processor, and the processor executes the machine-executable instructions to implement the above-described method for displaying image data.

[0008] Fourthly, embodiments of this disclosure provide a computer-readable storage medium storing computer-executable instructions. When the computer-executable instructions are invoked and executed by a processor, the computer-executable instructions cause the processor to implement the above-described method for displaying image data.

[0009] The embodiments disclosed herein bring the following beneficial effects:

[0010] The aforementioned image data display system, method, electronic device, and storage medium achieve high-resolution and high-refresh-rate image display through a collaborative mechanism of SPI bus overclocking, data enhancement, and clock shaping, without altering or at low cost modifying existing hardware interfaces.

[0011] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objects and other advantages of this disclosure are realized and obtained through the structures particularly pointed out in the description, claims and drawings.

[0012] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the specific embodiments of this disclosure or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of an image data display system according to an embodiment of the present disclosure;

[0015] Figure 2 A flowchart illustrating an embodiment of a method for displaying image data provided in this disclosure;

[0016] Figure 3 This is a schematic diagram of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0018] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in this disclosure, claims, and accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” or “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0019] For ease of understanding, the embodiments of this disclosure are described in detail below. Please refer to [link / reference]. Figure 1 Please see Figure 1 , Figure 1The diagram shows a schematic of an image data display system provided in an embodiment of this disclosure. The display system transmits data via a serial peripheral interface (SPI) bus. The display system includes a master device 22 and a slave device 24. The master device 22 includes a data input circuit 221, a data output circuit 222, and a serial clock circuit 223. The serial clock circuit 223 includes a phase-locked loop (PLL) circuit 2231. The slave device 24 includes a display device 241. The master device is used to: acquire image data to be transmitted; the PLL circuit is used to: boost the original master clock frequency of the serial clock circuit, and the serial clock circuit outputs a master clock signal at the boosted target master clock frequency; the master device is used to: encode and enhance the image data, and transmit the processed image data through the data output circuit based on the master clock signal output by the serial clock circuit; during data transmission, the master device is used to: dynamically shape the master clock signal output by the serial clock circuit; the display device is used to: receive the image data transmitted by the data output circuit, decode and time-match the received image data, and then display it.

[0020] This disclosure provides a display system that transmits data via a Serial Peripheral Interface (SPI) bus. The display system includes a master device and a slave device. The master device includes a data input circuit, a data output circuit, and a serial clock circuit. The serial clock circuit includes a phase-locked loop (PLL) circuit. The slave device includes a display device. It is understood that the display system that transmits data via the SPI bus is a display system based on the SPI communication protocol, also known as an SPI communication system. Its features include master-slave mode, full-duplex communication, chip select function, mode error identification and CPU interrupt, buffered data register, and configurable clock phase polarity. This disclosure aims to achieve high resolution and high refresh rate display through a collaborative mechanism of SPI bus overclocking, clock shaping, and data enhancement without changing or with low cost the existing hardware interface.

[0021] It should be noted that the above display system includes one and only one master device and one or more slave devices. The device that provides the clock is the master device, and the device that receives the clock is the slave device. When there are multiple slave devices, the master device can select a specific slave device through its chip select signal, so that the master device can communicate with a specific slave device independently and avoid conflicts on the data line.

[0022] In this embodiment of the disclosure, the SPI bus includes at least four logic circuits: a data input (Master input slave output, MISO) circuit, a data output (Master output slave input, MOSI) circuit, a serial clock (SCK) circuit, and a chip select (Slave Select, SS) circuit. The data in the MISO circuit comes from the slave device and is input to the master device by the slave device. The data in the MOSI circuit comes from the master device and is output to the slave device by the master device. The SCK circuit is used to send the serial clock signal generated by the master device to the slave device. The SS circuit is used by the master to send the chip select signal to control the specified slave device.

[0023] In this embodiment of the disclosure, the SCK circuit is used to generate, control and output the SPI master clock signal, and may include a phase-locked loop (PLL) circuit for frequency boosting, and may also include an on-chip oscillator and a clock management unit, the specifics of which are not limited here.

[0024] In this embodiment of the disclosure, the master device may be a microcontroller unit (MCU, microprocessor unit, MPU) or a system on a chip (SoC), etc., and the slave device includes at least a display device, specifically a liquid crystal or OLED (Organic Light-Emitting Diode) display screen smaller than a certain size, but the specific size is not limited here.

[0025] When the master device acquires image data to be transmitted:

[0026] In this embodiment, the image data to be transmitted can be obtained by the master device. This embodiment can be used to display video stream frame by frame. The image data to be transmitted can be any frame in the video stream. The master device can store the image data to be transmitted into the frame buffer and then obtain the image data to be transmitted, such as the next frame to be displayed in the video stream, through the Direct Memory Access (DMA) channel, thereby improving the display efficiency and performance of the image.

[0027] In one implementation, the acquired image data to be transmitted can be directly written to a readable / writable buffer. The resolution of the image data to be transmitted can be the same as the current resolution of the corresponding display device, and no specific limitation is made here.

[0028] A phase-locked loop (PLL) circuit is used to boost the original master clock frequency of a serial clock circuit. When the serial clock circuit outputs the master clock signal at the boosted target master clock frequency:

[0029] In this embodiment, the phase-locked loop circuit can boost the original master clock frequency of the serial clock circuit. The original master clock frequency of the serial clock circuit refers to the master clock frequency originally supported by the serial clock circuit, i.e., the input reference clock. Typically, the original master clock frequency of the serial clock circuit is related to the hardware configuration performance of the display system; the higher the performance, the higher the upper limit of the master clock frequency. This embodiment can boost the original master clock frequency to any frequency value lower than the preset upper limit; specific values ​​are not limited here.

[0030] In one implementation, when the phase-locked loop circuit increases the original master clock frequency of the serial clock circuit, the phase-locked loop circuit can multiply the original master clock frequency of the serial clock circuit to increase the original master clock frequency to an integer multiple, such as 2-4 times, thereby achieving the effect of overclocking.

[0031] Specifically, the phase-locked loop circuit can adopt a fractional-N structure to double the original master clock frequency of the serial clock circuit. For example, assuming the original master clock frequency of the serial clock circuit is 40-60MHz, by multiplying the frequency by 3, the target master clock frequency after the boost is 120-180MHz. The specific value is not limited here.

[0032] In one embodiment, the master device may further include a phase-adjustable delay line and a phase compensation module for sampling feedback to adjust the phase offset angle, thereby synchronizing the data line with the clock line. For example, when the master clock signal is increased from the original master clock frequency of 60MHz to the target master clock frequency of 180MHz, the data arrival delay is determined to be approximately 2.5ns based on the phase-adjustable delay line. The phase offset angle is adjusted by the phase compensation module to achieve signal alignment.

[0033] In one implementation, a differential routing method can be used to add a shielding layer to the master clock signal line to reduce electromagnetic interference (EMI) effects. A low-noise amplifier can also be configured in the feedback loop of the phase-locked loop circuit to suppress phase noise generated at high frequencies.

[0034] In one implementation, after increasing the original master clock frequency of the serial clock circuit, the increased master clock frequency can be optimized, and the optimized master clock frequency can be used as the target master clock frequency. The serial clock circuit outputs the master clock signal at the target master clock frequency.

[0035] The main device is used to encode and enhance image data, and transmits the processed image data through the data output circuit based on the main clock signal output by the serial clock circuit:

[0036] In this embodiment, after encoding and signal enhancement processing of the image data to be transmitted, the master dual device sends it to the slave device through the data output circuit (MOSI) according to the serial timing indicated by the master clock signal output by the serial clock circuit. The master clock signal output by the serial clock circuit is used to ensure that the receiving end samples the signal on the data line at the exact time. The master clock signal output by the serial clock circuit is output according to the target master clock frequency mentioned above.

[0037] In this embodiment, encoding the image data can increase its verifiability. In one embodiment, when encoding the image data, preset redundant verification information can be added to the image data, or a preset encoding method, such as BHC encoding, can be used to detect and correct multi-bit errors that occur during transmission.

[0038] In one implementation, signal enhancement processing can be performed by integrating a high-slew-rate buffer into the data output circuit, integrating a pre-emphasis circuit into the MOSI signal path to compensate for high-frequency attenuation by applying an additional voltage at the moment of signal transition, and integrating an adaptive level converter into the data output circuit with programmable reference voltage control to match the input voltage level required by the slave device.

[0039] During data transmission, when the master device dynamically shapes the master clock signal output by the serial clock circuit:

[0040] In this embodiment, the master clock signal output by the serial clock circuit is not fixed at the target master clock frequency, but dynamically changes based on the target master clock frequency, and can adaptively adjust according to real-time feedback or preset conditions. During data transmission, the master clock signal output by the serial clock circuit can be shaped according to the jitter amplitude between the rising and falling edges of the master clock signal output by the serial clock circuit, so as to optimize the waveform and timing of the overclocked SCK signal, and eliminate signal glitches and jitter caused by high-frequency effects and noise.

[0041] In one implementation, signal shaping can include any operation that can correct the SCK waveform, including but not limited to filtering, amplification, and correction. Specifically, a multi-stage low-pass filter and a limiting amplifier can be connected in series on the SCK signal path to stabilize the peak-to-peak voltage of SCK within the error range; however, no specific limitation is made here.

[0042] The display device receives image data transmitted by the data output circuit, and displays the received image data after decoding and timing matching:

[0043] In this embodiment, the image data transmitted from the slave device's synchronous acquisition data output circuit (MOSI) is decoded and time-matched before it can be displayed. It is understood that time-matching is used to ensure that the time when image data is written to the display device is consistent with the physical scanning cycle and clock rhythm of the display device, thereby achieving tear-free, high refresh rate display.

[0044] The image data display method provided in the above embodiments achieves high resolution and high refresh rate display of images through a collaborative mechanism of SPI bus overclocking, data enhancement and clock shaping, without changing or with low cost the existing hardware interface.

[0045] Next, we will explain the specific methods for displaying image data.

[0046] In one embodiment, when the master device acquires image data to be transmitted, it includes: the master device prefetching at least one frame of target image data through a direct memory access channel and storing the prefetched data in a first-in-first-out buffer; the master device acquiring the frame of target image data most recent to the currently transmitted data from the first-in-first-out buffer as the image data to be transmitted.

[0047] In this embodiment, the master device bypasses the central processing unit (CPU) to move data via a direct memory access (DMA) channel. It extracts at least one complete frame of target image data from system memory (e.g., DDR SDRAM) and continuously, non-blockingly writes the extracted data into a first-in-first-out (FIFO) buffer, achieving seamless data stream switching and avoiding inter-frame latency. During continuous video playback, the buffering mechanism can reduce inter-frame latency by approximately 12%, improving display continuity. When image data is written to the FIFO, a frame header can be written simultaneously. The frame header can contain information such as frame ID, resolution, and checksum for subsequent frame identification and error checking.

[0048] In this embodiment, the DMA channel is a dedicated high-speed data path between the system memory and the SPI bus controller. In one embodiment, the DMA channel can be configured in Circular Buffer Mode, which allows image frame data to be continuously prefetched and written, eliminating the delay of the DMA controller switching between frames.

[0049] In one implementation, the FIFO buffer can adopt a dual-port asynchronous cache structure, which decouples the clock of the memory write clock domain from the clock of the SPI transmission clock domain, thereby isolating the difference between memory access speed fluctuations and SPI transmission speed. The DMA writes data to the FIFO quickly and in bursts, while the SPI controller reads data from the FIFO stably and continuously at the overclocked target master clock frequency, ensuring the smoothness of transmission.

[0050] In this embodiment, when the master device reads data from the FIFO buffer, it reads the target image frame to be displayed, which is the target image data closest to the currently transmitted data, and uses it as the image data to be transmitted, satisfying the first-in-first-out principle.

[0051] Understandably, the operation of the master device reading data from the FIFO is strictly synchronized with the master clock signal (SCK). Whenever SCK generates a clock edge, the SPI controller reads one or more data bits from the FIFO and sends them.

[0052] In one embodiment, the phase-locked loop (PLL) circuit is used to boost the original master clock frequency of the serial clock circuit. When the serial clock circuit outputs a master clock signal at the boosted target master clock frequency, the circuit includes: the PLL circuit receiving a master clock signal input at the original master clock frequency; a voltage-controlled oscillator (VCO) in the PLL circuit adjusting the frequency of its generated oscillation signal according to preset multiplication and division coefficients; the PLL circuit using the frequency of the output master clock signal as the target master clock frequency when the ratio of the frequency of the output master clock signal to the multiplication coefficient is equal to the original master clock frequency and the phase difference remains constant; and the serial clock circuit outputting the master clock signal at the target master clock frequency.

[0053] In this embodiment, the PLL circuit receives a stable but relatively low-frequency original master clock signal (i.e., the master clock signal at the original master clock frequency) from the system clock source. This signal serves as the reference input signal for the PLL. The voltage-controlled oscillator (VCO) in the phase-locked loop dynamically adjusts the frequency of its generated oscillation signal according to the control voltage output by the phase detector (PD) and the low-pass filter, in order to approach the desired target master clock frequency. When the frequency and phase difference between the feedback signal and the reference signal reach a stable equilibrium state, it is determined that the frequency of the PLL can be locked. The output frequency of the PLL is confirmed and locked at the target master clock frequency. After locking, the serial clock circuit can output a higher frequency clock signal at the target master clock frequency to the SPI bus (SCK line), which can effectively suppress the drift and low-frequency jitter of the clock source. Even if environmental factors change, its output frequency and phase can remain highly stable.

[0054] Understandably, the original master clock signal can originate from the crystal oscillator or system clock management unit within the master device. In one implementation, the original master clock frequency is within the SPI standard rate range of 40-60MHz. Before the original master clock signal enters the phase detector, it can also undergo preprocessing in a buffer and input divider to determine the multiplication and division coefficients.

[0055] In one implementation, the master device can configure a preset multiplication factor M and a division factor N via registers, and the target master clock frequency of the PLL circuit can be determined. With reference master clock frequency The relationship (i.e., the original master clock frequency) is as follows:

[0056]

[0057] For example, if the original SPI clock frequency Given a PLL frequency multiplication factor of M=3 and a frequency division factor of N=1, the output frequency is 60MHz. =3×60=180MHz, achieving a 3x overclock.

[0058] When the PLL is not locked to the target master clock frequency, the phase detector detects the phase difference between the input and feedback signals and outputs an error voltage. This error voltage is smoothed by a low-pass filter (LPF) and becomes the control voltage V, which drives the VCO to adjust its output frequency in real time, so that its output frequency quickly approaches the target multiplication frequency (i.e., the target master clock frequency). This achieves the ratio of the frequency of the PLL output master clock signal to the multiplication factor being equal to the original master clock frequency, while keeping the phase difference constant. In other words, the frequency of the PLL output master clock signal is locked to the target master clock frequency.

[0059] In one implementation, the target master clock frequency can be increased not only by doubling the original master clock frequency, but also by non-doubling. Specifically, the phase-locked loop circuit is used to increase the original master clock frequency of the serial clock circuit. When the serial clock circuit outputs the master clock signal at the increased target master clock frequency, the following steps are included: the master device is used to: receive the duration required for transmitting one frame of image data on the SPI bus and obtain the transmission duration of the current frame; the master device is used to: calculate the target master clock frequency based on the transmission duration of the current frame; the phase-locked loop circuit is used to: receive the master clock signal input at the original master clock frequency and lock the frequency of the output master clock signal at the target master clock frequency; the serial clock circuit is used to: output the master clock signal at the target master clock frequency.

[0060] In this embodiment, the master device calculates the minimum operating frequency that the SPI bus must reach in overclocking mode based on the time required to transmit one frame of image data on the SPI bus. This is the target master clock frequency. Then, the phase-locked loop circuit dynamically adjusts its multiplication and division coefficients according to the target master clock frequency to lock the frequency. Finally, the serial clock circuit outputs a high-frequency clock signal that is stably locked at the target master clock frequency to the SPI bus.

[0061] In one embodiment, when the master device calculates the target master clock frequency based on the current frame transmission duration, the method includes: the master device determining a dynamic adjustment coefficient based on the difference between the current frame transmission duration and a preset target frame transmission duration; determining an electromagnetic interference suppression factor based on the relationship between the current signal-to-noise ratio and a preset signal-to-noise ratio threshold; and calculating the target master clock frequency based on the dynamic adjustment coefficient and the electromagnetic interference suppression factor.

[0062] In this embodiment, the dynamic adjustment coefficient for adjusting the overclocking amplitude is determined by comparing the actual required duration (i.e., the current frame transmission duration) with the ideal duration (i.e., the preset target frame transmission duration). The dynamic adjustment coefficient can be determined by querying a preset dynamic adjustment table or by calculating the dynamic adjustment coefficient using a preset formula. The specific method is not limited here.

[0063] In this embodiment, the electromagnetic interference suppression factor, which characterizes the channel quality, is also incorporated into the calculation process of the master clock frequency. By monitoring the signal quality on the SPI bus in real time, the quality of the transmission environment can be judged, and the conservatism of overclocking can be determined. The master device can collect and calculate the signal-to-noise ratio of the current channel on the bus in real time to obtain the current signal-to-noise ratio. The electromagnetic interference suppression factor can be determined by querying a preset interference suppression table or by calculating a preset relational formula. The specific method is not limited here.

[0064] In this embodiment, after obtaining the dynamic adjustment coefficient and the electromagnetic interference suppression factor, the master clock frequency that takes into account timing requirements, timing margin and channel quality can be calculated by a preset formula and used as the target master clock frequency.

[0065] If so, the target master clock frequency can be calculated using the following formula:

[0066]

[0067]

[0068] in, Indicates the target master clock frequency. Indicates the original master clock frequency. Indicates the dynamic adjustment coefficient. This represents the difference between the current frame transmission duration and the preset target frame transmission duration. The preset target frame transmission duration, SNR is the electromagnetic interference (EMI) suppression factor, k represents the sigmoid function steepness coefficient, and SNR represents the current signal-to-noise ratio. This indicates the preset signal-to-noise ratio threshold.

[0069] This algorithm dynamically adjusts the clock frequency based on the real-time transmission status, improving data transmission efficiency and effectively reducing frame latency compared to a fixed-frequency scheme. It establishes a non-linear relationship between signal-to-noise ratio and frequency adjustment using the Sigmoid function, automatically reducing the frequency when signal quality deteriorates, thus reducing EMI interference and improving system stability. The algorithm has low complexity and low computation time per calculation, enabling frequency adjustment between each frame transmission interval, achieving frame-level dynamic optimization. Furthermore, this algorithm requires no hardware circuit modification; it can be implemented solely through software configuration of PLL parameters. It is suitable for display scenarios with different resolutions and refresh rates, ensuring display performance while dynamically adjusting the frequency according to actual needs, further reducing system power consumption.

[0070] In one embodiment, the data output circuit includes a differential signal driver and an adaptive level converter. When the master device encodes and enhances image data, and transmits the processed image data through the data output circuit based on the master clock signal output by the serial clock circuit, the process includes: the master device performing redundant encoding on at least a portion of the image data to obtain encoded image data; the differential signal driver converting the encoded image data into a differential signal; the adaptive level converter performing voltage matching and edge speed boosting on the converted differential signal to obtain processed image data; and the serial clock circuit transmitting the processed image data through the data output circuit using the output master clock signal.

[0071] In this embodiment, to improve anti-interference capability during transmission, before the data stream enters the physical transmission stage, the master device can add extra redundant check bits to all / part of the key information in the image data using a specific algorithm to obtain encoded image data. Then, a differential signal driver (DSD) generates a differential signal pair with strong anti-interference capability, and an automatic level control (ALC) performs level adaptation across voltage domains and boosts signal edge speed. The signal output by the differential signal driver and the automatic level control is the processed image data. Then, using the current master clock signal as the rhythm, the encoded and signal-enhanced image data is sent to the slave device on the SPI bus, thereby realizing high-bandwidth data transmission.

[0072] This implementation improves the anti-interference capability of the data stream at both the physical layer and the data link layer through differential signal driving and redundant coding, effectively solving the problem of susceptibility to noise and crosstalk in ultra-high frequency transmission. The adaptive level converter not only solves the voltage domain matching problem between master and slave devices, but more importantly, it ensures the integrity of ultra-high frequency signals by increasing edge speed, avoiding signal distortion and inter-symbol interference. Furthermore, the high-drive differential signal generated by DSD can effectively overcome the signal attenuation caused by PCB traces and connectors, enabling the overclocked SPI bus to maintain reliability over relatively long transmission distances.

[0073] In one implementation, when redundantly encoding at least a portion of the image data, BCH encoding or Hamming encoding can be used to encode key parts of the image data, such as pixel values ​​or frame control information, thereby obtaining encoded image data. For example, 4 parity bits can be added for every 11 bits of valid data transmitted to detect and correct single-bit errors.

[0074] In one implementation, after receiving the encoded image data, the DSD converts it into two complementary differential signals input to the ALC. The ALC converts the voltage level of the differential signal output by the DSD into the logic voltage required by the slave device (display) driver chip. The ALC can also accelerate and reshape the rising and falling edges of the high-frequency signal through a built-in hysteresis comparator and push-pull buffer to ensure that the data can be accurately sampled by the ultra-high frequency clock.

[0075] In one implementation, during data transmission, when the master device dynamically shapes the master clock signal output by the serial clock circuit, it includes: calculating the jitter amplitude between the rising and falling edges of the master clock signal output by the serial clock circuit using a preset dynamic jitter detection algorithm during data transmission; determining whether the jitter amplitude is greater than a preset jitter threshold; if it is greater, the master device dynamically shapes the master clock signal output by the serial clock circuit.

[0076] In this embodiment, the timing uncertainty of the SCK signal waveform is acquired and quantified in real time by a preset dynamic jitter detection algorithm, that is, the jitter amplitude is calculated. The jitter amplitude calculated in real time is compared with a preset jitter threshold to determine whether signal shaping operation needs to be initiated. Once the real-time jitter amplitude exceeds the preset jitter threshold, the master device immediately starts the signal shaping module and / or timing calibration mechanism to restore the waveform quality of the SCK signal, thereby realizing adaptive shaping of the master clock signal.

[0077] In one embodiment, during data transmission, when calculating the jitter amplitude between the rising and falling edges of the main clock signal output by the serial clock circuit using a preset dynamic jitter detection algorithm, the process includes: during data transmission, acquiring the clock edge times of multiple sampling points on the main clock signal output by the serial clock circuit; calculating the deviation between the clock edge time of each sampling point and the average clock edge time; and determining the jitter amplitude between the rising and falling edges of the main clock signal output by the serial clock circuit based on the deviation.

[0078] In this embodiment, during data transmission, multiple consecutive clock cycles of the serial clock signal (i.e., the main clock signal output by the serial clock circuit) are sampled, and the time point of each clock signal transition (rising edge or falling edge) is recorded. Based on all the clock edge times that have been collected, the average clock edge time can be calculated, and then the instantaneous deviation (i.e., the above deviation) between each clock edge time and the average clock edge time can be calculated. All instantaneous deviations are statistically analyzed to determine the jitter amplitude representing the timing uncertainty of the SCK signal.

[0079] Specifically, the aforementioned jitter amplitude One possible calculation formula is:

[0080]

[0081] in, This represents the clock edge time of the i-th sample. The average clock edge time is represented by N, and the number of sampling points is represented by N. In one implementation, the preset jitter threshold is set to 0.1T (T is the clock period, such as T=5.56ns for 180MHz). When this occurs, the main equipment immediately activates the signal shaping module and / or timing calibration mechanism to restore the waveform quality of the SCK signal.

[0082] In one implementation, the signal shaping module may include a programmable delay compensation circuit. During signal shaping, new control parameters can be written into the programmable delay compensation circuit to dynamically adjust the phase and duty cycle of the SCK signal.

[0083] In one embodiment, the signal shaping module may include a shaping filter circuit, i.e., a serial clock circuit is connected in series with a shaping filter circuit, and the shaping filter circuit includes a buffer amplifier, an RC filter and a waveform correction circuit; when the main device dynamically shapes the main clock signal output by the serial clock circuit, it includes: suppressing the jitter amplitude of the main clock signal output by the serial clock circuit through the buffer amplifier, the RC filter and the waveform correction circuit.

[0084] In this embodiment, the high-frequency SCK signal output by the PLL is processed by the coordinated operation of the buffer amplifier, RC filter and waveform correction circuit in the shaping filter circuit, so as to physically eliminate its timing uncertainty and waveform distortion, thereby realizing signal shaping.

[0085] A buffer amplifier, located at the input or output of a shaping filter circuit, isolates the load coupling between the PLL circuit and the SPI bus and provides high current drive capability. Specifically, the buffer amplifier receives the SCK signal (i.e., the master clock signal output by the serial clock circuit), amplifies it to increase the current drive capability of the SCK signal to over 8mA, thereby ensuring that the SCK signal maintains sufficient strength and low output impedance after passing through PCB traces and connectors, avoiding clock drift caused by load changes.

[0086] An RC filter can be a low-pass filter used to remove high-frequency noise and spikes (glitches) from an SCK signal. In one implementation, the RC filter utilizes the energy storage and impedance characteristics of its capacitor and resistor to perform analog filtering on the SCK signal. The cutoff frequency of the RC filter is set to 1.5 to 2 times the target master clock frequency to filter out high-order harmonics, spikes, and other high-frequency interference components, thus smoothing the SCK signal waveform.

[0087] A waveform correction circuit is used to steepen and re-digitize the edges of the filtered SCK signal to restore its standard square wave shape. In one embodiment, the waveform correction circuit can be a Schmitt trigger, which uses hysteresis to eliminate noise at the signal input and converts the input waveform into a clear square wave with fast rising and falling edges. The waveform correction circuit can suppress jitter amplitude and eliminate jitter when the signal crosses a logic threshold.

[0088] In one embodiment, when a display device receives image data transmitted by a data output circuit and displays the received image data after decoding and timing matching, the method includes: the display device receiving image data transmitted by the data output circuit; decoding the received image data to obtain decoded image data; detecting frame header signals and line synchronization signals on the decoded image data; dividing the received image data into multiple blocks of image data according to the current resolution of the display device; and refreshing and displaying the multiple blocks of image data in parallel based on the detected frame header signals and line synchronization signals.

[0089] In this embodiment, the display device synchronously acquires data streams through its data input interface (MISO / MOSI), decodes the received encoded data, and obtains the recovered original valid image information, i.e., the decoded image data. The display device identifies the frame header signal indicating the start of a new frame and the line synchronization signal indicating the start of a new line from the decoded data stream or external synchronization signal line. Based on the parallel processing capability of its driver chip and the current working resolution, the received whole frame image data is logically divided to obtain multiple blocks of image data. Then, using the frame header signal and the line synchronization signal as scheduling references, multiple blocks are simultaneously driven for writing and display, thereby significantly shortening the frame cycle and achieving a high refresh rate.

[0090] In one implementation, the decoded image data can be stored in the high-speed frame buffer (Graphic RAM / Graphics memory, GRAM) inside the display device. The write operation of the GRAM is synchronized with the receiving clock, which can improve the read and write efficiency of the screen.

[0091] In one implementation, the frame header signal may include a frame header flag or an external vertical synchronization signal to indicate the end of writing a frame of image data and the start of the next frame display scan. The frame header signal may be written simultaneously with the image data being written to the FIFO. Similarly, the line synchronization signal is used to indicate the end of writing a line of pixel data and the timing point at which the display panel starts scanning the next line. It may also be written simultaneously with the image data being written to the FIFO. The specific details are not limited here.

[0092] The current resolution of a display device refers to its current working resolution (e.g., 1080p). Display devices can use a dynamic refresh partitioning mechanism to logically divide the entire frame of image data into multiple sub-blocks (e.g., 12 sub-blocks). The GRAM area or multiple sets of parallel cache areas inside the display device will reserve independent storage space for each sub-block to drive multiple blocks to be written and displayed in parallel, thereby greatly shortening the frame cycle and achieving a high refresh rate.

[0093] In one embodiment, during data transmission, the method further includes: the master device being configured to: in response to a task triggering instruction that competes for SPI bus bandwidth, determine a first bandwidth priority of the triggered task from a preset task bandwidth priority based on the type of the triggered task; the master device being configured to: allocate SPI bus bandwidth to the triggered task based on the first bandwidth priority.

[0094] This embodiment provides a task priority arbitration mechanism. In addition to image display tasks, other tasks that require SPI bus bandwidth can participate in the competition for SPI bus bandwidth. The competition is triggered by a task triggering command that competes for SPI bus bandwidth. Tasks other than image display tasks can include: data display tasks, touch response tasks, sensor response tasks, etc. Different types of tasks are pre-set with a level value or identifier used to measure the importance and urgency of the task, which represents the bandwidth priority.

[0095] For example, when the interrupt controller of the master device receives a "data ready" interrupt (i.e., a task trigger instruction) from the touch control chip, the master device immediately queries the preset task bandwidth priority, confirms that the task type is "touch data", and determines that its corresponding bandwidth priority is the first bandwidth priority.

[0096] In one implementation, when the master device allocates SPI bus bandwidth to the triggered task according to the first bandwidth priority, the master device can allocate the idle SPI bus bandwidth to the triggered task while ensuring that the SPI bus bandwidth of the image display task is not lower than the minimum guaranteed bandwidth. The master device can also use other bus bandwidth allocation algorithms to allocate SPI bus bandwidth, which are not limited here.

[0097] In one embodiment, during data transmission, the method further includes: the master device sending a safety mode switching command to the phase-locked loop circuit in response to the chip temperature of the master device or the voltage of the SPI bus exceeding a preset safety threshold; the phase-locked loop circuit adjusting the frequency of the output master clock signal to below a preset safety value by adjusting a preset multiplication factor in response to the safety mode switching command; wherein the safety value is greater than or equal to the original master clock frequency.

[0098] This implementation defines a safety protection program for the master device. When the chip temperature or SPI bus voltage of the master device exceeds the safe range, the master device can write a specific value to the control register of the phase-locked loop circuit to trigger the phase-locked loop circuit to respond to the safety mode switching instruction. After receiving the instruction, the PLL circuit immediately performs frequency adjustment to reduce the current overclocking operating frequency to a safe and stable low frequency value to avoid permanent hardware damage caused by chip overheating or power instability due to overclocking.

[0099] For the system embodiments described above, see [link to relevant documentation]. Figure 2 A flowchart illustrating an embodiment of an image data display method is shown, comprising the following steps:

[0100] Step S10: The master device acquires the image data to be transmitted;

[0101] Step S20: The phase-locked loop circuit boosts the original master clock frequency of the serial clock circuit, and the serial clock circuit outputs the master clock signal at the boosted target master clock frequency.

[0102] Step S30: The main device encodes and enhances the image data, and transmits the processed image data through the data output circuit based on the main clock signal output by the serial clock circuit.

[0103] Step S40: During data transmission, the master device dynamically shapes the master clock signal output by the serial clock circuit.

[0104] Step S50: The display device receives image data transmitted by the data output circuit, decodes and matches the timing of the received image data, and then displays it.

[0105] The above-mentioned image data display method achieves high-resolution and high-refresh-rate image display through a collaborative mechanism of SPI bus overclocking, data enhancement, and clock shaping, without changing or with low cost the existing hardware interface.

[0106] Optionally, the step of the master device acquiring the image data to be transmitted includes: the master device prefetching at least one frame of target image data through a direct memory access channel and storing the prefetched data in a first-in-first-out buffer; the master device acquiring the frame of target image data most recent to the currently transmitted data from the first-in-first-out buffer as the image data to be transmitted.

[0107] Optionally, the step of the phase-locked loop circuit boosting the original master clock frequency of the serial clock circuit, and the serial clock circuit outputting the master clock signal at the boosted target master clock frequency, includes: the phase-locked loop circuit receiving the master clock signal input at the original master clock frequency; the voltage-controlled oscillator in the phase-locked loop circuit adjusting the frequency of its generated oscillation signal according to preset multiplication and division coefficients; when the ratio of the frequency of the output master clock signal to the multiplication coefficient is equal to the original master clock frequency and the phase difference remains constant, the phase-locked loop circuit uses the frequency of the output master clock signal as the target master clock frequency; and the serial clock circuit outputs the master clock signal at the target master clock frequency.

[0108] Optionally, the step of the phase-locked loop circuit boosting the original master clock frequency of the serial clock circuit, and the serial clock circuit outputting the master clock signal at the boosted target master clock frequency, includes: the master device receiving the duration required for transmitting one frame of image data on the SPI bus to obtain the current frame transmission duration; the master device calculating the target master clock frequency based on the current frame transmission duration; the phase-locked loop circuit receiving the master clock signal input at the original master clock frequency and locking the frequency of the output master clock signal at the target master clock frequency; and the serial clock circuit outputting the master clock signal at the target master clock frequency.

[0109] Optionally, the step of the master device calculating the target master clock frequency based on the current frame transmission duration includes: determining a dynamic adjustment coefficient based on the difference between the current frame transmission duration and the preset target frame transmission duration; determining an electromagnetic interference suppression factor based on the relationship between the current signal-to-noise ratio and a preset signal-to-noise ratio threshold; and calculating the target master clock frequency based on the dynamic adjustment coefficient and the electromagnetic interference suppression factor.

[0110] Optionally, the data output circuit includes a differential signal driver and an adaptive level converter; the steps of the master device encoding and signal enhancement processing of image data, and transmitting the processed image data through the data output circuit based on the master clock signal output by the serial clock circuit, include: the master device performing redundant encoding on at least a portion of the image data to obtain encoded image data; the differential signal driver converting the encoded image data into a differential signal, and the adaptive level converter performing voltage matching and edge speed boosting on the converted differential signal to obtain processed image data; the master clock signal output by the serial clock circuit transmitting the processed image data through the data output circuit.

[0111] Optionally, during data transmission, the step of the master device dynamically shaping the master clock signal output by the serial clock circuit includes: during data transmission, calculating the jitter amplitude between the rising and falling edges of the master clock signal output by the serial clock circuit using a preset dynamic jitter detection algorithm; determining whether the jitter amplitude is greater than a preset jitter threshold; if it is greater, then the master device dynamically shapes the master clock signal output by the serial clock circuit.

[0112] Optionally, during data transmission, the step of calculating the jitter amplitude between the rising and falling edges of the main clock signal output by the serial clock circuit using a preset dynamic jitter detection algorithm includes: during data transmission, acquiring the clock edge times of multiple sampling points on the main clock signal output by the serial clock circuit; calculating the deviation between the clock edge time of each sampling point and the average clock edge time; and determining the jitter amplitude between the rising and falling edges of the main clock signal output by the serial clock circuit based on the deviation.

[0113] Optionally, the serial clock circuit is connected in series with a shaping filter circuit, which includes a buffer amplifier, an RC filter, and a waveform correction circuit. The step of the master device dynamically shaping the master clock signal output by the serial clock circuit includes: suppressing jitter amplitude of the master clock signal output by the serial clock circuit through the buffer amplifier, RC filter, and waveform correction circuit.

[0114] Optionally, the step of the display device receiving image data transmitted by the data output circuit, decoding and timing-matching the received image data, and then displaying it includes: the display device receiving image data transmitted by the data output circuit, decoding the received image data to obtain decoded image data; detecting frame header signals and horizontal synchronization signals on the decoded image data; dividing the received image data into multiple blocks of image data according to the current resolution of the display device; and refreshing and displaying the multiple blocks of image data in parallel based on the detected frame header signals and horizontal synchronization signals.

[0115] Optionally, during data transmission, the process further includes: the master device responding to a task triggering command that competes for SPI bus bandwidth, determining the first bandwidth priority of the triggered task from a preset task bandwidth priority based on the type of the triggered task; and the master device allocating SPI bus bandwidth to the triggered task based on the first bandwidth priority.

[0116] Optionally, during data transmission, the process further includes: the master device sending a safety mode switching command to the phase-locked loop circuit in response to the master device's chip temperature or SPI bus voltage exceeding a preset safety threshold; the phase-locked loop circuit responding to the safety mode switching command adjusting the frequency of the output master clock signal to below a preset safety value by adjusting a preset multiplication factor; wherein the safety value is greater than or equal to the original master clock frequency.

[0117] This embodiment also provides an electronic device, including a processor and a memory. The memory stores machine-executable instructions that can be executed by the processor. The processor executes the machine-executable instructions to implement the above-described method for displaying image data. This electronic device can be a server or a terminal device.

[0118] See Figure 3 As shown, the electronic device includes a processor 100 and a memory 101. The memory 101 stores machine-executable instructions that can be executed by the processor 100. The processor 100 executes the machine-executable instructions to implement the above-described method for displaying image data.

[0119] Furthermore, Figure 3 The electronic device shown also includes a bus 102 and a communication interface 103, with the processor 100, the communication interface 103 and the memory 101 connected via the bus 102.

[0120] The memory 101 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device. Communication between this system network element and at least one other network element is achieved through at least one communication interface 103 (which can be wired or wireless), such as the Internet, wide area network, local area network, metropolitan area network, etc. The bus 102 may be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 3 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0121] The processor 100 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of the processor 100 or by instructions in software form. The processor 100 may be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this disclosure. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this disclosure can be directly manifested as execution by a hardware decoding processor, or execution by a combination of hardware and software modules in the decoding processor. The software module can reside in a readily available storage medium in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory 101. The processor 100 reads information from memory 101 and, in conjunction with its hardware, completes the steps of the method described in the foregoing embodiments, for example:

[0122] This invention relates to a display system that transmits data via a serial peripheral interface (SPI) bus. The display system includes a master device and slave devices. The master device includes a data input circuit, a data output circuit, and a serial clock circuit. The serial clock circuit includes a phase-locked loop (PLL) circuit. The slave device includes a display device. The method includes: the master device acquiring image data to be transmitted; the PLL circuit boosting the original master clock frequency of the serial clock circuit, and the serial clock circuit outputting a master clock signal at the boosted target master clock frequency; the master device encoding and signal enhancement processing of the image data, and transmitting the processed image data through the data output circuit based on the master clock signal output by the serial clock circuit; during data transmission, the master device dynamically shaping the master clock signal output by the serial clock circuit; and the display device receiving the image data transmitted by the data output circuit, decoding and timing-matching the received image data, and then displaying it.

[0123] In this approach, high-resolution and high-refresh-rate image display is achieved through a collaborative mechanism of SPI bus overclocking, data enhancement, and clock shaping, without changing or at low cost modifying the existing hardware interface.

[0124] Optionally, the step of the master device acquiring the image data to be transmitted includes: the master device prefetching at least one frame of target image data through a direct memory access channel and storing the prefetched data in a first-in-first-out buffer; the master device acquiring the frame of target image data most recent to the currently transmitted data from the first-in-first-out buffer as the image data to be transmitted.

[0125] Optionally, the step of the phase-locked loop circuit boosting the original master clock frequency of the serial clock circuit, and the serial clock circuit outputting the master clock signal at the boosted target master clock frequency, includes: the phase-locked loop circuit receiving the master clock signal input at the original master clock frequency; the voltage-controlled oscillator in the phase-locked loop circuit adjusting the frequency of its generated oscillation signal according to preset multiplication and division coefficients; when the ratio of the frequency of the output master clock signal to the multiplication coefficient is equal to the original master clock frequency and the phase difference remains constant, the phase-locked loop circuit uses the frequency of the output master clock signal as the target master clock frequency; and the serial clock circuit outputs the master clock signal at the target master clock frequency.

[0126] Optionally, the step of the phase-locked loop circuit boosting the original master clock frequency of the serial clock circuit, and the serial clock circuit outputting the master clock signal at the boosted target master clock frequency, includes: the master device receiving the duration required for transmitting one frame of image data on the SPI bus to obtain the current frame transmission duration; the master device calculating the target master clock frequency based on the current frame transmission duration; the phase-locked loop circuit receiving the master clock signal input at the original master clock frequency and locking the frequency of the output master clock signal at the target master clock frequency; and the serial clock circuit outputting the master clock signal at the target master clock frequency.

[0127] Optionally, the step of the master device calculating the target master clock frequency based on the current frame transmission duration includes: determining a dynamic adjustment coefficient based on the difference between the current frame transmission duration and the preset target frame transmission duration; determining an electromagnetic interference suppression factor based on the relationship between the current signal-to-noise ratio and a preset signal-to-noise ratio threshold; and calculating the target master clock frequency based on the dynamic adjustment coefficient and the electromagnetic interference suppression factor.

[0128] Optionally, the data output circuit includes a differential signal driver and an adaptive level converter; the steps of the master device encoding and signal enhancement processing of image data, and transmitting the processed image data through the data output circuit based on the master clock signal output by the serial clock circuit, include: the master device performing redundant encoding on at least a portion of the image data to obtain encoded image data; the differential signal driver converting the encoded image data into a differential signal, and the adaptive level converter performing voltage matching and edge speed boosting on the converted differential signal to obtain processed image data; the master clock signal output by the serial clock circuit transmitting the processed image data through the data output circuit.

[0129] Optionally, during data transmission, the step of the master device dynamically shaping the master clock signal output by the serial clock circuit includes: during data transmission, calculating the jitter amplitude between the rising and falling edges of the master clock signal output by the serial clock circuit using a preset dynamic jitter detection algorithm; determining whether the jitter amplitude is greater than a preset jitter threshold; if it is greater, then the master device dynamically shapes the master clock signal output by the serial clock circuit.

[0130] Optionally, during data transmission, the step of calculating the jitter amplitude between the rising and falling edges of the main clock signal output by the serial clock circuit using a preset dynamic jitter detection algorithm includes: during data transmission, acquiring the clock edge times of multiple sampling points on the main clock signal output by the serial clock circuit; calculating the deviation between the clock edge time of each sampling point and the average clock edge time; and determining the jitter amplitude between the rising and falling edges of the main clock signal output by the serial clock circuit based on the deviation.

[0131] Optionally, the serial clock circuit is connected in series with a shaping filter circuit, which includes a buffer amplifier, an RC filter, and a waveform correction circuit. The step of the master device dynamically shaping the master clock signal output by the serial clock circuit includes: suppressing jitter amplitude of the master clock signal output by the serial clock circuit through the buffer amplifier, RC filter, and waveform correction circuit.

[0132] Optionally, the step of the display device receiving image data transmitted by the data output circuit, decoding and timing-matching the received image data, and then displaying it includes: the display device receiving image data transmitted by the data output circuit, decoding the received image data to obtain decoded image data; detecting frame header signals and horizontal synchronization signals on the decoded image data; dividing the received image data into multiple blocks of image data according to the current resolution of the display device; and refreshing and displaying the multiple blocks of image data in parallel based on the detected frame header signals and horizontal synchronization signals.

[0133] Optionally, during data transmission, the process further includes: the master device responding to a task triggering command that competes for SPI bus bandwidth, determining the first bandwidth priority of the triggered task from a preset task bandwidth priority based on the type of the triggered task; and the master device allocating SPI bus bandwidth to the triggered task based on the first bandwidth priority.

[0134] Optionally, during data transmission, the process further includes: the master device sending a safety mode switching command to the phase-locked loop circuit in response to the master device's chip temperature or SPI bus voltage exceeding a preset safety threshold; the phase-locked loop circuit responding to the safety mode switching command adjusting the frequency of the output master clock signal to below a preset safety value by adjusting a preset multiplication factor; wherein the safety value is greater than or equal to the original master clock frequency.

[0135] This embodiment also provides a computer-readable storage medium storing computer-executable instructions. When these computer-executable instructions are invoked and executed by a processor, they cause the processor to implement the aforementioned image data display method, for example:

[0136] This invention relates to a display system that transmits data via a serial peripheral interface (SPI) bus. The display system includes a master device and slave devices. The master device includes a data input circuit, a data output circuit, and a serial clock circuit. The serial clock circuit includes a phase-locked loop (PLL) circuit. The slave device includes a display device. The method includes: the master device acquiring image data to be transmitted; the PLL circuit boosting the original master clock frequency of the serial clock circuit, and the serial clock circuit outputting a master clock signal at the boosted target master clock frequency; the master device encoding and signal enhancement processing of the image data, and transmitting the processed image data through the data output circuit based on the master clock signal output by the serial clock circuit; during data transmission, the master device dynamically shaping the master clock signal output by the serial clock circuit; and the display device receiving the image data transmitted by the data output circuit, decoding and timing-matching the received image data, and then displaying it.

[0137] In this approach, high-resolution and high-refresh-rate image display is achieved through a collaborative mechanism of SPI bus overclocking, data enhancement, and clock shaping, without changing or at low cost modifying the existing hardware interface.

[0138] Optionally, the step of the master device acquiring the image data to be transmitted includes: the master device prefetching at least one frame of target image data through a direct memory access channel and storing the prefetched data in a first-in-first-out buffer; the master device acquiring the frame of target image data most recent to the currently transmitted data from the first-in-first-out buffer as the image data to be transmitted.

[0139] Optionally, the step of the phase-locked loop circuit boosting the original master clock frequency of the serial clock circuit, and the serial clock circuit outputting the master clock signal at the boosted target master clock frequency, includes: the phase-locked loop circuit receiving the master clock signal input at the original master clock frequency; the voltage-controlled oscillator in the phase-locked loop circuit adjusting the frequency of its generated oscillation signal according to preset multiplication and division coefficients; when the ratio of the frequency of the output master clock signal to the multiplication coefficient is equal to the original master clock frequency and the phase difference remains constant, the phase-locked loop circuit uses the frequency of the output master clock signal as the target master clock frequency; and the serial clock circuit outputs the master clock signal at the target master clock frequency.

[0140] Optionally, the step of the phase-locked loop circuit boosting the original master clock frequency of the serial clock circuit, and the serial clock circuit outputting the master clock signal at the boosted target master clock frequency, includes: the master device receiving the duration required for transmitting one frame of image data on the SPI bus to obtain the current frame transmission duration; the master device calculating the target master clock frequency based on the current frame transmission duration; the phase-locked loop circuit receiving the master clock signal input at the original master clock frequency and locking the frequency of the output master clock signal at the target master clock frequency; and the serial clock circuit outputting the master clock signal at the target master clock frequency.

[0141] Optionally, the step of the master device calculating the target master clock frequency based on the current frame transmission duration includes: determining a dynamic adjustment coefficient based on the difference between the current frame transmission duration and the preset target frame transmission duration; determining an electromagnetic interference suppression factor based on the relationship between the current signal-to-noise ratio and a preset signal-to-noise ratio threshold; and calculating the target master clock frequency based on the dynamic adjustment coefficient and the electromagnetic interference suppression factor.

[0142] Optionally, the data output circuit includes a differential signal driver and an adaptive level converter; the steps of the master device encoding and signal enhancement processing of image data, and transmitting the processed image data through the data output circuit based on the master clock signal output by the serial clock circuit, include: the master device performing redundant encoding on at least a portion of the image data to obtain encoded image data; the differential signal driver converting the encoded image data into a differential signal, and the adaptive level converter performing voltage matching and edge speed boosting on the converted differential signal to obtain processed image data; the master clock signal output by the serial clock circuit transmitting the processed image data through the data output circuit.

[0143] Optionally, during data transmission, the step of the master device dynamically shaping the master clock signal output by the serial clock circuit includes: during data transmission, calculating the jitter amplitude between the rising and falling edges of the master clock signal output by the serial clock circuit using a preset dynamic jitter detection algorithm; determining whether the jitter amplitude is greater than a preset jitter threshold; if it is greater, then the master device dynamically shapes the master clock signal output by the serial clock circuit.

[0144] Optionally, during data transmission, the step of calculating the jitter amplitude between the rising and falling edges of the main clock signal output by the serial clock circuit using a preset dynamic jitter detection algorithm includes: during data transmission, acquiring the clock edge times of multiple sampling points on the main clock signal output by the serial clock circuit; calculating the deviation between the clock edge time of each sampling point and the average clock edge time; and determining the jitter amplitude between the rising and falling edges of the main clock signal output by the serial clock circuit based on the deviation.

[0145] Optionally, the serial clock circuit is connected in series with a shaping filter circuit, which includes a buffer amplifier, an RC filter, and a waveform correction circuit. The step of the master device dynamically shaping the master clock signal output by the serial clock circuit includes: suppressing jitter amplitude of the master clock signal output by the serial clock circuit through the buffer amplifier, RC filter, and waveform correction circuit.

[0146] Optionally, the step of the display device receiving image data transmitted by the data output circuit, decoding and timing-matching the received image data, and then displaying it includes: the display device receiving image data transmitted by the data output circuit, decoding the received image data to obtain decoded image data; detecting frame header signals and horizontal synchronization signals on the decoded image data; dividing the received image data into multiple blocks of image data according to the current resolution of the display device; and refreshing and displaying the multiple blocks of image data in parallel based on the detected frame header signals and horizontal synchronization signals.

[0147] Optionally, during data transmission, the process further includes: the master device responding to a task triggering command that competes for SPI bus bandwidth, determining the first bandwidth priority of the triggered task from a preset task bandwidth priority based on the type of the triggered task; and the master device allocating SPI bus bandwidth to the triggered task based on the first bandwidth priority.

[0148] Optionally, during data transmission, the process further includes: the master device sending a safety mode switching command to the phase-locked loop circuit in response to the master device's chip temperature or SPI bus voltage exceeding a preset safety threshold; the phase-locked loop circuit responding to the safety mode switching command adjusting the frequency of the output master clock signal to below a preset safety value by adjusting a preset multiplication factor; wherein the safety value is greater than or equal to the original master clock frequency.

[0149] The computer program products of the image data display system, method, electronic device and storage medium provided in the embodiments of this disclosure include a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods described in the preceding method embodiments. For specific implementation, please refer to the method embodiments, which will not be repeated here.

[0150] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the system and apparatus described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0151] Furthermore, in the description of the embodiments of this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure based on the specific circumstances.

[0152] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0153] In the description of this disclosure, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0154] Finally, it should be noted that the above embodiments are merely specific implementations of this disclosure, used to illustrate the technical solutions of this disclosure, and not to limit it. The protection scope of this disclosure is not limited thereto. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this disclosure. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure, and should all be covered within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A display system for image data, characterized in that, The display system transmits data via a Serial Peripheral Interface (SPI) bus. The display system includes a master device and slave devices. The master device includes a data input circuit, a data output circuit, and a serial clock circuit. The serial clock circuit includes a phase-locked loop (PLL) circuit. The slave device includes a display device. The main device is used to: acquire image data to be transmitted; The phase-locked loop circuit is used to: boost the original master clock frequency of the serial clock circuit, and the serial clock circuit outputs the master clock signal at the boosted target master clock frequency; The main device is used to: encode and enhance the image data, and transmit the processed image data through the data output circuit based on the main clock signal output by the serial clock circuit; During data transmission, the master device is used to: dynamically shape the master clock signal output by the serial clock circuit; The display device is used to: receive image data transmitted by the data output circuit, and display the received image data after decoding and timing matching; timing matching is used to ensure that the time when the image data is written to the display device is consistent with the physical scanning cycle and clock rhythm of the display device. The phase-locked loop circuit is used to boost the original master clock frequency of the serial clock circuit. When the serial clock circuit outputs the master clock signal at the boosted target master clock frequency, it includes: The phase-locked loop circuit is used to: receive the master clock signal input at the original master clock frequency; The voltage-controlled oscillator in the phase-locked loop circuit is used to: adjust the frequency of the oscillation signal it generates according to the preset multiplication and division coefficients; The phase-locked loop circuit is used to: when the ratio of the frequency of the output master clock signal to the frequency multiplication factor is equal to the original master clock frequency and the phase difference remains constant, take the frequency of the master clock signal output by the phase-locked loop circuit as the target master clock frequency. The serial clock circuit is used to: output a master clock signal at the target master clock frequency; During data transmission, when the master device dynamically shapes the master clock signal output by the serial clock circuit, it includes: During data transmission, the jitter amplitude between the rising and falling edges of the main clock signal output by the serial clock circuit is calculated using a preset dynamic jitter detection algorithm. Determine whether the jitter amplitude is greater than a preset jitter threshold; If the value is greater than the value, the master device dynamically shapes the master clock signal output by the serial clock circuit.

2. The system according to claim 1, characterized in that, When the master device acquires image data to be transmitted, it includes: The master device is used to: prefetch at least one frame of target image data through a direct memory access channel and store the prefetched data in a first-in-first-out buffer. The master device is used to: obtain the target image data that is most recent to the currently transmitted data from the first-in-first-out buffer, and use it as the image data to be transmitted.

3. The system according to claim 1, characterized in that, The phase-locked loop circuit is used to boost the original master clock frequency of the serial clock circuit. When the serial clock circuit outputs the master clock signal at the boosted target master clock frequency, it includes: The master device is used to: receive the duration required for the current transmission of one frame of image data on the SPI bus, and obtain the transmission duration of the current frame; The master device is used to: calculate the target master clock frequency based on the current frame transmission duration; The phase-locked loop circuit is used to: receive the master clock signal input at the original master clock frequency, and lock the frequency of the output master clock signal at the target master clock frequency; The serial clock circuit is used to output a master clock signal at the target master clock frequency.

4. The system according to claim 3, characterized in that, When the master device calculates the target master clock frequency based on the current frame transmission duration, it includes: The master device is used to determine a dynamic adjustment coefficient based on the difference between the current frame transmission duration and the preset target frame transmission duration; The electromagnetic interference suppression factor is determined based on the relationship between the current signal-to-noise ratio and the preset signal-to-noise ratio threshold. The target master clock frequency is calculated based on the dynamic adjustment coefficient and the electromagnetic interference suppression factor.

5. The system according to claim 1, characterized in that, The data output circuit includes a differential signal driver and an adaptive level converter; The main device is used to encode and enhance the image data, and transmits the processed image data through the data output circuit based on the main clock signal output by the serial clock circuit, including: The main device is used to: perform redundant encoding on at least a portion of the image data to obtain encoded image data; The differential signal driver is used to convert the encoded image data into a differential signal, and the adaptive level converter is used to perform voltage matching and edge speed boosting on the converted differential signal to obtain processed image data. The master clock signal output by the serial clock circuit is used to transmit the processed image data through the data output circuit.

6. The system according to claim 1, characterized in that, During data transmission, when calculating the jitter amplitude between the rising and falling edges of the main clock signal output by the serial clock circuit using a preset dynamic jitter detection algorithm, the calculation includes: During data transmission, the clock edge times of multiple sampling points on the main clock signal output by the serial clock circuit are collected. Calculate the deviation between the clock edge time of each sampling point and the average clock edge time; Based on the deviation, the jitter amplitude between the rising and falling edges of the main clock signal output by the serial clock circuit is determined.

7. The system according to claim 1, characterized in that, The serial clock circuit is connected in series with a shaping filter circuit, which includes a buffer amplifier, an RC filter, and a waveform correction circuit. When the master device dynamically shapes the master clock signal output by the serial clock circuit, it includes: The jitter amplitude of the master clock signal output by the serial clock circuit is suppressed by the buffer amplifier, the RC filter and the waveform correction circuit.

8. The system according to claim 1, characterized in that, The display device is used to receive image data transmitted by the data output circuit, and when displaying the received image data after decoding and timing matching, it includes: The display device is used to: receive image data transmitted by the data output circuit, decode the received image data, and obtain decoded image data; The decoded image data is subjected to frame header signal and line synchronization signal detection; Based on the current resolution of the display device, the received image data is divided into multiple blocks of image data; Based on the detected frame header signal and line synchronization signal, the image data of the multiple blocks are refreshed and displayed in parallel.

9. The system according to claim 1, characterized in that, The data transmission process also includes: The master device is configured to: in response to a task triggering command that competes for the SPI bus bandwidth, determine the first bandwidth priority of the triggered task from a preset task bandwidth priority based on the type of the triggered task; The master device is used to: allocate SPI bus bandwidth to the triggered task according to the first bandwidth priority.

10. The system according to claim 1, characterized in that, The data transmission process also includes: The master device is used to: send a safety mode switching command to the phase-locked loop circuit in response to the chip temperature of the master device or the voltage of the SPI bus exceeding a preset safety threshold; The phase-locked loop circuit is used to: respond to the safety mode switching command and adjust the frequency of the output master clock signal to below a preset safety value by adjusting a preset multiplication factor; wherein the safety value is greater than or equal to the original master clock frequency.

11. A method for displaying image data, said display method being applied to a display system as described in any one of claims 1-10, characterized in that, The method includes: The master device acquires the image data to be transmitted; The phase-locked loop circuit boosts the original master clock frequency of the serial clock circuit, and the serial clock circuit outputs the master clock signal at the boosted target master clock frequency. The main device encodes and enhances the image data, and transmits the processed image data through the data output circuit based on the main clock signal output by the serial clock circuit. During data transmission, the master device dynamically shapes the master clock signal output by the serial clock circuit; The display device receives image data transmitted by the data output circuit, and displays the received image data after decoding and timing matching; timing matching is used to ensure that the time when the image data is written to the display device is consistent with the physical scanning cycle and clock rhythm of the display device. The steps of a phase-locked loop (PLL) circuit boosting the original master clock frequency of a serial clock circuit, and the serial clock circuit outputting the master clock signal at the boosted target master clock frequency, include: The phase-locked loop circuit receives the master clock signal input at the original master clock frequency; The voltage-controlled oscillator in the phase-locked loop circuit adjusts the frequency of its generated oscillation signal according to the preset multiplication and division coefficients; When the ratio of the frequency of the output master clock signal to the frequency multiplication factor is equal to the original master clock frequency and the phase difference remains constant, the frequency of the output master clock signal of the phase-locked loop circuit is taken as the target master clock frequency. The serial clock circuit outputs the master clock signal at the target master clock frequency; During data transmission, the master device dynamically shapes the master clock signal output by the serial clock circuit, including the following steps: During data transmission, the jitter amplitude between the rising and falling edges of the main clock signal output by the serial clock circuit is calculated using a preset dynamic jitter detection algorithm. Determine whether the jitter amplitude is greater than a preset jitter threshold; If the value is greater than the value, the master device dynamically shapes the master clock signal output by the serial clock circuit.

12. An electronic device, characterized in that, It includes a processor and a memory, the memory storing machine-executable instructions that can be executed by the processor, the processor executing the machine-executable instructions to implement the image data display method of claim 11.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when invoked and executed by a processor, cause the processor to implement the image data display method of claim 11.

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