A method and system for multi-channel synchronous receiving detection and correction in a phased array system

Abstract

The application discloses a kind of methods and systems of multichannel synchronous receiving detection and correction in phased array system, it is related to phased array radar signal wave control technical field, comprising: receiving the standard pulse signal sent by sending end, the standard pulse signal is written into the dynamic buffer area of this channel preset and start recording clock period, dynamic buffer area is all set to synchronous reading output, when detecting the power of written pulse signal reaches preset threshold, set this moment as the pulse signal arrival time of dynamic buffer area, at pulse signal arrival time, the IQ sample value of this moment is grabbed, the phase angle of the IQ sample value is calculated based on CORDIC algorithm, the phase difference of the phase angle of the IQ sample value and the starting phase of the standard pulse signal stored by transmitting end is calculated;After using measured time difference and phase difference, the real pulse signal is corrected.The application improves the quality of received data source, and overall improves the stability and reliability of phased array system.

Description

Technical Field

[0001] This invention relates to the field of phased array radar signal beam control technology, and in particular to a method and system for multi-channel synchronous reception detection and correction in a phased array system. Background Technology

[0002] To meet the technical requirements of phased array beamforming and beam synthesis, multi-channel synchronous reception is employed in radar systems to achieve longer detection ranges and higher accuracy. However, the different physical paths of the hardware and components in multi-channel reception prevent simultaneous reception. Hardware-wise, signal transmission, buffering, and synchronization via a high-speed JESD204B link cause deviations between the data arrival time and the theoretical time, resulting in poor signal processing quality and reduced system reception performance. Therefore, a multi-channel synchronous reception detection and correction method and system for phased array systems has been developed to address these issues. Summary of the Invention

[0003] This invention proposes a method and system for multi-channel synchronous reception detection and correction in a phased array system, in order to solve the problem that existing multi-channel reception cannot receive signals simultaneously due to differences in hardware and device physical paths.

[0004] The present invention achieves the above objectives through the following technical solutions:

[0005] This invention discloses a multi-channel synchronous reception detection and correction method in a phased array system, used at the receiving end, comprising:

[0006] Use the same clock and trigger signal as the transmitter;

[0007] Measurement Phase: For each channel, after the external synchronization trigger signal is generated, the receiving end sends a standard pulse signal. The standard pulse signal is a known signal with a fixed waveform, starting phase, and power. The standard pulse signal is written into the channel's preset dynamic buffer and the clock cycle is recorded. The dynamic buffer is set to synchronous read output. When the power of the written pulse signal is detected to reach a preset threshold, this moment is set as the pulse signal arrival time in the dynamic buffer, so that there is a time difference between the pulse signal arrival time and the preset standard arrival time. The IQ sample value of the pulse signal arrival time is captured, and the phase angle of the IQ sample value is calculated based on the CORDIC algorithm. The phase difference between the phase angle of the IQ sample value and the starting phase of the standard pulse signal stored at the transmitting end is calculated.

[0008] Working phase: For each channel, after the external synchronization trigger signal is generated, the receiver sends the real pulse signal, writes the real pulse signal into the dynamic buffer, outputs the time-aligned IQ data stream, rotates the phase of the time-aligned IQ data stream by an angle equal to the phase difference, and outputs the calibrated pulse signal.

[0009] Furthermore, the transmitting end sends a standard pulse signal, including:

[0010] When an external trigger signal is generated, the transmitting end reads the stored waveform data and broadcasts it in a fixed period of single-frequency pulse. The time of its appearance is always relatively fixed with the time of the external trigger signal, and the initial position of the pulse phase is always fixed.

[0011] An oscilloscope is used to measure the RF output position to trigger the signal reference. The output signal is a fixed waveform, i.e., a standard pulse signal.

[0012] Furthermore, the standard pulse signal single-frequency pulse is fixed to a 16-bit 64-point sampling data width, and the dynamic buffer is a 256-bit 16-bit BRAM.

[0013] Furthermore, when the power of the written signal reaches 1 / 3 of the preset maximum value, the arrival time of the pulse signal in the dynamic buffer is recorded at the current moment.

[0014] Furthermore, the phase of the time-aligned IQ data stream is rotated by an angle equal to the phase difference, including: calculating the complex number of the phase difference as a rotation factor, multiplying the IQ data stream by the rotation factor to obtain the rotated IQ data stream.

[0015] The present invention also provides a system for a multi-channel synchronous reception detection and correction method in a phased array system, comprising:

[0016] The transmitting end is equipped with a standard pulse data transmission module, which is used to transmit a standard pulse signal. The standard pulse signal is a known signal with a fixed waveform, starting phase, and power.

[0017] The receiving end, for each channel, includes a measurement module and a working module, wherein:

[0018] The measurement module is used to receive a standard pulse signal sent by the transmitter after an external synchronous trigger signal is generated. The standard pulse signal is a known signal with a fixed waveform, starting phase and power. The standard pulse signal is written into a preset dynamic buffer of the channel and the clock cycle is recorded. The dynamic buffer is set to synchronous read output. When the power of the written pulse signal is detected to reach a preset threshold, this moment is set as the pulse signal arrival time of the dynamic buffer. There is a time difference between the pulse signal arrival time and the preset standard arrival time. The IQ sample value of the pulse signal arrival time is captured, and the phase angle of the IQ sample value is calculated based on the CORDIC algorithm. The phase difference between the phase angle of the IQ sample value and the starting phase of the standard pulse signal stored at the transmitter is calculated.

[0019] The working module is used to receive the real pulse signal sent by the transmitting end after the external synchronization trigger signal is generated, write the real pulse signal into the dynamic buffer, output the time-aligned IQ data stream, rotate the phase of the time-aligned IQ data stream as a whole by an angle equal to the phase difference, and output the calibrated pulse signal.

[0020] Furthermore, the transmitting end sends a standard pulse signal, including:

[0021] When an external trigger signal is generated, the transmitting end reads the stored waveform data and broadcasts it in a fixed period of single-frequency pulse. The time of its appearance is always relatively fixed with the time of the external trigger signal, and the initial position of the pulse phase is always fixed.

[0022] An oscilloscope is used to measure the RF output position to trigger the signal reference. The output signal is a fixed waveform, i.e., a standard pulse signal.

[0023] Furthermore, the standard pulse signal single-frequency pulse is fixed to a 16-bit 64-point sampling data width, and the dynamic buffer is a 256-bit 16-bit BRAM.

[0024] Furthermore, when the power of the written signal reaches 1 / 3 of the preset maximum value, the arrival time of the pulse signal in the dynamic buffer is recorded at the current moment.

[0025] Furthermore, the phase of the time-aligned IQ data stream is rotated by an angle equal to the phase difference, including: calculating the complex number of the phase difference as a rotation factor, multiplying the IQ data stream by the rotation factor to obtain the rotated IQ data stream.

[0026] The beneficial effects of this invention are as follows:

[0027] The present invention proposes a multi-channel synchronous reception detection and correction method and system in a phased array system. Through dynamic buffer and phase correction multiplication, the quality of the received data source is improved. The corrected data is closer to the true value of the target, and the synthesized result is more accurate and precise. Interference is removed, and the overall stability and reliability of the phased array system are improved. The method automatically detects and calibrates, which is completed instantaneously. After the detection and correction are completed, the radar enters the normal working mode. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the system connection of the present invention;

[0029] Figure 2 A schematic diagram showing the different actual starting points for multi-channel ADC acquisition and reception;

[0030] Figure 3This is a schematic diagram illustrating the measurement and movement of a certain signal to a fixed relative position.

[0031] Figure 4 This is a schematic diagram illustrating the rotation principle of the CORDIC algorithm.

[0032] Figure 5 This is a schematic diagram showing the location of the received pulse data in the dynamic buffer;

[0033] Figure 6 This diagram illustrates how all channels output aligned IQ data at a uniform time. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0035] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0036] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0037] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0038] This invention discloses a multi-channel synchronous reception detection and correction method in a phased array system, used at the receiving end, comprising:

[0039] Use the same clock and trigger signal as the transmitter;

[0040] Measurement Phase: For each channel, after the external synchronization trigger signal is generated, the receiving end sends a standard pulse signal. The standard pulse signal is a known signal with a fixed waveform, starting phase, and power. The standard pulse signal is written into the channel's preset dynamic buffer and the clock cycle is recorded. The dynamic buffer is set to synchronous read output. When the power of the written pulse signal is detected to reach a preset threshold, this moment is set as the pulse signal arrival time in the dynamic buffer. The IQ sample value of the pulse signal arrival time is captured, and the phase angle of the IQ sample value is calculated based on the CORDIC algorithm. The phase difference between the phase angle of the IQ sample value and the starting phase of the standard pulse signal stored at the transmitting end is calculated.

[0041] Working phase: For each channel, after the external synchronization trigger signal is generated, the receiver sends the real pulse signal, writes the real pulse signal into the dynamic buffer, outputs the time-aligned IQ data stream, rotates the phase of the time-aligned IQ data stream by an angle equal to the phase difference, and outputs the calibrated pulse signal.

[0042] In one embodiment, the transmitting end transmits a standard pulse signal, including:

[0043] When an external trigger signal is generated, the transmitting end reads the stored waveform data and broadcasts it in a fixed period of single-frequency pulse. The time of its appearance is always relatively fixed with the time of the external trigger signal, and the initial position of the pulse phase is always fixed.

[0044] An oscilloscope is used to measure the RF output position to trigger the signal reference. The output signal is a fixed waveform, i.e., a standard pulse signal.

[0045] In one embodiment, the standard pulse signal single-frequency pulse is fixed to a 16-bit 64-point sampling data width, and the dynamic buffer is a 256-bit 16-bit BRAM.

[0046] In one embodiment, when the power of the write signal reaches 1 / 3 of the preset maximum value, the arrival time of the pulse signal in the dynamic buffer is recorded at the current moment.

[0047] In one embodiment, rotating the phase of the time-aligned IQ data stream as a whole by an angle equal to the phase difference includes: calculating a complex number of the phase difference as a rotation factor, multiplying the IQ data stream by the rotation factor to obtain the rotated IQ data stream.

[0048] The present invention also provides a system for a multi-channel synchronous reception detection and correction method in a phased array system, comprising:

[0049] The transmitting end is equipped with a standard pulse data transmission module, which is used to transmit a standard pulse signal. The standard pulse signal is a known signal with a fixed waveform, starting phase, and power.

[0050] The receiving end, for each channel, includes a measurement module and a working module, wherein:

[0051] The measurement module is used to receive a standard pulse signal sent by the transmitter after an external synchronous trigger signal is generated. The standard pulse signal is a known signal with a fixed waveform, starting phase and power. The standard pulse signal is written into a preset dynamic buffer of the channel and the clock cycle is recorded. The dynamic buffer is set to synchronous read output. When the power of the written pulse signal is detected to reach a preset threshold, the pulse signal arrival time in the dynamic buffer is set at this moment. The time difference between the pulse signal arrival time and the preset standard arrival time is calculated. The IQ sample value of the pulse signal arrival time is captured. The phase angle of the IQ sample value is calculated based on the CORDIC algorithm. The phase difference between the phase angle of the IQ sample value and the starting phase of the standard pulse signal stored at the transmitter is calculated.

[0052] The working module is used to receive the real pulse signal sent by the transmitting end after the external synchronization trigger signal is generated, write the real pulse signal into the dynamic buffer, output the time-aligned IQ data stream, rotate the phase of the time-aligned IQ data stream as a whole by an angle equal to the phase difference, and output the calibrated pulse signal.

[0053] In one embodiment, the transmitting end transmits a standard pulse signal, including:

[0054] When an external trigger signal is generated, the transmitting end reads the stored waveform data and broadcasts it in a fixed period of single-frequency pulse. The time of its appearance is always relatively fixed with the time of the external trigger signal, and the initial position of the pulse phase is always fixed.

[0055] An oscilloscope is used to measure the RF output position to trigger the signal reference. The output signal is a fixed waveform, i.e., a standard pulse signal.

[0056] In one embodiment, the standard pulse signal single-frequency pulse is fixed to a 16-bit 64-point sampling data width, and the dynamic buffer is a 256-bit 16-bit BRAM.

[0057] In one embodiment, when the power of the write signal reaches 1 / 3 of the preset maximum value, the arrival time of the pulse signal in the dynamic buffer is recorded at the current moment.

[0058] In one embodiment, rotating the phase of the time-aligned IQ data stream as a whole by an angle equal to the phase difference includes: calculating a complex number of the phase difference as a rotation factor, multiplying the IQ data stream by the rotation factor to obtain the rotated IQ data stream.

[0059] In summary, the core idea of ​​this invention is as follows: Since beamforming is used in phased array systems to improve detection range and sensitivity, the phase of each channel must remain relatively consistent to ensure reception performance. Inconsistent timing or phase severely weakens or interferes with the identification and processing of normal signals. Therefore, starting at the external trigger signal moment, the amplitude of the signal is continuously calculated. When the power reaches a certain threshold, the time difference between the current signal and the trigger signal is saved and recorded as the pulse signal arrival time. Then, the instantaneous phase of the pulse signal arrival time is calculated. The time difference and phase difference are compared with the original transmitter to make adjustments. In traditional calibration schemes, multi-channel time synchronization typically uses a fixed delay line, and then the static calibration value is written into the FPGA and synchronized via JESD204B timing. However, this scheme achieves dynamic alignment through pulse detection. This invention automatically identifies the arrival time based on the pulse power threshold and uses an adaptive delay alignment mechanism based on a dynamic BRAM buffer to achieve independent offset correction for each ADC signal, ultimately achieving multi-channel synchronous output.

[0060] The standard pulse waveform data used for measurement at the transmitting end is a single-frequency pulse with a fixed 16-bit 64-point sampling data width. When these samples are measured at the receiving end, they will fall within a certain position range of the dynamic buffer.

[0061] The principle for calculating the power of the written signal is: Power P = |S 2 |, where S is the IQ signal, and the formula is S = I + jQ (j is the imaginary unit), |S 2 |=(I+jQ)×(I-jQ)=I 2 +Q 2 Where S is the IQ signal, I is the in-phase component, and Q is the quadrature component with a 90° phase difference, the start of the signal power judgment pulse signal is obtained. The power value is used to mark the start time of the signal.

[0062] A 256-bit, 16-bit BRAM is configured as the channel signal write buffer, i.e., a dynamic buffer for receiving data. The dynamic buffer is tentatively set to simultaneous read and output. When external synchronization is triggered, a pulse signal is received. At the receiving end, the clock cycle recording begins. The arrival time of the pulse signal is recorded when the power of the write signal reaches 1 / 3 of its maximum value. This ensures that the pulse signal arrival time is always later than the time when the transmitter finishes transmitting. In this embodiment, the overall signal delay of the transmit and receive link in actual measurement is much less than the time required for 256 sampling clock cycles. Therefore, the read time can be adjusted to be no later than 255 clock cycles after writing, achieving a dynamic change in the input signal with a delay of 1 to 255. By adjusting the relative position offset of the read address, the signal is relatively moved to a fixed output time. The system's transmit and receive are time-invariant systems; the adjustment of the relative delay matches the receive and transmit times. The time when the transmitter finishes transmitting is set as the start time for the receiver's signal output. At the time the transmitter finishes transmitting, the signal is fully present in the dynamic buffer. Adjusting the read position ensures that the receive signal appears at a fixed delay time; that is, the time from the start of the transmit signal to the start of the receive signal remains relatively constant. In the FPGA, the new address obtained by subtracting the measured clock cycle from the BRAM read address is used as the starting address for data transmission. This means the read address is delayed based on the time difference, achieving automatic read address adjustment. During the loop where the write address remains constant, the decrease in the read address delays the signal, ensuring that the signals read from the BRAM are aligned for output. The sampling phase adjustment of the received data is achieved by calculating the phase deviation between the starting point and the starting phase of the original signal, and then rotating the angle using a complex product (i.e., modulus multiplication and amplitude addition) to correct the sampling deviation. Since the sampling clock source is synchronized and the frequency is fixed, meaning the sampling rate is always consistent, the corrected sampling deviation is the fixed relative deviation between the sampling ADC clock and the DAC clock. The corrected data maintains consistency with the original transmitted data in both amplitude and phase.

[0063] CORDIC is short for Coordinate Rotation Digital Computer Algorithm. Its calculation steps mainly include:

[0064] Point P on the unit circle with origin O has a vector OP that makes an angle α with the positive x-axis. Therefore, the rectangular coordinates of point P are: , ;

[0065] Rotate vector OP counterclockwise Angle to vector OQ, at which point the angle between OQ and the positive x-axis is... Therefore, the coordinates of point Q can be expressed as , , For the target rotation angle, use the trigonometric function formulas. , The above conversion yields the formula as follows: , ;

[0066] extract Then, the formula is obtained as follows: , Remove The new coordinate point R is , Each angular rotation increases its magnitude. ;

[0067] By rotating the angle N times, the angle that most closely approximates the original coordinates of point P can be obtained. To make the algorithm easy to implement, the tangent value of the selected angle is set to a binary decimal form, such as: {1,0.5,0.25,0.125,0.0625,..}. The tangent value of the angle is reduced by half with each rotation. After more than ten rotations, the final approximate angle error is less than one-thousandth.

[0068] like Figure 4 As shown in the figure, this is an example of the CORDIC algorithm. The IQ point, i.e., the coordinates (x1, y1) to (x2, y2), is obtained by rotating it by an angle. Since only the angle is considered, the rotation can be obtained by the tangent of the rotation angle. The final accurate angle is obtained through multiple rotations. The specific algorithm is implemented using the CORDIC algorithm.

[0069] like Figure 1 As shown, this invention also provides a multi-channel synchronous reception detection and correction device for a phased array system, comprising a standard pulse data transmission module, a power divider, a clock source chip, a high-speed DAC converter, a synchronous high-speed ADC converter, an SMA connector, and multiple parallel pulse measurement units and BRAM, as well as a large-scale FPGA logic device. Due to differences in physical channel connections and electrical characteristics between channels, the same signal may appear at different times at the receiving end. By setting a fixed external reference clock and trigger signal from the same source, a single transmitting source can simultaneously receive in-phase source data at multiple receiving ends, thus meeting the transmission and reception performance requirements of the phased array system. Figure 1 In the diagram, RX represents receive; RX(0): the 0th receive channel; RX(N): the Nth receive channel; DCLK represents the device clock; SYSREF represents the system reference signal; SYNC represents synchronization; RFCLK represents the radio frequency sampling clock; REFCLK represents the reference clock.

[0070] According to the synchronization requirements of phased array radar transmission and reception, a source synchronization clock and trigger signal are required. The transmitter uses the trigger signal as a time reference, mixes the preset pulse waveform data, and then converts it into an RF signal via a high-speed DAC converter. External signals are received by SMA connectors on different boards via a power divider. The receiving board uses a synchronous high-speed ADC converter to receive the signals simultaneously. The FPGA receives JESD204B data to correct and restore the pulse data waveform from the transmitter. The parameters of the data waveform are measured at preset time points. The amplitude, phase, and delay of the starting point are calculated, and the reception is adjusted based on the measurements to ensure that the time, phase, and amplitude of each signal received by the signal processing unit are consistent with those of the transmitter. This adjustment is due to the physical relative delay on the system's fixed link, correcting deviations caused by the system.

[0071] The standard pulse data transmission module can use a DAC chip with a high-speed JESD204B to output RF signals. The receiving end uses multiple different modules, with multiple ADC chips synchronously acquiring data using the same clock source. The FPGAs on each module receive the pulse signal from the transmitting end within a certain time period. Data transmission for each channel occurs on different JESD204B links. Before adjustment, there are different clock deviations between the sampling position and the reference position. The single-chip multi-channel link establishment and data buffer start points differ, resulting in different receiving positions. The position after each power-on differs from the previous power-on position, exhibiting a small range of variation. This is related to the different fixed deviations between the VCO locking phase timing and the source within the synchronous clock source. Multiple phase-locked loops with different frequency points are used in the DAC or ADC. After locking, the clock output phase and the input reference clock phase remain fixed, but there is a different offset from the reference clock each time power is applied.

[0072] A fixed transmitter continuously generates pulse signals. To correct the fact that the data collected remains constant after each power-on of the ADC receiver, it is necessary to detect and correct data deviations at the data receiving front end to ensure that the data is in phase with the original data.

[0073] At the reference time, before any pulse is transmitted, the received noise amplitude is below the signal amplitude. Clock counting begins at this moment and continues until pulse data is received. Both the transmitting and receiving ends include the same NCO mixer to move the IQ signal to RF and restore the baseband IQ signal from RF. Measurements and calculations are all performed on the baseband IQ signal. When the first IQ data point of a pulse is detected, the current count value is retained, representing the relative time between the actual received pulse and the reference time. The angle of the first IQ data point is calculated using CORDIC and compared with the angle of the first point of the original IQ signal; the angle deviation is recorded, representing the DAC and ADC sampling deviation.

[0074] A 256-bit deep 16-bit BRAM circular buffer is set to dynamically delay the signal to a new fixed standard position, and this position is set to the correct time when the signal should appear. By counting the clock occurrences of the measured pulses, the address of the BRAM is controlled to change from being the same for both read and write addresses to decreasing the read address, which delays the received data. After the delay, the output data will be fixed at the new standard position, aligning the data points of all receiving channels.

[0075] The sampling clock remains fixed, and the resulting phase difference is converted into a deviation of the sampling point. The IQ data angle value of the first point of each channel calculated by CORDIC has a slight deviation. This value is converted into a complex number, and the phase angle of the IQ data is rotated using the complex number product to correct the deviation caused by the sampling clock and align the sampling points. Through position adjustment and phase rotation, the received signal is made the same as the original signal.

[0076] In a unified transmission and reception system, the IQ signal source is pulse data with a fixed sampling rate of 240MHz and a clock of 240MHz. After analog RF conversion and correction of signal position and phase, the received IQ data before signal processing is almost identical to the signal from the transmission source. This corrects the asynchronous problem caused during system transmission, and the received signal truly reflects the signal characteristics of the transmitting end.

[0077] like Figure 2 As shown in the figure, in actual testing, various factors, such as the physical connection of multiple channel hardware, cause the received signals to not arrive at the same time, failing to meet the requirement of simultaneous data input for subsequent processing. Taking the synchronous trigger signal input as the reference point P, DAC(TX) represents the time interval of the signal at the transmitting end relative to point P. The receiving time is unique at the transmitting end. However, for multiple channels receiving the same signal, due to the differences in the connected devices and boards after the power divider output, the starting positions of the received waveform signals are not the same, even with point P as the reference time. ADC(RX.0) represents the 0th receiving channel, ADC(RX.1) represents the 1st receiving channel, and so on, with ADC(RX.N) representing the Nth receiving channel. The receiving start times do not coincide, resulting in different receiving times.

[0078] like Figure 3 As shown in the example channel 0, IQ data is obtained by mixing ADC data with an NCO. The initial amplitude and phase of the waveform signal are detected on the IQ data to obtain the time difference ΔT and Δt. The phase and I are calculated using CORDIC. 2 +Q 2The amplitude is calculated by measuring the actual received IQ data time difference from the ideal IQ data time difference. Since all receiving channels need to be aligned, the signal must be delayed until all signals have arrived. Therefore, a fixed time delay D is set, at which point all channels have received the initial IQ data. The measured time difference is dynamically delayed relative to this fixed time difference so that the signal received by channel 0 is output at the same fixed delay D. The input signal is written to the channel's dynamic buffer, a 256-bit deep 16-bit BRAM. The channel measurement value is fed back to the read address, controlling the BRAM read address to dynamically adjust the output signal. Each channel is processed in this way, resulting in aligned output from all channels.

[0079] The DAC output signal at the transmitting end will have a slight τ offset when received. Since both DAC and ADC sampling use the same clock source, the ADC sampling at the receiving end will inevitably lag behind the DAC sampling at the transmitting end, requiring compensation at the receiving end. The IQ data phase at the transmitting end starts from 0°, and the position of the first data received at the receiving end should also be corrected to 0°. The slight τ time at the receiving end is converted into phase and corrected using CORDIC to ensure that the signal at the receiving end has the same phase as that at the transmitting end.

[0080] like Figure 5 As shown in the figure, a 256-bit BRAM is described. During the data writing process, due to different reception times, the position of the first signal written differs. The read address IQ_STD is adjusted. Each channel has its own read address based on the calculated measurement deviation, such as IQ_STD(RX.0), IQ_STD(RX.1), and IQ_STD(RX.N), ensuring that the data waveforms are output at the same time, achieving IQ data alignment. In actual measurements, the mutual data sampling point deviation between channels is within 32 data points, preventing a situation where one channel has already filled 256 bits while another has not yet received the initial data. The adjusted output cancels out the sequential arrival of data from different channels, aligning the outputs.

[0081] like Figure 6 As shown in the figure, the output state after final synchronization alignment is illustrated. Channels IQ(RX.0), IQ(RX.1), and IQ(RX.N) will receive output at a fixed time D. Each channel is shifted by different measurement values, delaying the channel signal at different time scales, and finally aligning the output.

[0082] The multi-channel synchronous reception detection and correction method and system proposed in this invention corrects time and phase deviations in the signal before subsequent processing, improving the overall received signal performance and reducing interference. By improving the method to compensate for differences, the system is adjusted to operate in its optimal state. Under the same reference clock and trigger, multiple chips or multiple boards can receive signals synchronously and consistently, while minimizing hardware resources and rationally combining performance and resources to meet the requirements of simultaneous multi-channel processing.

[0083] This invention achieves automatic calibration by adding a dynamic BRAM buffer, automatic time detection, and automatic address adjustment, eliminating the need for manual calibration, reducing the cumulative error of multi-channel differences, solving the unpredictable time drift caused by JESD204B link and VCO phase-locked offset, and improving the working accuracy of the phased array system.

[0084] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for multi-channel synchronous reception detection and correction in a phased array system, characterized in that, For the receiving end, including: Use the same clock and trigger signal as the transmitter; Measurement Phase: For each channel, after the external synchronization trigger signal is generated, the receiving end sends a standard pulse signal. The standard pulse signal is a known signal with a fixed waveform, starting phase, and power. The standard pulse signal is written into the channel's preset dynamic buffer and the clock cycle is recorded. The dynamic buffer is set to synchronous read output. When the power of the written pulse signal is detected to reach a preset threshold, this moment is set as the pulse signal arrival time in the dynamic buffer. The IQ sample value of the pulse signal arrival time is captured, and the phase angle of the IQ sample value is calculated based on the CORDIC algorithm. The phase difference between the phase angle of the IQ sample value and the starting phase of the standard pulse signal stored at the transmitting end is calculated. Working phase: For each channel, after the external synchronization trigger signal is generated, the receiver sends the real pulse signal, writes the real pulse signal into the dynamic buffer, outputs the time-aligned IQ data stream, rotates the phase of the time-aligned IQ data stream by an angle equal to the phase difference, and outputs the calibrated pulse signal.

2. The method for multi-channel synchronous reception detection and correction in a phased array system according to claim 1, characterized in that, The transmitting end sends standard pulse signals, including: When an external trigger signal is generated, the transmitting end reads the stored waveform data and broadcasts it in a fixed period of single-frequency pulse. The time when the pulse appears is always relatively fixed with respect to the external trigger signal, and the initial position of the pulse phase is always fixed. An oscilloscope is used to measure the RF output position to trigger the signal reference. The output signal is a fixed waveform, i.e., a standard pulse signal.

3. The method for multi-channel synchronous reception detection and correction in a phased array system according to claim 1, characterized in that, The standard pulse signal single-frequency pulse is fixed with a 16-bit 64-point sampling data width, and the dynamic buffer is a 256-bit 16-bit BRAM.

4. The method for multi-channel synchronous reception detection and correction in a phased array system according to claim 1, characterized in that, When the power of the written signal reaches 1 / 3 of the preset maximum value, the arrival time of the pulse signal in the dynamic buffer is recorded.

5. The method for multi-channel synchronous reception detection and correction in a phased array system according to claim 1, characterized in that, The phase of the time-aligned IQ data stream is rotated by an angle equal to the phase difference, including: calculating the complex number of the phase difference as a rotation factor, multiplying the IQ data stream by the rotation factor to obtain the rotated IQ data stream.

6. A system for multi-channel synchronous reception detection and correction in a phased array system, characterized in that, include: The transmitting end is equipped with a standard pulse data transmission module, which is used to transmit a standard pulse signal. The standard pulse signal is a known signal with a fixed waveform, starting phase, and power. The receiving end, for each channel, includes a measurement module and a working module, wherein: The measurement module is used to receive a standard pulse signal after an external synchronous trigger signal is generated, write the standard pulse signal into a preset dynamic buffer of the channel and start recording the clock cycle. The dynamic buffer is set to synchronous read output. When the power of the written pulse signal is detected to reach a preset threshold, this moment is set as the pulse signal arrival time of the dynamic buffer. The IQ sample value of the pulse signal arrival time is captured, the phase angle of the IQ sample value is calculated based on the CORDIC algorithm, and the phase difference between the phase angle of the IQ sample value and the starting phase of the standard pulse signal stored at the transmitter is calculated. The working module is used to receive the real pulse signal sent by the transmitting end after the external synchronization trigger signal is generated, write the real pulse signal into the dynamic buffer, output the time-aligned IQ data stream, rotate the phase of the time-aligned IQ data stream as a whole by an angle equal to the phase difference, and output the calibrated pulse signal.

7. The system for a multi-channel synchronous reception detection and correction method in a phased array system according to claim 6, characterized in that, The transmitting end sends standard pulse signals, including: When an external trigger signal is generated, the transmitting end reads the stored waveform data and broadcasts it in a fixed period of single-frequency pulse. The time when the pulse appears is always relatively fixed with respect to the external trigger signal, and the initial position of the pulse phase is always fixed. An oscilloscope is used to measure the RF output position to trigger the signal reference. The output signal is a fixed waveform, i.e., a standard pulse signal.

8. The system for a multi-channel synchronous reception detection and correction method in a phased array system according to claim 6, characterized in that, The standard pulse signal single-frequency pulse is fixed with a 16-bit 64-point sampling data width, and the dynamic buffer is a 256-bit 16-bit BRAM.

9. The system for a multi-channel synchronous reception detection and correction method in a phased array system according to claim 6, characterized in that, When the power of the written signal reaches 1 / 3 of the preset maximum value, the arrival time of the pulse signal in the dynamic buffer is recorded.

10. The system for a multi-channel synchronous reception detection and correction method in a phased array system according to claim 6, characterized in that, The phase of the time-aligned IQ data stream is rotated by an angle equal to the phase difference, including: calculating the complex number of the phase difference as a rotation factor, multiplying the IQ data stream by the rotation factor to obtain the rotated IQ data stream.

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