An on-orbit reconfiguration system for spaceborne SRAM-based FPGA programs
By designing an on-orbit reconfiguration system for satellite-borne SRAM-type FPGA programs, the problem of single-event upsets in the space environment of SRAM-type FPGAs was solved, enabling flexible program reconfiguration and improving satellite reliability and mission success rate.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NAT SPACE SCI CENT CAS
- Filing Date
- 2025-10-14
- Publication Date
- 2026-06-30
AI Technical Summary
SRAM-based FPGAs are susceptible to single-event upsets caused by high-energy radiation particles in the space environment, leading to logic errors. Furthermore, they are difficult to reconfigure flexibly to adapt to mission changes during on-orbit operation.
An on-orbit reconfiguration system for a spaceborne SRAM-type FPGA program was designed, comprising a data processing unit, a JFMRS01RH unit, an external storage unit, and a target FPGA. The system performs data packet detection and buffering by receiving and demodulating intermediate frequency signals, recovering AOS data frames, and decoding LDPC signals. The JFMRS01RH unit is used for status monitoring and task scheduling to achieve on-orbit reconfiguration of the FPGA.
It improves the reliability and flexibility of satellites, enhances their adaptability to missions, reduces maintenance costs, and increases the reliability of satellites in orbit and the success rate of missions.
Smart Images
Figure CN121365030B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the fields of satellite integrated electronics and on-orbit software / FPGA reconfiguration technology, and particularly relates to an on-orbit reconfiguration system for satellite SRAM-type FPGA programs. Background Technology
[0002] In recent years, with the rapid development of aerospace technology, satellite payloads have become increasingly complex, placing higher demands on the real-time performance, flexibility, and reliability of data processing and logic control. SRAM-based FPGAs, with their advantages of reprogrammability, flexible configuration, and high performance, have gradually become the core control chips in satellite payload design, playing an irreplaceable role in onboard data processing and logic control management.
[0003] The advantages of SRAM-based FPGAs are mainly reflected in the following aspects: First, their reprogrammable nature allows them to be flexibly configured according to different application requirements, meeting the diverse mission requirements of satellite payloads; second, SRAM-based FPGAs have parallel processing capabilities, enabling them to efficiently process massive amounts of data and meet the real-time requirements of onboard data processing; in addition, SRAM-based FPGAs also have advantages such as short design cycles and low development costs, which can effectively shorten the R&D cycle of satellite payloads.
[0004] However, SRAM-based FPGAs also face severe challenges in the space environment. First, the space environment contains a large number of high-energy radiation particles. These particles bombard the memory cells of SRAM-based FPGAs, potentially causing state flips, a phenomenon known as Single Event Upset (SEU). SEUs can trigger internal logic errors within the FPGA and even lead to satellite payload malfunctions, seriously threatening the safety and reliability of satellite operations in orbit. Second, during satellite operation, errors or vulnerabilities in the FPGA logic design may be discovered. These errors or vulnerabilities could cause the satellite to malfunction or even lead to mission failure. Furthermore, the adaptability requirements of spacecraft during in-orbit operation place higher demands on the reconfigurability of FPGAs. Some in-orbit satellite products also face the challenge of adapting to different mission requirements while maintaining the same hardware.
[0005] Therefore, for satellites in orbit, FPGA on-orbit reconfiguration systems, which reconfigure FPGA programs via ground commands or autonomous decision-making to fix logic errors, update functions, or adapt to new mission requirements, have significant practical value. Simultaneously, FPGA on-orbit reconfiguration technology can effectively improve satellite reliability and flexibility, extend satellite lifespan, and reduce satellite maintenance costs. FPGA on-orbit reconfiguration technology will provide stronger support for satellite payload design and application, and will also greatly improve the reliability of satellites in orbit and the success rate of missions. Summary of the Invention
[0006] The purpose of this invention is to overcome the shortcomings of the prior art and to propose an on-orbit reconfiguration system for spaceborne SRAM-type FPGA programs.
[0007] In view of this, the present invention proposes an on-orbit reconfiguration system for a spaceborne SRAM-type FPGA program. The system includes: a data processing unit, a JFMRS01RH unit, an external storage unit, and a target FPGA.
[0008] The data processing unit includes a satellite-to-ground data processing module and an onboard data processing module. The satellite-to-ground data processing module is used to receive intermediate frequency signals from the satellite, perform demodulation, AOS data frame recovery, data descrambling, and LDPC decoding. The onboard data processing module is used to sequentially perform AOS data frame parsing, uploading data packet reassembly, verification, and secondary encapsulation, and then transmit the data to the JFMRS01RH unit.
[0009] The JFMRS01RH unit is used to receive the uploading data packet after secondary encapsulation by the data processing unit, perform status monitoring and feedback the status to the data processing unit, and also to perform task scheduling management.
[0010] The external storage unit is used for caching the reassembled data packets and for storing the upload files to be loaded into the target FPGA.
[0011] The target FPGA is used to provide logic control and algorithm implementation for the payload of the satellite in orbit.
[0012] As an improvement to the above system, the processing procedure of the satellite-to-ground data processing module includes:
[0013] It receives intermediate frequency signals from satellites, samples them, and performs frequency acquisition, carrier synchronization, and timing synchronization on the sampled uplink digital signals, thereby completing the conversion from analog to digital signals.
[0014] Based on the transmit and receive levels, in the receive time slot, remove the pilot of the unnumbered information frame in the air interface and restore it to the standard AOS frame format;
[0015] The system receives data transmission frames from the depilot group AOS frames, descrambles the original scrambled region, performs validity processing on the descrambled valid frames, performs LDPC decoding according to the decoding rules of the (8160,7136) low-density parity check code, and outputs the decoded data and instructions from the ground to the onboard data processing module.
[0016] As an improvement to the above system, the processing procedure of the on-board data processing module includes:
[0017] Perform a validity check on the data packet to determine if the packet's initial information is correct. If it is, the packet is considered valid; otherwise, it is considered invalid and discarded.
[0018] The virtual channel identifier in the above-injected data packet is extracted and latched to generate the logical address of SDRAM. At the same time, the data source packet information of the FPGA program to be reconstructed is extracted from the AOS transmission frame according to the link protocol.
[0019] Extract the length field of valid data packets and perform verification; for data packets that are determined to be correct, generate a logical address for caching based on the virtual channel identifier and data packet number, and map it to a physical address, and cache the data packets in SDRAM; for data packets that are determined to be incorrect, send the data packet sequence number back to the ground, wait for the ground to send back the updated correct data packets, generate a logical address for caching based on the virtual channel identifier and data packet number, and map it to a physical address, and cache it in the corresponding location in SDRAM.
[0020] The valid data packets are encapsulated into data packets that conform to NOR Flash programming operations according to the format required by the JFMRS01RH protocol, and sent to the JFMRS01RH unit through the UART interface in the agreed format.
[0021] As an improvement to the above system, the data processing unit further includes: a clock management module, a UART control module, and an SDRAM control module; wherein,
[0022] The clock management module is used to generate clocks for the satellite-to-ground data processing module and the on-board data processing module respectively according to the clock frequency of the external crystal oscillator, and at the same time provide clock signals to the JFMRS01RH unit.
[0023] The UART control module is used to send instruction information to the JFMRS01RH unit and receive status information fed back by the JFMRS01RH unit.
[0024] The SDRAM control module is used for scheduling and controlling the external SDRAM chip, which is used to provide a cache for the on-orbit reconstruction file of the target FPGA received by the on-board data processing module.
[0025] As an improvement to the above system, the JFMRS01RH unit includes: a clock module, a UART control module, a configuration control module, an FPGA control module, and a NOR Flash control module, wherein...
[0026] The clock module is used to receive clock signals from the clock management module of the data processing unit and generate clocks of different frequencies for use by other modules inside the JFMRS01RH unit.
[0027] The UART control module is used to receive and parse instruction information from the data processing unit, and at the same time to feed back status information to the UART control module of the data processing unit.
[0028] The configuration control module is used to detect the model, interface mode and interface connection method of the target FPGA, and is also used to detect and count whether the target FPGA has readback errors and / or refresh errors due to single-event interruption events during refresh and loading, and to configure the refresh and readback mode, refresh and readback time interval of the target FPGA.
[0029] The FPGA control module is used to configure the bit stream of the target FPGA according to a predetermined process for the program that needs to be updated.
[0030] The NOR Flash control module is used to monitor the status of the JFMRS01RH unit. When the data writing conditions are met, it updates the program storage area identifier, encapsulates the valid data in the correct uploading data packet into a data packet that conforms to the NOR Flash programming operation according to the format required by the JFMRS01RH protocol, and sends it to the JFMRS01RH unit through the UART interface according to the agreed format, while starting the NOR Flash writing operation.
[0031] As an improvement to the above system, the JFMRS01RH unit uses RS422 serial communication to feed back the status to the data processing unit. The feedback status includes: FPGA refresh status, reload status, reload and refresh bit stream CRC detection results, UART command CRC status, FLASH operation results, UART processing status, and FIFO data status. The communication baud rate is 115200bps, and the status data packet format is: frame header + offset address + 1B data + 2B CRC check + frame tail, with 21 bytes sent at a time.
[0032] As an improvement to the above system, the external storage unit includes: an SDRAM cache and a NOR Flash cache, wherein,
[0033] The SDRAM cache interacts with the data processing unit to cache the data packets reassembled on the satellite.
[0034] The NOR Flash cache interacts with the JFMRS01RH unit to store the upload file loaded onto the target FPGA.
[0035] As an improvement to the above system, the target FPGA is any one of the JFM4V, JFM7V, and JFM7K series from Fudan Microelectronics and the VIRTEX2, VIRTEX4~7, and KINTEX7 series from Xilinx.
[0036] Compared with the prior art, the advantages of the present invention are:
[0037] 1. This invention has the capability to receive and analyze uplink intermediate frequency data from satellites;
[0038] 2. This invention supports out-of-order packet processing and packet retransmission;
[0039] 3. This invention has multi-level data packet integrity detection and caching capabilities;
[0040] 4. This invention efficiently realizes the on-orbit reconfiguration function of SRAM-type FPGA with a modular architecture, providing stronger support for the design and application of satellite payloads, and greatly improving the reliability of on-orbit satellites and the success rate of missions. Attached Figure Description
[0041] Figure 1 This is a schematic diagram of the on-orbit reconfiguration system architecture of the spaceborne SRAM-type FPGA program of the present invention;
[0042] Figure 2 This is a schematic diagram of the standard AOS frame format;
[0043] Figure 3 This is a schematic diagram of SRAM-type FPGA program loading;
[0044] Figure 4 This is a schematic diagram of the planetary-to-Earth link. Detailed Implementation
[0045] This invention provides an on-orbit reconfiguration system for spaceborne SRAM-type FPGA programs. The system includes: a data processing unit, a JFMRS01RH unit, an external storage unit, and a target FPGA.
[0046] The data processing unit includes a clock management module, a UART control module, a satellite-to-ground data processing module, an on-board data processing module, and an SDRAM control module. On one hand, it processes satellite-to-ground data, including intermediate frequency data reception and demodulation, AOS data frame recovery, data descrambling, and LDPC decoding; on the other hand, it processes on-board data, including AOS frame parsing, uplink data packet reassembly and verification, and uplink data packet secondary encapsulation.
[0047] The JFMRS01RH unit, with its core being the JFMRS01RH chip, includes a clock module, a UART control module, a configuration control module, an FPGA control module, and a NOR Flash control module. It is used to perform JFMRS01RH communication, status monitoring, initialization, data writing and reading, as well as task scheduling and management.
[0048] The external cache unit includes an SDRAM cache and a NOR Flash cache. The SDRAM cache interacts with the data processing unit and is used for caching the uploaded data packets after they are reassembled on the satellite. The NOR Flash cache interacts with the JFMRS01RH unit and is used to store the uploaded files loaded onto the target FPGA.
[0049] The target FPGA is an SRAM-type FPGA of a specific model specified by Fudan Microelectronics and Xilinx.
[0050] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.
[0051] Example
[0052] Embodiments of the present invention provide an on-orbit reconfiguration system for a spaceborne SRAM-type FPGA program, comprising: a data processing unit, a JFMRS01RH unit, an external storage unit, and a target FPGA. The target FPGA is any one of the JFM4V, JFM7V, and JFM7K series from Fudan Microelectronics, and the VIRTEX2, VIRTEX4~7, and KINTEX7 series from Xilinx. Figure 1 As shown.
[0053] The data processing unit includes a satellite-to-ground data processing module and an onboard data processing module.
[0054] The processing steps of the satellite-to-ground data processing module include:
[0055] Intermediate Frequency (IF) Signal Analysis: Receives IF signals from satellites and inputs them into the AD9361 data acquisition chip. The sampled uplink digital signals are then subjected to frequency acquisition, carrier synchronization, and timing synchronization, thereby completing the conversion from analog to digital signals.
[0056] AOS frame format recovery: Based on the transmit and receive levels, in the receive time slot, remove the pilot of the unnumbered information frame (UW) and restore it to the standard AOS (Advanced Orbiting Systems) frame format;
[0057] Descrambling and decoding: The descrambling module receives the data transmission frame of the depilot group AOS frame and descrambles the original scrambling area; after validating the descrambled valid frame, it decodes it according to the decoding rules of (8160,7136) Low-Density Parity-Check Code (LDPC) and outputs the decoded data.
[0058] The processing steps of the onboard data processing module include:
[0059] Packet validity check: If the packet start information is 0x1ACFFCD, it is considered a valid packet; otherwise, it is considered invalid data and discarded.
[0060] Upload data packet parsing: Extract and latch the virtual channel identifier in the upload data packet to generate the logical address of SDRAM, and at the same time extract the data source packet information of the FPGA program to be reconstructed from the AOS transmission frame according to the link protocol;
[0061] Data packet verification: Except for the last packet, all uplink data packets are fixed-length data packets (packet length). The length of the last packet depends on the actual size of the uplink file. Therefore, it is necessary to verify the valid data based on the extracted length field to ensure the correctness of the link. This system supports two methods: cumulative summation and CRC-CCITT, which can be selected through command configuration. The default is CRC-CCITT.
[0062] Secondary data packet encapsulation: The valid data in the correct upload packet is encapsulated into a data packet that conforms to the NOR Flash programming operation according to the format required by the JFMRS01RH protocol, and sent to JFMRS01RH through the UART interface in the agreed format.
[0063] This system supports out-of-order packet uploading. A logical address for buffering is generated based on the virtual channel identifier and packet number, and then mapped to a physical address. Verified packets are buffered in SDRAM. For erroneous packets, the sequence number of the erroneous packet is fed back to the ground, and the received updated correct packet is inserted into the corresponding position of the original packet in the SDRAM.
[0064] The JFMRS01RH unit uses RS422 serial communication to report status to the data processing unit and has autonomous task management capabilities. The reported status includes: FPGA refresh status, reload status, reload and refresh bitstream CRC detection results, UART command CRC status, FLASH operation results, UART processing status, and FIFO data status. The communication baud rate is 115200bps. The status data packet consists of a "frame header + offset address + 1B data + 2B CRC check + frame tail" format, and is sent in 21-byte chunks.
[0065] After power-on, the JFMRS01RH chip requires initialization settings, including FPGA loading mode selection, FLASH peripheral model selection, automatic telemetry control, and refresh control. The task scheduling of JFMRS01RH includes FLASH programming tasks, FLASH erasure tasks, Flash ID monitoring tasks, Flash bit stream CRC detection tasks, and Flash data readback tasks.
[0066] After the satellite enters the airspace and establishes the satellite-to-ground link, it first receives the modulated carrier signal transmitted by the ground station. The satellite-to-ground data processing module in the data processing unit receives the intermediate frequency signal from the satellite and inputs it into the AD9361 data acquisition chip. The sampled uplink digital signal undergoes frequency acquisition, carrier synchronization, and timing synchronization, thus completing the analog-to-digital signal conversion. Then, based on the transmit and receive levels, in the receive time slot, the pilot signal of the UW frame is removed, and the signal is restored to the standard AOS frame format, such as... Figure 2 As shown; then, the descrambling module receives the data transmission frame sent by the depilot group AOS frame module and descrambles the original scrambling area; after the validity processing of the descrambled valid frame, it decodes it according to the decoding rules of (8160,7136) LDPC code and outputs the decoded data to the on-board data processing module.
[0067] The onboard data processing module first checks the validity of data packets. If the packet's initial information is 0x1ACFFCD, it is considered a valid packet; otherwise, it is considered invalid and discarded. Then, by parsing the uplink data packets, it extracts and latches the virtual channel identifier from the uplink data packets to generate logical addresses for SDRAM. During parsing, it simultaneously extracts the valid information of the data packets for the FPGA program to be reconstructed from the AOS transmission frame according to the link protocol. After reception, it verifies the valid data using a checksum mechanism to determine the correctness of the link and the integrity of the data. For correctly verified data packets, it generates a buffered logical address based on the virtual channel identifier and packet number, maps it to a physical address, and caches the uplink data packets in SDRAM. For erroneous data packets, it sends the sequence number of the erroneous packet back to the ground and inserts the correct data packet, updated from the ground, into the corresponding position of the metadata in SDRAM. Finally, the system monitors the status of JFMRS01RH through the UART control module of the data processing unit. When it is ready to write data, it updates the program storage area identifier and encapsulates the valid data in the correct uplink packets into a format compliant with the JFMRS01RH protocol. The data packets for Flash programming operations are sent to the JFMRS01RH unit via the UART interface in the agreed format. At the same time, the NOR Flash write operation is initiated. The data packets are cached in the external NOR Flash through its internal autonomous task management. After the data packets are cached, the storage area identifier is restored, thereby completing the caching of the data packets on the target FPGA.
[0068] The system monitors the on-orbit operating status of the target FPGA. If on-orbit program reconfiguration is required due to mission requirements or abnormal status, the ground sends a target FPGA reconfiguration command to the system. Upon receiving the command, the system first configures the target FPGA to be loaded, including FPGA model selection, loading mode, and update source file generation. Then, it uses the JFMRS01 unit to... Figure 3 The system autonomously monitors the status of the target FPGA and completes the transfer of the bitstream file from NOR Flash to the target FPGA. Upon completion, it provides feedback on the success status, thus realizing the on-orbit reconfiguration function for SRAM-type FPGA programs. For example... Figure 4 The diagram shown is a schematic of the planetary-to-ground link.
[0069] The JFMRS01RH unit uses RS422 serial communication to feed back status to the data processing unit. The feedback status includes: FPGA refresh status, reload status, reload and refresh bit stream CRC detection results, UART command CRC status, FLASH operation results, UART processing status, and FIFO data status. The communication baud rate is 115200bps. The status data packet is composed of the format "frame header + offset address + 1B data + 2B CRC check + frame tail", and 21 bytes are sent at a time.
[0070] It is worth noting that in the embodiments of the above system, the modules included are divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of each functional module are only for easy differentiation and are not used to limit the scope of protection of the present invention.
[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.
Claims
1. A system for on-orbit reconfiguration of a space-borne SRAM-based FPGA program, characterized in that, The system includes: a data processing unit, a JFMRS01RH unit, an external storage unit, and a target FPGA, wherein, The data processing unit includes a satellite-to-ground data processing module and an onboard data processing module. The satellite-to-ground data processing module is used to receive intermediate frequency signals from the satellite, perform demodulation, AOS data frame recovery, data descrambling, and LDPC decoding. The onboard data processing module is used to sequentially perform AOS data frame parsing, uploading data packet reassembly, verification, and secondary encapsulation, and then transmit the data to the JFMRS01RH unit. The JFMRS01RH unit is used to receive the uploading data packet after secondary encapsulation by the data processing unit, perform status monitoring and feedback the status to the data processing unit, and also to perform task scheduling management. The external storage unit is used for caching the reassembled data packets and for storing the upload files to be loaded into the target FPGA. The target FPGA is used to provide logic control and algorithm implementation for the payload of the satellite in orbit.
2. The on-orbit reconfiguration system for spaceborne SRAM-type FPGA programs according to claim 1, characterized in that, The processing procedure of the satellite-to-ground data processing module includes: It receives intermediate frequency signals from satellites, samples them, and performs frequency acquisition, carrier synchronization, and timing synchronization on the sampled uplink digital signals, thereby completing the conversion from analog to digital signals. Based on the transmit and receive levels, in the receive time slot, remove the pilot of the unnumbered information frame in the air interface and restore it to the standard AOS frame format; The system receives data transmission frames from the depilot group AOS frames, descrambles the original scrambled region, performs validity processing on the descrambled valid frames, performs LDPC decoding according to the decoding rules of the (8160,7136) low-density parity check code, and outputs the decoded data and instructions from the ground to the onboard data processing module.
3. The on-orbit reconfiguration system for spaceborne SRAM-type FPGA programs according to claim 1, characterized in that, The processing procedure of the on-board data processing module includes: Perform a validity check on the data packet to determine if the packet's initial information is correct. If it is, the packet is considered valid; otherwise, it is considered invalid and discarded. The virtual channel identifier in the above-injected data packet is extracted and latched to generate the logical address of SDRAM. At the same time, the data source packet information of the FPGA program to be reconstructed is extracted from the AOS transmission frame according to the link protocol. Extract the length field of valid data packets and perform verification; for data packets that are determined to be correct, generate a logical address for caching based on the virtual channel identifier and data packet number, and map it to a physical address, and cache the data packets in SDRAM; for data packets that are determined to be incorrect, send the data packet sequence number back to the ground, wait for the ground to send back the updated correct data packets, generate a logical address for caching based on the virtual channel identifier and data packet number, and map it to a physical address, and cache it in the corresponding location in SDRAM. The valid data packets are encapsulated into data packets that conform to NOR Flash programming operations according to the format required by the JFMRS01RH protocol, and sent to the JFMRS01RH unit through the UART interface in the agreed format.
4. The on-orbit reconfiguration system for spaceborne SRAM-type FPGA programs according to claim 3, characterized in that, The data processing unit further includes: a clock management module, a UART control module, and an SDRAM control module; wherein... The clock management module is used to generate clocks for the satellite-to-ground data processing module and the on-board data processing module respectively according to the clock frequency of the external crystal oscillator, and at the same time provide clock signals to the JFMRS01RH unit. The UART control module is used to send instruction information to the JFMRS01RH unit and receive status information fed back by the JFMRS01RH unit. The SDRAM control module is used for scheduling and controlling the external SDRAM chip, which is used to provide a cache for the on-orbit reconstruction file of the target FPGA received by the on-board data processing module.
5. The on-orbit reconfiguration system for spaceborne SRAM-type FPGA programs according to claim 4, characterized in that, The JFMRS01RH unit includes: a clock module, a UART control module, a configuration control module, an FPGA control module, and a NOR Flash control module, wherein... The clock module is used to receive clock signals from the clock management module of the data processing unit and generate clocks of different frequencies for use by other modules inside the JFMRS01RH unit. The UART control module is used to receive and parse instruction information from the data processing unit, and at the same time to feed back status information to the UART control module of the data processing unit. The configuration control module is used to detect the model, interface mode and interface connection method of the target FPGA, and is also used to detect and count whether the target FPGA has readback errors and / or refresh errors due to single-event interruption events during refresh and loading, and to configure the refresh and readback mode, refresh and readback time interval of the target FPGA. The FPGA control module is used to configure the bit stream of the target FPGA according to a predetermined process for the program that needs to be updated. The NOR Flash control module is used to monitor the status of the JFMRS01RH unit. When the data writing conditions are met, it updates the program storage area identifier, encapsulates the valid data in the correct uploading data packet into a data packet that conforms to the NOR Flash programming operation according to the format required by the JFMRS01RH protocol, and sends it to the JFMRS01RH unit through the UART interface according to the agreed format, while starting the NOR Flash writing operation.
6. The on-orbit reconfiguration system for spaceborne SRAM-type FPGA programs according to claim 1, characterized in that, The JFMRS01RH unit uses RS422 serial communication to feed back status to the data processing unit. The feedback status includes: FPGA refresh status, reload status, reload and refresh bit stream CRC detection results, UART command CRC status, FLASH operation results, UART processing status, and FIFO data status. The communication baud rate is 115200bps, and the status data packet format is: frame header + offset address + 1B data + 2B CRC check + frame tail, with 21 bytes sent at a time.
7. The on-orbit reconfiguration system for spaceborne SRAM-type FPGA programs according to claim 1, characterized in that, The external storage unit includes: an SDRAM cache and a NOR Flash cache, wherein, The SDRAM cache interacts with the data processing unit to cache the data packets reassembled on the satellite. The NOR Flash cache interacts with the JFMRS01RH unit to store the upload file loaded onto the target FPGA.
8. The on-orbit reconfiguration system for spaceborne SRAM-type FPGA programs according to claim 1, characterized in that, The target FPGA is any one of the JFM4V, JFM7V, and JFM7K series from Fudan Microelectronics and the VIRTEX2, VIRTEX4~7, and KINTEX7 series from Xilinx.