FPGA layout and wiring acceleration method and system based on RTL code features

Abstract

The invention discloses an FPGA layout and wiring acceleration method and system based on RTL code features, and belongs to the technical field of FPGA design and automation, the implementation of the method comprises the following steps: RTL code feature extraction and analysis: analyzing the structural features, resource requirements and time sequence attributes of RTL codes, and providing a data basis for physical constraint generation; physical constraint automatic generation: based on code features and FPGA resource distribution, automatically generating a Pblock division and implementation strategy; incremental layout and wiring multiplexing: realizing incremental compiling and incremental layout and wiring, and improving the compiling speed; and closed-loop feedback optimization: dynamically optimizing constraint generation rules and strategy selection logic based on a historical layout result. According to the method, the problems of high manual dependence, low iteration efficiency and frequent resource conflicts in the existing FPGA layout wiring technology can be solved, manual layout experience dependence is eliminated, iteration time consumption is greatly shortened, and design maintainability is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of FPGA design and automation, in particular to an FPGA placement and routing acceleration method and system based on RTL code features. BACKGROUND

[0002] FPGA (Field Programmable Gate Array) is widely used in 5G base stations, autonomous driving, spacecraft control and other fields due to its reconfigurable characteristics. Placement and routing, as a core link in the FPGA design process, is responsible for mapping the synthesized logic units to FPGA physical resources and completing signal connection, directly determining the timing performance and resource utilization of the design. With the FPGA scale jumping from tens of millions of gates to billions of gates, the placement and routing time of large projects has become a major bottleneck in research and development iteration. Existing FPGA placement and routing techniques mainly rely on the automatic process of EDA tools (such as Vivado), but have the following key defects:

[0003] 1. Physical constraints rely on manual experience, and the division of Pblock (physical region constraint) needs to be completed manually by engineers, which requires repeated debugging in combination with the FPGA resource distribution manual. Due to the lack of code and physical resource correlation analysis, DRC errors often occur due to insufficient resources in Pblock, which can lead to multiple iterations of placement and routing in large projects, increasing the time consumption.

[0004] 2. Full-process iteration redundancy, after each RTL code modification, the complete placement and routing process needs to be re-executed. Even if only a local module (such as logic optimization of a sub-module) is modified, the tool will still recalculate the entire design, which can take several hours in a large project, seriously affecting iteration efficiency.

[0005] 3. Strategy selection lacks adaptive ability, and needs to be specified manually when implementing strategies (such as timing priority, balance mode), which cannot dynamically adapt to the resource characteristics and timing requirements of modules.

[0006] These defects make it difficult for existing technologies to meet the rapid iteration needs of large-scale FPGA projects, and an optimization technology breakthrough is needed to break through the efficiency bottleneck by integrating code analysis, automatic constraint generation and incremental reuse. SUMMARY

[0007] The technical task of the present application is to solve the above problems, provide an FPGA placement and routing acceleration method and system based on RTL code features, solve the problems of strong manual dependence, low iteration efficiency and frequent resource conflicts in existing FPGA placement and routing techniques, eliminate the dependence on manual placement experience, greatly shorten the iteration time, and improve the design maintainability.

[0008] The technical solution adopted by the present application to solve its technical problems is:

[0009] The FPGA layout and routing acceleration method based on RTL code features includes the following steps:

[0010] RTL code feature extraction and analysis: analyze the structural features, resource requirements and timing properties of the RTL code to provide data basis for physical constraint generation;

[0011] Automatic generation of physical constraints: based on the code features and FPGA resource distribution, automatically generate Pblock partition and implementation strategy;

[0012] Incremental layout and routing reuse: implement incremental compilation and incremental layout and routing to improve compilation speed;

[0013] Closed-loop feedback optimization: dynamically optimize constraint generation rules and strategy selection logic based on historical layout results.

[0014] The method realizes automatic Pblock partition based on RTL code features, eliminates the dependence on manual layout experience, and reduces resource conflict rate; proposes an incremental layout and routing reuse mechanism, only performs local calculation on the code change module, greatly shortens the iteration time consumption; constructs an adaptive strategy selection and closed-loop optimization system, improves the timing convergence rate and resource utilization rate of layout and routing; establishes a collaborative optimization link between code quality and physical implementation, guides physical constraint generation through structured code analysis, and improves design maintainability.

[0015] Further, the RTL code feature extraction and analysis includes:

[0016] Use code collection tools to perform lexical and syntax analysis on Verilog / VHDL code to generate abstract syntax tree AST; traverse the AST to identify module hierarchical relationships (such as the parent-child relationship between top / u_ram_T11 and top / u_logic_T12), and construct a "parent module-submodule" adjacency list;

[0017] Resource feature quantification; for storage modules, identify RAM / FIFO types through the (*ram_style="block"*) attribute, and calculate the equivalent RAMB36 quantity according to the formula ceil((bit width+1)×depth / 36×1024); for operation modules, combine DSP inference rules based on the density of * and + operators to count the demand for DSP48E1 units; for logic modules, count the number of LUTs and FFs, and mark timing critical modules with the (*dont_touch="yes"*) attribute.

[0018] Further, after code collection, output in json format, including:

[0019] Code relationship, including class level (parent class), whether top-level, code classification (whether logical resources or ram resources), whether critical code, etc.

[0020] Statistical resource consumption, including RAM, LUT, etc.

[0021] Related constraints, including maximum delay time, etc.

[0022] Further, the physical constraints are automatically generated, including:

[0023] Build FPGA resource database: parse the target FPGA device (such as xcvp1902) xdc official file report_device command output (refer to the official manual), xdc file is used to determine the pin position, report_device file is used to count resources, so as to build a two-dimensional grid indexed resource database;

[0024] Store the physical coordinates (x / y range) and available number of RAMB36 cluster, DSP cluster, and logic area. For automatic division of Pblock, follow the following principles:

[0025] Resource matching: filter the cluster combination whose total available resources ≥ module demand (such as u_ram_T11 requires 236 RAMB36, and the total of matching clusters A+B+C is 280);

[0026] Region merging: calculate the minimum bounding rectangle (x min , x max , y min , y max ) of the selected cluster, and generate Pblock coordinates (such as X0Y0:X300Y50);

[0027] Conflict detection: compare the coordinate range of the newly generated Pblock with the existing Pblock. If they overlap, assign them to the timing critical module first;

[0028] After completing resource matching and resource summary, adapt different default strategies according to different types. If it is a large prototype verification platform, support code automatic splitting, then it will have better matching degree.

[0029] Further, the default strategy adaptation complies with the following rules:

[0030] If it is RAM-intensive, that is, there are many RAM resources and low timing requirements, use the compromise strategy, that is, balance strategy;

[0031] If it is DSP / logic-intensive, with high timing requirements, use Explore strategy;

[0032] If it is low timing requirements, and for auxiliary module premise, auxiliary module needs artificial marking, reduce its priority, then adopt Flowquick or Flowoptimize strategy, at this time, the standard of selecting two strategies is to judge according to the size of LUT: if LUT is greater than 10,000, then Flowoptimize more stable is adopted, although the speed priority is increased, but the timing will not be too bad;If LUT is less than 10,000, then the fast Flowquick strategy is adopted to obtain the maximum layout and wiring speed.

[0033] Further, the closed loop feedback optimization, the host computer stores the input characteristics and output indexes of each layout and wiring, and constructs a SQLite timing database;

[0034] The input characteristics include module resources, constraint parameters;

[0035] The output indexes include time consumption, WNS and resource utilization.

[0036] Further, a gradient boosting decision tree (GBDT) is used to train a prediction model, the input is "module resource characteristics + device model", and the output is "optimal Pblock range + recommended strategy";

[0037] Initially, 100 groups of artificial optimization data are pre-trained, and subsequently, the parameters are updated through online learning;

[0038] When the timing compliance rate of a certain type of module (such as RAMB36 requiring 200-250) is less than 90%, the rule optimization is triggered, for example, the original Pblock cluster combination A+B is adjusted to A+B+C, and the model training sample is updated.

[0039] The application also claims a FPGA layout and wiring acceleration system based on RTL code characteristics, which can realize the above method, and the system comprises:

[0040] An RTL code characteristic extraction and analysis module is used to analyze the structural characteristics, resource requirements and timing attributes of the RTL code, and provide a data basis for physical constraint generation;

[0041] A physical constraint automatic generation module is used to automatically generate Pblock division and implementation strategy based on code characteristics and FPGA resource distribution;

[0042] An incremental layout and wiring reuse module is used to realize incremental compilation and incremental layout and wiring, and improve the compilation speed;

[0043] A closed loop feedback optimization module is used to dynamically optimize constraint generation rules and strategy selection logic based on historical layout results;

[0044] The modules interact with feature data, constraint instructions and layout results through a data bus.

[0045] The application also claims to protect an FPGA layout and routing acceleration implementation device based on RTL code features, comprising: at least one memory and at least one processor;

[0046] The at least one memory is used for storing a machine readable program;

[0047] The at least one processor is used for calling the machine readable program to realize the above method.

[0048] The application also claims to protect a computer readable medium, wherein computer instructions are stored on the computer readable medium, and the computer instructions can realize the above method when executed by a processor.

[0049] Compared with the prior art, the FPGA layout and routing acceleration method and system based on RTL code features have the following beneficial effects:

[0050] 1. Iterative efficiency is greatly improved: the incremental reuse mechanism reduces the layout and routing time after local code modification;

[0051] 2. Resource conflict rate is significantly reduced: the Pblock automatic partitioning algorithm is based on code resource demand and device distribution matching to reduce the workload of manual adjustment;

[0052] 3. Timing convergence rate is improved: adaptive strategy selection and closed-loop optimization increase the timing compliance rate and reduce the average delay of the critical path;

[0053] 4. Strong compatibility: can be integrated into the existing EDA tool chain, called through the Tcl interface, and does not need to replace the existing design process. BRIEF DESCRIPTION OF DRAWINGS

[0054] Figure 1 It is a flowchart of the FPGA layout and routing acceleration method based on RTL code features provided by an embodiment of the application. DETAILED DESCRIPTION

[0055] The application will be further described below in combination with specific embodiments.

[0056] The embodiment of the application provides an FPGA layout and routing acceleration method based on RTL code features, which realizes the dual improvement of layout and routing efficiency and design quality through the closed-loop architecture of "code analysis-constraint generation-incremental reuse-feedback optimization".

[0057] The implementation of the method includes:

[0058] 1. RTL code feature extraction and analysis: analyze the structural features, resource requirements and timing attributes of the RTL code to provide a data basis for physical constraint generation.

[0059] Code collection tools are used to perform lexical and syntax analysis on Verilog / VHDL code to generate an abstract syntax tree AST; the AST is traversed to identify module hierarchical relationships (such as the parent-child relationship between top / u_ram_T11 and top / u_logic_T12), and an “parent module-child module” adjacency list is constructed;

[0060] Resource feature quantification; for storage modules, the RAM / FIFO type is identified through the (*ram_style = "block"*) attribute, and the equivalent RAMB36 quantity is calculated according to the formula ceil((bit width + 1) x depth / 36 x 1024); for operation modules, the DSP48E1 unit requirement is calculated by combining the operator density with DSP inference rules; for logic modules, the LUT and FF quantities are counted, and the (*dont_touch = "yes"*) attribute is used to mark timing critical modules.

[0061] A simple example is as follows: after collection, the output is in json format, the first type is code relationship module_hierarchy, which respectively represents class level (parent class), whether it is the top level, code classification (whether it is a logic resource or a ram resource), and whether it is a critical code; the second type is the resource consumption obtained by statistics, such as RAM, LUT, etc.; the third type is related constraints, such as maximum delay time, etc.:

[0062]

[0063] 2. Automatic generation of physical constraints: based on code features and FPGA resource distribution, Pblock partitioning and implementation strategies are automatically generated.

[0064] First, the FPGA resource database needs to be constructed: parse the report_device command output of the official xdc file of the target FPGA device (such as xcvp1902) (refer to the official manual), the xdc file is used to determine the pin position, and the report_device file is used to count the resources, thereby constructing a two-dimensional grid indexed resource database.

[0065] The physical coordinates (x / y range) and available quantities of storage RAMB36 clusters, DSP clusters, and logic regions are stored, and for the automatic partitioning of Pblocks, the following principles are followed:

[0066] (1) Resource matching: filter cluster combinations whose total available resources are greater than or equal to the module requirements (such as u_ram_T11 requires 236 RAMB36, and the total of clusters A+B+C is 280);

[0067] (2) Region merging: calculate the minimum bounding rectangle (xmin , x max , y min , y max ), generate Pblock coordinate (e.g. X0Y0:X300Y50);

[0068] (3) Conflict detection: compare the new generated Pblock with the existing Pblock coordinate range, if overlap, then assign to the timing critical module first.

[0069] After completing resource matching and resource aggregation, different default strategies will be adapted according to different types. If it is a large prototype verification platform, it supports automatic code splitting, and then there will be better matching degree. The default strategy complies with the following rules:

[0070] If it is RAM-intensive, i.e. more RAM resources and not high timing requirements, a compromise strategy, i.e. balance strategy, is adopted;

[0071] If it is DSP / logic-intensive, the timing requirement is higher, then the Explore strategy will be adopted;

[0072] If the timing requirement is not high, and it is a prerequisite for auxiliary modules, the auxiliary modules need to be manually marked, and the priority is reduced, then the Flow quick or Flow optimize strategy will be adopted. At this time, the standard for choosing the two strategies is to see the size of LUT. If LUT is greater than 10,000, then the more stable Flow optimize will be adopted. Although the speed is increased first, but the timing will not be too bad. If LUT is less than 10,000, then the fast Flow quick strategy will be adopted to obtain the maximum layout and routing speed.

[0073] 3, Incremental layout and routing reuse: realize incremental compilation and incremental layout and routing, and improve the compilation speed.

[0074] The incremental reuse function is supported by Vivado2019 version. In the case of ensuring that the modification is not large, the incremental compilation and incremental layout and routing functions can be started. This function can further improve the compilation speed and is the function of EDA tool.

[0075] 4, Closed-loop feedback optimization: dynamically optimize constraint generation rules and strategy selection logic based on historical layout results.

[0076] The upper computer can store the input characteristics (module resources, constraint parameters) and output indicators (time consumption, WNS, resource utilization) of each layout and routing, and construct a SQLite timing database, such as:

[0077] CREATE TABLE layout_history(

[0078] id INT PRIMARY KEY,

[0079] module_resources JSON,

[0080] pblock_definition JSON,

[0081] strategy_used TEXT,

[0082] runtime FLOAT,

[0083] wns FLOAT,

[0084] utilization JSON );

[0086] The prediction model is trained by using gradient boosting decision tree (GBDT), the input is "module resource features + device model", and the output is "optimal Pblock range + recommended strategy". Initially, 100 sets of artificial optimization data are pre-trained, and then the parameters are updated through online learning. When the timing compliance rate of a certain type of module (such as RAMB36 demand 200-250) is less than 90%, the rule optimization is triggered, for example, the original Pblock cluster combination A+B is adjusted to A+B+C, and the model training sample is updated.

[0087] The method fuses code feature analysis and incremental reuse to realize FPGA layout and routing optimization; realizes Pblock automatic division based on RTL code features, eliminates the dependence on manual layout experience, and reduces the resource conflict rate; proposes an incremental layout and routing reuse mechanism, only performs local calculation on the code change module, and greatly shortens the iteration time consumption; constructs an adaptive strategy selection and closed-loop optimization system, improves the timing convergence rate and resource utilization rate of layout and routing; establishes a collaborative optimization link between code quality and physical implementation, guides physical constraint generation through structured code analysis, and improves design maintainability. It is suitable for rapid iteration design scenarios of large-scale FPGA projects, and can improve the layout and routing efficiency and design quality of EDA tools.

[0088] The embodiment of the present application also provides an FPGA layout and routing acceleration system based on RTL code features, which can realize the FPGA layout and routing acceleration method based on RTL code features described in the above embodiment. The system includes four core modules: RTL code feature extraction and analysis module, physical constraint automatic generation module, incremental layout and routing reuse module, and closed-loop feedback optimization module. Each module realizes the interaction of feature data, constraint instructions and layout results through a data bus. The overall architecture is as shown in Figure 1 .

[0089] 1. RTL code feature extraction and analysis module, for parsing the structural features, resource requirements and timing attributes of RTL code, providing data basis for physical constraint generation.

[0090] Using code collection tools to perform lexical and syntax analysis on Verilog / VHDL code to generate abstract syntax tree AST; traversing AST to identify module hierarchical relationship (such as the parent-child relationship between top / u_ram_T11 and top / u_logic_T12), and constructing "parent module-submodule" adjacency list;

[0091] Resource feature quantification; for storage modules, identify RAM / FIFO types through the (*ram_style="block"*) attribute, and calculate the equivalent RAMB36 quantity according to the formula ceil((bit width+1) x depth / 36 x 1024); for operation modules, combine DSP inference rules with operator density to count DSP48E1 unit requirements; for logic modules, count LUT and FF quantities, and mark timing critical modules with the (*dont_touch="yes"*) attribute.

[0092] After completion of collection, output in json format, including: code relationship module_hierarchy, which respectively represents class level (parent class), whether top level, code classification (logic resource or ram resource), and whether critical code; resource consumption obtained by statistics, such as RAM, LUT, etc.; related constraints, maximum delay time, etc.

[0093] 2. Physical constraint automatic generation module, for automatically generating Pblock division and implementation strategy based on code features and FPGA resource distribution.

[0094] First, need to build FPGA resource database: parse the report_device command output of the official xdc file of the target FPGA device (such as xcvp1902) (refer to the official manual), the xdc file is used to determine the pin position, and the report_device file is used to count resources, thereby constructing a two-dimensional grid indexed resource database.

[0095] Physical coordinates (x / y range) and available quantity of storage RAMB36 cluster, DSP cluster, and logic region, for automatic division of Pblock, according to the following principles:

[0096] (1) Resource matching: filter cluster combinations with total available resources ≥ module requirements (such as u_ram_T11 requires 236 RAMB36, matching cluster A+B+C total 280);

[0097] (2) Region merging: calculate the minimum bounding rectangle (x / y range) of selected clusters, and divide the Pblock according to the principle of "minimum resource consumption"min , x max , y min , y max ), generate Pblock coordinates (such as X0Y0:X300Y50);

[0098] (3) Conflict detection: compare the newly generated Pblock with the existing Pblock coordinate range, if overlapping, preferentially allocate to the timing critical module.

[0099] After completing resource matching and resource aggregation, different default strategies are adapted according to different types, and if it is a large prototype verification platform, the code automatic splitting is supported, and the matching degree is better. The default strategy complies with the following rules:

[0100] If it is RAM-intensive, that is, there are more RAM resources and the timing requirement is not high, a compromise strategy, that is, balance strategy, is adopted;

[0101] If it is DSP / logic-intensive, the timing requirement is higher, and Explore strategy will be adopted;

[0102] If the timing requirement is not high, and it is a prerequisite for auxiliary modules, the auxiliary modules need to be manually marked, and the priority is reduced, then Flow quick or Flow optimize strategy will be adopted, at this time, the standard of choosing two strategies is to see the size of LUT, if LUT is greater than 10,000, Flow optimize will be adopted, although the speed is increased first, but the timing will not be too bad, if LUT is less than 10,000, Flow quick strategy will be adopted to obtain the maximum layout and routing speed.

[0103] 3, incremental layout and routing reuse module, used to realize incremental compilation and incremental layout and routing, and improve the compilation speed.

[0104] Incremental reuse function is supported by Vivado2019 version, under the condition of ensuring that the modification is not large, the functions of incremental compilation and incremental layout and routing can be started, which can further improve the compilation speed, and is the function of EDA tool.

[0105] 4, closed-loop feedback optimization module, used to dynamically optimize constraint generation rules and strategy selection logic based on historical layout results.

[0106] The host computer stores the input features (module resources, constraint parameters) and output indicators (time consumption, WNS, resource utilization) of each layout and routing, and constructs SQLite timing database.

[0107] The gradient boosting decision tree (GBDT) is used to train the prediction model, the input is "module resource features + device model", and the output is "optimal Pblock range + recommended strategy". Initially, 100 sets of artificial optimization data are pre-trained, and then the parameters are updated through online learning. When the timing compliance rate of a certain type of module (such as RAMB36 demand 200-250) is less than 90%, trigger rule optimization, for example, adjust the original Pblock cluster combination A+B to A+B+C, and update the model training sample.

[0108] The system can be applied to many-core chip design and is suitable for rapid iterative design scenarios of large-scale FPGA engineering, and can improve the layout and routing efficiency and design quality of EDA tools.

[0109] The embodiment of the application also provides an FPGA layout and routing acceleration implementation device based on RTL code features, comprising at least one memory and at least one processor.

[0110] The at least one memory is used to store machine readable programs.

[0111] The at least one processor is used to call the machine readable programs to realize the FPGA layout and routing acceleration method based on RTL code features in the above embodiment.

[0112] The embodiment of the application also provides a computer readable medium, which stores computer instructions, and the computer instructions make the processor execute the FPGA layout and routing acceleration method based on RTL code features in the above embodiment when the processor executes the computer instructions. Specifically, a system or device equipped with a storage medium can be provided, the storage medium stores software program code realizing the functions of any one of the above embodiments, and the computer (or CPU or MPU) of the system or device reads and executes the program code stored in the storage medium.

[0113] In this case, the program code read from the storage medium itself can realize the functions of any one of the above embodiments, so the program code and the storage medium storing the program code constitute a part of the application.

[0114] The storage medium embodiments for providing program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROM. Alternatively, the program code can be downloaded from a server computer through a communication network.

[0115] Furthermore, it should be understood that, not only the program codes read by the computer can be executed, but also the operating system and the like operating on the computer can be caused to perform part or all of the actual operations based on the instructions of the program codes, thereby realizing the functions of any one of the above-described embodiments.

[0116] Furthermore, it should be understood that, not only the program codes read by the computer can be executed, but also the operating system and the like operating on the computer can be caused to perform part or all of the actual operations based on the instructions of the program codes, thereby realizing the functions of any one of the above-described embodiments.

[0117] The present application has been described in detail by the above drawings and preferred embodiments, however, the present application is not limited to these disclosed embodiments, and those skilled in the art can know that, the code review means in the above different embodiments can be combined to obtain more embodiments of the present application, and these embodiments are also within the protection scope of the present application.

Claims

1. An FPGA placement and routing acceleration method based on RTL code features, characterized in that, The implementation of this method includes: RTL Code Feature Extraction and Analysis: Analyzing the structural features, resource requirements, and temporal attributes of RTL code to provide a data foundation for physical constraint generation; Automatic physical constraint generation: Based on code features and FPGA resource distribution, Pblock partitioning and implementation strategies are automatically generated; Incremental place and route reuse: Enables incremental compilation and incremental place and route, improving compilation speed; Closed-loop feedback optimization: Dynamically optimize constraint generation rules and strategy selection logic based on historical layout results.

2. The FPGA placement and routing acceleration method based on RTL code features according to claim 1, characterized in that, The RTL code feature extraction and analysis includes: A code acquisition tool was used to perform lexical and syntactic analysis on Verilog / VHDL code to generate an abstract syntax tree (AST). The AST was traversed to identify the module hierarchy and to construct a parent-child module adjacency list. Resource characteristics are quantified; for storage modules, RAM / FIFO types are identified by the (*ram_style="block"*) attribute, and the equivalent number of RAMB36 is calculated using the formula ceil((bit width + 1) × depth / 36 × 1024); for arithmetic modules, the DSP48E1 unit requirements are statistically determined by combining operator density with DSP inference rules; for logic modules, the number of LUTs and FFs is statistically determined, and timing-critical modules are marked by combining the (*dont_touch="yes"*) attribute.

3. The FPGA placement and routing acceleration method based on RTL code features according to claim 1 or 2, characterized in that, After the code collection is complete, the output should be in JSON format, including: Code relationships, including class level, whether it is top-level, code categorization, and whether it is critical code; The statistically obtained resource consumption includes RAM and LUTs; Relevant constraints, including maximum delay time.

4. The FPGA placement and routing acceleration method based on RTL code features according to claim 1, characterized in that, The physical constraints are automatically generated, including: Building an FPGA resource database: Parsing the report_device command output of the target FPGA device's official xdc file. The xdc file is used to determine pin locations, and the reportdevice file is used to count resources, thereby building a resource database with a two-dimensional grid index. The physical coordinates and available quantity of the storage RAMB36 cluster, DSP cluster, and logical area are determined according to the following principles for the automatic partitioning of Pblocks: Resource matching: Filter cluster combinations where the total available resources are greater than or equal to the module requirements; Region merging: Calculate the minimum bounding rectangle (x) of the selected cluster. min x max y min y max Generate Pblock coordinates; Conflict detection: Compare the coordinate ranges of the newly generated Pblock with those of the existing Pblock. If they overlap, prioritize assigning them to time-critical modules. After completing resource matching and aggregation, different default strategies are adapted according to different types.

5. The FPGA placement and routing acceleration method based on RTL code features according to claim 4, characterized in that, The default strategy adaptation follows these rules: If it is RAM-intensive, that is, there is a lot of RAM resources and low timing requirements, a compromise strategy, namely the balance strategy, is adopted. If it is a DSP / logic-intensive application with high timing requirements, then the Explore strategy should be adopted. If timing requirements are low and the auxiliary module is a prerequisite, the auxiliary module needs to be manually marked to reduce its priority. In this case, the Flowquick or Flowoptimize strategy is adopted. The criterion for choosing the two strategies is based on the size of the LUT: if the LUT is greater than 10,000, then Flowoptimize is adopted; if the LUT is less than 10,000, then the Flowquick strategy is adopted to obtain the maximum placement and routing speed.

6. The FPGA placement and routing acceleration method based on RTL code features according to claim 1, characterized in that, The closed-loop feedback optimization involves the host computer storing the input features and output indicators of each layout and routing step, and constructing an SQLite time-series database. Input features include: module resources and constraint parameters; Output metrics include: time elapsed, WNS (Waste N / A), and resource utilization.

7. The FPGA placement and routing acceleration method based on RTL code features according to claim 6, characterized in that, The prediction model is trained using gradient boosting trees. The input is "module resource features + device model", and the output is "optimal Pblock range + recommendation strategy". Initially, 100 sets of manually optimized data were used for pre-training, and the parameters were subsequently updated through online learning. When the time-series compliance rate of a certain type of module is less than 90%, rule optimization is triggered, and the model training samples are updated at the same time.

8. An FPGA placement and routing acceleration system based on RTL code features, characterized in that, The system is capable of implementing the method of any one of claims 1 to 7, and the system comprises: The RTL code feature extraction and analysis module is used to parse the structural features, resource requirements and temporal attributes of RTL code, providing a data foundation for physical constraint generation. The physical constraint automatic generation module is used to automatically generate Pblock partitioning and implementation strategies based on code features and FPGA resource distribution; The incremental placement and routing reuse module is used to implement incremental compilation and incremental placement and routing, thereby improving compilation speed. The closed-loop feedback optimization module is used to dynamically optimize the constraint generation rules and strategy selection logic based on historical layout results. Each module interacts with feature data, constraint instructions, and layout results through a data bus.

9. An FPGA placement and routing acceleration implementation device based on RTL code features, characterized in that, include: At least one memory and at least one processor; The at least one memory is used to store a machine-readable program; The at least one processor is configured to invoke the machine-readable program to implement the method according to any one of claims 1 to 7.

10. A computer-readable medium, characterized in that, The computer-readable medium stores computer instructions that, when executed by a processor, enable the implementation of the method described in any one of claims 1 to 7.

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